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/* Altera - ALT_USB */

#ifndef __ALTERA_ALT_USB_H__
#define __ALTERA_ALT_USB_H__

#ifdef __cplusplus
extern "C"
{
#endif  /* __cplusplus */

/*
 * Component : USB OTG Controller Module Registers - ALT_USB
 * USB OTG Controller Module Registers
 * 
 * Registers in the USB OTG Controller Module.
 * 
 * Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port
 * registers can be accessedin both Host and Device modes. When the USB OTG
 * Controller is operating in one mode, either Device or Host, the application must
 * not access registers from the other mode. If an illegal access occurs, a Mode
 * Mismatch interrupt is generated and reflected in the Core Interrupt register
 * (GINTSTS.ModeMis).
 * 
 * When the core switches from one mode to another, the registers in the new mode
 * must be reprogrammed as they would be after a power-on reset.
 * 
 * The register address map is fixed and does not depend on the module
 * configuration (for example, how many endpoints are implemented). Host and Device
 * mode registers occupy different addresses.
 * 
 */
/*
 * Register Group : Global Registers - ALT_USB_GLOB
 * Global Registers
 * 
 * These registers are available in both Host and Device modes, and do not need to
 * be reprogrammed when switching between these modes.
 * 
 */
/*
 * Register : OTG Control and Status Register - gotgctl
 * 
 * The OTG Control and Status register controls the behavior and reflects the
 * status of the OTG function.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                               
 * :--------|:-------|:------|:-------------------------------------------
 *  [0]     | R      | 0x0   | Session Request Success                   
 *  [1]     | RW     | 0x0   | Session Request                           
 *  [2]     | RW     | 0x0   | VBUS Valid Override Enable                
 *  [3]     | RW     | 0x0   | VBUS Valid Override Value                 
 *  [4]     | RW     | 0x0   | A-Peripheral Session Valid Override Enable
 *  [5]     | RW     | 0x0   | A-Peripheral Session Valid OverrideValue  
 *  [6]     | RW     | 0x0   | B-Peripheral Session Valid Override Enable
 *  [7]     | RW     | 0x0   | B-Peripheral Session Valid OverrideValue  
 *  [8]     | R      | 0x0   | Host Negotiation Success                  
 *  [9]     | RW     | 0x0   | HNP Request                               
 *  [10]    | RW     | 0x0   | Host Set HNP Enable                       
 *  [11]    | RW     | 0x0   | Device HNP Enabled                        
 *  [15:12] | ???    | 0x0   | *UNDEFINED*                               
 *  [16]    | R      | 0x1   | Connector ID Status                       
 *  [17]    | R      | 0x0   | Long Short Debounce Time                  
 *  [18]    | R      | 0x0   | A-Session Valid                           
 *  [19]    | R      | 0x0   | B-Session Valid                           
 *  [20]    | RW     | 0x0   | OTG Version                               
 *  [31:21] | ???    | 0x0   | *UNDEFINED*                               
 * 
 */
/*
 * Field : Session Request Success - sesreqscs
 * 
 * This bit is set when a session request initiation is successful. This bit is
 * valid only For Device Only configuration when OTG_MODE == 3 or OTG_MODE == 4.
 * Applies for device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL    | 0x0   | Session request failure
 *  ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS | 0x1   | Session request success
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS
 * 
 * Session request failure
 */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL       0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS
 * 
 * Session request success
 */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_MSB        0
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQSCS field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Session Request - sesreq
 * 
 * The application sets this bit to initiate a session request on the USB. The
 * application can clear this bit by writing a 0 when the Host Negotiation Success
 * Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is
 * SET. The core clears this bit when the HstNegSucStsChng bit is cleared. If you
 * use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the session
 * request, the application must wait until the VBUS discharges to 0.2 V, after the
 * B-Session Valid bit in  this register (GOTGCTL.BSesVld) is cleared. This
 * discharge time varies between different PHYs and can be obtained from the PHY
 * vendor.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description       
 * :----------------------------------------|:------|:-------------------
 *  ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST | 0x0   | No session request
 *  ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST   | 0x1   | Session request   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ
 * 
 * No session request
 */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ
 * 
 * Session request
 */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_MSB        1
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQ field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GOTGCTL_SESREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : VBUS Valid Override Enable - vbvalidoven
 * 
 * This bit is used to enable/disable the software to override the vbus-valid
 * signal using the GOTGCTL.vbvalidOvVal..
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                    
 * :----------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD | 0x0   | Override is disabled and bvalid signal from the
 * :                                        |       | respective PHY selected is used internally by  
 * :                                        |       | the force                                      
 *  ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END  | 0x1   | The vbus-valid signal received from the PHY is 
 * :                                        |       | overridden with GOTGCTL.vbvalidOvVal           
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
 * 
 * Override is disabled and bvalid signal from the respective PHY selected is used
 * internally by the force
 */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
 * 
 * The vbus-valid signal received from the PHY is overridden with
 * GOTGCTL.vbvalidOvVal
 */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_MSB        2
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : VBUS Valid Override Value - vbvalidovval
 * 
 * This bit is used to set Override value for vbus valid signal when
 * GOTGCTL.VbvalidOvEn is set.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                  
 * :-----------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 | 0x0   | vbusvalid value when GOTGCTL.VbvalidOvEn = 1 
 *  ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 | 0x1   | vbusvalid value when GOTGCTL.VbvalidOvEn is 1
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
 * 
 * vbusvalid value when GOTGCTL.VbvalidOvEn = 1
 */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
 * 
 * vbusvalid value when GOTGCTL.VbvalidOvEn is 1
 */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_MSB        3
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : A-Peripheral Session Valid Override Enable - avalidoven
 * 
 * This bit is used to enable/disable the software to override the Avalid signal
 * using the GOTGCTL.AvalidOvVal.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD | 0x0   | Override is disabled and Avalid signal from the
 * :                                       |       | respective PHY is used internally by the core. 
 *  ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END  | 0x1   | Internally Avalid received from the PHY is     
 * :                                       |       | overridden with GOTGCTL.AvalidOvVa             
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
 * 
 * Override is disabled and Avalid signal from the respective PHY is used
 * internally by the core.
 */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
 * 
 * Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVa
 */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_MSB        4
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : A-Peripheral Session Valid OverrideValue - avalidovval
 * 
 * This bit is used to set Override value for Avalid signal when GOTGCTL.BvalidOvEn
 * is set.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                    
 * :------------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 | 0x0   | Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
 *  ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 | 0x1   | Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
 * 
 * Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
 */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
 * 
 * Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
 */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_MSB        5
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : B-Peripheral Session Valid Override Enable - bvalidoven
 * 
 * This bit is used to enable/disable the software to  override the Bvalid signal
 * using the GOTGCTL.BvalidOvVal.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD | 0x0   | Override is disabled and bvalid signal from the
 * :                                       |       | respective PHY selected is used internally by  
 * :                                       |       | the core                                       
 *  ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END  | 0x1   | Internally Bvalid received from the PHY is     
 * :                                       |       | overridden with GOTGCTL.BvalidOvVal            
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
 * 
 * Override is disabled and bvalid signal from the respective PHY selected is used
 * internally by the core
 */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
 * 
 * Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal
 */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_MSB        6
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : B-Peripheral Session Valid OverrideValue - bvalidovval
 * 
 * This bit is used to set Override value for Bvalid signalwhen GOTGCTL.BvalidOvEn
 * is set.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                            
 * :------------------------------------------|:------|:----------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 | 0x0   | Bvalid value when GOTGCTL.AvalidOvEn =1
 *  ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 | 0x1   | Bvalid value when GOTGCTL.AvalidOvEn =1
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
 * 
 * Bvalid value when GOTGCTL.AvalidOvEn =1
 */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
 * 
 * Bvalid value when GOTGCTL.AvalidOvEn =1
 */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_MSB        7
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Host Negotiation Success - hstnegscs
 * 
 * Mode: Device only. Host Negotiation Success (HstNegScs) The core sets this bit
 * when host negotiation is successful. The core clears this bit when the HNP
 * Request (HNPReq) bit in this register is SET.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description             
 * :-----------------------------------------|:------|:-------------------------
 *  ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL    | 0x0   | Host negotiation failure
 *  ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS | 0x1   | Host negotiation success
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
 * 
 * Host negotiation failure
 */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL       0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
 * 
 * Host negotiation success
 */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_MSB        8
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : HNP Request - hnpreq
 * 
 * Mode: Device only. The application sets this bit to initiate an HNP request to
 * the connected USB host. The application can clear this bit by writing a 0 when
 * the Host Negotiation Success Status Change bit in the OTG Interrupt register
 * (GOTGINT.HstNegSucStsChng) is SET.The core clears this bit when the
 * HstNegSucStsChng bit iscleared.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description   
 * :-----------------------------------|:------|:---------------
 *  ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD | 0x0   | No HNP request
 *  ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END  | 0x1   | HNP request   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ
 * 
 * No HNP request
 */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ
 * 
 * HNP request
 */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_MSB        9
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_HNPREQ field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GOTGCTL_HNPREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Host Set HNP Enable - hstsethnpen
 * 
 * Mode: Host only. The application sets this bit when it has successfully enabled
 * HNP (using the SetFeature.SetHNPEnable command) on the connected device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                
 * :----------------------------------------|:------|:----------------------------
 *  ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD | 0x0   | Host Set HNP is not enabled
 *  ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END  | 0x1   | Host Set HNP is enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
 * 
 * Host Set HNP is not enabled
 */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
 * 
 * Host Set HNP is enabled
 */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_MSB        10
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Device HNP Enabled - devhnpen
 * 
 * Mode: Device only. The application sets this bit when it successfully receives a
 * SetFeature.SetHNPEnable command from the connected USB host.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                          
 * :-------------------------------------|:------|:--------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD | 0x0   | HNP is not enabled in the application
 *  ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END  | 0x1   | HNP Enabled                          
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN
 * 
 * HNP is not enabled in the application
 */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN
 * 
 * HNP Enabled
 */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_MSB        11
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_DEVHNPEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Connector ID Status - conidsts
 * 
 * Mode: Host and Device. Indicates the connector ID status on a connect event.This
 * bit is valid only for Host and Device mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                         
 * :-------------------------------------|:------|:-------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA | 0x0   | The DWC_otg core is in A-Device mode
 *  ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB | 0x1   | The otg core is in B-Device mode    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS
 * 
 * The DWC_otg core is in A-Device mode
 */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS
 * 
 * The otg core is in B-Device mode
 */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_MSB        16
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_RESET      0x1
/* Extracts the ALT_USB_GLOB_GOTGCTL_CONIDSTS field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Long Short Debounce Time - dbnctime
 * 
 * Mode: Host only. Indicates the debounce time of a detected connection.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG  | 0x0   | Long debounce time, used FOR physical         
 * :                                      |       | connections (100 ms + 2.5 s)                  
 *  ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT | 0x1   | Short debounce time, used FOR soft connections
 * :                                      |       | (2.5 s                                        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME
 * 
 * Long debounce time, used FOR physical connections (100 ms + 2.5 s)
 */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME
 * 
 * Short debounce time, used FOR soft connections (2.5 s
 */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_MSB        17
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_DBNCTIME field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : A-Session Valid - asesvld
 * 
 * Mode: Host only. Indicates the Host mode transceiver status. If you do not
 * enabled OTG features (such as SRP and HNP), the read reset value will be 1.The
 * vbus assigns the values internally for non-SRP or non-HNP configurations.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description           
 * :----------------------------------------|:------|:-----------------------
 *  ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID    | 0x0   | A-session is not valid
 *  ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID | 0x1   | A-session is valid    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD
 * 
 * A-session is not valid
 */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD
 * 
 * A-session is valid
 */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_MSB        18
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_ASESVLD field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GOTGCTL_ASESVLD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : B-Session Valid - bsesvld
 * 
 * Mode: Device only. Indicates the Device mode transceiver status. In OTG mode,
 * you can use this bit to determine IF the device is connected or disconnected. If
 * you do not enable OTG features (such as SRP and HNP), the read reset value will
 * be 1. The vbus assigns the values internally for non-SRP or non-HNP
 * configurations.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description           
 * :----------------------------------------|:------|:-----------------------
 *  ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID | 0x0   | B-session is not valid
 *  ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID    | 0x1   | B-session is valid    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD
 * 
 * B-session is not valid
 */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD
 * 
 * B-session is valid
 */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_MSB        19
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_BSESVLD field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GOTGCTL_BSESVLD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : OTG Version - otgver
 * 
 * Indicates the OTG revision. In OTG Version 1.3. the core supports Data line
 * pulsing and VBus pulsing for SRP. In OTG Version 2.0 the core supports only Data
 * line pulsing for SRP.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                              
 * :------------------------------------|:------|:------------------------------------------
 *  ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 | 0x0   | OTG Version 1.3. In this version the core
 * :                                    |       | supports Data line                       
 *  ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 | 0x1   | OTG Version 2.0. In this version the core
 * :                                    |       | supports only Data line pulsing for SRP  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER
 * 
 * OTG Version 1.3. In this version the core supports Data line
 */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER
 * 
 * OTG Version 2.0. In this version the core supports only Data line pulsing for
 * SRP
 */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_MSB        20
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_OTGVER field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GOTGCTL_OTGVER register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_SET(value) (((value) << 20) & 0x00100000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GOTGCTL.
 */
struct ALT_USB_GLOB_GOTGCTL_s
{
    const uint32_t  sesreqscs    :  1;  /* Session Request Success */
    uint32_t        sesreq       :  1;  /* Session Request */
    uint32_t        vbvalidoven  :  1;  /* VBUS Valid Override Enable */
    uint32_t        vbvalidovval :  1;  /* VBUS Valid Override Value */
    uint32_t        avalidoven   :  1;  /* A-Peripheral Session Valid Override Enable */
    uint32_t        avalidovval  :  1;  /* A-Peripheral Session Valid OverrideValue */
    uint32_t        bvalidoven   :  1;  /* B-Peripheral Session Valid Override Enable */
    uint32_t        bvalidovval  :  1;  /* B-Peripheral Session Valid OverrideValue */
    const uint32_t  hstnegscs    :  1;  /* Host Negotiation Success */
    uint32_t        hnpreq       :  1;  /* HNP Request */
    uint32_t        hstsethnpen  :  1;  /* Host Set HNP Enable */
    uint32_t        devhnpen     :  1;  /* Device HNP Enabled */
    uint32_t                     :  4;  /* *UNDEFINED* */
    const uint32_t  conidsts     :  1;  /* Connector ID Status */
    const uint32_t  dbnctime     :  1;  /* Long Short Debounce Time */
    const uint32_t  asesvld      :  1;  /* A-Session Valid */
    const uint32_t  bsesvld      :  1;  /* B-Session Valid */
    uint32_t        otgver       :  1;  /* OTG Version */
    uint32_t                     : 11;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GOTGCTL. */
typedef volatile struct ALT_USB_GLOB_GOTGCTL_s  ALT_USB_GLOB_GOTGCTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GOTGCTL register from the beginning of the component. */
#define ALT_USB_GLOB_GOTGCTL_OFST        0x0
/* The address of the ALT_USB_GLOB_GOTGCTL register. */
#define ALT_USB_GLOB_GOTGCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGCTL_OFST))

/*
 * Register : OTG Interrupt Register - gotgint
 * 
 * The application reads this register whenever there is an OTG interrupt and
 * clears the bits in this register to clear the OTG interrupt.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [1:0]   | ???    | 0x0   | *UNDEFINED*                           
 *  [2]     | R      | 0x0   | Session End Detected                  
 *  [7:3]   | ???    | 0x0   | *UNDEFINED*                           
 *  [8]     | R      | 0x0   | Session Request Success Status Change 
 *  [9]     | R      | 0x0   | Host Negotiation Success Status Change
 *  [16:10] | ???    | 0x0   | *UNDEFINED*                           
 *  [17]    | R      | 0x0   | Host Negotiation Detected             
 *  [18]    | R      | 0x0   | A-Device Timeout Change               
 *  [19]    | R      | 0x0   | Debounce Done                         
 *  [31:20] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Session End Detected - sesenddet
 * 
 * Mode:Host and Device.This bit can be set only by the core and the application
 * should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                 
 * :---------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT | 0x0   | Non Active State                            
 *  ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT   | 0x1   | Set when utmisrp_bvalid signal is deasserted
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET
 * 
 * Non Active State
 */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET
 * 
 * Set when utmisrp_bvalid signal is deasserted
 */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_MSB        2
/* The width in bits of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_SESENDDET field value from a register. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GOTGINT_SESENDDET register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Session Request Success Status Change - sesreqsucstschng
 * 
 * Mode: Host and Device. The core sets this bit on the success or failure of a
 * session request. The application must read the Session Request Success bit in
 * the OTG Control and Status register (GOTGCTL.SesReqScs) to check for success or
 * failure. This bit can be set only by the core and the application should write 1
 * to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description           
 * :----------------------------------------------|:------|:-----------------------
 *  ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT | 0x0   | No change             
 *  ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT   | 0x1   | Session Request Status
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
 * 
 * No change
 */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
 * 
 * Session Request Status
 */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_MSB        8
/* The width in bits of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG field value from a register. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Host Negotiation Success Status Change - hstnegsucstschng
 * 
 * Mode: Host and Device. The core sets this bit on the success or failure of a USB
 * host negotiation request. The application must read the Host Negotiation Success
 * bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check for
 * success or failure. This bit can be set only by the core and the application
 * should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                   
 * :----------------------------------------------|:------|:-------------------------------
 *  ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT | 0x0   | No Change                     
 *  ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT   | 0x1   | Host Negotiation Status Change
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
 * 
 * No Change
 */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
 * 
 * Host Negotiation Status Change
 */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_MSB        9
/* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG field value from a register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Host Negotiation Detected - hstnegdet
 * 
 * Mode:Host and Device. The core sets this bit when it detects a host negotiation
 * request on the USB. This bit can be set only by the core and the application
 * should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description              
 * :---------------------------------------|:------|:--------------------------
 *  ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT | 0x0   | No Change                
 *  ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT   | 0x1   | Host Negotiation Detected
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET
 * 
 * No Change
 */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET
 * 
 * Host Negotiation Detected
 */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_MSB        17
/* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGDET field value from a register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : A-Device Timeout Change - adevtoutchg
 * 
 * Mode:Host and Device. The core sets this bit to indicate that the A-device has
 * timed out WHILE waiting FOR the B-device to connect. This bit can be set only by
 * the core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description     
 * :-----------------------------------------|:------|:-----------------
 *  ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT | 0x0   | No Change       
 *  ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT   | 0x1   | A-Device Timeout
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
 * 
 * No Change
 */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
 * 
 * A-Device Timeout
 */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_MSB        18
/* The width in bits of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG field value from a register. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Debounce Done - dbncedone
 * 
 * Mode: Host only. The core sets this bit when the debounce is completed after the
 * device connect. The application can start driving USB reset after seeing this
 * interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET
 * in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap,
 * respectively). This bit can be set only by the core and the application should
 * write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description       
 * :---------------------------------------|:------|:-------------------
 *  ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT | 0x0   | No Change         
 *  ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT   | 0x1   | Debounce completed
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE
 * 
 * No Change
 */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE
 * 
 * Debounce completed
 */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_MSB        19
/* The width in bits of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_DBNCEDONE field value from a register. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET(value) (((value) << 19) & 0x00080000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GOTGINT.
 */
struct ALT_USB_GLOB_GOTGINT_s
{
    uint32_t                         :  2;  /* *UNDEFINED* */
    const uint32_t  sesenddet        :  1;  /* Session End Detected */
    uint32_t                         :  5;  /* *UNDEFINED* */
    const uint32_t  sesreqsucstschng :  1;  /* Session Request Success Status Change */
    const uint32_t  hstnegsucstschng :  1;  /* Host Negotiation Success Status Change */
    uint32_t                         :  7;  /* *UNDEFINED* */
    const uint32_t  hstnegdet        :  1;  /* Host Negotiation Detected */
    const uint32_t  adevtoutchg      :  1;  /* A-Device Timeout Change */
    const uint32_t  dbncedone        :  1;  /* Debounce Done */
    uint32_t                         : 12;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GOTGINT. */
typedef volatile struct ALT_USB_GLOB_GOTGINT_s  ALT_USB_GLOB_GOTGINT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GOTGINT register from the beginning of the component. */
#define ALT_USB_GLOB_GOTGINT_OFST        0x4
/* The address of the ALT_USB_GLOB_GOTGINT register. */
#define ALT_USB_GLOB_GOTGINT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGINT_OFST))

/*
 * Register : AHB Configuration Register - gahbcfg
 * 
 * This register can be used to configure the core after power-on or a change in
 * mode. This register mainly contains AHB system-related configuration parameters.
 * Do not change this register after the initial programming. The application must
 * program this register before starting any transactions on either the AHB or the
 * USB.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Global Interrupt Mask            
 *  [4:1]   | RW     | 0x0   | Burst Length Type                
 *  [5]     | RW     | 0x0   | DMA Enable                       
 *  [6]     | ???    | 0x0   | *UNDEFINED*                      
 *  [7]     | RW     | 0x0   | Non-Periodic TxFIFO Empty Level  
 *  [8]     | RW     | 0x0   | Periodic TxFIFO Empty Leve       
 *  [20:9]  | ???    | 0x0   | *UNDEFINED*                      
 *  [21]    | RW     | 0x0   | Remote Memory Support            
 *  [22]    | RW     | 0x0   | Notify All Dma Write Transactions
 *  [31:23] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Global Interrupt Mask - glblintrmsk
 * 
 * Mode: Host and device. The application uses this bit to mask or unmask the
 * interrupt line assertion to itself. Irrespective of this bits setting, the
 * interrupt status registers are updated by the core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                    
 * :-----------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK   | 0x0   | Mask the interrupt assertion to the application
 *  ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK | 0x1   | Unmask the interrupt assertion to the          
 * :                                         |       | application.                                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
 * 
 * Mask the interrupt assertion to the application
 */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
 * 
 * Unmask the interrupt assertion to the application.
 */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_MSB        0
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Burst Length Type - hbstlen
 * 
 * Mode:Host and device. This field is used in Internal DMA modes.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description       
 * :-----------------------------------------------|:------|:-------------------
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE   | 0x0   | 1 word or single  
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR     | 0x1   | 4 word or incr    
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8           | 0x2   | 8 word            
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4   | 0x3   | 16 word or incr4  
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32          | 0x4   | 32 word           
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8   | 0x5   | 64 word or incr8  
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128         | 0x6   | 128 word          
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 | 0x7   | 256 word or incr16
 *  ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX           | 0x8   | Others reserved   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 1 word or single
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 4 word or incr
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR      0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 8 word
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8            0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 16 word or incr4
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4    0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 32 word
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32           0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 64 word or incr8
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8    0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 128 word
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128          0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * 256 word or incr16
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16  0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
 * 
 * Others reserved
 */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX            0x8

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_MSB        4
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET_MSK    0x0000001e
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_CLR_MSK    0xffffffe1
/* The reset value of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_HBSTLEN field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_GET(value) (((value) & 0x0000001e) >> 1)
/* Produces a ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET(value) (((value) << 1) & 0x0000001e)

/*
 * Field : DMA Enable - dmaen
 * 
 * Mode:Host and device. Enables switching from DMA mode to slave mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD | 0x0   | Core operates in Slave mode
 *  ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD | 0x1   | Core operates in a DMA mode
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN
 * 
 * Core operates in Slave mode
 */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN
 * 
 * Core operates in a DMA mode
 */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_MSB        5
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_DMAEN field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GAHBCFG_DMAEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Non-Periodic TxFIFO Empty Level - nptxfemplvl
 * 
 * Mode:Host and device. This bit is used only in Slave mode. In host mode and with
 * Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO
 * Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is
 * triggered. With dedicated FIFO in device mode, this bit indicates when IN
 * endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. Host mode
 * and with Shared FIFO with device mode:
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                                     
 * :---------------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY | 0x0   | DIEPINTn.TxFEmp interrupt indicates that the IN 
 * :                                             |       | Endpoint TxFIFO is half empty or DIEPINTn.TxFEmp
 * :                                             |       | interrupt indicates that the IN Endpoint TxFIFO 
 * :                                             |       | is half empty                                   
 *  ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY     | 0x1   | GINTSTS.NPTxFEmp interrupt indicates that the   
 * :                                             |       | Non-Periodic TxFIFO is completely empty or      
 * :                                             |       | DIEPINTn.TxFEmp interrupt indicates that the IN 
 * :                                             |       | Endpoint TxFIFO is completely empty             
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
 * 
 * DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty or
 * DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty
 */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
 * 
 * GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely
 * empty or DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is
 * completely empty
 */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY        0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_MSB        7
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Periodic TxFIFO Empty Leve - ptxfemplvl
 * 
 * Mode:Host only. Indicates when the Periodic TxFIFO Empty Interrupt bit in the
 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in
 * Slave mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                                 
 * :--------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY | 0x0   | GINTSTS.PTxFEmp interrupt indicates that the
 * :                                            |       | Periodic TxFIFO is half empty               
 *  ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY     | 0x1   | GINTSTS.PTxFEmp interrupt indicates that the
 * :                                            |       | Periodic TxFIFO is completely empty         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
 * 
 * GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty
 */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
 * 
 * GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty
 */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_MSB        8
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Remote Memory Support - remmemsupp
 * 
 * This bit is programmed to enable/disable the functionality to wait for the
 * system DMA Done Signal for the DMA Write Transfers.
 * 
 * * The int_dma_req output signal is asserted when HSOTG DMA starts write transfer
 *   to the external memory. When the core is done with the Transfers it asserts
 *   int_dma_done signal to flag the completion of DMA writes from HSOTG. The core
 *   then waits for sys_dma_done signal from the system to proceed further and
 *   complete the Data Transfer corresponding to a particular Channel/Endpoint.
 * 
 * * The int_dma_req and int_dma_done signals are not asserted and the core
 *   proceeds with the assertion of the XferComp interrupt as soon as wait for the
 *   system DMA Done Signal for the DMA Write Transfers the DMA write transfer is
 *   done at the HSOTG Core Boundary and it doesn't wait for the sys_dma_done
 *   signal to complete the DATA
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD | 0x0   | Disable wait for system DMA Done Signal       
 *  ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END  | 0x1   | Enable wait for the system DMA Done Signal for
 * :                                       |       | the DMA Write Transfers                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
 * 
 * Disable wait for system DMA Done Signal
 */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
 * 
 * Enable wait for the system DMA Done Signal for the DMA Write Transfers
 */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_MSB        21
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Notify All Dma Write Transactions - notialldmawrit
 * 
 * This bit is programmed to enable the System DMA Done functionality for all the
 * DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid
 * only when GAHBCFG.RemMemSupp is set to 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                                     
 * :------------------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS  | 0x1   | HSOTG core asserts int_dma_req for all the DMA  
 * :                                                |       | write transactions on the AHB interface along   
 * :                                                |       | with int_dma_done, chep_last_transact and       
 * :                                                |       | chep_number signal informations. The core waits 
 * :                                                |       | for sys_dma_done signal for all the DMA write   
 * :                                                |       | transactions in order to complete the transfer  
 * :                                                |       | of a particular Channel/Endpoint                
 *  ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS | 0x0   | HSOTG core asserts int_dma_req signal only for  
 * :                                                |       | the last transaction of DMA write transfer      
 * :                                                |       | corresponding to a particular Channel/Endpoint. 
 * :                                                |       | Similarly, the core waits for sys_dma_done      
 * :                                                |       | signal only for that transaction of DMA write to
 * :                                                |       | complete the transfer of a particular           
 * :                                                |       | Channel/Endpoint                                
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
 * 
 * HSOTG core asserts int_dma_req for all the DMA write transactions on the AHB
 * interface along with int_dma_done, chep_last_transact and chep_number signal
 * informations. The core waits for sys_dma_done signal for all the DMA write
 * transactions in order to complete the transfer of a particular Channel/Endpoint
 */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS  0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
 * 
 * HSOTG core asserts int_dma_req signal only for the last transaction of DMA write
 * transfer corresponding to a particular Channel/Endpoint. Similarly, the core
 * waits for sys_dma_done signal only for that transaction of DMA write to complete
 * the transfer of a particular Channel/Endpoint
 */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS 0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_MSB        22
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET(value) (((value) << 22) & 0x00400000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GAHBCFG.
 */
struct ALT_USB_GLOB_GAHBCFG_s
{
    uint32_t  glblintrmsk    :  1;  /* Global Interrupt Mask */
    uint32_t  hbstlen        :  4;  /* Burst Length Type */
    uint32_t  dmaen          :  1;  /* DMA Enable */
    uint32_t                 :  1;  /* *UNDEFINED* */
    uint32_t  nptxfemplvl    :  1;  /* Non-Periodic TxFIFO Empty Level */
    uint32_t  ptxfemplvl     :  1;  /* Periodic TxFIFO Empty Leve */
    uint32_t                 : 12;  /* *UNDEFINED* */
    uint32_t  remmemsupp     :  1;  /* Remote Memory Support */
    uint32_t  notialldmawrit :  1;  /* Notify All Dma Write Transactions */
    uint32_t                 :  9;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GAHBCFG. */
typedef volatile struct ALT_USB_GLOB_GAHBCFG_s  ALT_USB_GLOB_GAHBCFG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GAHBCFG register from the beginning of the component. */
#define ALT_USB_GLOB_GAHBCFG_OFST        0x8
/* The address of the ALT_USB_GLOB_GAHBCFG register. */
#define ALT_USB_GLOB_GAHBCFG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GAHBCFG_OFST))

/*
 * Register : USB Configuration Registe - gusbcfg
 * 
 * This register can be used to configure the core after power-on or a changing to
 * Host mode or Device mode. It contains USB and USB-PHY related configuration
 * parameters. The application must program this register before starting any
 * transactions on either the AHB or the USB. Do not make changes to this register
 * after the initial programming.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                       
 * :--------|:-------|:------|:-----------------------------------
 *  [2:0]   | RW     | 0x0   | HS FS Timeout Calibration         
 *  [3]     | R      | 0x0   | PHY Interfac                      
 *  [4]     | R      | 0x1   | ULPI Select                       
 *  [5]     | R      | 0x0   | Full-Speed Serial Interface Select
 *  [6]     | R      | 0x0   | USB 2.0 High-Speed PHY            
 *  [7]     | RW     | 0x0   | ULPI DDR Select                   
 *  [8]     | RW     | 0x0   | SRP-Capable                       
 *  [9]     | RW     | 0x0   | HNP-Capable                       
 *  [13:10] | RW     | 0x5   | USB Turnaround Time               
 *  [17:14] | ???    | 0x0   | *UNDEFINED*                       
 *  [18]    | RW     | 0x0   | ULPI Auto Resume                  
 *  [19]    | RW     | 0x0   | ULPI Clock SuspendM               
 *  [20]    | RW     | 0x0   | ULPI External VBUS Drive          
 *  [21]    | RW     | 0x0   | ULPI External VBUS Indicato       
 *  [22]    | RW     | 0x0   | TermSel DLine Pulsing Selection   
 *  [23]    | RW     | 0x0   | Indicator Complement              
 *  [24]    | RW     | 0x0   | Indicator Pass Throug             
 *  [25]    | RW     | 0x0   | ULPI Interface Protect Disable    
 *  [27:26] | ???    | 0x0   | *UNDEFINED*                       
 *  [28]    | RW     | 0x0   | Tx End Delay                      
 *  [29]    | RW     | 0x0   | Force Host Mode.                  
 *  [30]    | RW     | 0x0   | Force Device Mode                 
 *  [31]    | W      | 0x0   | Corrupt Tx packet                 
 * 
 */
/*
 * Field : HS FS Timeout Calibration - toutcal
 * 
 * Mode:Host and Device. The number of PHY clocks that the application programs in
 * this field is added to the high-speed/full-speed interpacket timeout duration in
 * the core to account for any additional delays introduced by the PHY. This can be
 * required, because the delay introduced by the PHY in generating the linestate
 * condition can vary from one PHY to another. The USB standard timeout value for
 * high-speed operation is 736 to 816 (inclusive) bit times. The USB standard
 * timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
 * application must program this field based on the speed of enumeration. The
 * number of bit times added per PHY clock are: High-speed operation:
 * 
 * * One 30-MHz PHY clock = 16 bit times
 * 
 * * One 60-MHz PHY clock = 8 bit times
 * 
 * Full-speed operation:
 * 
 * * One 30-MHz PHY clock = 0.4 bit times
 * 
 * * One 60-MHz PHY clock = 0.2 bit times
 * 
 * * One 48-MHz PHY clock = 0.25 bit times
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_MSB        2
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_WIDTH      3
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET_MSK    0x00000007
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_CLR_MSK    0xfffffff8
/* The reset value of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_TOUTCAL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_GET(value) (((value) & 0x00000007) >> 0)
/* Produces a ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET(value) (((value) << 0) & 0x00000007)

/*
 * Field : PHY Interfac - phyif
 * 
 * Mode:Host and Device. This application uses a ULPI interface only. Hence only
 * 8-bit setting is relevant. This setting should not matter since UTMI is not
 * enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description  
 * :-----------------------------------|:------|:--------------
 *  ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 | 0x0   | PHY 8bit Mode
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYIF
 * 
 * PHY 8bit Mode
 */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_MSB        3
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_PHYIF field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GUSBCFG_PHYIF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : ULPI Select - ulpi_utmi_sel
 * 
 * Mode:Host and Device. The application uses ULPI Only in 8bit mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI | 0x0   | ULPI PHY   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL
 * 
 * ULPI PHY
 */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_MSB        4
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_RESET      0x1
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Full-Speed Serial Interface Select - fsintf
 * 
 * Mode:Host and Device. The application can Set this bit to select between the 3-
 * and 6-pin interfaces, and access is Read and Write.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                     
 * :-------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN | 0x0   | 6-pin unidirectional full-speed serial interface
 *  ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN | 0x1   | 3-pin bidirectional full-speed serial interface 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF
 * 
 * 6-pin unidirectional full-speed serial interface
 */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF
 * 
 * 3-pin bidirectional full-speed serial interface
 */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_MSB        5
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_FSINTF field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GUSBCFG_FSINTF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : USB 2.0 High-Speed PHY - physel
 * 
 * Mode:Host and Device. The application uses USB 2.0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description            
 * :------------------------------------|:------|:------------------------
 *  ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 | 0x0   | USB 2.0 high-speed ULPI
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYSEL
 * 
 * USB 2.0 high-speed ULPI
 */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_MSB        6
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_PHYSEL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GUSBCFG_PHYSEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : ULPI DDR Select - ddrsel
 * 
 * Mode:Host and Device. The application uses this bit to select a Single Data Rate
 * (SDR) or Double Data Rate (DDR) or ULPI interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                                     
 * :----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR | 0x0   | Single Data Rate ULPI Interfacewith 8-bit-wide  
 * :                                  |       | data bus                                        
 *  ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR | 0x1   | Double Data Rate ULPI Interface, with 4-bit-wide
 * :                                  |       | data bus                                        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL
 * 
 * Single Data Rate ULPI Interfacewith 8-bit-wide data bus
 */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL
 * 
 * Double Data Rate ULPI Interface, with 4-bit-wide data bus
 */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_MSB        7
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_DDRSEL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GUSBCFG_DDRSEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : SRP-Capable - srpcap
 * 
 * Mode:Host and Device. The application uses this bit to control the otg core SRP
 * capabilities. If the core operates as a non-SRP-capable B-device, it cannot
 * request the connected A-device (host) to activate VBUS and start a session. This
 * bit is writable only If an SRP mode was specified for Mode of Operation in
 * coreConsultant (parameter OTG_MODE). Otherwise, reads Return 0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                  
 * :-----------------------------------|:------|:------------------------------
 *  ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD | 0x0   | SRP capability is not enabled
 *  ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END  | 0x1   | SRP capability is enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP
 * 
 * SRP capability is not enabled
 */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP
 * 
 * SRP capability is enabled
 */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_MSB        8
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_SRPCAP field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GUSBCFG_SRPCAP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : HNP-Capable - hnpcap
 * 
 * Mode:Host and Device. The application uses this bit to control the otg core's
 * HNP capabilities.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                   
 * :-----------------------------------|:------|:-------------------------------
 *  ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD | 0x0   | HNP capability is not enabled.
 *  ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END  | 0x1   | HNP capability is enabled     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP
 * 
 * HNP capability is not enabled.
 */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP
 * 
 * HNP capability is enabled
 */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_MSB        9
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_HNPCAP field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GUSBCFG_HNPCAP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : USB Turnaround Time - usbtrdtim
 * 
 * Mode: Device only. Sets the turnaround time in PHY clocks. Specifies the
 * response time for a MAC request to the Packet FIFO Controller (PFC) to fetch
 * data from the DFIFO (SPRAM).
 * 
 * The value is calculated for the minimum AHB frequency of 30 MHz. USB turnaround
 * time is critical for certification where long cables and 5-Hubs are used, so If
 * you need the AHB to run at less than 30 MHz, and If USB turnaround time is not
 * critical, these bits can be programmed to a larger value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                  
 * :------------------------------------------|:------|:------------------------------
 *  ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME | 0x9   | MAC interface is 8-bit UTMI+.
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_USBTRDTIM
 * 
 * MAC interface is 8-bit UTMI+.
 */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME   0x9

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_MSB        13
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET_MSK    0x00003c00
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_CLR_MSK    0xffffc3ff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_RESET      0x5
/* Extracts the ALT_USB_GLOB_GUSBCFG_USBTRDTIM field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_GET(value) (((value) & 0x00003c00) >> 10)
/* Produces a ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET(value) (((value) << 10) & 0x00003c00)

/*
 * Field : ULPI Auto Resume - ulpiautores
 * 
 * Mode:Host and Device. This bit sets the AutoResume bit in the Interface Control
 * register on the ULPI PHY.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD | 0x0   | PHY does not use AutoResume feature
 *  ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END  | 0x1   | PHY uses AutoResume feature        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
 * 
 * PHY does not use AutoResume feature
 */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
 * 
 * PHY uses AutoResume feature
 */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_MSB        18
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : ULPI Clock SuspendM - ulpiclksusm
 * 
 * Mode:Host and Device. This bit sets the ClockSuspendM bit in the Interface
 * Control register on the ULPI PHY. This bit applies only in serial or carkit
 * modes.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                                  
 * :---------------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK    | 0x0   | PHY powers down internal clock during suspend
 *  ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK | 0x1   | PHY does not power down internal clock       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
 * 
 * PHY powers down internal clock during suspend
 */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK       0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
 * 
 * PHY does not power down internal clock
 */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_MSB        19
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : ULPI External VBUS Drive - ulpiextvbusdrv
 * 
 * Mode:Host only. This bit selects between internal or external supply to drive 5V
 * on VBUS, in ULPI PHY.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                               
 * :---------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN | 0x0   | PHY drives VBUS using internal charge pump
 *  ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN | 0x1   | PHY drives VBUS using external supply     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
 * 
 * PHY drives VBUS using internal charge pump
 */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
 * 
 * PHY drives VBUS using external supply
 */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_MSB        20
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : ULPI External VBUS Indicato - ulpiextvbusindicator
 * 
 * Mode:Host only. This bit indicates to the ULPI PHY to use an external VBUS
 * overcurrent indicator.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                            
 * :---------------------------------------------------|:------|:----------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN | 0x0   | PHY uses internal VBUS valid comparator
 *  ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN | 0x1   | PHY uses external VBUS valid comparator
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
 * 
 * PHY uses internal VBUS valid comparator
 */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
 * 
 * PHY uses external VBUS valid comparator
 */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_MSB        21
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TermSel DLine Pulsing Selection - termseldlpulse
 * 
 * Mode:Device only. This bit selects utmi_termselect to drive data line pulse
 * during SRP.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                         
 * :----------------------------------------------|:------|:-------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID | 0x0   | Data line pulsing using utmi_txvalid
 *  ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL | 0x1   | Data line pulsing using utmi_termsel
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
 * 
 * Data line pulsing using utmi_txvalid
 */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
 * 
 * Data line pulsing using utmi_termsel
 */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_MSB        22
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : Indicator Complement - complement
 * 
 * Mode:Host only. Controls the PHY to invert the ExternalVbusIndicator
 * inputsignal, generating the ComplementOutput. Please refer to the ULPI Spec for
 * more detail.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                                     
 * :--------------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT | 0x0   | PHY does not invert ExternalVbusIndicator signal
 *  ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT    | 0x1   | PHY does invert ExternalVbusIndicator signal    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT
 * 
 * PHY does not invert ExternalVbusIndicator signal
 */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT
 * 
 * PHY does invert ExternalVbusIndicator signal
 */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_MSB        23
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_COMPLEMENT field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Indicator Pass Throug - indicator
 * 
 * Mode:Host only. Controls wether the Complement Output is qualified with the
 * Internal Vbus Valid comparator before being used in the Vbus State in the RX
 * CMD.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                                    
 * :----------------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED    | 0x0   | Complement Output signal is qualified with the 
 * :                                              |       | Internal VbusValid comparator                  
 *  ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED | 0x1   | Complement Output signal is not qualified  with
 * :                                              |       | the Internal VbusValid comparator              
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR
 * 
 * Complement Output signal is qualified with the Internal VbusValid comparator
 */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR
 * 
 * Complement Output signal is not qualified  with the Internal VbusValid
 * comparator
 */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_MSB        24
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_INDICATOR field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GUSBCFG_INDICATOR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : ULPI Interface Protect Disable - ulpi
 * 
 * Mode:Host only. Controls circuitry built into the PHY for protecting the ULPI
 * interface when the link tri-states STP and data. Any pull-ups or pull-downs
 * employed by this feature can be disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                           
 * :---------------------------------|:------|:---------------------------------------
 *  ALT_USB_GLOB_GUSBCFG_ULPI_E_END  | 0x0   | Enables the interface protect circuit 
 *  ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD | 0x1   | Disables the interface protect circuit
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI
 * 
 * Enables the interface protect circuit
 */
#define ALT_USB_GLOB_GUSBCFG_ULPI_E_END     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI
 * 
 * Disables the interface protect circuit
 */
#define ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_MSB        25
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPI register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Tx End Delay - txenddelay
 * 
 * Mode: Device only. Set to non UTMI+.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description
 * :---------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD | 0x0   | Normal Mode
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TXENDDELAY
 * 
 * Normal Mode
 */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_MSB        28
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_TXENDDELAY field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Force Host Mode. - forcehstmode
 * 
 * Mode:Host and device. Writing a 1 to this bit forces the core to host mode After
 * setting the force bit, the application must wait at least 25 ms before the
 * change to take effect. When the simulation is in scale down mode, waiting for
 * 500 micro-sec is sufficient.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description    
 * :----------------------------------------|:------|:----------------
 *  ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD | 0x0   | Normal Mode    
 *  ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END  | 0x1   | Force Host Mode
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
 * 
 * Normal Mode
 */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
 * 
 * Force Host Mode
 */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_MSB        29
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Force Device Mode - forcedevmode
 * 
 * Mode:Host and device. Writing a 1 to this bit forces the core to device mode.
 * After setting the force bit, the application must wait at least 25 ms before the
 * change to take effect. When the simulation is in scale down mode, waiting for
 * 500 micro-sec is sufficient.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description      
 * :----------------------------------------|:------|:------------------
 *  ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD | 0x0   | Normal Mode      
 *  ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END  | 0x1   | Force Device Mode
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
 * 
 * Normal Mode
 */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
 * 
 * Force Device Mode
 */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_MSB        30
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Corrupt Tx packet - corrupttxpkt
 * 
 * Mode: Host and device. This bit is for debug purposes only. Never Set this bit
 * to 1. The application should always write 0 to this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG | 0x0   | Normal Mode
 *  ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG   | 0x1   | Debug Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
 * 
 * Normal Mode
 */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
 * 
 * Debug Mode
 */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_MSB        31
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GUSBCFG.
 */
struct ALT_USB_GLOB_GUSBCFG_s
{
    uint32_t        toutcal              :  3;  /* HS FS Timeout Calibration */
    const uint32_t  phyif                :  1;  /* PHY Interfac */
    const uint32_t  ulpi_utmi_sel        :  1;  /* ULPI Select */
    const uint32_t  fsintf               :  1;  /* Full-Speed Serial Interface Select */
    const uint32_t  physel               :  1;  /* USB 2.0 High-Speed PHY */
    uint32_t        ddrsel               :  1;  /* ULPI DDR Select */
    uint32_t        srpcap               :  1;  /* SRP-Capable */
    uint32_t        hnpcap               :  1;  /* HNP-Capable */
    uint32_t        usbtrdtim            :  4;  /* USB Turnaround Time */
    uint32_t                             :  4;  /* *UNDEFINED* */
    uint32_t        ulpiautores          :  1;  /* ULPI Auto Resume */
    uint32_t        ulpiclksusm          :  1;  /* ULPI Clock SuspendM */
    uint32_t        ulpiextvbusdrv       :  1;  /* ULPI External VBUS Drive */
    uint32_t        ulpiextvbusindicator :  1;  /* ULPI External VBUS Indicato */
    uint32_t        termseldlpulse       :  1;  /* TermSel DLine Pulsing Selection */
    uint32_t        complement           :  1;  /* Indicator Complement */
    uint32_t        indicator            :  1;  /* Indicator Pass Throug */
    uint32_t        ulpi                 :  1;  /* ULPI Interface Protect Disable */
    uint32_t                             :  2;  /* *UNDEFINED* */
    uint32_t        txenddelay           :  1;  /* Tx End Delay */
    uint32_t        forcehstmode         :  1;  /* Force Host Mode. */
    uint32_t        forcedevmode         :  1;  /* Force Device Mode */
    uint32_t        corrupttxpkt         :  1;  /* Corrupt Tx packet */
};

/* The typedef declaration for register ALT_USB_GLOB_GUSBCFG. */
typedef volatile struct ALT_USB_GLOB_GUSBCFG_s  ALT_USB_GLOB_GUSBCFG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GUSBCFG register from the beginning of the component. */
#define ALT_USB_GLOB_GUSBCFG_OFST        0xc
/* The address of the ALT_USB_GLOB_GUSBCFG register. */
#define ALT_USB_GLOB_GUSBCFG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUSBCFG_OFST))

/*
 * Register : Reset Register - grstctl
 * 
 * The application uses this register to reset various hardware features inside the
 * core
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description             
 * :--------|:-------|:------|:-------------------------
 *  [0]     | R      | 0x0   | Core Soft Reset         
 *  [1]     | ???    | 0x0   | *UNDEFINED*             
 *  [2]     | R      | 0x0   | Host Frame Counter Reset
 *  [3]     | ???    | 0x0   | *UNDEFINED*             
 *  [4]     | R      | 0x0   | RxFIFO Flush            
 *  [5]     | R      | 0x0   | TxFIFO Flush            
 *  [10:6]  | RW     | 0x0   | TxFIFO Number           
 *  [29:11] | ???    | 0x0   | *UNDEFINED*             
 *  [30]    | R      | 0x0   | DMA Request Signal      
 *  [31]    | R      | 0x1   | AHB Master Idle         
 * 
 */
/*
 * Field : Core Soft Reset - csftrst
 * 
 * Mode:Host and Device. Resets the hclk and phy_clock domains as follows:Clears
 * the interrupts and all the CSR registers except the following register bits:
 * 
 * * PCGCCTL.RstPdwnModule
 * 
 * * PCGCCTL.GateHclk
 * 
 * * PCGCCTL.PwrClmp
 * 
 * * PCGCCTL.StopPPhyLPwrClkSelclk
 * 
 * * GUSBCFG.PhyLPwrClkSel
 * 
 * * GUSBCFG.DDRSel
 * 
 * * GUSBCFG.PHYSel
 * 
 * * GUSBCFG.FSIntf
 * 
 * * GUSBCFG.ULPI_UTMI_Sel
 * 
 * * GUSBCFG.PHYIf
 * 
 * * HCFG.FSLSPclkSel
 * 
 * * DCFG.DevSpd
 * 
 * * GGPIO
 * 
 * * GPWRDN
 * 
 * * GADPCTL
 * 
 * All module state machines (except the AHB Slave Unit) are reset to the IDLE
 * state, and all the transmit FIFOs and the receive FIFO are flushed. Any
 * transactions on the AHB Master are terminated as soonas possible, after
 * gracefully completing the last data phase of an AHB transfer. Any transactions
 * on the USB are terminated immediately. When Hibernation or ADP feature is
 * enabled, the PMU module is not reset by the Core Soft Reset.The application can
 * write to this bit any time it wants to reset the core. This is a self-clearing
 * bit and the core clears this bit after all the necessary logic is reset in the
 * core, which can take several clocks, depending on the current state of the core.
 * Once this bit is cleared software must wait at least 3 PHY clocks before doing
 * any access to the PHY domain (synchronization delay). Software must also must
 * check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any
 * operation.Typically software reset is used during software development and also
 * when you dynamically change the PHY selection bits in the USB configuration
 * registers listed above. When you change the PHY, the corresponding clock for the
 * PHY is selected and used in the PHY domain. Once a new clock is selected, the
 * PHY domain has to be reset for proper operation.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                      
 * :--------------------------------------|:------|:----------------------------------
 *  ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT | 0x0   | No reset                         
 *  ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT    | 0x1   | Resets hclk and phy_clock domains
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST
 * 
 * No reset
 */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST
 * 
 * Resets hclk and phy_clock domains
 */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_MSB        0
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_CSFTRST field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GRSTCTL_CSFTRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Host Frame Counter Reset - frmcntrrst
 * 
 * Mode:Host only. The application writes this bit to reset the (micro)frame number
 * counter inside the core. When the (micro)frame counter is reset, the subsequent
 * SOF sent out by the core has a (micro)frame number of 0. When application writes
 * 1 to the bit, it might not be able to read back the value as it will get cleared
 * by the core in a few clock cycles.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description             
 * :-----------------------------------------|:------|:-------------------------
 *  ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT | 0x0   | No reset                
 *  ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT    | 0x1   | Host Frame Counter Reset
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
 * 
 * No reset
 */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
 * 
 * Host Frame Counter Reset
 */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_MSB        2
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : RxFIFO Flush - rxfflsh
 * 
 * Mode:Host and Device. The application can flush the entire RxFIFO using this
 * bit, but must first ensure that the core is not in the middle of a transaction.
 * The application must only write to this bit after checking that the core is
 * neither reading from the RxFIFO nor writing to the RxFIFO. The application must
 * wait until the bit is cleared before performing any other operations. This bit
 * requires 8 clocks (slowest of PHY or AHB clock) to clear.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description               
 * :-------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT | 0x0   | no flush the entire RxFIFO
 *  ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT   | 0x1   | flush the entire RxFIFO   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH
 * 
 * no flush the entire RxFIFO
 */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH
 * 
 * flush the entire RxFIFO
 */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_MSB        4
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_RXFFLSH field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : TxFIFO Flush - txfflsh
 * 
 * Mode:Host and Device. This bit selectively flushes a single or all transmit
 * FIFOs, but cannot do so If the core is in the midst of a transaction. The
 * application must write this bit only after checking that the core is neither
 * writing to the TxFIFO nor reading from the TxFIFO. Verify using these registers:
 * ReadNAK Effective Interrupt ensures the core is notreading from the FIFO
 * WriteGRSTCTL.AHBIdle ensures the core is not writinganything to the FIFO.
 * Flushing is normally recommended when FIFOs are reconfigured or when switching
 * between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also
 * recommended during device endpoint disable. The application must wait until the
 * core clears this bit before performing any operations. This bit takes eight
 * clocks to clear, using the slower clock of phy_clk or hclk.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                 
 * :-------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT | 0x0   | No Flush                                    
 *  ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT   | 0x1   | selectively flushes a single or all transmit
 * :                                     |       | FIFOs                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH
 * 
 * No Flush
 */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH
 * 
 * selectively flushes a single or all transmit FIFOs
 */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_MSB        5
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_TXFFLSH field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Mode:Host and Device. This is the FIFO number that must be flushed using the
 * TxFIFO Flush bit. This field must not be changed until the core clears the
 * TxFIFO Flush bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0  | 0x0   | - Non-periodic TxFIFO flush in Host mode - Non- 
 * :                                    |       | periodic TxFIFO flush in device mode when in    
 * :                                    |       | shared FIFO operation                           
 *  ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1  | 0x1   | - Periodic TxFIFO flush in Host mode - Periodic 
 * :                                    |       | TxFIFO 1 flush in Device mode when in sharedFIFO
 * :                                    |       | operation                                       
 *  ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2  | 0x2   | - Periodic TxFIFO 2 flush in Device mode when in
 * :                                    |       | sharedFIFO operation- TXFIFO 2 flush in device  
 * :                                    |       | mode when in dedicated FIFO mode                
 *  ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 | 0xf   | - Periodic TxFIFO 15 flush in Device mode when  
 * :                                    |       | in shared FIFO operation - TXFIFO 15 flush in   
 * :                                    |       | device mode when in dedicated FIFO mode         
 *  ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 | 0x10  | Flush all the transmit FIFOs in device or host  
 * :                                    |       | mode.                                           
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
 * 
 * * Non-periodic TxFIFO flush in Host mode
 * 
 * * Non-periodic TxFIFO flush in device mode when in shared FIFO operation
 */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
 * 
 * * Periodic TxFIFO flush in Host mode
 * 
 * * Periodic TxFIFO 1 flush in Device mode when in sharedFIFO operation
 */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1  0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
 * 
 * * Periodic TxFIFO 2 flush in Device mode when in sharedFIFO operation- TXFIFO 2
 *   flush in device mode when in dedicated FIFO mode
 */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2  0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
 * 
 * * Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation
 * 
 * * TXFIFO 15 flush in device mode when in dedicated FIFO mode
 */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 0xf
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
 * 
 * Flush all the transmit FIFOs in device or host mode.
 */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 0x10

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_MSB        10
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_WIDTH      5
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET_MSK    0x000007c0
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_CLR_MSK    0xfffff83f
/* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_TXFNUM field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_USB_GLOB_GRSTCTL_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET(value) (((value) << 6) & 0x000007c0)

/*
 * Field : DMA Request Signal - dmareq
 * 
 * Mode:Host and Device. Indicates that the DMA request is in progress. Used for
 * debug.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description               
 * :------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT | 0x0   | No DMA request            
 *  ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT   | 0x1   | DMA request is in progress
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ
 * 
 * No DMA request
 */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ
 * 
 * DMA request is in progress
 */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_MSB        30
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_DMAREQ field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GRSTCTL_DMAREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : AHB Master Idle - ahbidle
 * 
 * Mode:Host and Device. Indicates that the AHB Master State Machine is in the IDLE
 * condition.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description    
 * :-------------------------------------|:------|:----------------
 *  ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT | 0x0   | Not Idle       
 *  ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT   | 0x1   | AHB Master Idle
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE
 * 
 * Not Idle
 */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE
 * 
 * AHB Master Idle
 */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_MSB        31
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_RESET      0x1
/* Extracts the ALT_USB_GLOB_GRSTCTL_AHBIDLE field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GRSTCTL.
 */
struct ALT_USB_GLOB_GRSTCTL_s
{
    const uint32_t  csftrst    :  1;  /* Core Soft Reset */
    uint32_t                   :  1;  /* *UNDEFINED* */
    const uint32_t  frmcntrrst :  1;  /* Host Frame Counter Reset */
    uint32_t                   :  1;  /* *UNDEFINED* */
    const uint32_t  rxfflsh    :  1;  /* RxFIFO Flush */
    const uint32_t  txfflsh    :  1;  /* TxFIFO Flush */
    uint32_t        txfnum     :  5;  /* TxFIFO Number */
    uint32_t                   : 19;  /* *UNDEFINED* */
    const uint32_t  dmareq     :  1;  /* DMA Request Signal */
    const uint32_t  ahbidle    :  1;  /* AHB Master Idle */
};

/* The typedef declaration for register ALT_USB_GLOB_GRSTCTL. */
typedef volatile struct ALT_USB_GLOB_GRSTCTL_s  ALT_USB_GLOB_GRSTCTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GRSTCTL register from the beginning of the component. */
#define ALT_USB_GLOB_GRSTCTL_OFST        0x10
/* The address of the ALT_USB_GLOB_GRSTCTL register. */
#define ALT_USB_GLOB_GRSTCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRSTCTL_OFST))

/*
 * Register : Interrupt Register - gintsts
 * 
 * This register interrupts the application for system-level events in the current
 * mode (Device mode or Host mode). Some of the bits in this register are valid
 * only in Host mode, while others are valid in Device mode only. This register
 * also indicates the current mode. To clear the interrupt status bits of type
 * R_SS_WC, the application must write 1 into the bit. The FIFO status interrupts
 * are read only; once software reads from or writes to the FIFO while servicing
 * these interrupts, FIFO interrupt conditions are cleared automatically. The
 * application must clear the GINTSTS register at initialization before unmasking
 * the interrupt bit to avoid any interrupts generated prior to initialization.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                   
 * :--------|:-------|:------|:-----------------------------------------------
 *  [0]     | R      | 0x0   | Current Mode of Operation                     
 *  [1]     | R      | 0x0   | Mode Mismatch Interrupt                       
 *  [2]     | R      | 0x0   | OTG Interrupt                                 
 *  [3]     | R      | 0x0   | Start of Frame                                
 *  [4]     | R      | 0x0   | RxFIFO Non-Empty                              
 *  [5]     | ???    | 0x0   | *UNDEFINED*                                   
 *  [6]     | R      | 0x0   | Global IN Non-periodic NAK Effective          
 *  [7]     | R      | 0x0   | Global OUT NAK Effective                      
 *  [9:8]   | ???    | 0x0   | *UNDEFINED*                                   
 *  [10]    | R      | 0x0   | Early Suspend                                 
 *  [11]    | R      | 0x0   | USB Suspend                                   
 *  [12]    | R      | 0x0   | USB Reset                                     
 *  [13]    | R      | 0x0   | Enumeration Done                              
 *  [14]    | R      | 0x0   | Isochronous OUT Packet Dropped Interrupt      
 *  [16:15] | ???    | 0x0   | *UNDEFINED*                                   
 *  [17]    | R      | 0x0   | Endpoint Mismatch Interrupt                   
 *  [18]    | R      | 0x0   | IN Endpoints Interrupt                        
 *  [19]    | R      | 0x0   | OUT Endpoints Interrupt                       
 *  [20]    | R      | 0x0   | Incomplete Isochronous IN Transfer            
 *  [21]    | R      | 0x0   | Incomplete Periodic Transfer                  
 *  [22]    | R      | 0x0   | Data Fetch Suspended                          
 *  [23]    | R      | 0x0   | Reset detected Interrupt                      
 *  [24]    | R      | 0x0   | Host Port Interrupt                           
 *  [25]    | R      | 0x0   | Host Channels Interrupt                       
 *  [26]    | R      | 0x1   | Periodic TxFIFO Empty                         
 *  [27]    | ???    | 0x0   | *UNDEFINED*                                   
 *  [28]    | R      | 0x1   | Connector ID Status Change                    
 *  [29]    | R      | 0x0   | Disconnect Detected Interrupt                 
 *  [30]    | R      | 0x0   | Session Request New Session Detected Interrupt
 *  [31]    | R      | 0x0   | Resume Remote Wakeup Detected Interrupt       
 * 
 */
/*
 * Field : Current Mode of Operation - curmod
 * 
 * Mode: Host and Device. Indicates the current mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE | 0x0   | Device mode
 *  ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST   | 0x1   | Host mode  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD
 * 
 * Device mode
 */
#define ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD
 * 
 * Host mode
 */
#define ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_MSB        0
/* The width in bits of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_CURMOD field value from a register. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GINTSTS_CURMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Mode Mismatch Interrupt - modemis
 * 
 * Mode: Host and Device. The core sets this bit when the application is trying to
 * access:
 * 
 * * A Host mode register, when the core is operating in Device mode. -A Device
 *   mode register, when the core is operating in Host mode.
 * 
 * The register access is completed on the AHB with an OKAYresponse, but is ignored
 * by the core internally and does not affect the operation of the core. This bit
 * can be set only by the core and the application should write 1 to clearit
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description               
 * :------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT | 0x0   | No Mode Mismatch Interrupt
 *  ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT   | 0x1   | Mode Mismatch Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS
 * 
 * No Mode Mismatch Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS
 * 
 * Mode Mismatch Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_MSB        1
/* The width in bits of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_MODMIS field value from a register. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GINTSTS_MODMIS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : OTG Interrupt - otgint
 * 
 * Mode: Host and Device. The core sets this bit to indicate an OTG protocol event.
 * The application must read the OTG Interrupt Status (GOTGINT) register to
 * determine the exact event that caused this interrupt. The application must clear
 * the appropriate status bit in the GOTGINT register to clear this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description  
 * :------------------------------------|:------|:--------------
 *  ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT | 0x0   | No Interrupt 
 *  ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT   | 0x1   | OTG Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT
 * 
 * No Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT
 * 
 * OTG Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_MSB        2
/* The width in bits of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_OTGINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GINTSTS_OTGINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Start of Frame - sof
 * 
 * Mode: Host and Device. In Host mode, the core sets this bit to indicate that an
 * SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB. The
 * application must write a 1 to this bit to clear the interrupt. In Device mode,
 * the core sets this bit to indicate that an SOF token has been received on the
 * USB. The application can read the Device Status register to get the current
 * (micro)Frame number. This interrupt is seen only when the core is operating at
 * either HS or FS. This bit can be set only by the core and the application should
 * write 1 to clear it. This register may return 1 if read immediately after power
 * on reset. If the register bit reads 1 immediately after power on reset it does
 * not indicate that an SOF has been sent (in case of host mode) or SOF has been
 * received (in case of device mode). The read value of this interrupt is valid
 * only after a valid connection between host and device is established. If the bit
 * is set after power on reset the application can clear the bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description   
 * :----------------------------------|:------|:---------------
 *  ALT_USB_GLOB_GINTSTS_SOF_E_INTACT | 0x0   | No sof        
 *  ALT_USB_GLOB_GINTSTS_SOF_E_ACT    | 0x1   | Start of Frame
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF
 * 
 * No sof
 */
#define ALT_USB_GLOB_GINTSTS_SOF_E_INTACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF
 * 
 * Start of Frame
 */
#define ALT_USB_GLOB_GINTSTS_SOF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_MSB        3
/* The width in bits of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_SOF register field value. */
#define ALT_USB_GLOB_GINTSTS_SOF_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_SOF register field value. */
#define ALT_USB_GLOB_GINTSTS_SOF_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_SOF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_SOF_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GINTSTS_SOF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_SOF_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : RxFIFO Non-Empty - rxflvl
 * 
 * Mode: Host and Device. Indicates that there is at least one packet pending to be
 * read from the RxFIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT | 0x0   | Not Active       
 *  ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT   | 0x1   | Rx Fifo Non Empty
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL
 * 
 * Not Active
 */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL
 * 
 * Rx Fifo Non Empty
 */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_MSB        4
/* The width in bits of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_RXFLVL field value from a register. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GINTSTS_RXFLVL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Global IN Non-periodic NAK Effective - ginnakeff
 * 
 * Mode: Device only. Indicates that the Set Global Non-periodic IN NAK bit in the
 * Device Control register (DCTL.SGNPInNak), Set by the application, has taken
 * effect in the core. That is, the core has sampled the Global IN NAK bit Set by
 * the application. This bit can be cleared by clearing the Clear Global Non-
 * periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). This
 * interrupt does not necessarily mean that a NAK handshake is sent out on the USB.
 * The STALL bit takes precedence over the NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                      
 * :---------------------------------------|:------|:----------------------------------
 *  ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT | 0x0   | Not active                       
 *  ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT   | 0x1   | Set Global Non-periodic IN NAK bi
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF
 * 
 * Set Global Non-periodic IN NAK bi
 */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_MSB        6
/* The width in bits of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_GINNAKEFF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Global OUT NAK Effective - goutnakeff
 * 
 * Mode: Device only. Indicates that the Set Global OUT NAK bit in the Device
 * Control register (DCTL.SGOUTNak), Set by the application, has taken effect in
 * the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the
 * Device Control register (DCTL.CGOUTNak).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description             
 * :----------------------------------------|:------|:-------------------------
 *  ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT | 0x0   | No Active               
 *  ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT   | 0x1   | Global OUT NAK Effective
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
 * 
 * No Active
 */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
 * 
 * Global OUT NAK Effective
 */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_MSB        7
/* The width in bits of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Early Suspend - erlysusp
 * 
 * Mode: Device only. The core sets this bit to indicate that an Idle state has
 * been detected on the USB for 3 ms.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT | 0x0   | No Idle            
 *  ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT   | 0x1   | Idle state detecetd
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP
 * 
 * No Idle
 */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP
 * 
 * Idle state detecetd
 */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_MSB        10
/* The width in bits of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_ERLYSUSP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : USB Suspend - usbsusp
 * 
 * Mode: Device only. The core sets this bit to indicate that a suspend was
 * detected on the USB. The core enters the Suspended state when there is no
 * activity on the phy_line_state_i signal for an extended period of time.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT | 0x0   | Not Active 
 *  ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT   | 0x1   | USB Suspend
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP
 * 
 * Not Active
 */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP
 * 
 * USB Suspend
 */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_MSB        11
/* The width in bits of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_USBSUSP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GINTSTS_USBSUSP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : USB Reset - usbrst
 * 
 * Mode: Device only. The core sets this bit to indicate that a reset is detected
 * on the USB.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GINTSTS_USBRST_E_INACT | 0x0   | Not active 
 *  ALT_USB_GLOB_GINTSTS_USBRST_E_ACT   | 0x1   | USB Reset  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_USBRST_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST
 * 
 * USB Reset
 */
#define ALT_USB_GLOB_GINTSTS_USBRST_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_MSB        12
/* The width in bits of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_USBRST register field value. */
#define ALT_USB_GLOB_GINTSTS_USBRST_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBRST register field value. */
#define ALT_USB_GLOB_GINTSTS_USBRST_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_USBRST field value from a register. */
#define ALT_USB_GLOB_GINTSTS_USBRST_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_GLOB_GINTSTS_USBRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_USBRST_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Enumeration Done - enumdone
 * 
 * Mode: Device only. The core sets this bit to indicate that speed enumeration is
 * complete. The application must read the Device Status register to obtain the
 * enumerated speed.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT | 0x0   | Not active      
 *  ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT   | 0x1   | Enumeration Done
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE
 * 
 * Enumeration Done
 */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_MSB        13
/* The width in bits of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_ENUMDONE field value from a register. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_GLOB_GINTSTS_ENUMDONE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Isochronous OUT Packet Dropped Interrupt - isooutdrop
 * 
 * Mode: Device only. The core sets this bit when it fails to write an isochronous
 * OUT packet into the RxFIFO because the RxFIFO does not have enough space to
 * accommodate a maximum packet size packet for the isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                            
 * :----------------------------------------|:------|:----------------------------------------
 *  ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT | 0x0   | Not active                             
 *  ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT   | 0x1   | Isochronous OUT Packet Dropped Interrup
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP
 * 
 * Isochronous OUT Packet Dropped Interrup
 */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_MSB        14
/* The width in bits of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_ISOOUTDROP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : Endpoint Mismatch Interrupt - epmis
 * 
 * Mode: Device only. This interrupt is valid only in shared FIFO operation.
 * Indicates that an IN token has been received for a non-periodic endpoint, but
 * the data for another endpoint is present in the top of the Non-periodic Transmit
 * FIFO and the IN endpoint mismatch count programmed by the application has
 * expired.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description               
 * :-----------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT | 0x0   | Not active                
 *  ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT   | 0x1   | Endpoint Mismatch Interrup
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS
 * 
 * Endpoint Mismatch Interrup
 */
#define ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_MSB        17
/* The width in bits of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_EPMIS field value from a register. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GINTSTS_EPMIS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : IN Endpoints Interrupt - iepint
 * 
 * Mode: Device only. The core sets this bit to indicate that an interrupt is
 * pending on one of the IN endpoints of the core (in Device mode). The application
 * must read the Device All Endpoints Interrupt (DAINT) register to determine the
 * exact number of the IN endpoint on Device IN Endpoint-n Interrupt (DIEPINTn)
 * register to determine the exact cause of the interrupt. The application must
 * clear the appropriate status bit in the corresponding DIEPINTn register to clear
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description           
 * :------------------------------------|:------|:-----------------------
 *  ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT | 0x0   | Not active            
 *  ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT   | 0x1   | IN Endpoints Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT
 * 
 * IN Endpoints Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_MSB        18
/* The width in bits of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_IEPINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GINTSTS_IEPINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : OUT Endpoints Interrupt - oepint
 * 
 * Mode: Device only. The core sets this bit to indicate that an interrupt is
 * pending on one of the OUT endpoints of the core (in Device mode). The
 * application must read the Device All Endpoints Interrupt (DAINT) register to
 * determine the exact number of the OUT endpoint on which the interrupt occurred,
 * and Then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
 * register to determine the exact cause of the interrupt. The application must
 * clear the appropriate status bit in the corresponding DOEPINTn register to clear
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description            
 * :------------------------------------|:------|:------------------------
 *  ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT | 0x0   | Not active             
 *  ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT   | 0x1   | OUT Endpoints Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT
 * 
 * OUT Endpoints Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_MSB        19
/* The width in bits of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_OEPINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GINTSTS_OEPINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Incomplete Isochronous IN Transfer - incompisoin
 * 
 * Mode: Device only. The core sets this interrupt to indicate that there is at
 * least isochronous IN endpoint on which the transfer is not completed in the
 * current microframe. This interrupt is asserted along with the End of Periodic
 * Frame Interrupt (EOPF) bit in this register. This interrupt is not asserted in
 * Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                       
 * :-----------------------------------------|:------|:-----------------------------------
 *  ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT | 0x0   | Not active                        
 *  ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT   | 0x1   | Incomplete Isochronous IN Transfer
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN
 * 
 * Incomplete Isochronous IN Transfer
 */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_MSB        20
/* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPISOIN field value from a register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Incomplete Periodic Transfer - incomplp
 * 
 * Mode: Device only. In Host mode, the core sets this interrupt bit when there are
 * incomplete periodic transactions still pending which arescheduled for the
 * current microframe. Incomplete Isochronous OUT Transfer (incompISOOUT) The
 * Device mode, the core sets this interrupt to indicate that there is at least one
 * isochronous OUT endpoint on which the transfer is not completed in the current
 * microframe. This interrupt is asserted along with the End of Periodic Frame
 * Interrupt (EOPF) bit in this register. This bit can be set only by the core and
 * the application should write 1 to clear it
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT | 0x0   | Not active                  
 *  ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT   | 0x1   | Incomplete Periodic Transfer
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP
 * 
 * Incomplete Periodic Transfer
 */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_MSB        21
/* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPLP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GINTSTS_INCOMPLP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Data Fetch Suspended - fetsusp
 * 
 * Mode: Device only. This interrupt is valid only in DMA mode. This interrupt
 * indicates that the core has stopped fetching data for IN endpoints due to the
 * unavailability of TxFIFO space or Request Queue space. This interrupt is used by
 * the application for an endpoint mismatch algorithm. for example, after detecting
 * an endpoint mismatch, the application:
 * 
 * * Sets a Global non-periodic IN NAK handshake
 * 
 * * Disables In endpoints
 * 
 * * Flushes the FIFO
 * 
 * * Determines the token sequence from the IN Token Sequence
 * 
 * Learning Queue
 * 
 * * Re-enables the endpoints
 * 
 * * Clears the Global non-periodic IN NAK handshake
 * 
 * If the Global non-periodic IN NAK is cleared, the core has not yet fetched data
 * for the IN endpoint, and the IN token is received: the core generates an IN
 * token received when FIFO empty interrupt. The OTG Then sends the host a NAK
 * response. To avoid this scenario, the application can check the GINTSTS.FetSusp
 * interrupt, which ensures that the FIFO is full before clearing a Global NAK
 * handshake. Alternatively, the application can mask the "IN token received when
 * FIFO empty" interrupt when clearing a Global IN NAKhandshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT | 0x0   | Not active          
 *  ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT   | 0x1   | Data Fetch Suspended
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP
 * 
 * Data Fetch Suspended
 */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_MSB        22
/* The width in bits of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_FETSUSP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GINTSTS_FETSUSP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : Reset detected Interrupt - resetdet
 * 
 * Mode: Device only. In Device mode, this interrupt is asserted when a reset is
 * detected on the USB in partial power-down mode when the device is in Suspend. In
 * Host mode, this interrupt is not asserted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description            
 * :------------------------------------|:------|:------------------------
 *  ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT | 0x0   | Not active             
 *  ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT   | 0x1   | Reset detected Interrup
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET
 * 
 * Reset detected Interrup
 */
#define ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_MSB        23
/* The width in bits of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_RSTDET field value from a register. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GINTSTS_RSTDET register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Host Port Interrupt - prtint
 * 
 * Mode:Host only. The core sets this bit to indicate a change in port status of
 * one of the otg core ports in Host mode. The application must read the Host Port
 * Control and Status (HPRT) register to determine the exact event that caused this
 * interrupt. The application must clear the appropriate status bit in the Host PC
 * Control and Status register to clear this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT | 0x0   |                    
 *  ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT   | 0x1   | Host Port Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT
 * 
 */
#define ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT
 * 
 * Host Port Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_MSB        24
/* The width in bits of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_PRTINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GINTSTS_PRTINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Host Channels Interrupt - hchint
 * 
 * Mode:Host only. The core sets this bit to indicate that an interrupt is pending
 * on one of the channels of the core (in Host mode). The application must read the
 * Host All Channels Interrupt (HAINT) register to determine the exact number of
 * the channel on which the interrupt occurred, and Then read the corresponding
 * Host Channel-n Interrupt (HCINTn) register to determine the exact cause of the
 * interrupt. The application must clear the appropriate status bit in the HCINTn
 * register to clear this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description            
 * :------------------------------------|:------|:------------------------
 *  ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT | 0x0   | Not active             
 *  ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT   | 0x1   | Host Channels Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT
 * 
 * Host Channels Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_MSB        25
/* The width in bits of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_HCHINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GINTSTS_HCHINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Periodic TxFIFO Empty - ptxfemp
 * 
 * Mode:Host only. This interrupt is asserted when the Periodic Transmit FIFO is
 * either half or completely empty and there is space for at least one entry to be
 * written in the Periodic Request Queue. The half or completely empty status is
 * determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration
 * register (GAHBCFG.PTxFEmpLvl).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description          
 * :-------------------------------------|:------|:----------------------
 *  ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT | 0x0   | Not active           
 *  ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT   | 0x1   | Periodic TxFIFO Empty
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP
 * 
 * Periodic TxFIFO Empty
 */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_MSB        26
/* The width in bits of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_RESET      0x1
/* Extracts the ALT_USB_GLOB_GINTSTS_PTXFEMP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GINTSTS_PTXFEMP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Connector ID Status Change - ConIDStsChng
 * 
 * Mode:Host and Device. The core sets this bit when there is a change in connector
 * ID status. This bit can be set only by the core and the application should write
 * 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description               
 * :------------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT | 0x0   | Not Active                
 *  ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT   | 0x1   | Connector ID Status Change
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
 * 
 * Not Active
 */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
 * 
 * Connector ID Status Change
 */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_MSB        28
/* The width in bits of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_RESET      0x1
/* Extracts the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG field value from a register. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Disconnect Detected Interrupt - disconnint
 * 
 * Mode:Host only. Asserted when a device disconnect is detected. This bit can be
 * set only by the core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                  
 * :----------------------------------------|:------|:------------------------------
 *  ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT | 0x0   | Not active                   
 *  ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT   | 0x1   | Disconnect Detected Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT
 * 
 * Disconnect Detected Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_MSB        29
/* The width in bits of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_DISCONNINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_GLOB_GINTSTS_DISCONNINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Session Request New Session Detected Interrupt - sessreqint
 * 
 * Mode:Host and Device. In Host mode, this interrupt is asserted when a session
 * request is detected from the device. In Host mode, this interrupt is asserted
 * when a session request is detected from the device. In Device mode, this
 * interrupt is asserted when the utmisrp_bvalid signal goes high. This bit can be
 * set only by the core and the application should write 1 to clear.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                   
 * :----------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT | 0x0   | Not active                                    
 *  ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT   | 0x1   | Session Request New Session Detected Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT
 * 
 * Session Request New Session Detected Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_MSB        30
/* The width in bits of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_SESSREQINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GINTSTS_SESSREQINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Resume Remote Wakeup Detected Interrupt - wkupint
 * 
 * Mode:Host and Device. Wakeup Interrupt during Suspend(L2) or LPM(L1) state.
 * -During Suspend(L2):
 * 
 * * Device Mode - This interrupt is asserted only when Host Initiated Resume is
 *   detected on USB.
 * 
 * * Host Mode - This interrupt is asserted only when Device Initiated Remote
 *   Wakeup is detected on USB
 * 
 * * During LPM(L1):- - Device Mode - This interrupt is asserted for either Host
 *   Initiated Resume or Device Initiated Remote Wakeup on USB.
 * 
 * * Host Mode - This interrupt is asserted for either Host Initiated Resume or
 *   Device Initiated Remote Wakeup on USB.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT | 0x0   | Not active                             
 *  ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT   | 0x1   | Resume Remote Wakeup Detected Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT
 * 
 * Not active
 */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT
 * 
 * Resume Remote Wakeup Detected Interrupt
 */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_MSB        31
/* The width in bits of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_WKUPINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GINTSTS_WKUPINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GINTSTS.
 */
struct ALT_USB_GLOB_GINTSTS_s
{
    const uint32_t  curmod       :  1;  /* Current Mode of Operation */
    const uint32_t  modemis      :  1;  /* Mode Mismatch Interrupt */
    const uint32_t  otgint       :  1;  /* OTG Interrupt */
    const uint32_t  sof          :  1;  /* Start of Frame */
    const uint32_t  rxflvl       :  1;  /* RxFIFO Non-Empty */
    uint32_t                     :  1;  /* *UNDEFINED* */
    const uint32_t  ginnakeff    :  1;  /* Global IN Non-periodic NAK Effective */
    const uint32_t  goutnakeff   :  1;  /* Global OUT NAK Effective */
    uint32_t                     :  2;  /* *UNDEFINED* */
    const uint32_t  erlysusp     :  1;  /* Early Suspend */
    const uint32_t  usbsusp      :  1;  /* USB Suspend */
    const uint32_t  usbrst       :  1;  /* USB Reset */
    const uint32_t  enumdone     :  1;  /* Enumeration Done */
    const uint32_t  isooutdrop   :  1;  /* Isochronous OUT Packet Dropped Interrupt */
    uint32_t                     :  2;  /* *UNDEFINED* */
    const uint32_t  epmis        :  1;  /* Endpoint Mismatch Interrupt */
    const uint32_t  iepint       :  1;  /* IN Endpoints Interrupt */
    const uint32_t  oepint       :  1;  /* OUT Endpoints Interrupt */
    const uint32_t  incompisoin  :  1;  /* Incomplete Isochronous IN Transfer */
    const uint32_t  incomplp     :  1;  /* Incomplete Periodic Transfer */
    const uint32_t  fetsusp      :  1;  /* Data Fetch Suspended */
    const uint32_t  resetdet     :  1;  /* Reset detected Interrupt */
    const uint32_t  prtint       :  1;  /* Host Port Interrupt */
    const uint32_t  hchint       :  1;  /* Host Channels Interrupt */
    const uint32_t  ptxfemp      :  1;  /* Periodic TxFIFO Empty */
    uint32_t                     :  1;  /* *UNDEFINED* */
    const uint32_t  ConIDStsChng :  1;  /* Connector ID Status Change */
    const uint32_t  disconnint   :  1;  /* Disconnect Detected Interrupt */
    const uint32_t  sessreqint   :  1;  /* Session Request New Session Detected Interrupt */
    const uint32_t  wkupint      :  1;  /* Resume Remote Wakeup Detected Interrupt */
};

/* The typedef declaration for register ALT_USB_GLOB_GINTSTS. */
typedef volatile struct ALT_USB_GLOB_GINTSTS_s  ALT_USB_GLOB_GINTSTS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GINTSTS register from the beginning of the component. */
#define ALT_USB_GLOB_GINTSTS_OFST        0x14
/* The address of the ALT_USB_GLOB_GINTSTS register. */
#define ALT_USB_GLOB_GINTSTS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTSTS_OFST))

/*
 * Register : Interrupt Mask Register - gintmsk
 * 
 * This register works with the Interrupt Register (GINTSTS) to interrupt the
 * application. When an interrupt bit is masked, the interrupt associated with that
 * bit is not generated. However, the GINTSTS register bit corresponding to that
 * interrupt is still set.
 * 
 * Register Layout
 * 
 *  Bits  | Access | Reset | Description                                       
 * :------|:-------|:------|:---------------------------------------------------
 *  [0]   | ???    | 0x0   | *UNDEFINED*                                       
 *  [1]   | RW     | 0x0   | Mode Mismatch Interrupt Mask                      
 *  [2]   | RW     | 0x0   | OTG Interrupt Mask                                
 *  [3]   | RW     | 0x0   | Start of (micro)Frame Mask                        
 *  [4]   | RW     | 0x0   | Receive FIFO Non-Empty Mask                       
 *  [5]   | ???    | 0x0   | *UNDEFINED*                                       
 *  [6]   | RW     | 0x0   | Global Non-periodic IN NAK Effective Mask         
 *  [7]   | RW     | 0x0   | Global OUT NAK Effective Mask                     
 *  [9:8] | ???    | 0x0   | *UNDEFINED*                                       
 *  [10]  | RW     | 0x0   | Early Suspend Mask                                
 *  [11]  | RW     | 0x0   | USB Suspend Mask                                  
 *  [12]  | RW     | 0x0   | USB Reset Mask                                    
 *  [13]  | RW     | 0x0   | Enumeration Done Mask                             
 *  [14]  | RW     | 0x0   | Isochronous OUT Packet Dropped Interrupt Mask     
 *  [15]  | RW     | 0x0   | End of Periodic Frame Interrupt Mask              
 *  [16]  | ???    | 0x0   | *UNDEFINED*                                       
 *  [17]  | RW     | 0x0   | Endpoint Mismatch Interrupt Mask                  
 *  [18]  | RW     | 0x0   | IN Endpoints Interrupt Mask                       
 *  [19]  | RW     | 0x0   | OUT Endpoints Interrupt Mask                      
 *  [20]  | RW     | 0x0   | Incomplete Isochronous IN Transfer Mask           
 *  [21]  | RW     | 0x0   | Incomplete Periodic Transfer Mask                 
 *  [22]  | RW     | 0x0   | Data Fetch Suspended Mask                         
 *  [23]  | RW     | 0x0   | Reset detected Interrupt Mask                     
 *  [24]  | RW     | 0x0   | Host Port Interrupt Mask                          
 *  [25]  | RW     | 0x0   | Host Channels Interrupt Mask                      
 *  [26]  | RW     | 0x0   | Periodic TxFIFO Empty Mask                        
 *  [27]  | ???    | 0x0   | *UNDEFINED*                                       
 *  [28]  | RW     | 0x0   | Connector ID Status Change Mask                   
 *  [29]  | RW     | 0x0   | ALT_USB_GLOB_GINTMSK_DISCONNINTMSK                
 *  [30]  | RW     | 0x0   | Session Request New Session Detected Interrupt Mas
 *  [31]  | RW     | 0x0   | Resume Remote Wakeup Detected Interrupt Mask      
 * 
 */
/*
 * Field : Mode Mismatch Interrupt Mask - modemismsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                    
 * :---------------------------------------|:------|:--------------------------------
 *  ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK   | 0x0   | Mode Mismatch Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK | 0x1   | No Mask Mode Mismatch Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK
 * 
 * Mode Mismatch Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK
 * 
 * No Mask Mode Mismatch Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_MSB        1
/* The width in bits of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_MODMISMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GINTMSK_MODMISMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : OTG Interrupt Mask - otgintmsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description          
 * :---------------------------------------|:------|:----------------------
 *  ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK   | 0x0   | OTG Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK | 0x1   | No mask OTG Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK
 * 
 * OTG Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK
 * 
 * No mask OTG Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_MSB        2
/* The width in bits of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_OTGINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Start of (micro)Frame Mask - sofmsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description           
 * :------------------------------------|:------|:-----------------------
 *  ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK   | 0x0   | Start of Frame Mask   
 *  ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK | 0x1   | No Mask Start of Frame
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK
 * 
 * Start of Frame Mask
 */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK
 * 
 * No Mask Start of Frame
 */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_MSB        3
/* The width in bits of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_SOFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GINTMSK_SOFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Receive FIFO Non-Empty Mask - rxflvlmsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                   
 * :---------------------------------------|:------|:-------------------------------
 *  ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK   | 0x0   | Receive FIFO Non-Empty Mask   
 *  ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK | 0x1   | No maks Receive FIFO Non-Empty
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK
 * 
 * Receive FIFO Non-Empty Mask
 */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK
 * 
 * No maks Receive FIFO Non-Empty
 */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_MSB        4
/* The width in bits of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_RXFLVLMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Global Non-periodic IN NAK Effective Mask - ginnakeffmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK   | 0x0   | Global Non-periodic IN NAK Effective Mask   
 *  ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK | 0x1   | No mask Global Non-periodic IN NAK Effective
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
 * 
 * Global Non-periodic IN NAK Effective Mask
 */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
 * 
 * No mask Global Non-periodic IN NAK Effective
 */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_MSB        6
/* The width in bits of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Global OUT NAK Effective Mask - goutnakeffmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                     
 * :--------------------------------------------|:------|:---------------------------------
 *  ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK    | 0x0   | Global OUT NAK Effective Mask   
 *  ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS | 0x1   | No mask Global OUT NAK Effective
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
 * 
 * Global OUT NAK Effective Mask
 */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
 * 
 * No mask Global OUT NAK Effective
 */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_MSB        7
/* The width in bits of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Early Suspend Mask - erlysuspmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description               
 * :-----------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK   | 0x0   | Early Suspend Mask        
 *  ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK | 0x1   | No mask Early Suspend Mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
 * 
 * Early Suspend Mask
 */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
 * 
 * No mask Early Suspend Mask
 */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_MSB        10
/* The width in bits of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : USB Suspend Mask - usbsuspmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK   | 0x0   | USB Suspend Mask    
 *  ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK | 0x1   | No mask  USB Suspend
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK
 * 
 * USB Suspend Mask
 */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK
 * 
 * No mask  USB Suspend
 */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_MSB        11
/* The width in bits of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_USBSUSPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : USB Reset Mask - usbrstmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description      
 * :---------------------------------------|:------|:------------------
 *  ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK   | 0x0   | USB Reset Mask   
 *  ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK | 0x1   | No mask USB Reset
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK
 * 
 * USB Reset Mask
 */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK
 * 
 * No mask USB Reset
 */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_MSB        12
/* The width in bits of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_USBRSTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Enumeration Done Mask - enumdonemsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description             
 * :-----------------------------------------|:------|:-------------------------
 *  ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK   | 0x0   | Enumeration Done Mask   
 *  ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK | 0x1   | No mask Enumeration Done
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
 * 
 * Enumeration Done Mask
 */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
 * 
 * No mask Enumeration Done
 */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_MSB        13
/* The width in bits of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Isochronous OUT Packet Dropped Interrupt Mask - isooutdropmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                     
 * :-------------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK   | 0x0   | Isochronous OUT Packet Dropped Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK | 0x1   | No mask Isochronous OUT Packet Dropped Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
 * 
 * Isochronous OUT Packet Dropped Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
 * 
 * No mask Isochronous OUT Packet Dropped Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_MSB        14
/* The width in bits of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : End of Periodic Frame Interrupt Mask - eopfmsk
 * 
 * Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK   | 0x0   | End of Periodic Frame Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK | 0x1   | No mask End of Periodic Frame Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK
 * 
 * End of Periodic Frame Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK
 * 
 * No mask End of Periodic Frame Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_MSB        15
/* The width in bits of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_EOPFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_GLOB_GINTMSK_EOPFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Mismatch Interrupt Mask - epmismsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK   | 0x0   | Endpoint Mismatch Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK | 0x1   | No mask Endpoint Mismatch Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK
 * 
 * Endpoint Mismatch Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK
 * 
 * No mask Endpoint Mismatch Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_MSB        17
/* The width in bits of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_EPMISMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GINTMSK_EPMISMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : IN Endpoints Interrupt Mask - iepintmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK    | 0x0   | IN Endpoints Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS | 0x1   | No mask IN Endpoints Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK
 * 
 * IN Endpoints Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK
 * 
 * No mask IN Endpoints Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_MSB        18
/* The width in bits of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_IEPINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : OUT Endpoints Interrupt Mask - oepintmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                    
 * :---------------------------------------|:------|:--------------------------------
 *  ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK   | 0x0   | OUT Endpoints Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK | 0x1   | No mask OUT Endpoints Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK
 * 
 * OUT Endpoints Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK
 * 
 * No mask OUT Endpoints Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_MSB        19
/* The width in bits of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_OEPINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Incomplete Isochronous IN Transfer Mask - incompisoinmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                               
 * :--------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK   | 0x0   | Incomplete Isochronous IN Transfer Mask   
 *  ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK | 0x1   | No mask Incomplete Isochronous IN Transfer
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
 * 
 * Incomplete Isochronous IN Transfer Mask
 */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
 * 
 * No mask Incomplete Isochronous IN Transfer
 */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_MSB        20
/* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Incomplete Periodic Transfer Mask - incomplpmsk
 * 
 * Mode: Host only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                         
 * :-----------------------------------------|:------|:-------------------------------------
 *  ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK   | 0x0   | Incomplete Periodic Transfer Mask   
 *  ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK | 0x1   | No mask Incomplete Periodic Transfer
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
 * 
 * Incomplete Periodic Transfer Mask
 */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
 * 
 * No mask Incomplete Periodic Transfer
 */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_MSB        21
/* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Data Fetch Suspended Mask - fetsuspmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK   | 0x0   | Data Fetch Suspended Mask   
 *  ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK | 0x1   | No mask Data Fetch Suspended
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK
 * 
 * Data Fetch Suspended Mask
 */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK
 * 
 * No mask Data Fetch Suspended
 */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_MSB        22
/* The width in bits of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_FETSUSPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : Reset detected Interrupt Mask - resetdetmsk
 * 
 * Mode: Device only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                     
 * :---------------------------------------|:------|:---------------------------------
 *  ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK   | 0x0   | Reset detected Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK | 0x1   | No mask Reset detected Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK
 * 
 * Reset detected Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK
 * 
 * No mask Reset detected Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_MSB        23
/* The width in bits of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_RSTDETMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Host Port Interrupt Mask - prtintmsk
 * 
 * Mode: Host only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK   | 0x0   | Host Port Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK | 0x1   | No mask Host Port Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK
 * 
 * Host Port Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK
 * 
 * No mask Host Port Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_MSB        24
/* The width in bits of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_PRTINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Host Channels Interrupt Mask - hchintmsk
 * 
 * Mode: Host only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                    
 * :---------------------------------------|:------|:--------------------------------
 *  ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK   | 0x0   | Host Channels Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK | 0x1   | No mask Host Channels Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK
 * 
 * Host Channels Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK
 * 
 * No mask Host Channels Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_MSB        25
/* The width in bits of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_HCHINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Periodic TxFIFO Empty Mask - ptxfempmsk
 * 
 * Mode: Host only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                  
 * :----------------------------------------|:------|:------------------------------
 *  ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK   | 0x0   | Periodic TxFIFO Empty Mask   
 *  ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK | 0x1   | No mask Periodic TxFIFO Empty
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
 * 
 * Periodic TxFIFO Empty Mask
 */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
 * 
 * No mask Periodic TxFIFO Empty
 */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_MSB        26
/* The width in bits of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Connector ID Status Change Mask - conidstschngmsk
 * 
 * Mode: Host and Device. This bit can be set only by the core and the application
 * should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                       
 * :---------------------------------------------|:------|:-----------------------------------
 *  ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK   | 0x0   | Connector ID Status Change Mask   
 *  ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK | 0x1   | No mask Connector ID Status Change
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
 * 
 * Connector ID Status Change Mask
 */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
 * 
 * No mask Connector ID Status Change
 */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_MSB        28
/* The width in bits of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : disconnintmsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                          
 * :-------------------------------------------|:------|:--------------------------------------
 *  ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK   | 0x0   | Disconnect Detected Interrupt Mask   
 *  ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK | 0x1   | No mask Disconnect Detected Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
 * 
 * Disconnect Detected Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
 * 
 * No mask Disconnect Detected Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_MSB        29
/* The width in bits of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Session Request New Session Detected Interrupt Mas - sessreqintmsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                   
 * :-------------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK   | 0x0   | Session Request New Session Detected Interrupt
 * :                                           |       | Mask                                          
 *  ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK | 0x1   | No mask Session RequestNew Session Detected   
 * :                                           |       | Interrupt                                     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
 * 
 * Session Request New Session Detected Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
 * 
 * No mask Session RequestNew Session Detected Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_MSB        30
/* The width in bits of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Resume Remote Wakeup Detected Interrupt Mask - wkupintmsk
 * 
 * Mode: Host and Device.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                   
 * :----------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK   | 0x0   | Resume Remote Wakeup Detected Interrupt Mask  
 *  ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK | 0x1   | No maskResume Remote Wakeup Detected Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK
 * 
 * Resume Remote Wakeup Detected Interrupt Mask
 */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK
 * 
 * No maskResume Remote Wakeup Detected Interrupt
 */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_MSB        31
/* The width in bits of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_RESET      0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_WKUPINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GINTMSK.
 */
struct ALT_USB_GLOB_GINTMSK_s
{
    uint32_t                  :  1;  /* *UNDEFINED* */
    uint32_t  modemismsk      :  1;  /* Mode Mismatch Interrupt Mask */
    uint32_t  otgintmsk       :  1;  /* OTG Interrupt Mask */
    uint32_t  sofmsk          :  1;  /* Start of (micro)Frame Mask */
    uint32_t  rxflvlmsk       :  1;  /* Receive FIFO Non-Empty Mask */
    uint32_t                  :  1;  /* *UNDEFINED* */
    uint32_t  ginnakeffmsk    :  1;  /* Global Non-periodic IN NAK Effective Mask */
    uint32_t  goutnakeffmsk   :  1;  /* Global OUT NAK Effective Mask */
    uint32_t                  :  2;  /* *UNDEFINED* */
    uint32_t  erlysuspmsk     :  1;  /* Early Suspend Mask */
    uint32_t  usbsuspmsk      :  1;  /* USB Suspend Mask */
    uint32_t  usbrstmsk       :  1;  /* USB Reset Mask */
    uint32_t  enumdonemsk     :  1;  /* Enumeration Done Mask */
    uint32_t  isooutdropmsk   :  1;  /* Isochronous OUT Packet Dropped Interrupt Mask */
    uint32_t  eopfmsk         :  1;  /* End of Periodic Frame Interrupt Mask */
    uint32_t                  :  1;  /* *UNDEFINED* */
    uint32_t  epmismsk        :  1;  /* Endpoint Mismatch Interrupt Mask */
    uint32_t  iepintmsk       :  1;  /* IN Endpoints Interrupt Mask */
    uint32_t  oepintmsk       :  1;  /* OUT Endpoints Interrupt Mask */
    uint32_t  incompisoinmsk  :  1;  /* Incomplete Isochronous IN Transfer Mask */
    uint32_t  incomplpmsk     :  1;  /* Incomplete Periodic Transfer Mask */
    uint32_t  fetsuspmsk      :  1;  /* Data Fetch Suspended Mask */
    uint32_t  resetdetmsk     :  1;  /* Reset detected Interrupt Mask */
    uint32_t  prtintmsk       :  1;  /* Host Port Interrupt Mask */
    uint32_t  hchintmsk       :  1;  /* Host Channels Interrupt Mask */
    uint32_t  ptxfempmsk      :  1;  /* Periodic TxFIFO Empty Mask */
    uint32_t                  :  1;  /* *UNDEFINED* */
    uint32_t  conidstschngmsk :  1;  /* Connector ID Status Change Mask */
    uint32_t  disconnintmsk   :  1;  /* ALT_USB_GLOB_GINTMSK_DISCONNINTMSK */
    uint32_t  sessreqintmsk   :  1;  /* Session Request New Session Detected Interrupt Mas */
    uint32_t  wkupintmsk      :  1;  /* Resume Remote Wakeup Detected Interrupt Mask */
};

/* The typedef declaration for register ALT_USB_GLOB_GINTMSK. */
typedef volatile struct ALT_USB_GLOB_GINTMSK_s  ALT_USB_GLOB_GINTMSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GINTMSK register from the beginning of the component. */
#define ALT_USB_GLOB_GINTMSK_OFST        0x18
/* The address of the ALT_USB_GLOB_GINTMSK register. */
#define ALT_USB_GLOB_GINTMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTMSK_OFST))

/*
 * Register : Receive Status Debug Read Register - grxstsr
 * 
 * A read to the Receive Status Read and Pop register additionally pops the: top
 * data entry out of the RxFIFO. The receive status contents must be interpreted
 * differently in Host and Device modes. The core ignores the receive status
 * pop/read when the receive FIFO is empty and returns a value of 0. The
 * application must only pop the Receive Status FIFO when the Receive FIFO Non-
 * Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted.  Use of
 * these fields vary based on whether the HS OTG core is functioning as a host or a
 * device. Do not read this register's reset value before configuring the core
 * because the read value is "X" in the simulation.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description   
 * :--------|:-------|:------|:---------------
 *  [3:0]   | R      | 0x0   | Channel Number
 *  [14:4]  | R      | 0x0   | Byte Count    
 *  [16:15] | R      | 0x0   | Data PID      
 *  [20:17] | R      | 0x0   | Packet Status 
 *  [31:21] | ???    | 0x0   | *UNDEFINED*   
 * 
 */
/*
 * Field : Channel Number - chnum
 * 
 * Indicates the endpoint number to which the current received packet belongs.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_MSB        3
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_SET_MSK    0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_CLR_MSK    0xfffffff0
/* The reset value of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_CHNUM field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GRXSTSR_CHNUM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_SET(value) (((value) << 0) & 0x0000000f)

/*
 * Field : Byte Count - bcnt
 * 
 * Indicates the byte count of the received data packet.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_MSB        14
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_WIDTH      11
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_SET_MSK    0x00007ff0
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_CLR_MSK    0xffff800f
/* The reset value of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_BCNT field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_GET(value) (((value) & 0x00007ff0) >> 4)
/* Produces a ALT_USB_GLOB_GRXSTSR_BCNT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_SET(value) (((value) << 4) & 0x00007ff0)

/*
 * Field : Data PID - dpid
 * 
 * Indicates the Data PID of the received packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 | 0x0   | DATA0      
 *  ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 | 0x2   | DATA1      
 *  ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 | 0x1   | DATA2      
 *  ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA | 0x3   | MDATA      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
 * 
 * DATA0
 */
#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
 * 
 * DATA1
 */
#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
 * 
 * DATA2
 */
#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
 * 
 * MDATA
 */
#define ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_MSB        16
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSR_DPID_SET_MSK    0x00018000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSR_DPID_CLR_MSK    0xfffe7fff
/* The reset value of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_DPID field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_DPID_GET(value) (((value) & 0x00018000) >> 15)
/* Produces a ALT_USB_GLOB_GRXSTSR_DPID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_DPID_SET(value) (((value) << 15) & 0x00018000)

/*
 * Field : Packet Status - pktsts
 * 
 * Mode: Host only. Others: Reserved. Indicates the status of the received packet
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                 
 * :--------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX  | 0x2   | IN data packet received                     
 *  ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM | 0x3   | IN transfer completed (triggers an interrupt
 *  ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG   | 0x5   | Data toggle error (triggers an interrupt)   
 *  ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT  | 0x7   | Channel halted (triggers an interrupt)      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
 * 
 * IN data packet received
 */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX    0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
 * 
 * IN transfer completed (triggers an interrupt
 */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM   0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
 * 
 * Data toggle error (triggers an interrupt)
 */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG     0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
 * 
 * Channel halted (triggers an interrupt)
 */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT    0x7

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_MSB        20
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET_MSK    0x001e0000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_CLR_MSK    0xffe1ffff
/* The reset value of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_PKTSTS field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17)
/* Produces a ALT_USB_GLOB_GRXSTSR_PKTSTS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET(value) (((value) << 17) & 0x001e0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GRXSTSR.
 */
struct ALT_USB_GLOB_GRXSTSR_s
{
    const uint32_t  chnum  :  4;  /* Channel Number */
    const uint32_t  bcnt   : 11;  /* Byte Count */
    const uint32_t  dpid   :  2;  /* Data PID */
    const uint32_t  pktsts :  4;  /* Packet Status */
    uint32_t               : 11;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GRXSTSR. */
typedef volatile struct ALT_USB_GLOB_GRXSTSR_s  ALT_USB_GLOB_GRXSTSR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GRXSTSR register from the beginning of the component. */
#define ALT_USB_GLOB_GRXSTSR_OFST        0x1c
/* The address of the ALT_USB_GLOB_GRXSTSR register. */
#define ALT_USB_GLOB_GRXSTSR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSR_OFST))

/*
 * Register : Receive Status Read Pop Register - grxstsp
 * 
 * A read to the Receive Status Read and Pop register additionally pops the: top
 * data entry out of the RxFIFO. The receive status contents must be interpreted
 * differently in Host and Device modes. The core ignores the receive status
 * pop/read when the receive FIFO is empty and returns a value of 0. The
 * application must only pop the Receive Status FIFO when the Receive FIFO Non-
 * Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted.  Use of
 * these fields vary based on whether the HS OTG core is functioning as a host or a
 * device. Do not read this register'ss reset value before configuring the core
 * because the read value is "X" in the simulation.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description   
 * :--------|:-------|:------|:---------------
 *  [3:0]   | R      | 0x0   | Channel Number
 *  [14:4]  | R      | 0x0   | Byte Count    
 *  [16:15] | R      | 0x0   | Data PID      
 *  [20:17] | R      | 0x0   | Packet Status 
 *  [24:21] | R      | 0x0   | Frame Number  
 *  [31:25] | ???    | 0x0   | *UNDEFINED*   
 * 
 */
/*
 * Field : Channel Number - chnum
 * 
 * Mode: Host only. Indicates the channel number to which the current received
 * packet belongs.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_MSB        3
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_SET_MSK    0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_CLR_MSK    0xfffffff0
/* The reset value of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_CHNUM field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GRXSTSP_CHNUM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_SET(value) (((value) << 0) & 0x0000000f)

/*
 * Field : Byte Count - bcnt
 * 
 * Mode: Host only. Indicates the byte count of the received IN data packet.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_MSB        14
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_WIDTH      11
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_SET_MSK    0x00007ff0
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_CLR_MSK    0xffff800f
/* The reset value of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_BCNT field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_GET(value) (((value) & 0x00007ff0) >> 4)
/* Produces a ALT_USB_GLOB_GRXSTSP_BCNT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_SET(value) (((value) << 4) & 0x00007ff0)

/*
 * Field : Data PID - dpid
 * 
 * Indicates the Data PID of the received OUT data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 | 0x0   | DATA0      
 *  ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 | 0x2   | DATA1      
 *  ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 | 0x1   | DATA2      
 *  ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA | 0x3   | MDATA      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
 * 
 * DATA0
 */
#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
 * 
 * DATA1
 */
#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
 * 
 * DATA2
 */
#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
 * 
 * MDATA
 */
#define ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_MSB        16
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSP_DPID_SET_MSK    0x00018000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSP_DPID_CLR_MSK    0xfffe7fff
/* The reset value of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_DPID field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_DPID_GET(value) (((value) & 0x00018000) >> 15)
/* Produces a ALT_USB_GLOB_GRXSTSP_DPID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_DPID_SET(value) (((value) << 15) & 0x00018000)

/*
 * Field : Packet Status - pktsts
 * 
 * Mode: Host only. Others: Reserved. Indicates the status of the received packet
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 | 0x0   | DATA0      
 *  ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 | 0x2   | DATA1      
 *  ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 | 0x1   | DATA2      
 *  ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA | 0x3   | MDATA      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
 * 
 * DATA0
 */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
 * 
 * DATA1
 */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
 * 
 * DATA2
 */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
 * 
 * MDATA
 */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_MSB        20
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET_MSK    0x001e0000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_CLR_MSK    0xffe1ffff
/* The reset value of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_PKTSTS field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17)
/* Produces a ALT_USB_GLOB_GRXSTSP_PKTSTS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET(value) (((value) << 17) & 0x001e0000)

/*
 * Field : Frame Number - fn
 * 
 * Mode: Device only. This is the least significant 4 bits of the (micro)Frame
 * number in which the packet is received on the USB. This field is supported only
 * when isochronous OUT endpoints are supported.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_MSB        24
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_FN register field value. */
#define ALT_USB_GLOB_GRXSTSP_FN_SET_MSK    0x01e00000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_FN register field value. */
#define ALT_USB_GLOB_GRXSTSP_FN_CLR_MSK    0xfe1fffff
/* The reset value of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_FN field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_FN_GET(value) (((value) & 0x01e00000) >> 21)
/* Produces a ALT_USB_GLOB_GRXSTSP_FN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_FN_SET(value) (((value) << 21) & 0x01e00000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GRXSTSP.
 */
struct ALT_USB_GLOB_GRXSTSP_s
{
    const uint32_t  chnum  :  4;  /* Channel Number */
    const uint32_t  bcnt   : 11;  /* Byte Count */
    const uint32_t  dpid   :  2;  /* Data PID */
    const uint32_t  pktsts :  4;  /* Packet Status */
    const uint32_t  fn     :  4;  /* Frame Number */
    uint32_t               :  7;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GRXSTSP. */
typedef volatile struct ALT_USB_GLOB_GRXSTSP_s  ALT_USB_GLOB_GRXSTSP_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GRXSTSP register from the beginning of the component. */
#define ALT_USB_GLOB_GRXSTSP_OFST        0x20
/* The address of the ALT_USB_GLOB_GRXSTSP register. */
#define ALT_USB_GLOB_GRXSTSP_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSP_OFST))

/*
 * Register : Receive FIFO Size Register - grxfsiz
 * 
 * The application can program the RAM size that must be allocated to the RxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description 
 * :--------|:-------|:-------|:-------------
 *  [13:0]  | RW     | 0x2000 | RxFIFO Depth
 *  [31:14] | ???    | 0x0    | *UNDEFINED* 
 * 
 */
/*
 * Field : RxFIFO Depth - rxfdep
 * 
 * This value is in terms of 32-bit words.  Minimum value is 16  Maximum value is
 * 32,768 The power-on reset value of this register is specified as the Largest Rx
 * Data FIFO Dept 8192. Using the Dynamic FIFO Sizing, you can write a new value in
 * this field. Programmed values must not exceed 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_MSB        13
/* The width in bits of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET_MSK    0x00003fff
/* The mask used to clear the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_CLR_MSK    0xffffc000
/* The reset value of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_GRXFSIZ_RXFDEP field value from a register. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_GET(value) (((value) & 0x00003fff) >> 0)
/* Produces a ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET(value) (((value) << 0) & 0x00003fff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GRXFSIZ.
 */
struct ALT_USB_GLOB_GRXFSIZ_s
{
    uint32_t  rxfdep : 14;  /* RxFIFO Depth */
    uint32_t         : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GRXFSIZ. */
typedef volatile struct ALT_USB_GLOB_GRXFSIZ_s  ALT_USB_GLOB_GRXFSIZ_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GRXFSIZ register from the beginning of the component. */
#define ALT_USB_GLOB_GRXFSIZ_OFST        0x24
/* The address of the ALT_USB_GLOB_GRXFSIZ register. */
#define ALT_USB_GLOB_GRXFSIZ_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXFSIZ_OFST))

/*
 * Register : Non-periodic Transmit FIFO Size Register - gnptxfsiz
 * 
 * The application can program the RAM size and the memory start address for the
 * Non-periodic TxFIFO. The fields of this register change, depending on host or
 * device mode.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                            
 * :--------|:-------|:-------|:----------------------------------------
 *  [13:0]  | RW     | 0x2000 | Non-periodic Transmit RAM Start Address
 *  [15:14] | ???    | 0x0    | *UNDEFINED*                            
 *  [29:16] | RW     | 0x2000 | Non-periodic TxFIFO Depth              
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                            
 * 
 */
/*
 * Field : Non-periodic Transmit RAM Start Address - nptxfstaddr
 * 
 * Mode: Host only. for host mode, this field is always valid.This field contains
 * the memory start address for Non-periodic Transmit FIFO RAM. This field is set
 * from 16-8192 32 bit words. The application can write a new value in this field.
 * Programmed values must not exceed 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_MSB        13
/* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET_MSK    0x00003fff
/* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_CLR_MSK    0xffffc000
/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_RESET      0x2000
/* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_GET(value) (((value) & 0x00003fff) >> 0)
/* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET(value) (((value) << 0) & 0x00003fff)

/*
 * Field : Non-periodic TxFIFO Depth - nptxfdep
 * 
 * Mode: Host only. for host mode, this field is always valid. The application can
 * write a new value in this field. Programmed values must not exceed 8192
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP field value from a register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GNPTXFSIZ.
 */
struct ALT_USB_GLOB_GNPTXFSIZ_s
{
    uint32_t  nptxfstaddr : 14;  /* Non-periodic Transmit RAM Start Address */
    uint32_t              :  2;  /* *UNDEFINED* */
    uint32_t  nptxfdep    : 14;  /* Non-periodic TxFIFO Depth */
    uint32_t              :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GNPTXFSIZ. */
typedef volatile struct ALT_USB_GLOB_GNPTXFSIZ_s  ALT_USB_GLOB_GNPTXFSIZ_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GNPTXFSIZ register from the beginning of the component. */
#define ALT_USB_GLOB_GNPTXFSIZ_OFST        0x28
/* The address of the ALT_USB_GLOB_GNPTXFSIZ register. */
#define ALT_USB_GLOB_GNPTXFSIZ_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXFSIZ_OFST))

/*
 * Register : Non-periodic Transmit FIFO Queue Status Register - gnptxsts
 * 
 * In Device mode, this register is valid only in Shared FIFO operation. It
 * contains the free space information for the Non-periodic TxFIFO and the
 * Nonperiodic Transmit RequestQueue
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                        
 * :--------|:-------|:------|:----------------------------------------------------
 *  [15:0]  | R      | 0x400 | Non-periodic TxFIFO Space Avail                    
 *  [23:16] | R      | 0x8   | Non-periodic Transmit Request Queue Space Available
 *  [30:24] | R      | 0x0   | Top of the Non-periodic Transmit Request Queue     
 *  [31]    | ???    | 0x0   | *UNDEFINED*                                        
 * 
 */
/*
 * Field : Non-periodic TxFIFO Space Avail - nptxfspcavail
 * 
 * Indicates the amount of free space available in the Non-periodic TxFIFO.Values
 * are in terms of 32-bit words. 16h0: Non-periodic TxFIFO is full 16h1: 1 word
 * available 16h2: 2 words available 16hn: n words available (where 0  n  32,768)
 * 16h8000: 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_RESET      0x400
/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL field value from a register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Non-periodic Transmit Request Queue Space Available - nptxqspcavail
 * 
 * Indicates the amount of free space available in the Non-periodic Transmit
 * Request Queue. This queue holds both IN and OUT requests in Host mode. Device
 * mode has only IN requests. -Others: Reserved
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                
 * :-------------------------------------------|:------|:--------------------------------------------
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL | 0x0   | Non-periodic Transmit Request Queue is full
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 | 0x1   | 1 location available                       
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 | 0x2   | 2 locations available                      
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 | 0x3   | 3 locations available                      
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 | 0x4   | 4 locations available                      
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 | 0x5   | 5 locations available                      
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 | 0x6   | 6 locations available                      
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 | 0x7   | 7 locations available                      
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 | 0x8   | 8 locations available                      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * Non-periodic Transmit Request Queue is full
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 1 location available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1  0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 2 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2  0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 3 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3  0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 4 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4  0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 5 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5  0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 6 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6  0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 7 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7  0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
 * 
 * 8 locations available
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8  0x8

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_MSB        23
/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_WIDTH      8
/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET_MSK    0x00ff0000
/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_CLR_MSK    0xff00ffff
/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_RESET      0x8
/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL field value from a register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16)
/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000)

/*
 * Field : Top of the Non-periodic Transmit Request Queue - nptxqtop
 * 
 * Entry in the Non-periodic Tx Request Queue that is currently being processed by
 * the MAC.
 * 
 * * Bits [30:27]: Channel/endpoint number
 * 
 * * Bits [26:25]:
 * 
 * * Bit [24]: Terminate (last Entry for selected channel endpoint)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                                     
 * :--------------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK    | 0x0   | IN/OUT token                                    
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX     | 0x1   | Zero-length transmit packet (device IN/host OUT)
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT | 0x2   | PING/CSPLIT token                               
 *  ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT    | 0x3   | Channel halt command                            
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
 * 
 * IN/OUT token
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
 * 
 * Zero-length transmit packet (device IN/host OUT)
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX     0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
 * 
 * PING/CSPLIT token
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT 0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
 * 
 * Channel halt command
 */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_MSB        30
/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_WIDTH      7
/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET_MSK    0x7f000000
/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_CLR_MSK    0x80ffffff
/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_RESET      0x0
/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP field value from a register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_GET(value) (((value) & 0x7f000000) >> 24)
/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET(value) (((value) << 24) & 0x7f000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GNPTXSTS.
 */
struct ALT_USB_GLOB_GNPTXSTS_s
{
    const uint32_t  nptxfspcavail : 16;  /* Non-periodic TxFIFO Space Avail */
    const uint32_t  nptxqspcavail :  8;  /* Non-periodic Transmit Request Queue Space Available */
    const uint32_t  nptxqtop      :  7;  /* Top of the Non-periodic Transmit Request Queue */
    uint32_t                      :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GNPTXSTS. */
typedef volatile struct ALT_USB_GLOB_GNPTXSTS_s  ALT_USB_GLOB_GNPTXSTS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GNPTXSTS register from the beginning of the component. */
#define ALT_USB_GLOB_GNPTXSTS_OFST        0x2c
/* The address of the ALT_USB_GLOB_GNPTXSTS register. */
#define ALT_USB_GLOB_GNPTXSTS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXSTS_OFST))

/*
 * Register : PHY Vendor Control Register - gpvndctl
 * 
 * The application can use this register to access PHY registers. for a ULPI PHY,
 * the core uses the ULPI interface for PHY register access. The application sets
 * Vendor Control register for PHY register access and times the PHY register
 * access. The application polls the VStatus Done bit in this register for the
 * completion of the PHY register access
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                          
 * :--------|:-------|:------|:--------------------------------------
 *  [7:0]   | RW     | 0x0   | Register Data                        
 *  [15:8]  | RW     | 0x0   | UTMI+ Vendor Control Register Address
 *  [21:16] | RW     | 0x0   | Register Address                     
 *  [22]    | RW     | 0x0   | Register Write                       
 *  [24:23] | ???    | 0x0   | *UNDEFINED*                          
 *  [25]    | R      | 0x0   | New Register Request                 
 *  [26]    | R      | 0x0   | VStatus Busy                         
 *  [27]    | R      | 0x0   | VStatus Done                         
 *  [30:28] | ???    | 0x0   | *UNDEFINED*                          
 *  [31]    | R      | 0x0   | Disable ULPI Drivers                 
 * 
 */
/*
 * Field : Register Data - regdata
 * 
 * Contains the write data for register write. Read data for register read, valid
 * when VStatus Done is Set.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_MSB        7
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_WIDTH      8
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET_MSK    0x000000ff
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_CLR_MSK    0xffffff00
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGDATA field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_GET(value) (((value) & 0x000000ff) >> 0)
/* Produces a ALT_USB_GLOB_GPVNDCTL_REGDATA register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET(value) (((value) << 0) & 0x000000ff)

/*
 * Field : UTMI+ Vendor Control Register Address - vctrl
 * 
 * The 4-bit register address a vendor defined 4-bit parallel output bus. ULPI
 * Extended Register Address and the 6-bit PHY extended register address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_MSB        15
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_WIDTH      8
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_SET_MSK    0x0000ff00
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_CLR_MSK    0xffff00ff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_VCTL field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_GET(value) (((value) & 0x0000ff00) >> 8)
/* Produces a ALT_USB_GLOB_GPVNDCTL_VCTL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_SET(value) (((value) << 8) & 0x0000ff00)

/*
 * Field : Register Address - regaddr
 * 
 * The 6-bit PHY register address for immediate PHY Register Set access. Set to
 * 0x2F for Extended PHY Register Set access.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_MSB        21
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_WIDTH      6
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET_MSK    0x003f0000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_CLR_MSK    0xffc0ffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGADDR field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_GET(value) (((value) & 0x003f0000) >> 16)
/* Produces a ALT_USB_GLOB_GPVNDCTL_REGADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET(value) (((value) << 16) & 0x003f0000)

/*
 * Field : Register Write - regwr
 * 
 * Set this bit for register writes, and clear it for register reads.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description   
 * :---------------------------------|:------|:---------------
 *  ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD | 0x0   | Register Write
 *  ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR | 0x1   | Register Write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR
 * 
 * Register Write
 */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR
 * 
 * Register Write
 */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_MSB        22
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGWR field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GPVNDCTL_REGWR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : New Register Request - newregreq
 * 
 * The application sets this bit for a new vendor controlaccess.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                    
 * :----------------------------------------|:------|:--------------------------------
 *  ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT | 0x0   | New Register Request not active
 *  ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT   | 0x1   | New Register Request active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
 * 
 * New Register Request not active
 */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
 * 
 * New Register Request active
 */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_MSB        25
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : VStatus Busy - vstsbsy
 * 
 * The core sets this bit when the vendor control access is in progress and clears
 * this bit when done.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description          
 * :--------------------------------------|:------|:----------------------
 *  ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT | 0x0   | VStatus Busy inactive
 *  ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT   | 0x1   | VStatus Busy active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY
 * 
 * VStatus Busy inactive
 */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY
 * 
 * VStatus Busy active
 */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_MSB        26
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSBSY field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : VStatus Done - vstsdone
 * 
 * The core sets this bit when the vendor control access isdone. This bit is
 * cleared by the core when the application sets the New Register Request bit (bit
 * 25).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description          
 * :---------------------------------------|:------|:----------------------
 *  ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT | 0x0   | VStatus Done inactive
 *  ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT   | 0x1   | VStatus Done active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE
 * 
 * VStatus Done inactive
 */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE
 * 
 * VStatus Done active
 */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_MSB        27
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSDONE field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Disable ULPI Drivers - disulpidrvr
 * 
 * The application sets this bit when it has finished processing the ULPI Carkit
 * Interrupt (GINTSTS.ULPICKINT). When Set, the otg core disables drivers for
 * output signals and masks input signal for the ULPI interface. otg clears this
 * bit before enabling the ULPI interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description               
 * :-----------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END  | 0x0   | ULPI ouput signals        
 *  ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD | 0x1   | Disable ULPI ouput signals
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
 * 
 * ULPI ouput signals
 */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
 * 
 * Disable ULPI ouput signals
 */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_MSB        31
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GPVNDCTL.
 */
struct ALT_USB_GLOB_GPVNDCTL_s
{
    uint32_t        regdata     :  8;  /* Register Data */
    uint32_t        vctrl       :  8;  /* UTMI+ Vendor Control Register Address */
    uint32_t        regaddr     :  6;  /* Register Address */
    uint32_t        regwr       :  1;  /* Register Write */
    uint32_t                    :  2;  /* *UNDEFINED* */
    const uint32_t  newregreq   :  1;  /* New Register Request */
    const uint32_t  vstsbsy     :  1;  /* VStatus Busy */
    const uint32_t  vstsdone    :  1;  /* VStatus Done */
    uint32_t                    :  3;  /* *UNDEFINED* */
    const uint32_t  disulpidrvr :  1;  /* Disable ULPI Drivers */
};

/* The typedef declaration for register ALT_USB_GLOB_GPVNDCTL. */
typedef volatile struct ALT_USB_GLOB_GPVNDCTL_s  ALT_USB_GLOB_GPVNDCTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GPVNDCTL register from the beginning of the component. */
#define ALT_USB_GLOB_GPVNDCTL_OFST        0x34
/* The address of the ALT_USB_GLOB_GPVNDCTL register. */
#define ALT_USB_GLOB_GPVNDCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GPVNDCTL_OFST))

/*
 * Register : General Purpose Input Output Register - ggpio
 * 
 * The application can use this register for general purpose input/output ports or
 * for debugging.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description           
 * :--------|:-------|:------|:-----------------------
 *  [15:0]  | R      | 0x0   | General Purpose Input 
 *  [31:16] | RW     | 0x0   | General Purpose Output
 * 
 */
/*
 * Field : General Purpose Input - gpi
 * 
 * This field's read value reflects the gp_i[15:0] core input value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_MSB        15
/* The width in bits of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_GGPIO_GPI register field value. */
#define ALT_USB_GLOB_GGPIO_GPI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GGPIO_GPI register field value. */
#define ALT_USB_GLOB_GGPIO_GPI_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_RESET      0x0
/* Extracts the ALT_USB_GLOB_GGPIO_GPI field value from a register. */
#define ALT_USB_GLOB_GGPIO_GPI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GGPIO_GPI register field value suitable for setting the register. */
#define ALT_USB_GLOB_GGPIO_GPI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : General Purpose Output - gpo
 * 
 * This field is driven as an output from the core, gp_o[15:0]. The application can
 * program this field to determine the corresponding value on the gp_o[15:0]
 * output.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_MSB        31
/* The width in bits of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_GGPIO_GPO register field value. */
#define ALT_USB_GLOB_GGPIO_GPO_SET_MSK    0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GGPIO_GPO register field value. */
#define ALT_USB_GLOB_GGPIO_GPO_CLR_MSK    0x0000ffff
/* The reset value of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_RESET      0x0
/* Extracts the ALT_USB_GLOB_GGPIO_GPO field value from a register. */
#define ALT_USB_GLOB_GGPIO_GPO_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GGPIO_GPO register field value suitable for setting the register. */
#define ALT_USB_GLOB_GGPIO_GPO_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GGPIO.
 */
struct ALT_USB_GLOB_GGPIO_s
{
    const uint32_t  gpi : 16;  /* General Purpose Input */
    uint32_t        gpo : 16;  /* General Purpose Output */
};

/* The typedef declaration for register ALT_USB_GLOB_GGPIO. */
typedef volatile struct ALT_USB_GLOB_GGPIO_s  ALT_USB_GLOB_GGPIO_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GGPIO register from the beginning of the component. */
#define ALT_USB_GLOB_GGPIO_OFST        0x38
/* The address of the ALT_USB_GLOB_GGPIO register. */
#define ALT_USB_GLOB_GGPIO_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GGPIO_OFST))

/*
 * Register : User ID Register - guid
 * 
 * This is a read/write register containing the User ID. This register can be used
 * in the following ways:
 * 
 * * To store the version or revision of your system
 * 
 * * To store hardware configurations that are outside the otg core
 * 
 * As a scratch register
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description
 * :-------|:-------|:-----------|:------------
 *  [31:0] | RW     | 0x12345678 | User ID    
 * 
 */
/*
 * Field : User ID - guid
 * 
 * Application-programmable ID field.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_MSB        31
/* The width in bits of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_WIDTH      32
/* The mask used to set the ALT_USB_GLOB_GUID_GUID register field value. */
#define ALT_USB_GLOB_GUID_GUID_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_GLOB_GUID_GUID register field value. */
#define ALT_USB_GLOB_GUID_GUID_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_RESET      0x12345678
/* Extracts the ALT_USB_GLOB_GUID_GUID field value from a register. */
#define ALT_USB_GLOB_GUID_GUID_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_GLOB_GUID_GUID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUID_GUID_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GUID.
 */
struct ALT_USB_GLOB_GUID_s
{
    uint32_t  guid : 32;  /* User ID */
};

/* The typedef declaration for register ALT_USB_GLOB_GUID. */
typedef volatile struct ALT_USB_GLOB_GUID_s  ALT_USB_GLOB_GUID_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GUID register from the beginning of the component. */
#define ALT_USB_GLOB_GUID_OFST        0x3c
/* The address of the ALT_USB_GLOB_GUID register. */
#define ALT_USB_GLOB_GUID_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUID_OFST))

/*
 * Register : Synopsys ID Register - gsnpsid
 * 
 * This read-only register contains the release number of the core being used.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description
 * :-------|:-------|:-----------|:------------
 *  [31:0] | R      | 0x4f54293a | Synopsys ID
 * 
 */
/*
 * Field : Synopsys ID - gsnpsid
 * 
 * Release number of the otg core being used is currently OTG 2.93a
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_MSB        31
/* The width in bits of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_WIDTH      32
/* The mask used to set the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_RESET      0x4f54293a
/* Extracts the ALT_USB_GLOB_GSNPSID_GSNPSID field value from a register. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_GLOB_GSNPSID_GSNPSID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GSNPSID.
 */
struct ALT_USB_GLOB_GSNPSID_s
{
    const uint32_t  gsnpsid : 32;  /* Synopsys ID */
};

/* The typedef declaration for register ALT_USB_GLOB_GSNPSID. */
typedef volatile struct ALT_USB_GLOB_GSNPSID_s  ALT_USB_GLOB_GSNPSID_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GSNPSID register from the beginning of the component. */
#define ALT_USB_GLOB_GSNPSID_OFST        0x40
/* The address of the ALT_USB_GLOB_GSNPSID register. */
#define ALT_USB_GLOB_GSNPSID_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GSNPSID_OFST))

/*
 * Register : User HW Config1 Register - ghwcfg1
 * 
 * This register contains the logical endpoint direction(s).
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | Endpoint Direction
 * 
 */
/*
 * Field : Endpoint Direction - ghwcfg1
 * 
 * This 32-bit field uses two bits per endpoint to determine the endpoint
 * direction.
 * 
 * Endpoint
 * 
 * * Bits [31:30]: Endpoint 15 direction
 * 
 * * Bits [29:28]: Endpoint 14 direction
 * 
 * ...
 * 
 * * Bits [3:2]: Endpoint 1 direction
 * 
 * * Bits[1:0]: Endpoint 0 direction (always BIDIR)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                
 * :----------------------------------------|:------|:----------------------------
 *  ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR     | 0x0   | BIDIR (IN and OUT) endpoint
 *  ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT  | 0x1   | IN endpoint                
 *  ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT | 0x2   | OUT endpoint               
 *  ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD     | 0x3   | Reserved                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
 * 
 * BIDIR (IN and OUT) endpoint
 */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
 * 
 * IN endpoint
 */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT  0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
 * 
 * OUT endpoint
 */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT 0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
 * 
 * Reserved
 */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_MSB        31
/* The width in bits of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_WIDTH      32
/* The mask used to set the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG1_GHWCFG1 field value from a register. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GHWCFG1.
 */
struct ALT_USB_GLOB_GHWCFG1_s
{
    const uint32_t  ghwcfg1 : 32;  /* Endpoint Direction */
};

/* The typedef declaration for register ALT_USB_GLOB_GHWCFG1. */
typedef volatile struct ALT_USB_GLOB_GHWCFG1_s  ALT_USB_GLOB_GHWCFG1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GHWCFG1 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG1_OFST        0x44
/* The address of the ALT_USB_GLOB_GHWCFG1 register. */
#define ALT_USB_GLOB_GHWCFG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG1_OFST))

/*
 * Register : User HW Config2 Register - ghwcfg2
 * 
 * This register contains configuration options.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                       
 * :--------|:-------|:------|:---------------------------------------------------
 *  [2:0]   | R      | 0x0   | Mode of Operation                                 
 *  [4:3]   | R      | 0x2   | Architecture                                      
 *  [5]     | R      | 0x0   | Point-to-Point                                    
 *  [7:6]   | R      | 0x2   | High Speed PHY Interface Type                     
 *  [9:8]   | R      | 0x0   | Full Speed PHY Interface Type                     
 *  [13:10] | R      | 0xf   | Number of Device Endpoints                        
 *  [17:14] | R      | 0xf   | Number of Host Channels                           
 *  [18]    | R      | 0x1   | Periodic OUT Channels Supported in Host Mode      
 *  [19]    | R      | 0x1   | Dynamic FIFO Sizing Enabled                       
 *  [20]    | R      | 0x0   | Multi Processor Interrupt Enabled                 
 *  [21]    | ???    | 0x0   | *UNDEFINED*                                       
 *  [23:22] | R      | 0x2   | Non Periodic Request Queue Depth                  
 *  [25:24] | R      | 0x0   | Host Mode Periodic Request Queue Depth            
 *  [30:26] | R      | 0x8   | Device Mode IN Token Sequence Learning Queue Depth
 *  [31]    | ???    | 0x0   | *UNDEFINED*                                       
 * 
 */
/*
 * Field : Mode of Operation - otgmode
 * 
 * HNP- and SRP-Capable OTG (Device and Host).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP   | 0x0   | HNP- and SRP-Capable OTG (Host & Device        
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG   | 0x1   | SRP-Capable OTG (Host & Device)                
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP | 0x2   | Non-HNP and Non-SRP Capable OTG (Host & Device)
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD  | 0x3   | SRP-Capable Device                             
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD  | 0x4   | Non-OTG Device                                 
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH  | 0x5   | SRP-Capable Host                               
 *  ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH  | 0x6   | Non-OTG Host                                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * HNP- and SRP-Capable OTG (Host & Device
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * SRP-Capable OTG (Host & Device)
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG    0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * Non-HNP and Non-SRP Capable OTG (Host & Device)
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP  0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * SRP-Capable Device
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD   0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * Non-OTG Device
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD   0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * SRP-Capable Host
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH   0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
 * 
 * Non-OTG Host
 */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH   0x6

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_MSB        2
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_WIDTH      3
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET_MSK    0x00000007
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_CLR_MSK    0xfffffff8
/* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_OTGMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_GET(value) (((value) & 0x00000007) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG2_OTGMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET(value) (((value) << 0) & 0x00000007)

/*
 * Field : Architecture - otgarch
 * 
 * DMA Architecture.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description 
 * :--------------------------------------|:------|:-------------
 *  ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD | 0x2   | Internal DMA
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGARCH
 * 
 * Internal DMA
 */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD   0x2

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_MSB        4
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET_MSK    0x00000018
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_CLR_MSK    0xffffffe7
/* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_RESET      0x2
/* Extracts the ALT_USB_GLOB_GHWCFG2_OTGARCH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_GET(value) (((value) & 0x00000018) >> 3)
/* Produces a ALT_USB_GLOB_GHWCFG2_OTGARCH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET(value) (((value) << 3) & 0x00000018)

/*
 * Field : Point-to-Point - singpnt
 * 
 * Single Point Only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description            
 * :-------------------------------------------|:------|:------------------------
 *  ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT | 0x1   | Single-point applicatio
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_SINGPNT
 * 
 * Single-point applicatio
 */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_MSB        5
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_SINGPNT field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GHWCFG2_SINGPNT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : High Speed PHY Interface Type - hsphytype
 * 
 * Specifies the High Speed PHY in use.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                       
 * :--------------------------------------|:------|:-----------------------------------
 *  ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS | 0x0   | High-Speed interface not supported
 *  ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI | 0x2   | ULPI                              
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
 * 
 * High-Speed interface not supported
 */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
 * 
 * ULPI
 */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI   0x2

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_MSB        7
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET_MSK    0x000000c0
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_CLR_MSK    0xffffff3f
/* The reset value of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_RESET      0x2
/* Extracts the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_GET(value) (((value) & 0x000000c0) >> 6)
/* Produces a ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET(value) (((value) << 6) & 0x000000c0)

/*
 * Field : Full Speed PHY Interface Type - fsphytype
 * 
 * Specifies the Full Speed PHY in use.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED | 0x2   | ULPI Type  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_FSPHYTYPE
 * 
 * ULPI Type
 */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED  0x2

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_MSB        9
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET_MSK    0x00000300
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_CLR_MSK    0xfffffcff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_GET(value) (((value) & 0x00000300) >> 8)
/* Produces a ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET(value) (((value) << 8) & 0x00000300)

/*
 * Field : Number of Device Endpoints - numdeveps
 * 
 * The number of endpoints is 1 to 15 in Device mode in addition to control
 * endpoint 0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description  
 * :-----------------------------------------|:------|:--------------
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  0
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  1
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  2
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  3
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  4
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  5
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  6
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  7
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  8
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  9
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  10
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  11
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  12
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  13
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  14
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
 * 
 * End point  15
 */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_MSB        13
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET_MSK    0x00003c00
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_CLR_MSK    0xffffc3ff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_RESET      0xf
/* Extracts the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_GET(value) (((value) & 0x00003c00) >> 10)
/* Produces a ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET(value) (((value) << 10) & 0x00003c00)

/*
 * Field : Number of Host Channels - numhstchnl
 * 
 * Indicates the number of host channels supported by the core in Host mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description    
 * :-------------------------------------------|:------|:----------------
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0  | 0x0   | Host Channel 1 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1  | 0x1   | Host Channel 2 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2  | 0x2   | Host Channel 3 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3  | 0x3   | Host Channel 4 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4  | 0x4   | Host Channel 5 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5  | 0x5   | Host Channel 6 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6  | 0x6   | Host Channel 7 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7  | 0x7   | Host Channel 8 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8  | 0x8   | Host Channel 9 
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9  | 0x9   | Host Channel 10
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 | 0xa   | Host Channel 11
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 | 0xb   | Host Channel 12
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 | 0xc   | Host Channel 13
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 | 0xd   | Host Channel 14
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 | 0xe   | Host Channel 15
 *  ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 | 0xf   | Host Channel 16
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 1
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 2
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1   0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 3
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2   0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 4
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3   0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 5
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4   0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 6
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5   0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 7
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6   0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 8
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7   0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 9
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8   0x8
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 10
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9   0x9
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 11
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10  0xa
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 12
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11  0xb
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 13
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12  0xc
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 14
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13  0xd
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 15
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14  0xe
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
 * 
 * Host Channel 16
 */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15  0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_MSB        17
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET_MSK    0x0003c000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_CLR_MSK    0xfffc3fff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_RESET      0xf
/* Extracts the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_GET(value) (((value) & 0x0003c000) >> 14)
/* Produces a ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET(value) (((value) << 14) & 0x0003c000)

/*
 * Field : Periodic OUT Channels Supported in Host Mode - periosupport
 * 
 * Feature supported.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END | 0x1   | Periodic OUT Channels Supported in Host Mode
 * :                                        |       | Supported                                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT
 * 
 * Periodic OUT Channels Supported in Host Mode Supported
 */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_MSB        18
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Dynamic FIFO Sizing Enabled - dynfifosizing
 * 
 * Feature supported.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END | 0x1   | Dynamic FIFO Sizing Enabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING
 * 
 * Dynamic FIFO Sizing Enabled
 */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_MSB        19
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Multi Processor Interrupt Enabled - multiprocintrpt
 * 
 * Not implemented.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                         
 * :--------------------------------------------|:------|:-------------------------------------
 *  ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD | 0x0   | No Multi Processor Interrupt Enabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT
 * 
 * No Multi Processor Interrupt Enabled
 */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_MSB        20
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Non Periodic Request Queue Depth - nptxqdepth
 * 
 * Specifies the Non-periodic Request Queue depth, the maximum number of packets
 * that can reside in the Non-periodic TxFIFO.
 * 
 * In Device mode, the queue is used only in Shared FIFO Mode (Enable Dedicated
 * Transmit FIFO for device IN Endpoints? =No). In this mode, there is one entry in
 * the Non-periodic Request Queue for each packet in the Non-periodic TxFIFO.
 * 
 * In Host mode, this queue holds one entry corresponding to each IN or OUT
 * nonperiodic request. This queue is seven bits wide.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description
 * :----------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO   | 0x0   | Que size 2 
 *  ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR  | 0x1   | Que size 4 
 *  ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT | 0x2   | Que size 8 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
 * 
 * Que size 2
 */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
 * 
 * Que size 4
 */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR  0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
 * 
 * Que size 8
 */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT 0x2

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_MSB        23
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET_MSK    0x00c00000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_CLR_MSK    0xff3fffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_RESET      0x2
/* Extracts the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_GET(value) (((value) & 0x00c00000) >> 22)
/* Produces a ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET(value) (((value) << 22) & 0x00c00000)

/*
 * Field : Host Mode Periodic Request Queue Depth - ptxqdepth
 * 
 * Specifies the Host mode Periodic Request Queue depth.That is, the maximum number
 * of packets that can reside in the Host Periodic TxFIFO. This queue holds one
 * entry corresponding to each IN or OUT periodic request. This queue is 9 bits
 * wide.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description 
 * :---------------------------------------|:------|:-------------
 *  ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2  | 0x0   | Que Depth 2 
 *  ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4  | 0x1   | Que Depth 4 
 *  ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8  | 0x2   | Que Depth 8 
 *  ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 | 0x3   | Que Depth 16
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
 * 
 * Que Depth 2
 */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
 * 
 * Que Depth 4
 */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4   0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
 * 
 * Que Depth 8
 */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8   0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
 * 
 * Que Depth 16
 */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16  0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_MSB        25
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET_MSK    0x03000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_CLR_MSK    0xfcffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_GET(value) (((value) & 0x03000000) >> 24)
/* Produces a ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET(value) (((value) << 24) & 0x03000000)

/*
 * Field : Device Mode IN Token Sequence Learning Queue Depth - tknqdepth
 * 
 * Range: 0 to 30.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_MSB        30
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_WIDTH      5
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET_MSK    0x7c000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_CLR_MSK    0x83ffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_RESET      0x8
/* Extracts the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_GET(value) (((value) & 0x7c000000) >> 26)
/* Produces a ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET(value) (((value) << 26) & 0x7c000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GHWCFG2.
 */
struct ALT_USB_GLOB_GHWCFG2_s
{
    const uint32_t  otgmode         :  3;  /* Mode of Operation */
    const uint32_t  otgarch         :  2;  /* Architecture */
    const uint32_t  singpnt         :  1;  /* Point-to-Point */
    const uint32_t  hsphytype       :  2;  /* High Speed PHY Interface Type */
    const uint32_t  fsphytype       :  2;  /* Full Speed PHY Interface Type */
    const uint32_t  numdeveps       :  4;  /* Number of Device Endpoints */
    const uint32_t  numhstchnl      :  4;  /* Number of Host Channels */
    const uint32_t  periosupport    :  1;  /* Periodic OUT Channels Supported in Host Mode */
    const uint32_t  dynfifosizing   :  1;  /* Dynamic FIFO Sizing Enabled */
    const uint32_t  multiprocintrpt :  1;  /* Multi Processor Interrupt Enabled */
    uint32_t                        :  1;  /* *UNDEFINED* */
    const uint32_t  nptxqdepth      :  2;  /* Non Periodic Request Queue Depth */
    const uint32_t  ptxqdepth       :  2;  /* Host Mode Periodic Request Queue Depth */
    const uint32_t  tknqdepth       :  5;  /* Device Mode IN Token Sequence Learning Queue Depth */
    uint32_t                        :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_GHWCFG2. */
typedef volatile struct ALT_USB_GLOB_GHWCFG2_s  ALT_USB_GLOB_GHWCFG2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GHWCFG2 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG2_OFST        0x48
/* The address of the ALT_USB_GLOB_GHWCFG2 register. */
#define ALT_USB_GLOB_GHWCFG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG2_OFST))

/*
 * Register : User HW Config3 Register - ghwcfg3
 * 
 * This register contains the configuration options.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [3:0]   | R      | 0x8    | Width of Transfer Size Counters             
 *  [6:4]   | R      | 0x6    | Width of Packet Size Counters               
 *  [7]     | R      | 0x1    | OTG Function Enabled                        
 *  [8]     | R      | 0x0    | I2C Selection                               
 *  [9]     | R      | 0x1    | Vendor Control Interface Suppor             
 *  [10]    | R      | 0x0    | Optional Features Removed                   
 *  [11]    | R      | 0x0    | Reset Style for Clocked always Blocks in RTL
 *  [12]    | R      | 0x0    | OTG ADP Support                             
 *  [13]    | R      | 0x0    | OTG ENABLE HSIC                             
 *  [14]    | R      | 0x0    | OTG BC SUPPORT                              
 *  [15]    | R      | 0x0    | OTG ENABLE LPM                              
 *  [31:16] | R      | 0x1f80 | DFIFO Depth                                 
 * 
 */
/*
 * Field : Width of Transfer Size Counters - xfersizewidth
 * 
 * Width variable from 11 to 19 bits.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 | 0x0   | Width of Transfer Size Counter 11 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 | 0x1   | Width of Transfer Size Counter 12 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 | 0x2   | Width of Transfer Size Counter 13 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 | 0x3   | Width of Transfer Size Counter 14 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 | 0x4   | Width of Transfer Size Counter 15 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 | 0x5   | Width of Transfer Size Counter 16 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 | 0x6   | Width of Transfer Size Counter 17 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 | 0x7   | Width of Transfer Size Counter 18 bits
 *  ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 | 0x8   | Width of Transfer Size Counter 19 bits
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 11 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11    0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 12 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12    0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 13 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13    0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 14 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14    0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 15 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15    0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 16 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16    0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 17 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17    0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 18 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18    0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
 * 
 * Width of Transfer Size Counter 19 bits
 */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19    0x8

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_MSB        3
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET_MSK    0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_CLR_MSK    0xfffffff0
/* The reset value of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_RESET      0x8
/* Extracts the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET(value) (((value) << 0) & 0x0000000f)

/*
 * Field : Width of Packet Size Counters - pktsizewidth
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                    
 * :-------------------------------------------|:------|:--------------------------------
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4  | 0x0   | Width of Packet Size Counter 4 
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5  | 0x1   | Width of Packet Size Counter 5 
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6  | 0x2   | Width of Packet Size Counter 6 
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7  | 0x3   | Width of Packet Size Counter 7 
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8  | 0x4   | Width of Packet Size Counter 8 
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9  | 0x5   | Width of Packet Size Counter 9 
 *  ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 | 0x6   | Width of Packet Size Counter 10
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 4
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 5
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5   0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 6
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6   0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 7
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7   0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 8
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8   0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 9
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9   0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
 * 
 * Width of Packet Size Counter 10
 */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10  0x6

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_MSB        6
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_WIDTH      3
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET_MSK    0x00000070
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_CLR_MSK    0xffffff8f
/* The reset value of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_RESET      0x6
/* Extracts the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_GET(value) (((value) & 0x00000070) >> 4)
/* Produces a ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET(value) (((value) << 4) & 0x00000070)

/*
 * Field : OTG Function Enabled - otgen
 * 
 * HNP and SRP Capable OTG (Device and Host)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description
 * :---------------------------------|:------|:------------
 *  ALT_USB_GLOB_GHWCFG3_OTGEN_E_END | 0x1   | OTG Capable
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OTGEN
 * 
 * OTG Capable
 */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_MSB        7
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG3_OTGEN field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GHWCFG3_OTGEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : I2C Selection - i2cintsel
 * 
 * I2C Interface not used.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD | 0x0   | I2C Interface
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_I2CINTSEL
 * 
 * I2C Interface
 */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_MSB        8
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_I2CINTSEL field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Vendor Control Interface Suppor - vndctlsupt
 * 
 * ULPI  PHY internal registers can be accessed by software using register
 * reads/writes to otg
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                     
 * :--------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END | 0x1   | Vendor Control Interface is not available on the
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT
 * 
 * Vendor Control Interface is not available on the
 */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_MSB        9
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Optional Features Removed - optfeature
 * 
 * User ID register, GPIO interface ports, and SOF toggle and counter ports were
 * removed.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD | 0x0   | No Optional features
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OPTFEATURE
 * 
 * No Optional features
 */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_MSB        10
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_OPTFEATURE field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Reset Style for Clocked always Blocks in RTL - rsttype
 * 
 * Defines what reset type is used in the core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                           
 * :-----------------------------------|:------|:---------------------------------------
 *  ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END | 0x0   | Asynchronous reset is used in the core
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_RSTTYPE
 * 
 * Asynchronous reset is used in the core
 */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_MSB        11
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_RSTTYPE field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : OTG ADP Support - adpsupport
 * 
 * ADP logic support.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                     
 * :--------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END | 0x1   | ADP logic is present along with HSOTG controller
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_ADPSUPPORT
 * 
 * ADP logic is present along with HSOTG controller
 */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_MSB        12
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : OTG ENABLE HSIC - hsicmode
 * 
 * Supports HSIC and Non-HSIC Modes.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD | 0x0   | Non-HSIC-capable
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_HSICMOD
 * 
 * Non-HSIC-capable
 */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_MSB        13
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_HSICMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_GLOB_GHWCFG3_HSICMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : OTG BC SUPPORT - bcsupport
 * 
 * Battery Charger Support.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description               
 * :--------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD | 0x0   | No Battery Charger Support
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_BCSUPPORT
 * 
 * No Battery Charger Support
 */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_MSB        14
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_BCSUPPORT field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : OTG ENABLE LPM - lpmmode
 * 
 * LPM Mode Enabled/Disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD | 0x0   | LPM disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_LPMMOD
 * 
 * LPM disabled
 */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_MSB        15
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_LPMMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_GLOB_GHWCFG3_LPMMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : DFIFO Depth - dfifodepth
 * 
 * DFIFO Depth. This value is in terms of 35-bit words.
 * 
 * Minimum value is 32
 * 
 * Maximum value is 8192
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_MSB        31
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET_MSK    0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_CLR_MSK    0x0000ffff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_RESET      0x1f80
/* Extracts the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GHWCFG3.
 */
struct ALT_USB_GLOB_GHWCFG3_s
{
    const uint32_t  xfersizewidth :  4;  /* Width of Transfer Size Counters */
    const uint32_t  pktsizewidth  :  3;  /* Width of Packet Size Counters */
    const uint32_t  otgen         :  1;  /* OTG Function Enabled */
    const uint32_t  i2cintsel     :  1;  /* I2C Selection */
    const uint32_t  vndctlsupt    :  1;  /* Vendor Control Interface Suppor */
    const uint32_t  optfeature    :  1;  /* Optional Features Removed */
    const uint32_t  rsttype       :  1;  /* Reset Style for Clocked always Blocks in RTL */
    const uint32_t  adpsupport    :  1;  /* OTG ADP Support */
    const uint32_t  hsicmode      :  1;  /* OTG ENABLE HSIC */
    const uint32_t  bcsupport     :  1;  /* OTG BC SUPPORT */
    const uint32_t  lpmmode       :  1;  /* OTG ENABLE LPM */
    const uint32_t  dfifodepth    : 16;  /* DFIFO Depth */
};

/* The typedef declaration for register ALT_USB_GLOB_GHWCFG3. */
typedef volatile struct ALT_USB_GLOB_GHWCFG3_s  ALT_USB_GLOB_GHWCFG3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GHWCFG3 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG3_OFST        0x4c
/* The address of the ALT_USB_GLOB_GHWCFG3 register. */
#define ALT_USB_GLOB_GHWCFG3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG3_OFST))

/*
 * Register : User HW Config4 Register - ghwcfg4
 * 
 * This register contains the configuration options.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                      
 * :--------|:-------|:------|:------------------------------------------------------------------
 *  [3:0]   | R      | 0x0   | Number of Device Mode Periodic IN Endpoints                      
 *  [4]     | R      | 0x0   | Enable Partial Power Down                                        
 *  [5]     | R      | 0x1   | Minimum AHB Frequency Less Than 60 MHz                           
 *  [6]     | R      | 0x0   | Enable Hibernation                                               
 *  [13:7]  | ???    | 0x0   | *UNDEFINED*                                                      
 *  [15:14] | R      | 0x0   | UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width              
 *  [19:16] | R      | 0xf   | Number of Device Mode Control Endpoints in Addition to Endpoint 0
 *  [20]    | R      | 0x0   | Iddig Filter Enable                                              
 *  [21]    | R      | 0x0   | Vbus Valid Filter Enabled                                        
 *  [22]    | R      | 0x0   | a_valid Filter                                                   
 *  [23]    | R      | 0x0   | b_valid Filter                                                   
 *  [24]    | R      | 0x0   | Session End Filter                                               
 *  [25]    | R      | 0x1   | Enable Dedicated Transmit FIFO for device IN Endpoints           
 *  [29:26] | R      | 0xf   | Number of Device Mode IN Endpoints Including Control             
 *  [30]    | R      | 0x1   | Scatter Gather DMA configuration                                 
 *  [31]    | R      | 0x1   | Scatter Gather DMA                                               
 * 
 */
/*
 * Field : Number of Device Mode Periodic IN Endpoints - numdevperioeps
 * 
 * The maximum number of device IN operations is 16 active at any time including
 * endpoint 0, which is always present. This parameter determines the number of
 * device mode Tx FIFOs to be instantiated.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_MSB        3
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET_MSK    0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_CLR_MSK    0xfffffff0
/* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET(value) (((value) << 0) & 0x0000000f)

/*
 * Field : Enable Partial Power Down - partialpwrdn
 * 
 * Specifies whether to enable power optimization.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD | 0x0   | Partial Power Down disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN
 * 
 * Partial Power Down disabled
 */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_MSB        4
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Minimum AHB Frequency Less Than 60 MHz - ahbfreq
 * 
 * When the AHB frequency is less than 60 MHz, 4-deep clock-domain crossing sink
 * and source buffers are instantiated between the MAC and the Packet FIFO
 * Controller (PFC); otherwise, two-deep buffers are sufficient.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                          
 * :-----------------------------------|:------|:--------------------------------------
 *  ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END | 0x1   | Minimum AHB Frequency Less Than 60 MH
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AHBFREQ
 * 
 * Minimum AHB Frequency Less Than 60 MH
 */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_MSB        5
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_AHBFREQ field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Enable Hibernation - hibernation
 * 
 * Enables power saving mode hibernation.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD | 0x0   | Hibernation feature disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_HIBERNATION
 * 
 * Hibernation feature disabled
 */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_MSB        6
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_HIBERNATION field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width - phydatawidth
 * 
 * Uses a ULPI interface only. Hence only 8-bit setting is relevant. This setting
 * should not matter since UTMI is not enabled.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_MSB        15
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_WIDTH      2
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Number of Device Mode Control Endpoints in Addition to Endpoint 0 - numctleps
 * 
 * Specifies the number of Device mode control endpoints in addition to control
 * endpoint 0, which is always present. Range: 0-15.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description  
 * :-----------------------------------------|:------|:--------------
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  0
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  1
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  2
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  3
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  4
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  5
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  6
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  7
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  8
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  9
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  10
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  11
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  12
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  13
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  14
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
 * 
 * End point  15
 */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_MSB        19
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET_MSK    0x000f0000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_CLR_MSK    0xfff0ffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_RESET      0xf
/* Extracts the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_GET(value) (((value) & 0x000f0000) >> 16)
/* Produces a ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET(value) (((value) << 16) & 0x000f0000)

/*
 * Field : Iddig Filter Enable - iddgfltr
 * 
 * Specifies whether to add a filter on the iddig input from the PHY. This is not
 * relevant since we only support ULPI and there is no iddig pin exposed to I/O
 * pads.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description          
 * :-------------------------------------|:------|:----------------------
 *  ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD | 0x0   | Iddig Filter Disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_IDDGFLTR
 * 
 * Iddig Filter Disabled
 */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_MSB        20
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_IDDGFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Vbus Valid Filter Enabled - vbusvalidfltr
 * 
 * Vbus Valid Filter Enabled (VBusValidFltr) 0: No filter 1: Filter(coreConsultant
 * parameter: OTG_EN_VBUSVALID_FILTER)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description               
 * :------------------------------------------|:------|:---------------------------
 *  ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD | 0x0   | Vbus Valid Filter Disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR
 * 
 * Vbus Valid Filter Disabled
 */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_MSB        21
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : a_valid Filter - avalidfltr
 * 
 * Specifies whether to add a filter on the b_valid input from the PHY.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description
 * :---------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD | 0x0   | No filter  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AVALIDFLTR
 * 
 * No filter
 */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_MSB        22
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : b_valid Filter - bvalidfltr
 * 
 * Specifies whether to add a filter on the b_valid input from the PHY.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description
 * :---------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD | 0x0   | No Filter  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_BVALIDFLTR
 * 
 * No Filter
 */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_MSB        23
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Session End Filter - sessendfltr
 * 
 * Specifies whether to add a filter on the session_end input from the PHY.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description
 * :----------------------------------------|:------|:------------
 *  ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD | 0x0   | No filter  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_SESSENDFLTR
 * 
 * No filter
 */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_MSB        24
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_RESET      0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Enable Dedicated Transmit FIFO for device IN Endpoints - dedfifomode
 * 
 * Specifies whether Dedicated Transmit FIFOs should be enabled in device mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                              
 * :--------------------------------------|:------|:------------------------------------------
 *  ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END | 0x1   | Dedicated Transmit FIFO Operation enabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD
 * 
 * Dedicated Transmit FIFO Operation enabled
 */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_MSB        25
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Number of Device Mode IN Endpoints Including Control - ineps
 * 
 * Number of Device Mode IN Endpoints Including Control.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description   
 * :-------------------------------------|:------|:---------------
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1  | 0x0   | In Endpoint 1 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2  | 0x1   | In Endpoint 2 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3  | 0x2   | In Endpoint 3 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4  | 0x3   | In Endpoint 4 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5  | 0x4   | In Endpoint 5 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6  | 0x5   | In Endpoint 6 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7  | 0x6   | In Endpoint 7 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8  | 0x7   | In Endpoint 8 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9  | 0x8   | In Endpoint 9 
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 | 0x9   | In Endpoint 10
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 | 0xa   | In Endpoint 11
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 | 0xb   | In Endpoint 12
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 | 0xc   | In Endpoint 13
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 | 0xd   | In Endpoint 14
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 | 0xe   | In Endpoint 15
 *  ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 | 0xf   | In Endpoint 16
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 1
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1     0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 2
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2     0x1
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 3
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3     0x2
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 4
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4     0x3
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 5
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5     0x4
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 6
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6     0x5
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 7
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7     0x6
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 8
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8     0x7
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 9
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9     0x8
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 10
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10    0x9
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 11
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11    0xa
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 12
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12    0xb
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 13
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13    0xc
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 14
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14    0xd
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 15
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15    0xe
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
 * 
 * In Endpoint 16
 */
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_MSB        29
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_WIDTH      4
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_SET_MSK    0x3c000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_CLR_MSK    0xc3ffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_RESET      0xf
/* Extracts the ALT_USB_GLOB_GHWCFG4_INEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_GET(value) (((value) & 0x3c000000) >> 26)
/* Produces a ALT_USB_GLOB_GHWCFG4_INEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_SET(value) (((value) << 26) & 0x3c000000)

/*
 * Field : Scatter Gather DMA configuration - dma_configuration
 * 
 * Selects bewteen scatter and nonscatter configuration
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                         
 * :------------------------------------------|:------|:-------------------------------------
 *  ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER | 0x0   | Non-Scatter/Gather DMA configuration
 *  ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER    | 0x1   | Scatter/Gather DMA configuration    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG
 * 
 * Non-Scatter/Gather DMA configuration
 */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER   0x0
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG
 * 
 * Scatter/Gather DMA configuration
 */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_MSB        30
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_DMA_CFG field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Scatter Gather DMA - dma
 * 
 * Enable descriptor based scatter/gather DMA.  When enabled, DMA operations will
 * be serviced with descriptor based scatter/gather DMA
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description          
 * :-------------------------------|:------|:----------------------
 *  ALT_USB_GLOB_GHWCFG4_DMA_E_END | 0x1   | Dynamic configuration
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA
 * 
 * Dynamic configuration
 */
#define ALT_USB_GLOB_GHWCFG4_DMA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_MSB        31
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_WIDTH      1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_RESET      0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_DMA field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GHWCFG4_DMA register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GHWCFG4.
 */
struct ALT_USB_GLOB_GHWCFG4_s
{
    const uint32_t  numdevperioeps    :  4;  /* Number of Device Mode Periodic IN Endpoints */
    const uint32_t  partialpwrdn      :  1;  /* Enable Partial Power Down */
    const uint32_t  ahbfreq           :  1;  /* Minimum AHB Frequency Less Than 60 MHz */
    const uint32_t  hibernation       :  1;  /* Enable Hibernation */
    uint32_t                          :  7;  /* *UNDEFINED* */
    const uint32_t  phydatawidth      :  2;  /* UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */
    const uint32_t  numctleps         :  4;  /* Number of Device Mode Control Endpoints in Addition to Endpoint 0 */
    const uint32_t  iddgfltr          :  1;  /* Iddig Filter Enable */
    const uint32_t  vbusvalidfltr     :  1;  /* Vbus Valid Filter Enabled */
    const uint32_t  avalidfltr        :  1;  /* a_valid Filter */
    const uint32_t  bvalidfltr        :  1;  /* b_valid Filter */
    const uint32_t  sessendfltr       :  1;  /* Session End Filter */
    const uint32_t  dedfifomode       :  1;  /* Enable Dedicated Transmit FIFO for device IN Endpoints */
    const uint32_t  ineps             :  4;  /* Number of Device Mode IN Endpoints Including Control */
    const uint32_t  dma_configuration :  1;  /* Scatter Gather DMA configuration */
    const uint32_t  dma               :  1;  /* Scatter Gather DMA */
};

/* The typedef declaration for register ALT_USB_GLOB_GHWCFG4. */
typedef volatile struct ALT_USB_GLOB_GHWCFG4_s  ALT_USB_GLOB_GHWCFG4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GHWCFG4 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG4_OFST        0x50
/* The address of the ALT_USB_GLOB_GHWCFG4 register. */
#define ALT_USB_GLOB_GHWCFG4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG4_OFST))

/*
 * Register : DFIFO Software Config Register - gdfifocfg
 * 
 * Specifies whether Dedicated Transmit FIFOs should be enabled in device mode.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description             
 * :--------|:-------|:-------|:-------------------------
 *  [15:0]  | RW     | 0x2000 | DFIFO Software Config   
 *  [31:16] | RW     | 0x1f80 | End Point Info Basr Addr
 * 
 */
/*
 * Field : DFIFO Software Config - gdfifocfg
 * 
 * This field is for dynamic programming of the DFIFO Size. This value takes effect
 * only when the application programs a non zero value to this register. The otg
 * core does not have any corrective logic if the FIFO sizes are programmed
 * incorrectly.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_MSB        15
/* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_RESET      0x2000
/* Extracts the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG field value from a register. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : End Point Info Basr Addr - epinfobaseaddr
 * 
 * This field provides the start address of the EP info controller.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_MSB        31
/* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET_MSK    0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_CLR_MSK    0x0000ffff
/* The reset value of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_RESET      0x1f80
/* Extracts the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR field value from a register. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_GDFIFOCFG.
 */
struct ALT_USB_GLOB_GDFIFOCFG_s
{
    uint32_t  gdfifocfg      : 16;  /* DFIFO Software Config */
    uint32_t  epinfobaseaddr : 16;  /* End Point Info Basr Addr */
};

/* The typedef declaration for register ALT_USB_GLOB_GDFIFOCFG. */
typedef volatile struct ALT_USB_GLOB_GDFIFOCFG_s  ALT_USB_GLOB_GDFIFOCFG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_GDFIFOCFG register from the beginning of the component. */
#define ALT_USB_GLOB_GDFIFOCFG_OFST        0x5c
/* The address of the ALT_USB_GLOB_GDFIFOCFG register. */
#define ALT_USB_GLOB_GDFIFOCFG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GDFIFOCFG_OFST))

/*
 * Register : Host Periodic Transmit FIFO Size Register - hptxfsiz
 * 
 * This register holds the size and the memory start address of the Periodic TxFIFO
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                       
 * :--------|:-------|:-------|:-----------------------------------
 *  [14:0]  | RW     | 0x4000 | Host Periodic TxFIFO Start Address
 *  [15]    | ???    | 0x0    | *UNDEFINED*                       
 *  [29:16] | RW     | 0x2000 | Host Periodic TxFIFO Depth        
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                       
 * 
 */
/*
 * Field : Host Periodic TxFIFO Start Address - ptxfstaddr
 * 
 * The power-on reset value of this register is the sum of the Largest Rx Data FIFO
 * Depth and Largest Non-periodic Tx Data FIFO. Programmed values must not exceed
 * the power-on value
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_MSB        14
/* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_WIDTH      15
/* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET_MSK    0x00007fff
/* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_CLR_MSK    0xffff8000
/* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_RESET      0x4000
/* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
/* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)

/*
 * Field : Host Periodic TxFIFO Depth - ptxfsize
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 1024
 * 
 * The power-on reset value of this register is specified as the 1024.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_MSB        29
/* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_RESET      0x2000
/* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE field value from a register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value suitable for setting the register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_HPTXFSIZ.
 */
struct ALT_USB_GLOB_HPTXFSIZ_s
{
    uint32_t  ptxfstaddr : 15;  /* Host Periodic TxFIFO Start Address */
    uint32_t             :  1;  /* *UNDEFINED* */
    uint32_t  ptxfsize   : 14;  /* Host Periodic TxFIFO Depth */
    uint32_t             :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_HPTXFSIZ. */
typedef volatile struct ALT_USB_GLOB_HPTXFSIZ_s  ALT_USB_GLOB_HPTXFSIZ_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_HPTXFSIZ register from the beginning of the component. */
#define ALT_USB_GLOB_HPTXFSIZ_OFST        0x100
/* The address of the ALT_USB_GLOB_HPTXFSIZ register. */
#define ALT_USB_GLOB_HPTXFSIZ_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_HPTXFSIZ_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 1 - dieptxf1
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [14:0]  | RW     | 0x4000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [15]    | ???    | 0x0    | *UNDEFINED*                                 
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 1.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_MSB        14
/* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_WIDTH      15
/* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET_MSK    0x00007fff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_CLR_MSK    0xffff8000
/* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_RESET      0x4000
/* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF1.
 */
struct ALT_USB_GLOB_DIEPTXF1_s
{
    uint32_t  inepntxfstaddr : 15;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t                 :  1;  /* *UNDEFINED* */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF1. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF1_s  ALT_USB_GLOB_DIEPTXF1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF1 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF1_OFST        0x104
/* The address of the ALT_USB_GLOB_DIEPTXF1 register. */
#define ALT_USB_GLOB_DIEPTXF1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF1_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 2 - dieptxf2
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for instantiated IN endpoint FIFO. For IN endpoint FIFO 0
 * use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [14:0]  | RW     | 0x6000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [15]    | ???    | 0x0    | *UNDEFINED*                                 
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 2.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_MSB        14
/* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_WIDTH      15
/* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET_MSK    0x00007fff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_CLR_MSK    0xffff8000
/* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_RESET      0x6000
/* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF2.
 */
struct ALT_USB_GLOB_DIEPTXF2_s
{
    uint32_t  inepntxfstaddr : 15;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t                 :  1;  /* *UNDEFINED* */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF2. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF2_s  ALT_USB_GLOB_DIEPTXF2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF2 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF2_OFST        0x108
/* The address of the ALT_USB_GLOB_DIEPTXF2 register. */
#define ALT_USB_GLOB_DIEPTXF2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF2_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 3 - dieptxf3
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for instantiated IN endpoint FIFO. For IN endpoint FIFO 0
 * use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0x8000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 3.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_RESET      0x8000
/* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.Minimum value is 16Maximum value is 8192
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF3.
 */
struct ALT_USB_GLOB_DIEPTXF3_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF3. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF3_s  ALT_USB_GLOB_DIEPTXF3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF3 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF3_OFST        0x10c
/* The address of the ALT_USB_GLOB_DIEPTXF3 register. */
#define ALT_USB_GLOB_DIEPTXF3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF3_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 4 - dieptxf4
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0xa000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 4.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_RESET      0xa000
/* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF4.
 */
struct ALT_USB_GLOB_DIEPTXF4_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF4. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF4_s  ALT_USB_GLOB_DIEPTXF4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF4 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF4_OFST        0x110
/* The address of the ALT_USB_GLOB_DIEPTXF4 register. */
#define ALT_USB_GLOB_DIEPTXF4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF4_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 5 - dieptxf5
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0xc000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 5.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_RESET      0xc000
/* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF5.
 */
struct ALT_USB_GLOB_DIEPTXF5_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF5. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF5_s  ALT_USB_GLOB_DIEPTXF5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF5 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF5_OFST        0x114
/* The address of the ALT_USB_GLOB_DIEPTXF5 register. */
#define ALT_USB_GLOB_DIEPTXF5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF5_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 6 - dieptxf6
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0xe000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 6.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_RESET      0xe000
/* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF6.
 */
struct ALT_USB_GLOB_DIEPTXF6_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF6. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF6_s  ALT_USB_GLOB_DIEPTXF6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF6 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF6_OFST        0x118
/* The address of the ALT_USB_GLOB_DIEPTXF6 register. */
#define ALT_USB_GLOB_DIEPTXF6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF6_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 7 - dieptxf7
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0x0    | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 7.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_RESET      0x0
/* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF7.
 */
struct ALT_USB_GLOB_DIEPTXF7_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF7. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF7_s  ALT_USB_GLOB_DIEPTXF7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF7 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF7_OFST        0x11c
/* The address of the ALT_USB_GLOB_DIEPTXF7 register. */
#define ALT_USB_GLOB_DIEPTXF7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF7_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 8 - dieptxf8
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0x2000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 8.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF8.
 */
struct ALT_USB_GLOB_DIEPTXF8_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF8. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF8_s  ALT_USB_GLOB_DIEPTXF8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF8 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF8_OFST        0x120
/* The address of the ALT_USB_GLOB_DIEPTXF8 register. */
#define ALT_USB_GLOB_DIEPTXF8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF8_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 9 - dieptxf9
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                
 * :--------|:-------|:-------|:--------------------------------------------
 *  [15:0]  | RW     | 0x4000 | IN Endpoint FIFOn Transmit RAM Start Addres
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                   
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Addres - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 9.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_RESET      0x4000
/* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF9.
 */
struct ALT_USB_GLOB_DIEPTXF9_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Addres */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF9. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF9_s  ALT_USB_GLOB_DIEPTXF9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF9 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF9_OFST        0x124
/* The address of the ALT_USB_GLOB_DIEPTXF9 register. */
#define ALT_USB_GLOB_DIEPTXF9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF9_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 10 - dieptxf10
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0x6000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 10.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_RESET      0x6000
/* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF10.
 */
struct ALT_USB_GLOB_DIEPTXF10_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF10. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF10_s  ALT_USB_GLOB_DIEPTXF10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF10 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF10_OFST        0x128
/* The address of the ALT_USB_GLOB_DIEPTXF10 register. */
#define ALT_USB_GLOB_DIEPTXF10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF10_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 11 - dieptxf11
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0x8000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 11.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_RESET      0x8000
/* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF11.
 */
struct ALT_USB_GLOB_DIEPTXF11_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF11. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF11_s  ALT_USB_GLOB_DIEPTXF11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF11 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF11_OFST        0x12c
/* The address of the ALT_USB_GLOB_DIEPTXF11 register. */
#define ALT_USB_GLOB_DIEPTXF11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF11_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 12 - dieptxf12
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0xa000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 12.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_RESET      0xa000
/* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF12.
 */
struct ALT_USB_GLOB_DIEPTXF12_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF12. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF12_s  ALT_USB_GLOB_DIEPTXF12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF12 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF12_OFST        0x130
/* The address of the ALT_USB_GLOB_DIEPTXF12 register. */
#define ALT_USB_GLOB_DIEPTXF12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF12_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 13 - dieptxf13
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0xc000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 13.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_RESET      0xc000
/* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF13.
 */
struct ALT_USB_GLOB_DIEPTXF13_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF13. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF13_s  ALT_USB_GLOB_DIEPTXF13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF13 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF13_OFST        0x134
/* The address of the ALT_USB_GLOB_DIEPTXF13 register. */
#define ALT_USB_GLOB_DIEPTXF13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF13_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 14 - dieptxf14
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0xe000 | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 14.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_RESET      0xe000
/* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF14.
 */
struct ALT_USB_GLOB_DIEPTXF14_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF14. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF14_s  ALT_USB_GLOB_DIEPTXF14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF14 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF14_OFST        0x138
/* The address of the ALT_USB_GLOB_DIEPTXF14 register. */
#define ALT_USB_GLOB_DIEPTXF14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF14_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Size Register 15 - dieptxf15
 * 
 * This register holds the size and memory start address of IN endpoint TxFIFOs
 * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This
 * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint
 * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                 
 * :--------|:-------|:-------|:---------------------------------------------
 *  [15:0]  | RW     | 0x0    | IN Endpoint FIFOn Transmit RAM Start Address
 *  [29:16] | RW     | 0x2000 | IN Endpoint TxFIFO Depth                    
 *  [31:30] | ???    | 0x0    | *UNDEFINED*                                 
 * 
 */
/*
 * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr
 * 
 * This field contains the memory start address for IN endpoint Transmit FIFO 15.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_MSB        15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_WIDTH      16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_RESET      0x0
/* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : IN Endpoint TxFIFO Depth - inepntxfdep
 * 
 * This value is in terms of 32-bit words.
 * 
 * Minimum value is 16
 * 
 * Maximum value is 8192.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_MSB        29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_WIDTH      14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET_MSK    0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_CLR_MSK    0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_RESET      0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_GLOB_DIEPTXF15.
 */
struct ALT_USB_GLOB_DIEPTXF15_s
{
    uint32_t  inepntxfstaddr : 16;  /* IN Endpoint FIFOn Transmit RAM Start Address */
    uint32_t  inepntxfdep    : 14;  /* IN Endpoint TxFIFO Depth */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF15. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF15_s  ALT_USB_GLOB_DIEPTXF15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_GLOB_DIEPTXF15 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF15_OFST        0x13c
/* The address of the ALT_USB_GLOB_DIEPTXF15 register. */
#define ALT_USB_GLOB_DIEPTXF15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF15_OFST))

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_USB_GLOB.
 */
struct ALT_USB_GLOB_s
{
    volatile ALT_USB_GLOB_GOTGCTL_t    gotgctl;             /* ALT_USB_GLOB_GOTGCTL */
    volatile ALT_USB_GLOB_GOTGINT_t    gotgint;             /* ALT_USB_GLOB_GOTGINT */
    volatile ALT_USB_GLOB_GAHBCFG_t    gahbcfg;             /* ALT_USB_GLOB_GAHBCFG */
    volatile ALT_USB_GLOB_GUSBCFG_t    gusbcfg;             /* ALT_USB_GLOB_GUSBCFG */
    volatile ALT_USB_GLOB_GRSTCTL_t    grstctl;             /* ALT_USB_GLOB_GRSTCTL */
    volatile ALT_USB_GLOB_GINTSTS_t    gintsts;             /* ALT_USB_GLOB_GINTSTS */
    volatile ALT_USB_GLOB_GINTMSK_t    gintmsk;             /* ALT_USB_GLOB_GINTMSK */
    volatile ALT_USB_GLOB_GRXSTSR_t    grxstsr;             /* ALT_USB_GLOB_GRXSTSR */
    volatile ALT_USB_GLOB_GRXSTSP_t    grxstsp;             /* ALT_USB_GLOB_GRXSTSP */
    volatile ALT_USB_GLOB_GRXFSIZ_t    grxfsiz;             /* ALT_USB_GLOB_GRXFSIZ */
    volatile ALT_USB_GLOB_GNPTXFSIZ_t  gnptxfsiz;           /* ALT_USB_GLOB_GNPTXFSIZ */
    volatile ALT_USB_GLOB_GNPTXSTS_t   gnptxsts;            /* ALT_USB_GLOB_GNPTXSTS */
    volatile uint32_t                  _pad_0x30_0x33;      /* *UNDEFINED* */
    volatile ALT_USB_GLOB_GPVNDCTL_t   gpvndctl;            /* ALT_USB_GLOB_GPVNDCTL */
    volatile ALT_USB_GLOB_GGPIO_t      ggpio;               /* ALT_USB_GLOB_GGPIO */
    volatile ALT_USB_GLOB_GUID_t       guid;                /* ALT_USB_GLOB_GUID */
    volatile ALT_USB_GLOB_GSNPSID_t    gsnpsid;             /* ALT_USB_GLOB_GSNPSID */
    volatile ALT_USB_GLOB_GHWCFG1_t    ghwcfg1;             /* ALT_USB_GLOB_GHWCFG1 */
    volatile ALT_USB_GLOB_GHWCFG2_t    ghwcfg2;             /* ALT_USB_GLOB_GHWCFG2 */
    volatile ALT_USB_GLOB_GHWCFG3_t    ghwcfg3;             /* ALT_USB_GLOB_GHWCFG3 */
    volatile ALT_USB_GLOB_GHWCFG4_t    ghwcfg4;             /* ALT_USB_GLOB_GHWCFG4 */
    volatile uint32_t                  _pad_0x54_0x5b[2];   /* *UNDEFINED* */
    volatile ALT_USB_GLOB_GDFIFOCFG_t  gdfifocfg;           /* ALT_USB_GLOB_GDFIFOCFG */
    volatile uint32_t                  _pad_0x60_0xff[40];  /* *UNDEFINED* */
    volatile ALT_USB_GLOB_HPTXFSIZ_t   hptxfsiz;            /* ALT_USB_GLOB_HPTXFSIZ */
    volatile ALT_USB_GLOB_DIEPTXF1_t   dieptxf1;            /* ALT_USB_GLOB_DIEPTXF1 */
    volatile ALT_USB_GLOB_DIEPTXF2_t   dieptxf2;            /* ALT_USB_GLOB_DIEPTXF2 */
    volatile ALT_USB_GLOB_DIEPTXF3_t   dieptxf3;            /* ALT_USB_GLOB_DIEPTXF3 */
    volatile ALT_USB_GLOB_DIEPTXF4_t   dieptxf4;            /* ALT_USB_GLOB_DIEPTXF4 */
    volatile ALT_USB_GLOB_DIEPTXF5_t   dieptxf5;            /* ALT_USB_GLOB_DIEPTXF5 */
    volatile ALT_USB_GLOB_DIEPTXF6_t   dieptxf6;            /* ALT_USB_GLOB_DIEPTXF6 */
    volatile ALT_USB_GLOB_DIEPTXF7_t   dieptxf7;            /* ALT_USB_GLOB_DIEPTXF7 */
    volatile ALT_USB_GLOB_DIEPTXF8_t   dieptxf8;            /* ALT_USB_GLOB_DIEPTXF8 */
    volatile ALT_USB_GLOB_DIEPTXF9_t   dieptxf9;            /* ALT_USB_GLOB_DIEPTXF9 */
    volatile ALT_USB_GLOB_DIEPTXF10_t  dieptxf10;           /* ALT_USB_GLOB_DIEPTXF10 */
    volatile ALT_USB_GLOB_DIEPTXF11_t  dieptxf11;           /* ALT_USB_GLOB_DIEPTXF11 */
    volatile ALT_USB_GLOB_DIEPTXF12_t  dieptxf12;           /* ALT_USB_GLOB_DIEPTXF12 */
    volatile ALT_USB_GLOB_DIEPTXF13_t  dieptxf13;           /* ALT_USB_GLOB_DIEPTXF13 */
    volatile ALT_USB_GLOB_DIEPTXF14_t  dieptxf14;           /* ALT_USB_GLOB_DIEPTXF14 */
    volatile ALT_USB_GLOB_DIEPTXF15_t  dieptxf15;           /* ALT_USB_GLOB_DIEPTXF15 */
};

/* The typedef declaration for register group ALT_USB_GLOB. */
typedef volatile struct ALT_USB_GLOB_s  ALT_USB_GLOB_t;
/* The struct declaration for the raw register contents of register group ALT_USB_GLOB. */
struct ALT_USB_GLOB_raw_s
{
    volatile uint32_t  gotgctl;             /* ALT_USB_GLOB_GOTGCTL */
    volatile uint32_t  gotgint;             /* ALT_USB_GLOB_GOTGINT */
    volatile uint32_t  gahbcfg;             /* ALT_USB_GLOB_GAHBCFG */
    volatile uint32_t  gusbcfg;             /* ALT_USB_GLOB_GUSBCFG */
    volatile uint32_t  grstctl;             /* ALT_USB_GLOB_GRSTCTL */
    volatile uint32_t  gintsts;             /* ALT_USB_GLOB_GINTSTS */
    volatile uint32_t  gintmsk;             /* ALT_USB_GLOB_GINTMSK */
    volatile uint32_t  grxstsr;             /* ALT_USB_GLOB_GRXSTSR */
    volatile uint32_t  grxstsp;             /* ALT_USB_GLOB_GRXSTSP */
    volatile uint32_t  grxfsiz;             /* ALT_USB_GLOB_GRXFSIZ */
    volatile uint32_t  gnptxfsiz;           /* ALT_USB_GLOB_GNPTXFSIZ */
    volatile uint32_t  gnptxsts;            /* ALT_USB_GLOB_GNPTXSTS */
    volatile uint32_t  _pad_0x30_0x33;      /* *UNDEFINED* */
    volatile uint32_t  gpvndctl;            /* ALT_USB_GLOB_GPVNDCTL */
    volatile uint32_t  ggpio;               /* ALT_USB_GLOB_GGPIO */
    volatile uint32_t  guid;                /* ALT_USB_GLOB_GUID */
    volatile uint32_t  gsnpsid;             /* ALT_USB_GLOB_GSNPSID */
    volatile uint32_t  ghwcfg1;             /* ALT_USB_GLOB_GHWCFG1 */
    volatile uint32_t  ghwcfg2;             /* ALT_USB_GLOB_GHWCFG2 */
    volatile uint32_t  ghwcfg3;             /* ALT_USB_GLOB_GHWCFG3 */
    volatile uint32_t  ghwcfg4;             /* ALT_USB_GLOB_GHWCFG4 */
    volatile uint32_t  _pad_0x54_0x5b[2];   /* *UNDEFINED* */
    volatile uint32_t  gdfifocfg;           /* ALT_USB_GLOB_GDFIFOCFG */
    volatile uint32_t  _pad_0x60_0xff[40];  /* *UNDEFINED* */
    volatile uint32_t  hptxfsiz;            /* ALT_USB_GLOB_HPTXFSIZ */
    volatile uint32_t  dieptxf1;            /* ALT_USB_GLOB_DIEPTXF1 */
    volatile uint32_t  dieptxf2;            /* ALT_USB_GLOB_DIEPTXF2 */
    volatile uint32_t  dieptxf3;            /* ALT_USB_GLOB_DIEPTXF3 */
    volatile uint32_t  dieptxf4;            /* ALT_USB_GLOB_DIEPTXF4 */
    volatile uint32_t  dieptxf5;            /* ALT_USB_GLOB_DIEPTXF5 */
    volatile uint32_t  dieptxf6;            /* ALT_USB_GLOB_DIEPTXF6 */
    volatile uint32_t  dieptxf7;            /* ALT_USB_GLOB_DIEPTXF7 */
    volatile uint32_t  dieptxf8;            /* ALT_USB_GLOB_DIEPTXF8 */
    volatile uint32_t  dieptxf9;            /* ALT_USB_GLOB_DIEPTXF9 */
    volatile uint32_t  dieptxf10;           /* ALT_USB_GLOB_DIEPTXF10 */
    volatile uint32_t  dieptxf11;           /* ALT_USB_GLOB_DIEPTXF11 */
    volatile uint32_t  dieptxf12;           /* ALT_USB_GLOB_DIEPTXF12 */
    volatile uint32_t  dieptxf13;           /* ALT_USB_GLOB_DIEPTXF13 */
    volatile uint32_t  dieptxf14;           /* ALT_USB_GLOB_DIEPTXF14 */
    volatile uint32_t  dieptxf15;           /* ALT_USB_GLOB_DIEPTXF15 */
};

/* The typedef declaration for the raw register contents of register group ALT_USB_GLOB. */
typedef volatile struct ALT_USB_GLOB_raw_s  ALT_USB_GLOB_raw_t;
#endif  /* __ASSEMBLY__ */


/*
 * Register Group : Host Mode Registers - ALT_USB_HOST
 * Host Mode Registers
 * 
 * These registers must be programmed every time the USB OTG Controller changes to
 * Host mode.
 * 
 */
/*
 * Register : Host Configuration Register - hcfg
 * 
 * Host Mode control. This register must be programmed every time the core changes
 * to Host mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [1:0]   | RW     | 0x0   | FS LS PHY Clock Select                
 *  [2]     | RW     | 0x0   | FS- and LS-Only Suppor                
 *  [6:3]   | ???    | 0x0   | *UNDEFINED*                           
 *  [7]     | RW     | 0x0   | Enable 32 KHz Suspend mode            
 *  [15:8]  | RW     | 0x2   | Resume Validation Period              
 *  [22:16] | ???    | 0x0   | *UNDEFINED*                           
 *  [23]    | RW     | 0x0   | Enable Scatter Gather DMA in Host mode
 *  [25:24] | RW     | 0x0   | Frame List Entries                    
 *  [26]    | RW     | 0x0   | Enable Periodic Scheduling            
 *  [30:27] | ???    | 0x0   | *UNDEFINED*                           
 *  [31]    | RW     | 0x0   | Mode Change Ready Timer Enable        
 * 
 */
/*
 * Field : FS LS PHY Clock Select - fslspclksel
 * 
 * When the core is in FS Host mode. The internal PHY clock is running at 30/60 MHZ
 * for ULPI PHY Interfaces. The internal PHY clock is running at 48MHZ for 1.1 FS
 * transceiver Interface When the core is in LS Host mode, the internal PHY clock
 * is running at 30/60 MHZ for ULPI PHY Interfaces. The internal PHY clock is
 * running at 6 MHZ and the external clock is running at 48MHZ. When you select a 6
 * MHz clock during LS Mode, you must do a soft reset for 1.1 FS transceiver
 * Interface. * When Core in FS mode, the internal and external clocks have the
 * same frequency.
 * 
 * * When Core in LS mode,
 * 
 *     - If fslspclksel is 30/60 Mhz internal and external clocks have the same
 *       frequency.
 * 
 *     - If fslspclksel is 6Mhz the internal clock is divided by eight of external
 *       48 MHz clock (utmifs_clk).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                      
 * :----------------------------------------|:------|:----------------------------------
 *  ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 | 0x0   | PHY clock is running at 30/60 MHz
 *  ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48   | 0x1   | PHY clock is running at 48 MHz   
 *  ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6    | 0x2   | PHY clock is running at 6 MHz    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
 * 
 * PHY clock is running at 30/60 MHz
 */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
 * 
 * PHY clock is running at 48 MHz
 */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
 * 
 * PHY clock is running at 6 MHz
 */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6    0x2

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_MSB        1
/* The width in bits of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET_MSK    0x00000003
/* The mask used to clear the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_CLR_MSK    0xfffffffc
/* The reset value of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_FSLSPCLKSEL field value from a register. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET(value) (((value) << 0) & 0x00000003)

/*
 * Field : FS- and LS-Only Suppor - fslssupp
 * 
 * The application uses this bit to control the core's enumeration speed. Using
 * this bit, the application can make the core enumerate as a FS host, even If the
 * connected device supports HS traffic. Do not make changes to this field after
 * initial programming.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                   
 * :------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS | 0x0   | HS/FS/LS, based on the maximum speed supported
 * :                                    |       | by the connected device                       
 *  ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS   | 0x1   | FS/LS-only, even if the connected device can  
 * :                                    |       | support HS                                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP
 * 
 * HS/FS/LS, based on the maximum speed supported by the connected device
 */
#define ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP
 * 
 * FS/LS-only, even if the connected device can support HS
 */
#define ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_MSB        2
/* The width in bits of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_FSLSSUPP field value from a register. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCFG_FSLSSUPP register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Enable 32 KHz Suspend mode - ena32khzs
 * 
 * This bit can only be set if the USB 1.1 Full-Speed Serial Transceiver Interface
 * has been selected. If USB 1.1 Full-Speed Serial Transceiver Interface has not
 * been selected, this bit must be zero. When the USB 1.1 Full-Speed Serial
 * Transceiver Interface is chosen and this bit is set, the core expects the 48-MHz
 * PHY clock to be switched to 32 KHz during a suspend.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                    
 * :-----------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD | 0x0   | USB 1.1 Full-Speed Not Selected                
 *  ALT_USB_HOST_HCFG_ENA32KHZS_E_END  | 0x1   | USB 1.1 Full-Speed Serial Transceiver Interface
 * :                                   |       | selected                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS
 * 
 * USB 1.1 Full-Speed Not Selected
 */
#define ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS
 * 
 * USB 1.1 Full-Speed Serial Transceiver Interface selected
 */
#define ALT_USB_HOST_HCFG_ENA32KHZS_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_MSB        7
/* The width in bits of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_ENA32KHZS field value from a register. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCFG_ENA32KHZS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Resume Validation Period - resvalid
 * 
 * This field is effective only when HCFG.Ena32KHzS is set. It will control the
 * resume period when the core resumes from suspend. The core counts for ResValid
 * number of clock cycles to detect a valid resume when this is set.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_MSB        15
/* The width in bits of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_WIDTH      8
/* The mask used to set the ALT_USB_HOST_HCFG_RESVALID register field value. */
#define ALT_USB_HOST_HCFG_RESVALID_SET_MSK    0x0000ff00
/* The mask used to clear the ALT_USB_HOST_HCFG_RESVALID register field value. */
#define ALT_USB_HOST_HCFG_RESVALID_CLR_MSK    0xffff00ff
/* The reset value of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_RESET      0x2
/* Extracts the ALT_USB_HOST_HCFG_RESVALID field value from a register. */
#define ALT_USB_HOST_HCFG_RESVALID_GET(value) (((value) & 0x0000ff00) >> 8)
/* Produces a ALT_USB_HOST_HCFG_RESVALID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_RESVALID_SET(value) (((value) << 8) & 0x0000ff00)

/*
 * Field : Enable Scatter Gather DMA in Host mode - descdma
 * 
 * The application can set this bit during initialization to enable the
 * Scatter/Gather DMA operation. This bit must be modified only once after a reset.
 * The following combinations are available for programming:
 * 
 * GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode GAHBCFG.DMAEn=0,HCFG.DescDMA=1 =>
 * InvalidGAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode
 * GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                
 * :---------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCFG_DESCDMA_E_DISD | 0x0   | No Scatter/Gather DMA      
 *  ALT_USB_HOST_HCFG_DESCDMA_E_END  | 0x1   | Scatter/Gather DMA selected
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA
 * 
 * No Scatter/Gather DMA
 */
#define ALT_USB_HOST_HCFG_DESCDMA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA
 * 
 * Scatter/Gather DMA selected
 */
#define ALT_USB_HOST_HCFG_DESCDMA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_MSB        23
/* The width in bits of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCFG_DESCDMA register field value. */
#define ALT_USB_HOST_HCFG_DESCDMA_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_HOST_HCFG_DESCDMA register field value. */
#define ALT_USB_HOST_HCFG_DESCDMA_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_DESCDMA field value from a register. */
#define ALT_USB_HOST_HCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_HOST_HCFG_DESCDMA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Frame List Entries - frlisten
 * 
 * The value in the register specifies the number of entries in the Frame list.
 * This field is valid only in Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD    | 0x0   | Reserved   
 *  ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8  | 0x1   | 8  Entries 
 *  ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 | 0x2   | 16 Entries 
 *  ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 | 0x3   | 32 Entries 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
 * 
 * Reserved
 */
#define ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
 * 
 * 8  Entries
 */
#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
 * 
 * 16 Entries
 */
#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
 * 
 * 32 Entries
 */
#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_MSB        25
/* The width in bits of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCFG_FRLISTEN register field value. */
#define ALT_USB_HOST_HCFG_FRLISTEN_SET_MSK    0x03000000
/* The mask used to clear the ALT_USB_HOST_HCFG_FRLISTEN register field value. */
#define ALT_USB_HOST_HCFG_FRLISTEN_CLR_MSK    0xfcffffff
/* The reset value of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_FRLISTEN field value from a register. */
#define ALT_USB_HOST_HCFG_FRLISTEN_GET(value) (((value) & 0x03000000) >> 24)
/* Produces a ALT_USB_HOST_HCFG_FRLISTEN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_FRLISTEN_SET(value) (((value) << 24) & 0x03000000)

/*
 * Field : Enable Periodic Scheduling - perschedena
 * 
 * Applicable in Scatter/Gather DMA mode only. Enables periodic scheduling within
 * the core. Initially, the bit is reset. The core will not process any periodic
 * channels. As soon as this bit is set, the core will get ready to start
 * scheduling periodic channels. In non Scatter/Gather DMA mode, this bit is
 * reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                 
 * :-------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD | 0x0   | Disables periodic scheduling within the core
 *  ALT_USB_HOST_HCFG_PERSCHEDENA_E_END  | 0x1   | Enables periodic scheduling within the core 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA
 * 
 * Disables periodic scheduling within the core
 */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA
 * 
 * Enables periodic scheduling within the core
 */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_MSB        26
/* The width in bits of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_PERSCHEDENA field value from a register. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_HOST_HCFG_PERSCHEDENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mode Change Ready Timer Enable - modechtimen
 * 
 * This bit is used to enable or disable the host core to wait for 200 PHY clock
 * cycles at the end of Resume to change the opmode signal to the PHY to 00 after
 * Suspend or LPM.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                    
 * :------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCFG_MODCHTIMEN_E_END  | 0x0   | The Host core waits for either 200 PHY clock   
 * :                                    |       | cycles or a linestate of SE0 at the end of     
 * :                                    |       | resume to change the opmode from 0x2 to 0x0    
 *  ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD | 0x1   | The Host core waits only for a linestate of SE0
 * :                                    |       | at the end of resume to change the opmode from 
 * :                                    |       | 0x2 to 0x0                                     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN
 * 
 * The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the
 * end of resume to change the opmode from 0x2 to 0x0
 */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_E_END  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN
 * 
 * The Host core waits only for a linestate of SE0 at the end of resume to change
 * the opmode from 0x2 to 0x0
 */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_MSB        31
/* The width in bits of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCFG_MODCHTIMEN field value from a register. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCFG_MODCHTIMEN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCFG.
 */
struct ALT_USB_HOST_HCFG_s
{
    uint32_t  fslspclksel :  2;  /* FS LS PHY Clock Select */
    uint32_t  fslssupp    :  1;  /* FS- and LS-Only Suppor */
    uint32_t              :  4;  /* *UNDEFINED* */
    uint32_t  ena32khzs   :  1;  /* Enable 32 KHz Suspend mode */
    uint32_t  resvalid    :  8;  /* Resume Validation Period */
    uint32_t              :  7;  /* *UNDEFINED* */
    uint32_t  descdma     :  1;  /* Enable Scatter Gather DMA in Host mode */
    uint32_t  frlisten    :  2;  /* Frame List Entries */
    uint32_t  perschedena :  1;  /* Enable Periodic Scheduling */
    uint32_t              :  4;  /* *UNDEFINED* */
    uint32_t  modechtimen :  1;  /* Mode Change Ready Timer Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCFG. */
typedef volatile struct ALT_USB_HOST_HCFG_s  ALT_USB_HOST_HCFG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCFG register from the beginning of the component. */
#define ALT_USB_HOST_HCFG_OFST        0x0
/* The address of the ALT_USB_HOST_HCFG register. */
#define ALT_USB_HOST_HCFG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCFG_OFST))

/*
 * Register : Host Frame Interval Register - hfir
 * 
 * This register stores the frame interval information for the current speed to
 * which the otg core has enumerated
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description   
 * :--------|:-------|:-------|:---------------
 *  [15:0]  | RW     | 0xea60 | Frame IntervaL
 *  [16]    | RW     | 0x0    | Reload Control
 *  [31:17] | ???    | 0x0    | *UNDEFINED*   
 * 
 */
/*
 * Field : Frame IntervaL - frint
 * 
 * The value that the application programs to this field specifies the interval
 * between two consecutive SOFs (FS) or micro- SOFs (HS) or Keep-Alive tokens (HS).
 * This field contains the number of PHY clocks that constitute the required frame
 * interval. The Default value Set in this field for a FS operation when the PHY
 * clock frequency is 60 MHz. The application can write a value to this register
 * only after the Port Enable bit of the Host Port Control and Status register
 * (HPRT.PrtEnaPort) has been Set. If no value is programmed, the core calculates
 * the value based on the PHY clock specified in the FS/LS PHY Clock Select field
 * of the Host Configuration register (HCFG.FSLSPclkSel). Do not change the value
 * of this field after the initial configuration.
 * 
 * 125 s * (PHY clock frequency for HS)
 * 
 * 1 ms * (PHY clock frequency for FS/LS)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_MSB        15
/* The width in bits of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_WIDTH      16
/* The mask used to set the ALT_USB_HOST_HFIR_FRINT register field value. */
#define ALT_USB_HOST_HFIR_FRINT_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HFIR_FRINT register field value. */
#define ALT_USB_HOST_HFIR_FRINT_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_RESET      0xea60
/* Extracts the ALT_USB_HOST_HFIR_FRINT field value from a register. */
#define ALT_USB_HOST_HFIR_FRINT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HFIR_FRINT register field value suitable for setting the register. */
#define ALT_USB_HOST_HFIR_FRINT_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Reload Control - hfirrldctrl
 * 
 * This bit allows dynamic reloading of the HFIR register during run time. 0x0 :
 * The HFIR cannot be reloaded dynamically0x1: the HFIR can be dynamically reloaded
 * during runtime. This bit needs to be programmed during initial configuration and
 * its value should not be changed during runtime.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                
 * :------------------------------------|:------|:--------------------------------------------
 *  ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD | 0x0   | The HFIR cannot be reloaded dynamically    
 *  ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END  | 0x1   | The HFIR can be dynamically reloaded during
 * :                                    |       | runtime                                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL
 * 
 * The HFIR cannot be reloaded dynamically
 */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL
 * 
 * The HFIR can be dynamically reloaded during runtime
 */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_MSB        16
/* The width in bits of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_RESET      0x0
/* Extracts the ALT_USB_HOST_HFIR_HFIRRLDCTL field value from a register. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HFIR_HFIRRLDCTL register field value suitable for setting the register. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET(value) (((value) << 16) & 0x00010000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HFIR.
 */
struct ALT_USB_HOST_HFIR_s
{
    uint32_t  frint       : 16;  /* Frame IntervaL */
    uint32_t  hfirrldctrl :  1;  /* Reload Control */
    uint32_t              : 15;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HFIR. */
typedef volatile struct ALT_USB_HOST_HFIR_s  ALT_USB_HOST_HFIR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HFIR register from the beginning of the component. */
#define ALT_USB_HOST_HFIR_OFST        0x4
/* The address of the ALT_USB_HOST_HFIR register. */
#define ALT_USB_HOST_HFIR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFIR_OFST))

/*
 * Register : Host Frame Number Frame Time Remaining Register - hfnum
 * 
 * This register contains the free space information for the Periodic TxFIFO and
 * the Periodic Transmit Request Queue
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | R      | 0x3fff | Frame Number        
 *  [31:16] | R      | 0x0    | Frame Time Remaining
 * 
 */
/*
 * Field : Frame Number - frnum
 * 
 * This field increments when a new SOF is transmitted on the USB, and is reset to
 * 0 when it reaches 0x3FFF. Reads Return the Frame number value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description          
 * :---------------------------------|:------|:----------------------
 *  ALT_USB_HOST_HFNUM_FRNUM_E_INACT | 0x0   | No SOF is transmitted
 *  ALT_USB_HOST_HFNUM_FRNUM_E_ACT   | 0x1   | SOF is transmitted   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM
 * 
 * No SOF is transmitted
 */
#define ALT_USB_HOST_HFNUM_FRNUM_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM
 * 
 * SOF is transmitted
 */
#define ALT_USB_HOST_HFNUM_FRNUM_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_MSB        15
/* The width in bits of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_WIDTH      16
/* The mask used to set the ALT_USB_HOST_HFNUM_FRNUM register field value. */
#define ALT_USB_HOST_HFNUM_FRNUM_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HFNUM_FRNUM register field value. */
#define ALT_USB_HOST_HFNUM_FRNUM_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_RESET      0x3fff
/* Extracts the ALT_USB_HOST_HFNUM_FRNUM field value from a register. */
#define ALT_USB_HOST_HFNUM_FRNUM_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HFNUM_FRNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HFNUM_FRNUM_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Frame Time Remaining - frrem
 * 
 * Indicates the amount of time remaining in the current microframe (HS) or Frame
 * (FS/LS), in terms of PHY clocks. This field decrements on each PHY clock. When
 * it reaches zero, this field is reloaded with the value in the Frame Interval
 * register and a new SOF is transmitted on the USB.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_MSB        31
/* The width in bits of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_WIDTH      16
/* The mask used to set the ALT_USB_HOST_HFNUM_FRREM register field value. */
#define ALT_USB_HOST_HFNUM_FRREM_SET_MSK    0xffff0000
/* The mask used to clear the ALT_USB_HOST_HFNUM_FRREM register field value. */
#define ALT_USB_HOST_HFNUM_FRREM_CLR_MSK    0x0000ffff
/* The reset value of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_RESET      0x0
/* Extracts the ALT_USB_HOST_HFNUM_FRREM field value from a register. */
#define ALT_USB_HOST_HFNUM_FRREM_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_HOST_HFNUM_FRREM register field value suitable for setting the register. */
#define ALT_USB_HOST_HFNUM_FRREM_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HFNUM.
 */
struct ALT_USB_HOST_HFNUM_s
{
    const uint32_t  frnum : 16;  /* Frame Number */
    const uint32_t  frrem : 16;  /* Frame Time Remaining */
};

/* The typedef declaration for register ALT_USB_HOST_HFNUM. */
typedef volatile struct ALT_USB_HOST_HFNUM_s  ALT_USB_HOST_HFNUM_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HFNUM register from the beginning of the component. */
#define ALT_USB_HOST_HFNUM_OFST        0x8
/* The address of the ALT_USB_HOST_HFNUM register. */
#define ALT_USB_HOST_HFNUM_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFNUM_OFST))

/*
 * Register : Host Periodic Transmit FIFO Queue Status Register - hptxsts
 * 
 * This register contains the free space information for the Periodic TxFIFO and
 * the Periodic Transmit Request Queue.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                                    
 * :--------|:-------|:-------|:------------------------------------------------
 *  [15:0]  | R      | 0x2000 | Periodic Transmit Data FIFO Space Available    
 *  [23:16] | R      | 0x10   | Periodic Transmit Request Queue Space Available
 *  [24]    | R      | 0x0    | Terminate                                      
 *  [26:25] | R      | 0x0    | Type                                           
 *  [30:27] | R      | 0x0    | Channel Endpoint Number                        
 *  [31]    | R      | 0x0    | Odd Even Micro Frame                           
 * 
 */
/*
 * Field : Periodic Transmit Data FIFO Space Available - ptxfspcavail
 * 
 * Indicates the number of free locations available to be written to in the
 * Periodic TxFIFO. Values are in terms of 32-bit words
 * 
 * 16h0: Periodic TxFIFO is full
 * 
 * 16h1: 1 word available
 * 
 * 16h2: 2 words available
 * 
 * 16hn: n words available where n is 0 to 8192
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL field value from a register. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Periodic Transmit Request Queue Space Available - ptxqspcavail
 * 
 * Indicates the number of free locations available to be written in the Periodic
 * Transmit Request Queue. This queue holds both IN and OUT requests. Others:
 * Reserved
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                            
 * :------------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL  | 0x0   | Periodic Transmit Request Queue is full
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 | 0x1   | 1 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 | 0x2   | 2 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 | 0x3   | 3 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 | 0x4   | 4 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 | 0x5   | 5 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 | 0x6   | 6 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 | 0x7   | 7 location available                   
 *  ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 | 0x8   | 8 location available                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * Periodic Transmit Request Queue is full
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 1 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 2 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 3 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3   0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 4 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4   0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 5 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5   0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 6 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6   0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 7 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7   0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
 * 
 * 8 location available
 */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8   0x8

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_MSB        23
/* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_WIDTH      8
/* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET_MSK    0x00ff0000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_CLR_MSK    0xff00ffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_RESET      0x10
/* Extracts the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL field value from a register. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16)
/* Produces a ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000)

/*
 * Field : Terminate - term
 * 
 * Terminate last entry for selected channel/endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                      
 * :----------------------------------|:------|:----------------------------------
 *  ALT_USB_HOST_HPTXSTS_TERM_E_INACT | 0x0   | No termination                   
 *  ALT_USB_HOST_HPTXSTS_TERM_E_ACT   | 0x1   | Terminate last entry for selected
 * :                                  |       | channel/endpoint                 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM
 * 
 * No termination
 */
#define ALT_USB_HOST_HPTXSTS_TERM_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM
 * 
 * Terminate last entry for selected channel/endpoint
 */
#define ALT_USB_HOST_HPTXSTS_TERM_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_MSB        24
/* The width in bits of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPTXSTS_TERM register field value. */
#define ALT_USB_HOST_HPTXSTS_TERM_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_TERM register field value. */
#define ALT_USB_HOST_HPTXSTS_TERM_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_RESET      0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_TERM field value from a register. */
#define ALT_USB_HOST_HPTXSTS_TERM_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_HOST_HPTXSTS_TERM register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_TERM_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Type - type
 * 
 * This indicates the Entry in the Periodic Tx Request Queue that is currently
 * being processes by the MAC.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description            
 * :--------------------------------------|:------|:------------------------
 *  ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT     | 0x0   | IN/OUT type            
 *  ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH | 0x1   | Zero-length packet type
 *  ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT    | 0x2   | CSPLIT type            
 *  ALT_USB_HOST_HPTXSTS_TYPE_E_DIS       | 0x3   | Disable channel command
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
 * 
 * IN/OUT type
 */
#define ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
 * 
 * Zero-length packet type
 */
#define ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
 * 
 * CSPLIT type
 */
#define ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
 * 
 * Disable channel command
 */
#define ALT_USB_HOST_HPTXSTS_TYPE_E_DIS         0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_MSB        26
/* The width in bits of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HPTXSTS_TYPE register field value. */
#define ALT_USB_HOST_HPTXSTS_TYPE_SET_MSK    0x06000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_TYPE register field value. */
#define ALT_USB_HOST_HPTXSTS_TYPE_CLR_MSK    0xf9ffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_TYPE field value from a register. */
#define ALT_USB_HOST_HPTXSTS_TYPE_GET(value) (((value) & 0x06000000) >> 25)
/* Produces a ALT_USB_HOST_HPTXSTS_TYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_TYPE_SET(value) (((value) << 25) & 0x06000000)

/*
 * Field : Channel Endpoint Number - chanendpt
 * 
 * This indicates the channel endpoint number that is currently being processes by
 * the MAC.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description  
 * :-----------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0  | 0x0   | End point  1 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1  | 0x1   | End point  2 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2  | 0x2   | End point  3 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3  | 0x3   | End point  4 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4  | 0x4   | End point  5 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5  | 0x5   | End point  6 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6  | 0x6   | End point  7 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7  | 0x7   | End point  8 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8  | 0x8   | End point  9 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9  | 0x9   | End point  10
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 | 0xa   | End point 11 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 | 0xb   | End point 12 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 | 0xc   | End point 13 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 | 0xd   | End point 14 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 | 0xe   | End point 15 
 *  ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 | 0xf   | End point 16 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  1
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  2
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  3
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  4
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  5
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  6
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  7
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  8
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  9
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point  10
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point 11
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point 12
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point 13
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point 14
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point 15
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
 * 
 * End point 16
 */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_MSB        30
/* The width in bits of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET_MSK    0x78000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_CLR_MSK    0x87ffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_RESET      0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_CHANENDPT field value from a register. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_GET(value) (((value) & 0x78000000) >> 27)
/* Produces a ALT_USB_HOST_HPTXSTS_CHANENDPT register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET(value) (((value) << 27) & 0x78000000)

/*
 * Field : Odd Even Micro Frame - oddevnmframe
 * 
 * This indicates the odd/even micro frame that is currently being processes by the
 * MAC.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description              
 * :---------------------------------------|:------|:--------------------------
 *  ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN | 0x0   | Send in even (micro)Frame
 *  ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD  | 0x1   | Send in odd (micro)Frame 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM
 * 
 * Send in even (micro)Frame
 */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM
 * 
 * Send in odd (micro)Frame
 */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_MSB        31
/* The width in bits of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_RESET      0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM field value from a register. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HPTXSTS.
 */
struct ALT_USB_HOST_HPTXSTS_s
{
    const uint32_t  ptxfspcavail : 16;  /* Periodic Transmit Data FIFO Space Available */
    const uint32_t  ptxqspcavail :  8;  /* Periodic Transmit Request Queue Space Available */
    const uint32_t  term         :  1;  /* Terminate */
    const uint32_t  type         :  2;  /* Type */
    const uint32_t  chanendpt    :  4;  /* Channel Endpoint Number */
    const uint32_t  oddevnmframe :  1;  /* Odd Even Micro Frame */
};

/* The typedef declaration for register ALT_USB_HOST_HPTXSTS. */
typedef volatile struct ALT_USB_HOST_HPTXSTS_s  ALT_USB_HOST_HPTXSTS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HPTXSTS register from the beginning of the component. */
#define ALT_USB_HOST_HPTXSTS_OFST        0x10
/* The address of the ALT_USB_HOST_HPTXSTS register. */
#define ALT_USB_HOST_HPTXSTS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPTXSTS_OFST))

/*
 * Register : Host All Channels Interrupt Register - haint
 * 
 * When a significant event occurs on a channel, the Host All Channels Interrupt
 * register interrupts the application using the Host Channels Interrupt bit of the
 * Core Interrupt register (GINTSTS.HChInt). There is one interrupt bit per
 * channel, up to a maximum of 16 bits. Bits in this register are set and cleared
 * when the application sets and clears bits in the corresponding Host Channel-n
 * Interrupt register.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [15:0]  | R      | 0x0   | Channel Interrupts
 *  [31:16] | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Channel Interrupts - haint
 * 
 * One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_MSB        15
/* The width in bits of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_WIDTH      16
/* The mask used to set the ALT_USB_HOST_HAINT_HAINT register field value. */
#define ALT_USB_HOST_HAINT_HAINT_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HAINT_HAINT register field value. */
#define ALT_USB_HOST_HAINT_HAINT_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_RESET      0x0
/* Extracts the ALT_USB_HOST_HAINT_HAINT field value from a register. */
#define ALT_USB_HOST_HAINT_HAINT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HAINT_HAINT register field value suitable for setting the register. */
#define ALT_USB_HOST_HAINT_HAINT_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HAINT.
 */
struct ALT_USB_HOST_HAINT_s
{
    const uint32_t  haint : 16;  /* Channel Interrupts */
    uint32_t              : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HAINT. */
typedef volatile struct ALT_USB_HOST_HAINT_s  ALT_USB_HOST_HAINT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HAINT register from the beginning of the component. */
#define ALT_USB_HOST_HAINT_OFST        0x14
/* The address of the ALT_USB_HOST_HAINT register. */
#define ALT_USB_HOST_HAINT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINT_OFST))

/*
 * Register : Host All Channels Interrupt Mask Register - haintmsk
 * 
 * The Host All Channel Interrupt Mask register works with the Host All Channel
 * Interrupt register to interrupt the application when an event occurs on a
 * channel. There is one interrupt mask bit per channel, up to a maximum of 16
 * bits.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description           
 * :--------|:-------|:------|:-----------------------
 *  [15:0]  | RW     | 0x0   | Channel Interrupt Mask
 *  [31:16] | ???    | 0x0   | *UNDEFINED*           
 * 
 */
/*
 * Field : Channel Interrupt Mask - haintmsk
 * 
 * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description     
 * :---------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK   | 0x0   | Mask interrupt  
 *  ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK | 0x1   | Unmask interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK
 * 
 * Mask interrupt
 */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK
 * 
 * Unmask interrupt
 */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_MSB        15
/* The width in bits of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_WIDTH      16
/* The mask used to set the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HAINTMSK_HAINTMSK field value from a register. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HAINTMSK_HAINTMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HAINTMSK.
 */
struct ALT_USB_HOST_HAINTMSK_s
{
    uint32_t  haintmsk : 16;  /* Channel Interrupt Mask */
    uint32_t           : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HAINTMSK. */
typedef volatile struct ALT_USB_HOST_HAINTMSK_s  ALT_USB_HOST_HAINTMSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HAINTMSK register from the beginning of the component. */
#define ALT_USB_HOST_HAINTMSK_OFST        0x18
/* The address of the ALT_USB_HOST_HAINTMSK register. */
#define ALT_USB_HOST_HAINTMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINTMSK_OFST))

/*
 * Register : Host Frame List Base Address Register - hflbaddr
 * 
 * This Register is valid only for Host mode Scatter-Gather DMA. Starting address
 * of the Frame list. This register is used only for Isochronous and Interrupt
 * Channels.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                   
 * :-------|:-------|:------|:-------------------------------
 *  [31:0] | RW     | 0x0   | ALT_USB_HOST_HFLBADDR_HFLBADDR
 * 
 */
/*
 * Field : hflbaddr
 * 
 * This Register is valid only for Host mode Scatter-Gather DMA  mode. Starting
 * address of the Frame list. This register is used only for Isochronous and
 * Interrupt Channels.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_MSB        31
/* The width in bits of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HFLBADDR_HFLBADDR field value from a register. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HFLBADDR_HFLBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HFLBADDR.
 */
struct ALT_USB_HOST_HFLBADDR_s
{
    uint32_t  hflbaddr : 32;  /* ALT_USB_HOST_HFLBADDR_HFLBADDR */
};

/* The typedef declaration for register ALT_USB_HOST_HFLBADDR. */
typedef volatile struct ALT_USB_HOST_HFLBADDR_s  ALT_USB_HOST_HFLBADDR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HFLBADDR register from the beginning of the component. */
#define ALT_USB_HOST_HFLBADDR_OFST        0x1c
/* The address of the ALT_USB_HOST_HFLBADDR register. */
#define ALT_USB_HOST_HFLBADDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFLBADDR_OFST))

/*
 * Register : Host Port Control and Status Register - hprt
 * 
 * This register is available only in Host mode. Currently, the OTG Host supports
 * only one port. A single register holds USB port-related information such as USB
 * reset, enable, suspend, resume, connect status, and test mode for each port.The
 * R_SS_WC bits in this register can trigger an interrupt to the application
 * through the Host Port Interrupt bit of the Core Interrupt register
 * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register
 * and clear the bit that caused the interrupt. for the R_SS_WC bits, the
 * application must write a 1 to the bit to clear the interrupt
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description               
 * :--------|:-------|:------|:---------------------------
 *  [0]     | R      | 0x0   | Port Connect Status       
 *  [1]     | R      | 0x0   | Port Connect Detected     
 *  [2]     | R      | 0x0   | Port Enabl                
 *  [3]     | R      | 0x0   | Port Enable Disable Change
 *  [4]     | R      | 0x0   | Port Overcurrent Active   
 *  [5]     | R      | 0x0   | Port Overcurrent Change   
 *  [6]     | RW     | 0x0   | Port Resume               
 *  [7]     | R      | 0x0   | Port Suspend              
 *  [8]     | RW     | 0x0   | Port Reset                
 *  [9]     | ???    | 0x0   | *UNDEFINED*               
 *  [11:10] | R      | 0x0   | Port Line Status          
 *  [12]    | RW     | 0x0   | Port Power                
 *  [16:13] | RW     | 0x0   | Port Test Control         
 *  [18:17] | R      | 0x0   | Port Speed                
 *  [31:19] | ???    | 0x0   | *UNDEFINED*               
 * 
 */
/*
 * Field : Port Connect Status - prtconnsts
 * 
 * Defines whether port is attached.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                      
 * :-------------------------------------------|:------|:----------------------------------
 *  ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED | 0x0   | No device is attached to the port
 *  ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED    | 0x1   | A device is attached to the port 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS
 * 
 * No device is attached to the port
 */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS
 * 
 * A device is attached to the port
 */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_MSB        0
/* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTCONNSTS field value from a register. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HPRT_PRTCONNSTS register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Port Connect Detected - PrtConnDet
 * 
 * The core sets this bit when a device connection is detected to trigger an
 * interrupt to the application using the Host Port Interrupt bit of the Core
 * Interrupt register (GINTSTS.PrtInt). This bit can be set only by the core and
 * the application should write 1 to clear it.The application must write a 1 to
 * this bit to clear the interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT   | 0x0   | Device connection detected   
 *  ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT | 0x1   | No device connection detected
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET
 * 
 * Device connection detected
 */
#define ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET
 * 
 * No device connection detected
 */
#define ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_MSB        1
/* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTCONNDET field value from a register. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HPRT_PRTCONNDET register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Port Enabl - prtena
 * 
 * A port is enabled only by the core after a reset sequence, and is disabled by an
 * overcurrent condition, a disconnect condition, or by the application clearing
 * this bit. The application cannot Set this bit by a register write. It can only
 * clear it to disable the port by writing 1. This bit does not trigger any
 * interrupt to the application.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description  
 * :--------------------------------|:------|:--------------
 *  ALT_USB_HOST_HPRT_PRTENA_E_DISD | 0x0   | Port disabled
 *  ALT_USB_HOST_HPRT_PRTENA_E_END  | 0x1   | Port enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA
 * 
 * Port disabled
 */
#define ALT_USB_HOST_HPRT_PRTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA
 * 
 * Port enabled
 */
#define ALT_USB_HOST_HPRT_PRTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_MSB        2
/* The width in bits of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTENA register field value. */
#define ALT_USB_HOST_HPRT_PRTENA_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTENA register field value. */
#define ALT_USB_HOST_HPRT_PRTENA_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTENA field value from a register. */
#define ALT_USB_HOST_HPRT_PRTENA_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HPRT_PRTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTENA_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Port Enable Disable Change - prtenchng
 * 
 * The core sets this bit when the status of the Port Enable bit [2] of this
 * register changes. This bit can be set only by the core and the application
 * should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT | 0x0   | Port Enable bit 2 no change
 *  ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT   | 0x1   | Port Enable bit 2 changed  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG
 * 
 * Port Enable bit 2 no change
 */
#define ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG
 * 
 * Port Enable bit 2 changed
 */
#define ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_MSB        3
/* The width in bits of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTENCHNG field value from a register. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HPRT_PRTENCHNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Port Overcurrent Active - prtovrcurract
 * 
 * Indicates the overcurrent condition of the port. 0x0: No overcurrent condition
 * 0x1: Overcurrent condition
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description             
 * :----------------------------------------|:------|:-------------------------
 *  ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT | 0x0   | No overcurrent condition
 *  ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT   | 0x1   | Overcurrent condition   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT
 * 
 * No overcurrent condition
 */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT
 * 
 * Overcurrent condition
 */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_MSB        4
/* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRACT field value from a register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Port Overcurrent Change - prtovrcurrchng
 * 
 * The core sets this bit when the status of the PortOvercurrent Active bit (bit 4)
 * in this register changes.This bit can be set only by the core and the
 * application should write 1 to clear it
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                         
 * :-----------------------------------------|:------|:-------------------------------------
 *  ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT | 0x0   | Status of port overcurrent no change
 *  ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT   | 0x1   | Status of port overcurrent changed  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
 * 
 * Status of port overcurrent no change
 */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
 * 
 * Status of port overcurrent changed
 */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_MSB        5
/* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG field value from a register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Port Resume - prtres
 * 
 * The application sets this bit to drive resume signaling on the port. The core
 * continues to drive the resume signal until the application clears this bit. If
 * the core detects a USB remote wakeup sequence, as indicated by the Port
 * Resume/Remote Wakeup Detected Interrupt bit of the Core Interrupt register
 * (GINTSTS.WkUpInt), the core starts driving resume signaling without application
 * intervention and clears this bit when it detects a disconnect condition. The
 * read value of this bit indicates whether the core is currently drivingresume
 * signaling. When LPM is enabled and the core is in the L1 (Sleep) state, setting
 * this bit results in the following behavior:
 * 
 * The core continues to drive the resume signal until a pre-determined time
 * specified in the GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote
 * wakeup sequence, as indicated by the Port L1 Resume/Remote L1 Wakeup Detected
 * Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), the core
 * starts driving resume signaling without application intervention and clears this
 * bit at the end of the resume. The read value of this bit indicates whether the
 * core is currently driving resume signaling.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HPRT_PRTRES_E_NORESUME | 0x0   | No resume driven
 *  ALT_USB_HOST_HPRT_PRTRES_E_RESUME   | 0x1   | Resume driven   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES
 * 
 * No resume driven
 */
#define ALT_USB_HOST_HPRT_PRTRES_E_NORESUME 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES
 * 
 * Resume driven
 */
#define ALT_USB_HOST_HPRT_PRTRES_E_RESUME   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_MSB        6
/* The width in bits of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTRES register field value. */
#define ALT_USB_HOST_HPRT_PRTRES_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTRES register field value. */
#define ALT_USB_HOST_HPRT_PRTRES_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTRES field value from a register. */
#define ALT_USB_HOST_HPRT_PRTRES_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HPRT_PRTRES register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTRES_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Port Suspend - prtsusp
 * 
 * The application sets this bit to put this port in Suspend mode. The core only
 * stops sending SOFs when this is Set. To stop the PHY clock, the application must
 * Set the Port Clock Stop bit, which asserts the suspend input pin of the PHY. The
 * read value of this bit reflects the current suspend status of the port. This bit
 * is cleared by the core after a remote wakeup signal is detected or the
 * application sets the Port Reset bit or Port Resume bit in this register or the
 * Resume/Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit
 * in the Core Interrupt register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
 * respectively). This bit is cleared by the core even if there is no device
 * connected to the Host.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description             
 * :----------------------------------|:------|:-------------------------
 *  ALT_USB_HOST_HPRT_PRTSUSP_E_INACT | 0x0   | Port not in Suspend mode
 *  ALT_USB_HOST_HPRT_PRTSUSP_E_ACT   | 0x1   | Port in Suspend mode    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP
 * 
 * Port not in Suspend mode
 */
#define ALT_USB_HOST_HPRT_PRTSUSP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP
 * 
 * Port in Suspend mode
 */
#define ALT_USB_HOST_HPRT_PRTSUSP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_MSB        7
/* The width in bits of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTSUSP register field value. */
#define ALT_USB_HOST_HPRT_PRTSUSP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTSUSP register field value. */
#define ALT_USB_HOST_HPRT_PRTSUSP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTSUSP field value from a register. */
#define ALT_USB_HOST_HPRT_PRTSUSP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HPRT_PRTSUSP register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTSUSP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Port Reset - prtrst
 * 
 * When the application sets this bit, a reset sequence is started on this port.
 * The application must time the reset period and clear this bit after the reset
 * sequence is complete. The application must leave this bit Set for at least a
 * minimum duration mentioned below to start a reset on the port. The application
 * can leave it Set for another 10 ms in addition to the required minimum duration,
 * before clearing the bit, even though there is no maximum limit set by theUSB
 * standard. This bit is cleared by the core even if there is no device connected
 * to the Host.
 * 
 * High speed: 50 ms
 * 
 * Full speed/Low speed: 10 ms
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description      
 * :--------------------------------|:------|:------------------
 *  ALT_USB_HOST_HPRT_PRTRST_E_DISD | 0x0   | Port not in reset
 *  ALT_USB_HOST_HPRT_PRTRST_E_END  | 0x1   | Port in reset    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST
 * 
 * Port not in reset
 */
#define ALT_USB_HOST_HPRT_PRTRST_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST
 * 
 * Port in reset
 */
#define ALT_USB_HOST_HPRT_PRTRST_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_MSB        8
/* The width in bits of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTRST register field value. */
#define ALT_USB_HOST_HPRT_PRTRST_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTRST register field value. */
#define ALT_USB_HOST_HPRT_PRTRST_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTRST field value from a register. */
#define ALT_USB_HOST_HPRT_PRTRST_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HPRT_PRTRST register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTRST_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Port Line Status - prtlnsts
 * 
 * Indicates the current logic level USB data lines. Bit [10]: Logic level of D+
 * Bit [11]: Logic level of D-
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD  | 0x1   | Logic level of D+
 *  ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD | 0x2   | Logic level of D-
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS
 * 
 * Logic level of D+
 */
#define ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD  0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS
 * 
 * Logic level of D-
 */
#define ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD 0x2

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_MSB        11
/* The width in bits of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_SET_MSK    0x00000c00
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_CLR_MSK    0xfffff3ff
/* The reset value of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTLNSTS field value from a register. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_GET(value) (((value) & 0x00000c00) >> 10)
/* Produces a ALT_USB_HOST_HPRT_PRTLNSTS register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_SET(value) (((value) << 10) & 0x00000c00)

/*
 * Field : Port Power - prtpwr
 * 
 * The application uses this field to control power to this port, and the core can
 * clear this bit on an over current condition.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description
 * :-------------------------------|:------|:------------
 *  ALT_USB_HOST_HPRT_PRTPWR_E_OFF | 0x0   | Power off  
 *  ALT_USB_HOST_HPRT_PRTPWR_E_ON  | 0x1   | Power on   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR
 * 
 * Power off
 */
#define ALT_USB_HOST_HPRT_PRTPWR_E_OFF  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR
 * 
 * Power on
 */
#define ALT_USB_HOST_HPRT_PRTPWR_E_ON   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_MSB        12
/* The width in bits of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTPWR register field value. */
#define ALT_USB_HOST_HPRT_PRTPWR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTPWR register field value. */
#define ALT_USB_HOST_HPRT_PRTPWR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTPWR field value from a register. */
#define ALT_USB_HOST_HPRT_PRTPWR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HPRT_PRTPWR register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTPWR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Port Test Control - prttstctl
 * 
 * The application writes a nonzero value to this field to put the port into a Test
 * mode, and the corresponding pattern is signaled on the port.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description       
 * :---------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD     | 0x0   | Test mode disabled
 *  ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ    | 0x1   | Test_J mode       
 *  ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK    | 0x2   | Test_K mode       
 *  ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN   | 0x3   | Test_SE0_NAK mode 
 *  ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM   | 0x4   | Test_Packet mode  
 *  ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB | 0x5   | Test_force_Enable 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
 * 
 * Test mode disabled
 */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
 * 
 * Test_J mode
 */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
 * 
 * Test_K mode
 */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
 * 
 * Test_SE0_NAK mode
 */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
 * 
 * Test_Packet mode
 */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
 * 
 * Test_force_Enable
 */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB  0x5

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_MSB        16
/* The width in bits of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_SET_MSK    0x0001e000
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_CLR_MSK    0xfffe1fff
/* The reset value of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTTSTCTL field value from a register. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_GET(value) (((value) & 0x0001e000) >> 13)
/* Produces a ALT_USB_HOST_HPRT_PRTTSTCTL register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_SET(value) (((value) << 13) & 0x0001e000)

/*
 * Field : Port Speed - prtspd
 * 
 * Indicates the speed of the device attached to this port.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD | 0x0   | High speed 
 *  ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD | 0x1   | Full speed 
 *  ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD  | 0x2   | Low speed  
 *  ALT_USB_HOST_HPRT_PRTSPD_E_RSVD    | 0x3   | Reserved   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
 * 
 * High speed
 */
#define ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
 * 
 * Full speed
 */
#define ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD  0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
 * 
 * Low speed
 */
#define ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
 * 
 * Reserved
 */
#define ALT_USB_HOST_HPRT_PRTSPD_E_RSVD     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_MSB        18
/* The width in bits of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HPRT_PRTSPD register field value. */
#define ALT_USB_HOST_HPRT_PRTSPD_SET_MSK    0x00060000
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTSPD register field value. */
#define ALT_USB_HOST_HPRT_PRTSPD_CLR_MSK    0xfff9ffff
/* The reset value of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_RESET      0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTSPD field value from a register. */
#define ALT_USB_HOST_HPRT_PRTSPD_GET(value) (((value) & 0x00060000) >> 17)
/* Produces a ALT_USB_HOST_HPRT_PRTSPD register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTSPD_SET(value) (((value) << 17) & 0x00060000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HPRT.
 */
struct ALT_USB_HOST_HPRT_s
{
    const uint32_t  prtconnsts     :  1;  /* Port Connect Status */
    const uint32_t  PrtConnDet     :  1;  /* Port Connect Detected */
    const uint32_t  prtena         :  1;  /* Port Enabl */
    const uint32_t  prtenchng      :  1;  /* Port Enable Disable Change */
    const uint32_t  prtovrcurract  :  1;  /* Port Overcurrent Active */
    const uint32_t  prtovrcurrchng :  1;  /* Port Overcurrent Change */
    uint32_t        prtres         :  1;  /* Port Resume */
    const uint32_t  prtsusp        :  1;  /* Port Suspend */
    uint32_t        prtrst         :  1;  /* Port Reset */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  prtlnsts       :  2;  /* Port Line Status */
    uint32_t        prtpwr         :  1;  /* Port Power */
    uint32_t        prttstctl      :  4;  /* Port Test Control */
    const uint32_t  prtspd         :  2;  /* Port Speed */
    uint32_t                       : 13;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HPRT. */
typedef volatile struct ALT_USB_HOST_HPRT_s  ALT_USB_HOST_HPRT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HPRT register from the beginning of the component. */
#define ALT_USB_HOST_HPRT_OFST        0x40
/* The address of the ALT_USB_HOST_HPRT register. */
#define ALT_USB_HOST_HPRT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPRT_OFST))

/*
 * Register : Host Channel 0 Characteristics Register - hcchar0
 * 
 * Channel_number: 0.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description            
 * :--------|:-------|:------|:------------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size    
 *  [14:11] | RW     | 0x0   | Endpoint Number        
 *  [15]    | RW     | 0x0   | Endpoint Direction     
 *  [16]    | ???    | 0x0   | *UNDEFINED*            
 *  [17]    | RW     | 0x0   | Low-Speed Device       
 *  [19:18] | RW     | 0x0   | Endpoint Type          
 *  [21:20] | RW     | 0x0   | Multi Count Error Count
 *  [28:22] | RW     | 0x0   | Device Address         
 *  [29]    | ???    | 0x0   | *UNDEFINED*            
 *  [30]    | R      | 0x0   | Channel Disable        
 *  [31]    | R      | 0x0   | Channel Enable         
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR0_MPS register field value. */
#define ALT_USB_HOST_HCCHAR0_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_MPS register field value. */
#define ALT_USB_HOST_HCCHAR0_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR0_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR0_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR0_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR | 0x0   | OUT        
 *  ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR  | 0x1   | IN         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR
 * 
 * OUT
 */
#define ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR
 * 
 * IN
 */
#define ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR0_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is Set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                    
 * :-------------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED | 0x0   | Communicating with non lowspeed
 *  ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED    | 0x1   | Communicating with lowspeed    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV
 * 
 * Communicating with non lowspeed
 */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV
 * 
 * Communicating with lowspeed
 */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR0_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR0_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count Error Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1'b1), this field indicates
 * the number of immediate retries to be performed for a periodic split
 * transactions on transaction errors. This field must be Set to at least 2'b01.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR0_EC_E_RSVD       | 0x0   | Reserved This field yields undefined results 
 *  ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
 * 
 * Reserved This field yields undefined results
 */
#define ALT_USB_HOST_HCCHAR0_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EC register field value. */
#define ALT_USB_HOST_HCCHAR0_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EC register field value. */
#define ALT_USB_HOST_HCCHAR0_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR0_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR0_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                     
 * :-----------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT | 0x0   | No activity                     
 *  ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving data
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS
 * 
 * No activity
 */
#define ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS
 * 
 * Stop transmitting/receiving data
 */
#define ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR0_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled. This field is set by the application and
 * cleared by the OTG host.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR0_CHENA_E_RDY    | 0x1   | Indicates that the descriptor structure and data
 * :                                    |       | buffer with data is setup and this channel can  
 * :                                    |       | access the descriptor                           
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA
 * 
 * Indicates that the descriptor structure and data  buffer with data is setup and
 * this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR0_CHENA_E_RDY    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR0_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR0_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR0_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR0_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR0.
 */
struct ALT_USB_HOST_HCCHAR0_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count Error Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR0. */
typedef volatile struct ALT_USB_HOST_HCCHAR0_s  ALT_USB_HOST_HCCHAR0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR0 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR0_OFST        0x100
/* The address of the ALT_USB_HOST_HCCHAR0 register. */
#define ALT_USB_HOST_HCCHAR0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR0_OFST))

/*
 * Register : Host Channel 0 Split Control Register - hcsplt0
 * 
 * Channel_number 0
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT0_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT0_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT0_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT0_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT0_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT0_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT0_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT0.
 */
struct ALT_USB_HOST_HCSPLT0_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT0. */
typedef volatile struct ALT_USB_HOST_HCSPLT0_s  ALT_USB_HOST_HCSPLT0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT0 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT0_OFST        0x104
/* The address of the ALT_USB_HOST_HCSPLT0 register. */
#define ALT_USB_HOST_HCSPLT0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT0_OFST))

/*
 * Register : Host Channel 0 Interrupt Register - hcint0
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT0_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT0_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT0_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT0_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT0_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT0_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT0_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT0_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT0_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT0_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT0_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT0_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT0_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT0_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_AHBERR register field value. */
#define ALT_USB_HOST_HCINT0_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT0_AHBERR register field value. */
#define ALT_USB_HOST_HCINT0_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT0_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT0_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT0_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT0_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT0_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_STALL register field value. */
#define ALT_USB_HOST_HCINT0_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT0_STALL register field value. */
#define ALT_USB_HOST_HCINT0_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_STALL field value from a register. */
#define ALT_USB_HOST_HCINT0_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT0_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT0_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT0_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT0_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT0_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_NAK register field value. */
#define ALT_USB_HOST_HCINT0_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT0_NAK register field value. */
#define ALT_USB_HOST_HCINT0_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_NAK field value from a register. */
#define ALT_USB_HOST_HCINT0_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT0_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT0_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT0_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT0_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT0_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_ACK register field value. */
#define ALT_USB_HOST_HCINT0_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT0_ACK register field value. */
#define ALT_USB_HOST_HCINT0_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_ACK field value from a register. */
#define ALT_USB_HOST_HCINT0_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT0_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT0_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT0_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT0_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT0_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_NYET register field value. */
#define ALT_USB_HOST_HCINT0_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT0_NYET register field value. */
#define ALT_USB_HOST_HCINT0_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_NYET field value from a register. */
#define ALT_USB_HOST_HCINT0_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT0_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT0_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT0_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT0_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT0_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_XACTERR register field value. */
#define ALT_USB_HOST_HCINT0_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT0_XACTERR register field value. */
#define ALT_USB_HOST_HCINT0_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT0_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT0_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT0_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT0_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT0_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT0_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_BBLERR register field value. */
#define ALT_USB_HOST_HCINT0_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT0_BBLERR register field value. */
#define ALT_USB_HOST_HCINT0_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT0_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT0_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT0_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT0_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT0_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT0_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT0_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT0_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT0_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT0_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT0_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT0_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT0_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT0.
 */
struct ALT_USB_HOST_HCINT0_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT0. */
typedef volatile struct ALT_USB_HOST_HCINT0_s  ALT_USB_HOST_HCINT0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT0 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT0_OFST        0x108
/* The address of the ALT_USB_HOST_HCINT0 register. */
#define ALT_USB_HOST_HCINT0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT0_OFST))

/*
 * Register : Host Channel 0 Interrupt Mask Register - hcintmsk0
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK0.
 */
struct ALT_USB_HOST_HCINTMSK0_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK0. */
typedef volatile struct ALT_USB_HOST_HCINTMSK0_s  ALT_USB_HOST_HCINTMSK0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK0 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK0_OFST        0x10c
/* The address of the ALT_USB_HOST_HCINTMSK0 register. */
#define ALT_USB_HOST_HCINTMSK0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK0_OFST))

/*
 * Register : Host Channel 0 Transfer Size Register - hctsiz0
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * For an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ0_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ0_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ0_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_PID register field value. */
#define ALT_USB_HOST_HCTSIZ0_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PID register field value. */
#define ALT_USB_HOST_HCTSIZ0_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ0_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ0_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ0.
 */
struct ALT_USB_HOST_HCTSIZ0_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ0. */
typedef volatile struct ALT_USB_HOST_HCTSIZ0_s  ALT_USB_HOST_HCTSIZ0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ0 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ0_OFST        0x110
/* The address of the ALT_USB_HOST_HCTSIZ0 register. */
#define ALT_USB_HOST_HCTSIZ0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ0_OFST))

/*
 * Register : Host Channel 0 DMA Address Register - hcdma0
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma0
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC nTD   N                          nTD
 * N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 
 * 0 -  1 descriptor.
 * 
 * 63 - 64 descriptors.
 * 
 * This field indicates the current descriptor processed in the list. This field is
 * updated both by application and the core. for example, if the application
 * enables the channel after programming CTD=5, then the core will start processing
 * the 6th descriptor. The address is obtained by adding a value of (8bytes*5=)
 * 40(decimal)  to DMAAddr.  Isochronous: CTD for isochronous is based on the
 * current frame/microframe value. Need to be set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA0_HCDMA0 field value from a register. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA0_HCDMA0 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA0.
 */
struct ALT_USB_HOST_HCDMA0_s
{
    uint32_t  hcdma0 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA0. */
typedef volatile struct ALT_USB_HOST_HCDMA0_s  ALT_USB_HOST_HCDMA0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA0 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA0_OFST        0x114
/* The address of the ALT_USB_HOST_HCDMA0 register. */
#define ALT_USB_HOST_HCDMA0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA0_OFST))

/*
 * Register : Host Channel 0 DMA Buffer Address Register - hcdmab0
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 0 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 0 DMA Buffer Address - hcdmab0
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB0_HCDMAB0 field value from a register. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB0.
 */
struct ALT_USB_HOST_HCDMAB0_s
{
    uint32_t  hcdmab0 : 32;  /* Host Channel 0 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB0. */
typedef volatile struct ALT_USB_HOST_HCDMAB0_s  ALT_USB_HOST_HCDMAB0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB0 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB0_OFST        0x118
/* The address of the ALT_USB_HOST_HCDMAB0 register. */
#define ALT_USB_HOST_HCDMAB0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB0_OFST))

/*
 * Register : Host Channel 1 Characteristics Register - hcchar1
 * 
 * Host Channel 1 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR1_MPS register field value. */
#define ALT_USB_HOST_HCCHAR1_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_MPS register field value. */
#define ALT_USB_HOST_HCCHAR1_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR1_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR1_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description  
 * :---------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR1_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR1_EPDIR_E_IN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR1_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                            
 * :------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR1_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR1_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR1_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR1_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EC register field value. */
#define ALT_USB_HOST_HCCHAR1_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EC register field value. */
#define ALT_USB_HOST_HCCHAR1_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR1_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR1_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR1_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR1_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                   |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR1_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                   |       | data  buffer  with data is setup and this       
 * :                                   |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR1_CHENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR1_CHENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR1_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR1_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR1_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR1_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR1.
 */
struct ALT_USB_HOST_HCCHAR1_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR1. */
typedef volatile struct ALT_USB_HOST_HCCHAR1_s  ALT_USB_HOST_HCCHAR1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR1 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR1_OFST        0x120
/* The address of the ALT_USB_HOST_HCCHAR1 register. */
#define ALT_USB_HOST_HCCHAR1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR1_OFST))

/*
 * Register : Host Channel 1 Split Control Register - hcsplt1
 * 
 * Channel_number 1
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT1_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT1_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT1_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT1_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT1_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT1_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT1_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT1.
 */
struct ALT_USB_HOST_HCSPLT1_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT1. */
typedef volatile struct ALT_USB_HOST_HCSPLT1_s  ALT_USB_HOST_HCSPLT1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT1 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT1_OFST        0x124
/* The address of the ALT_USB_HOST_HCSPLT1 register. */
#define ALT_USB_HOST_HCSPLT1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT1_OFST))

/*
 * Register : Host Channel 1 Interrupt Register - hcint1
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT1_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT1_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT1_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT1_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT1_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT1_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT1_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT1_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT1_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT1_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT1_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT1_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT1_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT1_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_AHBERR register field value. */
#define ALT_USB_HOST_HCINT1_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT1_AHBERR register field value. */
#define ALT_USB_HOST_HCINT1_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT1_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT1_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT1_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT1_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT1_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_STALL register field value. */
#define ALT_USB_HOST_HCINT1_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT1_STALL register field value. */
#define ALT_USB_HOST_HCINT1_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_STALL field value from a register. */
#define ALT_USB_HOST_HCINT1_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT1_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT1_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT1_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT1_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT1_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_NAK register field value. */
#define ALT_USB_HOST_HCINT1_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT1_NAK register field value. */
#define ALT_USB_HOST_HCINT1_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_NAK field value from a register. */
#define ALT_USB_HOST_HCINT1_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT1_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT1_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT1_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT1_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT1_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_ACK register field value. */
#define ALT_USB_HOST_HCINT1_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT1_ACK register field value. */
#define ALT_USB_HOST_HCINT1_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_ACK field value from a register. */
#define ALT_USB_HOST_HCINT1_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT1_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT1_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT1_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT1_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT1_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_NYET register field value. */
#define ALT_USB_HOST_HCINT1_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT1_NYET register field value. */
#define ALT_USB_HOST_HCINT1_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_NYET field value from a register. */
#define ALT_USB_HOST_HCINT1_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT1_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT1_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT1_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT1_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT1_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_XACTERR register field value. */
#define ALT_USB_HOST_HCINT1_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT1_XACTERR register field value. */
#define ALT_USB_HOST_HCINT1_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT1_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT1_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT1_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT1_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT1_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT1_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_BBLERR register field value. */
#define ALT_USB_HOST_HCINT1_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT1_BBLERR register field value. */
#define ALT_USB_HOST_HCINT1_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT1_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT1_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT1_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT1_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT1_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT1_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT1_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT1_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT1_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT1_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT1_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT1_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT1_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT1.
 */
struct ALT_USB_HOST_HCINT1_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT1. */
typedef volatile struct ALT_USB_HOST_HCINT1_s  ALT_USB_HOST_HCINT1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT1 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT1_OFST        0x128
/* The address of the ALT_USB_HOST_HCINT1 register. */
#define ALT_USB_HOST_HCINT1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT1_OFST))

/*
 * Register : Host Channel 1 Interrupt Mask Register - hcintmsk1
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK1.
 */
struct ALT_USB_HOST_HCINTMSK1_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK1. */
typedef volatile struct ALT_USB_HOST_HCINTMSK1_s  ALT_USB_HOST_HCINTMSK1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK1 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK1_OFST        0x12c
/* The address of the ALT_USB_HOST_HCINTMSK1 register. */
#define ALT_USB_HOST_HCINTMSK1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK1_OFST))

/*
 * Register : Host Channel 1 Transfer Size Register - hctsiz1
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ1_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ1_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ1_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_PID register field value. */
#define ALT_USB_HOST_HCTSIZ1_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PID register field value. */
#define ALT_USB_HOST_HCTSIZ1_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ1_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ1_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ1.
 */
struct ALT_USB_HOST_HCTSIZ1_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ1. */
typedef volatile struct ALT_USB_HOST_HCTSIZ1_s  ALT_USB_HOST_HCTSIZ1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ1 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ1_OFST        0x130
/* The address of the ALT_USB_HOST_HCTSIZ1 register. */
#define ALT_USB_HOST_HCTSIZ1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ1_OFST))

/*
 * Register : Host Channel 1 DMA Address Register - hcdma1
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma1
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA1_HCDMA1 field value from a register. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA1_HCDMA1 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA1.
 */
struct ALT_USB_HOST_HCDMA1_s
{
    uint32_t  hcdma1 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA1. */
typedef volatile struct ALT_USB_HOST_HCDMA1_s  ALT_USB_HOST_HCDMA1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA1 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA1_OFST        0x134
/* The address of the ALT_USB_HOST_HCDMA1 register. */
#define ALT_USB_HOST_HCDMA1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA1_OFST))

/*
 * Register : Host Channel 1 DMA Buffer Address Register - hcdmab1
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 1 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 1 DMA Buffer Address - hcdmab1
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB1_HCDMAB1 field value from a register. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB1.
 */
struct ALT_USB_HOST_HCDMAB1_s
{
    uint32_t  hcdmab1 : 32;  /* Host Channel 1 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB1. */
typedef volatile struct ALT_USB_HOST_HCDMAB1_s  ALT_USB_HOST_HCDMAB1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB1 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB1_OFST        0x138
/* The address of the ALT_USB_HOST_HCDMAB1 register. */
#define ALT_USB_HOST_HCDMAB1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB1_OFST))

/*
 * Register : Host Channel 2 Characteristics Register - hcchar2
 * 
 * Host Channel 2 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR2_MPS register field value. */
#define ALT_USB_HOST_HCCHAR2_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_MPS register field value. */
#define ALT_USB_HOST_HCCHAR2_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR2_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR2_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description  
 * :---------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR2_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR2_EPDIR_E_IN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR2_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                            
 * :------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR2_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR2_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR2_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR2_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EC register field value. */
#define ALT_USB_HOST_HCCHAR2_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EC register field value. */
#define ALT_USB_HOST_HCCHAR2_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR2_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR2_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR2_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR2_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                   |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR2_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                   |       | data  buffer  with data is setup and this       
 * :                                   |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR2_CHENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR2_CHENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR2_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR2_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR2_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR2_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR2.
 */
struct ALT_USB_HOST_HCCHAR2_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR2. */
typedef volatile struct ALT_USB_HOST_HCCHAR2_s  ALT_USB_HOST_HCCHAR2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR2 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR2_OFST        0x140
/* The address of the ALT_USB_HOST_HCCHAR2 register. */
#define ALT_USB_HOST_HCCHAR2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR2_OFST))

/*
 * Register : Host Channel 2 Split Control Register - hcsplt2
 * 
 * Channel_number 2
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT2_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT2_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT2_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT2_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT2_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT2_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT2_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT2.
 */
struct ALT_USB_HOST_HCSPLT2_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT2. */
typedef volatile struct ALT_USB_HOST_HCSPLT2_s  ALT_USB_HOST_HCSPLT2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT2 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT2_OFST        0x144
/* The address of the ALT_USB_HOST_HCSPLT2 register. */
#define ALT_USB_HOST_HCSPLT2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT2_OFST))

/*
 * Register : Host Channel 2 Interrupt Register - hcint2
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT2_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT2_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT2_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT2_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT2_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT2_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT2_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT2_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT2_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT2_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT2_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT2_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT2_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT2_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_AHBERR register field value. */
#define ALT_USB_HOST_HCINT2_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT2_AHBERR register field value. */
#define ALT_USB_HOST_HCINT2_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT2_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT2_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT2_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT2_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT2_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_STALL register field value. */
#define ALT_USB_HOST_HCINT2_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT2_STALL register field value. */
#define ALT_USB_HOST_HCINT2_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_STALL field value from a register. */
#define ALT_USB_HOST_HCINT2_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT2_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT2_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT2_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT2_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT2_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_NAK register field value. */
#define ALT_USB_HOST_HCINT2_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT2_NAK register field value. */
#define ALT_USB_HOST_HCINT2_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_NAK field value from a register. */
#define ALT_USB_HOST_HCINT2_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT2_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT2_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT2_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT2_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT2_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_ACK register field value. */
#define ALT_USB_HOST_HCINT2_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT2_ACK register field value. */
#define ALT_USB_HOST_HCINT2_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_ACK field value from a register. */
#define ALT_USB_HOST_HCINT2_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT2_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT2_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT2_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT2_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT2_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_NYET register field value. */
#define ALT_USB_HOST_HCINT2_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT2_NYET register field value. */
#define ALT_USB_HOST_HCINT2_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_NYET field value from a register. */
#define ALT_USB_HOST_HCINT2_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT2_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT2_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT2_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT2_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT2_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_XACTERR register field value. */
#define ALT_USB_HOST_HCINT2_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT2_XACTERR register field value. */
#define ALT_USB_HOST_HCINT2_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT2_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT2_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT2_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT2_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT2_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT2_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_BBLERR register field value. */
#define ALT_USB_HOST_HCINT2_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT2_BBLERR register field value. */
#define ALT_USB_HOST_HCINT2_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT2_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT2_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT2_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT2_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT2_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT2_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT2_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT2_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT2_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT2_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT2_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT2_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT2_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT2.
 */
struct ALT_USB_HOST_HCINT2_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT2. */
typedef volatile struct ALT_USB_HOST_HCINT2_s  ALT_USB_HOST_HCINT2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT2 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT2_OFST        0x148
/* The address of the ALT_USB_HOST_HCINT2 register. */
#define ALT_USB_HOST_HCINT2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT2_OFST))

/*
 * Register : Host Channel 2 Interrupt Mask Register - hcintmsk2
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK2.
 */
struct ALT_USB_HOST_HCINTMSK2_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK2. */
typedef volatile struct ALT_USB_HOST_HCINTMSK2_s  ALT_USB_HOST_HCINTMSK2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK2 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK2_OFST        0x14c
/* The address of the ALT_USB_HOST_HCINTMSK2 register. */
#define ALT_USB_HOST_HCINTMSK2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK2_OFST))

/*
 * Register : Host Channel 2 Transfer Size Register - hctsiz2
 * 
 * Buffer DMA Mode.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ2_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ2_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ2_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_PID register field value. */
#define ALT_USB_HOST_HCTSIZ2_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PID register field value. */
#define ALT_USB_HOST_HCTSIZ2_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ2_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ2_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ2.
 */
struct ALT_USB_HOST_HCTSIZ2_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ2. */
typedef volatile struct ALT_USB_HOST_HCTSIZ2_s  ALT_USB_HOST_HCTSIZ2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ2 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ2_OFST        0x150
/* The address of the ALT_USB_HOST_HCTSIZ2 register. */
#define ALT_USB_HOST_HCTSIZ2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ2_OFST))

/*
 * Register : Host Channel 2 DMA Address Register - hcdma2
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma2
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA2_HCDMA2 field value from a register. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA2_HCDMA2 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA2.
 */
struct ALT_USB_HOST_HCDMA2_s
{
    uint32_t  hcdma2 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA2. */
typedef volatile struct ALT_USB_HOST_HCDMA2_s  ALT_USB_HOST_HCDMA2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA2 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA2_OFST        0x154
/* The address of the ALT_USB_HOST_HCDMA2 register. */
#define ALT_USB_HOST_HCDMA2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA2_OFST))

/*
 * Register : Host Channel 2 DMA Buffer Address Register - hcdmab2
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 2 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 2 DMA Buffer Address - hcdmab2
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB2_HCDMAB2 field value from a register. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB2.
 */
struct ALT_USB_HOST_HCDMAB2_s
{
    uint32_t  hcdmab2 : 32;  /* Host Channel 2 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB2. */
typedef volatile struct ALT_USB_HOST_HCDMAB2_s  ALT_USB_HOST_HCDMAB2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB2 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB2_OFST        0x158
/* The address of the ALT_USB_HOST_HCDMAB2 register. */
#define ALT_USB_HOST_HCDMAB2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB2_OFST))

/*
 * Register : Host Channel 3 Characteristics Register - hcchar3
 * 
 * Channel_number: 3.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description            
 * :--------|:-------|:------|:------------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size    
 *  [14:11] | RW     | 0x0   | Endpoint Number        
 *  [15]    | RW     | 0x0   | Endpoint Direction     
 *  [16]    | ???    | 0x0   | *UNDEFINED*            
 *  [17]    | RW     | 0x0   | Low-Speed Device       
 *  [19:18] | RW     | 0x0   | Endpoint Type          
 *  [21:20] | RW     | 0x0   | Multi Count Error Count
 *  [28:22] | RW     | 0x0   | Device Address         
 *  [29]    | ???    | 0x0   | *UNDEFINED*            
 *  [30]    | R      | 0x0   | Channel Disable        
 *  [31]    | R      | 0x0   | Channel Enable         
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR3_MPS register field value. */
#define ALT_USB_HOST_HCCHAR3_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_MPS register field value. */
#define ALT_USB_HOST_HCCHAR3_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR3_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR3_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR | 0x0   | OUT        
 *  ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR  | 0x1   | IN         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR
 * 
 * OUT
 */
#define ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR
 * 
 * IN
 */
#define ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR3_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is Set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                    
 * :-------------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED | 0x0   | Communicating with non lowspeed
 *  ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED    | 0x1   | Communicating with lowspeed    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV
 * 
 * Communicating with non lowspeed
 */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV
 * 
 * Communicating with lowspeed
 */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR3_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR3_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count Error Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be Set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR3_EC_E_RSVD       | 0x0   | Reserved This field yields undefined results 
 *  ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
 * 
 * Reserved This field yields undefined results
 */
#define ALT_USB_HOST_HCCHAR3_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EC register field value. */
#define ALT_USB_HOST_HCCHAR3_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EC register field value. */
#define ALT_USB_HOST_HCCHAR3_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR3_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR3_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                     
 * :-----------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT | 0x0   | No activity                     
 *  ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving data
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS
 * 
 * No activity
 */
#define ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS
 * 
 * Stop transmitting/receiving data
 */
#define ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR3_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled. This field is set by the application and
 * cleared by the OTG host.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR3_CHENA_E_RDY    | 0x1   | Indicates that the descriptor structure and data
 * :                                    |       | buffer with data is setup and this channel can  
 * :                                    |       | access the descriptor                           
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA
 * 
 * Indicates that the descriptor structure and data  buffer with data is setup and
 * this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR3_CHENA_E_RDY    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR3_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR3_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR3_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR3_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR3.
 */
struct ALT_USB_HOST_HCCHAR3_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count Error Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR3. */
typedef volatile struct ALT_USB_HOST_HCCHAR3_s  ALT_USB_HOST_HCCHAR3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR3 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR3_OFST        0x160
/* The address of the ALT_USB_HOST_HCCHAR3 register. */
#define ALT_USB_HOST_HCCHAR3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR3_OFST))

/*
 * Register : Host Channel 3 Split Control Register - hcsplt3
 * 
 * Channel_number 3
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT3_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT3_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT3_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT3_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT3_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT3_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT3_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT3.
 */
struct ALT_USB_HOST_HCSPLT3_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT3. */
typedef volatile struct ALT_USB_HOST_HCSPLT3_s  ALT_USB_HOST_HCSPLT3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT3 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT3_OFST        0x164
/* The address of the ALT_USB_HOST_HCSPLT3 register. */
#define ALT_USB_HOST_HCSPLT3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT3_OFST))

/*
 * Register : Host Channel 3 Interrupt Register - hcint3
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT3_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT3_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT3_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT3_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT3_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT3_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT3_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT3_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT3_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT3_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT3_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT3_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT3_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT3_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_AHBERR register field value. */
#define ALT_USB_HOST_HCINT3_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT3_AHBERR register field value. */
#define ALT_USB_HOST_HCINT3_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT3_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT3_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT3_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT3_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT3_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_STALL register field value. */
#define ALT_USB_HOST_HCINT3_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT3_STALL register field value. */
#define ALT_USB_HOST_HCINT3_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_STALL field value from a register. */
#define ALT_USB_HOST_HCINT3_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT3_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT3_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT3_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT3_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT3_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_NAK register field value. */
#define ALT_USB_HOST_HCINT3_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT3_NAK register field value. */
#define ALT_USB_HOST_HCINT3_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_NAK field value from a register. */
#define ALT_USB_HOST_HCINT3_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT3_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT3_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT3_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT3_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT3_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_ACK register field value. */
#define ALT_USB_HOST_HCINT3_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT3_ACK register field value. */
#define ALT_USB_HOST_HCINT3_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_ACK field value from a register. */
#define ALT_USB_HOST_HCINT3_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT3_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT3_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT3_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT3_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT3_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_NYET register field value. */
#define ALT_USB_HOST_HCINT3_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT3_NYET register field value. */
#define ALT_USB_HOST_HCINT3_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_NYET field value from a register. */
#define ALT_USB_HOST_HCINT3_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT3_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT3_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT3_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT3_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT3_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_XACTERR register field value. */
#define ALT_USB_HOST_HCINT3_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT3_XACTERR register field value. */
#define ALT_USB_HOST_HCINT3_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT3_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT3_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT3_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT3_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT3_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT3_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_BBLERR register field value. */
#define ALT_USB_HOST_HCINT3_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT3_BBLERR register field value. */
#define ALT_USB_HOST_HCINT3_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT3_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT3_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT3_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT3_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT3_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT3_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT3_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT3_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT3_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT3_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT3_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT3_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT3_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT3.
 */
struct ALT_USB_HOST_HCINT3_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT3. */
typedef volatile struct ALT_USB_HOST_HCINT3_s  ALT_USB_HOST_HCINT3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT3 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT3_OFST        0x168
/* The address of the ALT_USB_HOST_HCINT3 register. */
#define ALT_USB_HOST_HCINT3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT3_OFST))

/*
 * Register : Host Channel 3 Interrupt Mask Registe - hcintmsk3
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK3.
 */
struct ALT_USB_HOST_HCINTMSK3_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK3. */
typedef volatile struct ALT_USB_HOST_HCINTMSK3_s  ALT_USB_HOST_HCINTMSK3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK3 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK3_OFST        0x16c
/* The address of the ALT_USB_HOST_HCINTMSK3 register. */
#define ALT_USB_HOST_HCINTMSK3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK3_OFST))

/*
 * Register : Host Channel 3 Transfer Size Registe - hctsiz3
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ3_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ3_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ3_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_PID register field value. */
#define ALT_USB_HOST_HCTSIZ3_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PID register field value. */
#define ALT_USB_HOST_HCTSIZ3_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ3_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ3_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ3.
 */
struct ALT_USB_HOST_HCTSIZ3_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ3. */
typedef volatile struct ALT_USB_HOST_HCTSIZ3_s  ALT_USB_HOST_HCTSIZ3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ3 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ3_OFST        0x170
/* The address of the ALT_USB_HOST_HCTSIZ3 register. */
#define ALT_USB_HOST_HCTSIZ3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ3_OFST))

/*
 * Register : Host Channel 3 DMA Address Register - hcdma3
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma3
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA3_HCDMA3 field value from a register. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA3_HCDMA3 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA3.
 */
struct ALT_USB_HOST_HCDMA3_s
{
    uint32_t  hcdma3 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA3. */
typedef volatile struct ALT_USB_HOST_HCDMA3_s  ALT_USB_HOST_HCDMA3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA3 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA3_OFST        0x174
/* The address of the ALT_USB_HOST_HCDMA3 register. */
#define ALT_USB_HOST_HCDMA3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA3_OFST))

/*
 * Register : Host Channel 3 DMA Buffer Address Register - hcdmab3
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 3 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 3 DMA Buffer Address - hcdmab3
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB3_HCDMAB3 field value from a register. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB3.
 */
struct ALT_USB_HOST_HCDMAB3_s
{
    uint32_t  hcdmab3 : 32;  /* Host Channel 3 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB3. */
typedef volatile struct ALT_USB_HOST_HCDMAB3_s  ALT_USB_HOST_HCDMAB3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB3 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB3_OFST        0x178
/* The address of the ALT_USB_HOST_HCDMAB3 register. */
#define ALT_USB_HOST_HCDMAB3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB3_OFST))

/*
 * Register : Host Channel 4 Characteristics Register - hcchar4
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 0 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 0 DMA Buffer Address - hcdmab4
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR4_HCDMAB4 field value from a register. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR4.
 */
struct ALT_USB_HOST_HCCHAR4_s
{
    uint32_t  hcdmab4 : 32;  /* Host Channel 0 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR4. */
typedef volatile struct ALT_USB_HOST_HCCHAR4_s  ALT_USB_HOST_HCCHAR4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR4 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR4_OFST        0x180
/* The address of the ALT_USB_HOST_HCCHAR4 register. */
#define ALT_USB_HOST_HCCHAR4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR4_OFST))

/*
 * Register : Host Channel 4 Split Control Register - hcsplt4
 * 
 * Channel_number 4
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT4_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT4_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT4_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT4_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT4_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT4_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT4_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT4.
 */
struct ALT_USB_HOST_HCSPLT4_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT4. */
typedef volatile struct ALT_USB_HOST_HCSPLT4_s  ALT_USB_HOST_HCSPLT4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT4 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT4_OFST        0x184
/* The address of the ALT_USB_HOST_HCSPLT4 register. */
#define ALT_USB_HOST_HCSPLT4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT4_OFST))

/*
 * Register : Host Channel 4 Interrupt Register - hcint4
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT4_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT4_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT4_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT4_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT4_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT4_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT4_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT4_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT4_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT4_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT4_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT4_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT4_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT4_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_AHBERR register field value. */
#define ALT_USB_HOST_HCINT4_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT4_AHBERR register field value. */
#define ALT_USB_HOST_HCINT4_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT4_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT4_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT4_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT4_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT4_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_STALL register field value. */
#define ALT_USB_HOST_HCINT4_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT4_STALL register field value. */
#define ALT_USB_HOST_HCINT4_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_STALL field value from a register. */
#define ALT_USB_HOST_HCINT4_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT4_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT4_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT4_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT4_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT4_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_NAK register field value. */
#define ALT_USB_HOST_HCINT4_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT4_NAK register field value. */
#define ALT_USB_HOST_HCINT4_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_NAK field value from a register. */
#define ALT_USB_HOST_HCINT4_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT4_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT4_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT4_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT4_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT4_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_ACK register field value. */
#define ALT_USB_HOST_HCINT4_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT4_ACK register field value. */
#define ALT_USB_HOST_HCINT4_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_ACK field value from a register. */
#define ALT_USB_HOST_HCINT4_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT4_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT4_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT4_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT4_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT4_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_NYET register field value. */
#define ALT_USB_HOST_HCINT4_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT4_NYET register field value. */
#define ALT_USB_HOST_HCINT4_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_NYET field value from a register. */
#define ALT_USB_HOST_HCINT4_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT4_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT4_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT4_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT4_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT4_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_XACTERR register field value. */
#define ALT_USB_HOST_HCINT4_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT4_XACTERR register field value. */
#define ALT_USB_HOST_HCINT4_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT4_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT4_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT4_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT4_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT4_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT4_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_BBLERR register field value. */
#define ALT_USB_HOST_HCINT4_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT4_BBLERR register field value. */
#define ALT_USB_HOST_HCINT4_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT4_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT4_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT4_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT4_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT4_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT4_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT4_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT4_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT4_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT4_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT4_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT4_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT4_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT4.
 */
struct ALT_USB_HOST_HCINT4_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT4. */
typedef volatile struct ALT_USB_HOST_HCINT4_s  ALT_USB_HOST_HCINT4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT4 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT4_OFST        0x188
/* The address of the ALT_USB_HOST_HCINT4 register. */
#define ALT_USB_HOST_HCINT4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT4_OFST))

/*
 * Register : Host Channel 4 Interrupt Mask Register - hcintmsk4
 * 
 * This register reflects the mask for Channel 4 interrupt status bits.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK4.
 */
struct ALT_USB_HOST_HCINTMSK4_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK4. */
typedef volatile struct ALT_USB_HOST_HCINTMSK4_s  ALT_USB_HOST_HCINTMSK4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK4 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK4_OFST        0x18c
/* The address of the ALT_USB_HOST_HCINTMSK4 register. */
#define ALT_USB_HOST_HCINTMSK4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK4_OFST))

/*
 * Register : Host Channel 4 Transfer Size Register - hctsiz4
 * 
 * Buffer DMA Mode Channel 4
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ4_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ4_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ4_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_PID register field value. */
#define ALT_USB_HOST_HCTSIZ4_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PID register field value. */
#define ALT_USB_HOST_HCTSIZ4_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ4_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ4_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ4.
 */
struct ALT_USB_HOST_HCTSIZ4_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ4. */
typedef volatile struct ALT_USB_HOST_HCTSIZ4_s  ALT_USB_HOST_HCTSIZ4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ4 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ4_OFST        0x190
/* The address of the ALT_USB_HOST_HCTSIZ4 register. */
#define ALT_USB_HOST_HCTSIZ4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ4_OFST))

/*
 * Register : Host Channel 4 DMA Address Register - hcdma4
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma4
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page. The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA4_HCDMA4 field value from a register. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA4_HCDMA4 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA4.
 */
struct ALT_USB_HOST_HCDMA4_s
{
    uint32_t  hcdma4 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA4. */
typedef volatile struct ALT_USB_HOST_HCDMA4_s  ALT_USB_HOST_HCDMA4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA4 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA4_OFST        0x194
/* The address of the ALT_USB_HOST_HCDMA4 register. */
#define ALT_USB_HOST_HCDMA4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA4_OFST))

/*
 * Register : Host Channel 4 DMA Buffer Address Register - hcdmab4
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress. This
 * register is present only in Scatter/Gather DMA mode. Otherwise this field is
 * reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 0 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 0 DMA Buffer Address - hcdmab4
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB4_HCDMAB4 field value from a register. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB4.
 */
struct ALT_USB_HOST_HCDMAB4_s
{
    uint32_t  hcdmab4 : 32;  /* Host Channel 0 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB4. */
typedef volatile struct ALT_USB_HOST_HCDMAB4_s  ALT_USB_HOST_HCDMAB4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB4 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB4_OFST        0x198
/* The address of the ALT_USB_HOST_HCDMAB4 register. */
#define ALT_USB_HOST_HCDMAB4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB4_OFST))

/*
 * Register : Host Channel 5 Characteristics Register - hcchar5
 * 
 * Channel_number: 5.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description            
 * :--------|:-------|:------|:------------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size    
 *  [14:11] | RW     | 0x0   | Endpoint Number        
 *  [15]    | RW     | 0x0   | Endpoint Direction     
 *  [16]    | ???    | 0x0   | *UNDEFINED*            
 *  [17]    | RW     | 0x0   | Low-Speed Device       
 *  [19:18] | RW     | 0x0   | Endpoint Type          
 *  [21:20] | RW     | 0x0   | Multi Count Error Count
 *  [28:22] | RW     | 0x0   | Device Address         
 *  [29]    | ???    | 0x0   | *UNDEFINED*            
 *  [30]    | R      | 0x0   | Channel Disable        
 *  [31]    | R      | 0x0   | Channel Enable         
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR5_MPS register field value. */
#define ALT_USB_HOST_HCCHAR5_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_MPS register field value. */
#define ALT_USB_HOST_HCCHAR5_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR5_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR5_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR | 0x0   | OUT        
 *  ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR  | 0x1   | IN         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR
 * 
 * OUT
 */
#define ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR
 * 
 * IN
 */
#define ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR5_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is Set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                    
 * :-------------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED | 0x0   | Communicating with non lowspeed
 *  ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED    | 0x1   | Communicating with lowspeed    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV
 * 
 * Communicating with non lowspeed
 */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV
 * 
 * Communicating with lowspeed
 */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR5_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR5_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count Error Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration.  0x0: Reserved This field yields undefined results. 0x1:
 * transaction 0x2: 2 transactions to be issued for this endpoint permicroframe
 * 0x3: 3 transactions to be issued for this endpoint permicroframeWhen
 * HCSPLTn.SpltEna is Set (1), this field indicates thenumber of immediate retries
 * to be performed for a periodic splittransactions on transaction errors. This
 * field must be Set to atleast 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR5_EC_E_RSVD       | 0x0   | Reserved This field yields undefined results 
 *  ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
 * 
 * Reserved This field yields undefined results
 */
#define ALT_USB_HOST_HCCHAR5_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EC register field value. */
#define ALT_USB_HOST_HCCHAR5_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EC register field value. */
#define ALT_USB_HOST_HCCHAR5_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR5_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR5_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                     
 * :-----------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT | 0x0   | No activity                     
 *  ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving data
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS
 * 
 * No activity
 */
#define ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS
 * 
 * Stop transmitting/receiving data
 */
#define ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR5_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled. This field is set by the application and
 * cleared by the OTG host.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR5_CHENA_E_RDY    | 0x1   | Indicates that the descriptor structure and data
 * :                                    |       | buffer with data is setup and this channel can  
 * :                                    |       | access the descriptor                           
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA
 * 
 * Indicates that the descriptor structure and data  buffer with data is setup and
 * this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR5_CHENA_E_RDY    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR5_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR5_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR5_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR5_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR5.
 */
struct ALT_USB_HOST_HCCHAR5_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count Error Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR5. */
typedef volatile struct ALT_USB_HOST_HCCHAR5_s  ALT_USB_HOST_HCCHAR5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR5 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR5_OFST        0x1a0
/* The address of the ALT_USB_HOST_HCCHAR5 register. */
#define ALT_USB_HOST_HCCHAR5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR5_OFST))

/*
 * Register : Host Channel 5 Split Control Register - hcsplt5
 * 
 * Channel_number 5
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT5_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT5_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT5_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT5_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT5_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT5_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT5_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT5.
 */
struct ALT_USB_HOST_HCSPLT5_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT5. */
typedef volatile struct ALT_USB_HOST_HCSPLT5_s  ALT_USB_HOST_HCSPLT5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT5 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT5_OFST        0x1a4
/* The address of the ALT_USB_HOST_HCSPLT5 register. */
#define ALT_USB_HOST_HCSPLT5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT5_OFST))

/*
 * Register : Host Channel 5 Interrupt Register - hcint5
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT5_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT5_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT5_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT5_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT5_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT5_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT5_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT5_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT5_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT5_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT5_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT5_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT5_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT5_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_AHBERR register field value. */
#define ALT_USB_HOST_HCINT5_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT5_AHBERR register field value. */
#define ALT_USB_HOST_HCINT5_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT5_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT5_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT5_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT5_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT5_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_STALL register field value. */
#define ALT_USB_HOST_HCINT5_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT5_STALL register field value. */
#define ALT_USB_HOST_HCINT5_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_STALL field value from a register. */
#define ALT_USB_HOST_HCINT5_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT5_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT5_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT5_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT5_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT5_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_NAK register field value. */
#define ALT_USB_HOST_HCINT5_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT5_NAK register field value. */
#define ALT_USB_HOST_HCINT5_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_NAK field value from a register. */
#define ALT_USB_HOST_HCINT5_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT5_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT5_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT5_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT5_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT5_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_ACK register field value. */
#define ALT_USB_HOST_HCINT5_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT5_ACK register field value. */
#define ALT_USB_HOST_HCINT5_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_ACK field value from a register. */
#define ALT_USB_HOST_HCINT5_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT5_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT5_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT5_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT5_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT5_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_NYET register field value. */
#define ALT_USB_HOST_HCINT5_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT5_NYET register field value. */
#define ALT_USB_HOST_HCINT5_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_NYET field value from a register. */
#define ALT_USB_HOST_HCINT5_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT5_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT5_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT5_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT5_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT5_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_XACTERR register field value. */
#define ALT_USB_HOST_HCINT5_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT5_XACTERR register field value. */
#define ALT_USB_HOST_HCINT5_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT5_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT5_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT5_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT5_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT5_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT5_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_BBLERR register field value. */
#define ALT_USB_HOST_HCINT5_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT5_BBLERR register field value. */
#define ALT_USB_HOST_HCINT5_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT5_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT5_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT5_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT5_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT5_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT5_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT5_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT5_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT5_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT5_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT5_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT5_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT5_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT5.
 */
struct ALT_USB_HOST_HCINT5_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT5. */
typedef volatile struct ALT_USB_HOST_HCINT5_s  ALT_USB_HOST_HCINT5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT5 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT5_OFST        0x1a8
/* The address of the ALT_USB_HOST_HCINT5 register. */
#define ALT_USB_HOST_HCINT5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT5_OFST))

/*
 * Register : Host Channel 5 Interrupt Mask Register - hcintmsk5
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK5.
 */
struct ALT_USB_HOST_HCINTMSK5_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK5. */
typedef volatile struct ALT_USB_HOST_HCINTMSK5_s  ALT_USB_HOST_HCINTMSK5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK5 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK5_OFST        0x1ac
/* The address of the ALT_USB_HOST_HCINTMSK5 register. */
#define ALT_USB_HOST_HCINTMSK5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK5_OFST))

/*
 * Register : Host Channel 5 Transfer Size Register - hctsiz5
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ5_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ5_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ5_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_PID register field value. */
#define ALT_USB_HOST_HCTSIZ5_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PID register field value. */
#define ALT_USB_HOST_HCTSIZ5_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ5_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ5_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ5.
 */
struct ALT_USB_HOST_HCTSIZ5_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ5. */
typedef volatile struct ALT_USB_HOST_HCTSIZ5_s  ALT_USB_HOST_HCTSIZ5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ5 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ5_OFST        0x1b0
/* The address of the ALT_USB_HOST_HCTSIZ5 register. */
#define ALT_USB_HOST_HCTSIZ5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ5_OFST))

/*
 * Register : Host Channel 5 DMA Address Register - hcdma5
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma5
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA5_HCDMA5 field value from a register. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA5_HCDMA5 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA5.
 */
struct ALT_USB_HOST_HCDMA5_s
{
    uint32_t  hcdma5 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA5. */
typedef volatile struct ALT_USB_HOST_HCDMA5_s  ALT_USB_HOST_HCDMA5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA5 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA5_OFST        0x1b4
/* The address of the ALT_USB_HOST_HCDMA5 register. */
#define ALT_USB_HOST_HCDMA5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA5_OFST))

/*
 * Register : Host Channel 5 DMA Buffer Address Register - hcdmab5
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 5 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 5 DMA Buffer Address - hcdmab5
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB5_HCDMAB5 field value from a register. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB5.
 */
struct ALT_USB_HOST_HCDMAB5_s
{
    uint32_t  hcdmab5 : 32;  /* Host Channel 5 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB5. */
typedef volatile struct ALT_USB_HOST_HCDMAB5_s  ALT_USB_HOST_HCDMAB5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB5 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB5_OFST        0x1b8
/* The address of the ALT_USB_HOST_HCDMAB5 register. */
#define ALT_USB_HOST_HCDMAB5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB5_OFST))

/*
 * Register : Host Channel 6 Characteristics Register - hcchar6
 * 
 * Host Channel 6 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR6_MPS register field value. */
#define ALT_USB_HOST_HCCHAR6_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_MPS register field value. */
#define ALT_USB_HOST_HCCHAR6_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR6_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR6_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description  
 * :---------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR6_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR6_EPDIR_E_IN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR6_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                            
 * :------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR6_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR6_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR6_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR6_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EC register field value. */
#define ALT_USB_HOST_HCCHAR6_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EC register field value. */
#define ALT_USB_HOST_HCCHAR6_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR6_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR6_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR6_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR6_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                   |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR6_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                   |       | data  buffer  with data is setup and this       
 * :                                   |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR6_CHENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR6_CHENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR6_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR6_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR6_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR6_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR6.
 */
struct ALT_USB_HOST_HCCHAR6_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR6. */
typedef volatile struct ALT_USB_HOST_HCCHAR6_s  ALT_USB_HOST_HCCHAR6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR6 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR6_OFST        0x1c0
/* The address of the ALT_USB_HOST_HCCHAR6 register. */
#define ALT_USB_HOST_HCCHAR6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR6_OFST))

/*
 * Register : Host Channel 6 Split Control Register - hcsplt6
 * 
 * Channel_number 6
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT6_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT6_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT6_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT6_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT6_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT6_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT6_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT6.
 */
struct ALT_USB_HOST_HCSPLT6_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT6. */
typedef volatile struct ALT_USB_HOST_HCSPLT6_s  ALT_USB_HOST_HCSPLT6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT6 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT6_OFST        0x1c4
/* The address of the ALT_USB_HOST_HCSPLT6 register. */
#define ALT_USB_HOST_HCSPLT6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT6_OFST))

/*
 * Register : Host Channel 6 Interrupt Register - hcint6
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT6_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT6_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT6_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT6_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT6_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT6_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT6_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT6_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT6_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT6_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT6_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT6_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT6_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT6_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_AHBERR register field value. */
#define ALT_USB_HOST_HCINT6_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT6_AHBERR register field value. */
#define ALT_USB_HOST_HCINT6_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT6_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT6_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT6_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT6_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT6_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_STALL register field value. */
#define ALT_USB_HOST_HCINT6_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT6_STALL register field value. */
#define ALT_USB_HOST_HCINT6_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_STALL field value from a register. */
#define ALT_USB_HOST_HCINT6_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT6_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT6_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT6_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT6_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT6_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_NAK register field value. */
#define ALT_USB_HOST_HCINT6_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT6_NAK register field value. */
#define ALT_USB_HOST_HCINT6_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_NAK field value from a register. */
#define ALT_USB_HOST_HCINT6_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT6_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT6_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT6_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT6_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT6_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_ACK register field value. */
#define ALT_USB_HOST_HCINT6_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT6_ACK register field value. */
#define ALT_USB_HOST_HCINT6_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_ACK field value from a register. */
#define ALT_USB_HOST_HCINT6_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT6_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT6_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT6_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT6_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT6_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_NYET register field value. */
#define ALT_USB_HOST_HCINT6_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT6_NYET register field value. */
#define ALT_USB_HOST_HCINT6_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_NYET field value from a register. */
#define ALT_USB_HOST_HCINT6_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT6_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT6_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT6_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT6_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT6_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_XACTERR register field value. */
#define ALT_USB_HOST_HCINT6_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT6_XACTERR register field value. */
#define ALT_USB_HOST_HCINT6_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT6_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT6_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT6_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT6_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT6_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT6_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_BBLERR register field value. */
#define ALT_USB_HOST_HCINT6_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT6_BBLERR register field value. */
#define ALT_USB_HOST_HCINT6_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT6_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT6_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT6_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT6_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT6_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT6_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT6_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT6_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT6_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT6_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT6_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT6_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT6_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT6.
 */
struct ALT_USB_HOST_HCINT6_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT6. */
typedef volatile struct ALT_USB_HOST_HCINT6_s  ALT_USB_HOST_HCINT6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT6 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT6_OFST        0x1c8
/* The address of the ALT_USB_HOST_HCINT6 register. */
#define ALT_USB_HOST_HCINT6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT6_OFST))

/*
 * Register : Host Channel 6 Interrupt Mask Register - hcintmsk6
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK6.
 */
struct ALT_USB_HOST_HCINTMSK6_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK6. */
typedef volatile struct ALT_USB_HOST_HCINTMSK6_s  ALT_USB_HOST_HCINTMSK6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK6 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK6_OFST        0x1cc
/* The address of the ALT_USB_HOST_HCINTMSK6 register. */
#define ALT_USB_HOST_HCINTMSK6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK6_OFST))

/*
 * Register : Host Channel 6 Transfer Size Register - hctsiz6
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ6_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ6_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ6_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_PID register field value. */
#define ALT_USB_HOST_HCTSIZ6_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PID register field value. */
#define ALT_USB_HOST_HCTSIZ6_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ6_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ6_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ6.
 */
struct ALT_USB_HOST_HCTSIZ6_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ6. */
typedef volatile struct ALT_USB_HOST_HCTSIZ6_s  ALT_USB_HOST_HCTSIZ6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ6 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ6_OFST        0x1d0
/* The address of the ALT_USB_HOST_HCTSIZ6 register. */
#define ALT_USB_HOST_HCTSIZ6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ6_OFST))

/*
 * Register : Host Channel  DMA Address Registe - hcdma6
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma6
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA6_HCDMA6 field value from a register. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA6_HCDMA6 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA6.
 */
struct ALT_USB_HOST_HCDMA6_s
{
    uint32_t  hcdma6 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA6. */
typedef volatile struct ALT_USB_HOST_HCDMA6_s  ALT_USB_HOST_HCDMA6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA6 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA6_OFST        0x1d4
/* The address of the ALT_USB_HOST_HCDMA6 register. */
#define ALT_USB_HOST_HCDMA6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA6_OFST))

/*
 * Register : Host Channel 6 DMA Buffer Address Register - hcdmab6
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 6 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 6 DMA Buffer Address - hcdmab6
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB6_HCDMAB6 field value from a register. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB6.
 */
struct ALT_USB_HOST_HCDMAB6_s
{
    uint32_t  hcdmab6 : 32;  /* Host Channel 6 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB6. */
typedef volatile struct ALT_USB_HOST_HCDMAB6_s  ALT_USB_HOST_HCDMAB6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB6 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB6_OFST        0x1d8
/* The address of the ALT_USB_HOST_HCDMAB6 register. */
#define ALT_USB_HOST_HCDMAB6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB6_OFST))

/*
 * Register : Host Channel 7 Characteristics Register - hcchar7
 * 
 * Host Channel 7 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR7_MPS register field value. */
#define ALT_USB_HOST_HCCHAR7_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_MPS register field value. */
#define ALT_USB_HOST_HCCHAR7_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR7_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR7_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description  
 * :---------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR7_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR7_EPDIR_E_IN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR7_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                            
 * :------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR7_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR7_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR7_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR7_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EC register field value. */
#define ALT_USB_HOST_HCCHAR7_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EC register field value. */
#define ALT_USB_HOST_HCCHAR7_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR7_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR7_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR7_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR7_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                   |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR7_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                   |       | data  buffer  with data is setup and this       
 * :                                   |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR7_CHENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR7_CHENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR7_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR7_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR7_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR7_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR7.
 */
struct ALT_USB_HOST_HCCHAR7_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR7. */
typedef volatile struct ALT_USB_HOST_HCCHAR7_s  ALT_USB_HOST_HCCHAR7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR7 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR7_OFST        0x1e0
/* The address of the ALT_USB_HOST_HCCHAR7 register. */
#define ALT_USB_HOST_HCCHAR7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR7_OFST))

/*
 * Register : Host Channel 7 Split Control Register - hcsplt7
 * 
 * Channel_number 7
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT7_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT7_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT7_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT7_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT7_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT7_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT7_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT7.
 */
struct ALT_USB_HOST_HCSPLT7_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT7. */
typedef volatile struct ALT_USB_HOST_HCSPLT7_s  ALT_USB_HOST_HCSPLT7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT7 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT7_OFST        0x1e4
/* The address of the ALT_USB_HOST_HCSPLT7 register. */
#define ALT_USB_HOST_HCSPLT7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT7_OFST))

/*
 * Register : Host Channel 7 Interrupt Register - hcint7
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT7_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT7_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT7_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT7_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT7_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT7_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT7_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT7_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT7_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT7_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT7_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT7_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT7_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT7_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_AHBERR register field value. */
#define ALT_USB_HOST_HCINT7_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT7_AHBERR register field value. */
#define ALT_USB_HOST_HCINT7_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT7_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT7_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT7_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT7_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT7_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_STALL register field value. */
#define ALT_USB_HOST_HCINT7_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT7_STALL register field value. */
#define ALT_USB_HOST_HCINT7_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_STALL field value from a register. */
#define ALT_USB_HOST_HCINT7_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT7_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT7_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT7_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT7_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT7_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_NAK register field value. */
#define ALT_USB_HOST_HCINT7_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT7_NAK register field value. */
#define ALT_USB_HOST_HCINT7_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_NAK field value from a register. */
#define ALT_USB_HOST_HCINT7_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT7_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT7_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT7_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT7_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT7_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_ACK register field value. */
#define ALT_USB_HOST_HCINT7_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT7_ACK register field value. */
#define ALT_USB_HOST_HCINT7_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_ACK field value from a register. */
#define ALT_USB_HOST_HCINT7_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT7_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT7_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT7_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT7_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT7_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_NYET register field value. */
#define ALT_USB_HOST_HCINT7_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT7_NYET register field value. */
#define ALT_USB_HOST_HCINT7_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_NYET field value from a register. */
#define ALT_USB_HOST_HCINT7_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT7_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT7_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT7_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT7_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT7_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_XACTERR register field value. */
#define ALT_USB_HOST_HCINT7_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT7_XACTERR register field value. */
#define ALT_USB_HOST_HCINT7_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT7_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT7_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT7_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT7_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT7_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT7_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_BBLERR register field value. */
#define ALT_USB_HOST_HCINT7_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT7_BBLERR register field value. */
#define ALT_USB_HOST_HCINT7_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT7_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT7_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT7_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT7_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT7_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT7_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT7_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT7_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT7_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT7_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT7_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT7_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT7_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT7.
 */
struct ALT_USB_HOST_HCINT7_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT7. */
typedef volatile struct ALT_USB_HOST_HCINT7_s  ALT_USB_HOST_HCINT7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT7 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT7_OFST        0x1e8
/* The address of the ALT_USB_HOST_HCINT7 register. */
#define ALT_USB_HOST_HCINT7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT7_OFST))

/*
 * Register : Host Channel 7 Interrupt Mask Register - hcintmsk7
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK7.
 */
struct ALT_USB_HOST_HCINTMSK7_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK7. */
typedef volatile struct ALT_USB_HOST_HCINTMSK7_s  ALT_USB_HOST_HCINTMSK7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK7 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK7_OFST        0x1ec
/* The address of the ALT_USB_HOST_HCINTMSK7 register. */
#define ALT_USB_HOST_HCINTMSK7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK7_OFST))

/*
 * Register : Host Channel 7 Transfer Size Register - hctsiz7
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ7_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ7_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ7_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_PID register field value. */
#define ALT_USB_HOST_HCTSIZ7_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PID register field value. */
#define ALT_USB_HOST_HCTSIZ7_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ7_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ7_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ7.
 */
struct ALT_USB_HOST_HCTSIZ7_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ7. */
typedef volatile struct ALT_USB_HOST_HCTSIZ7_s  ALT_USB_HOST_HCTSIZ7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ7 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ7_OFST        0x1f0
/* The address of the ALT_USB_HOST_HCTSIZ7 register. */
#define ALT_USB_HOST_HCTSIZ7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ7_OFST))

/*
 * Register : Host Channel 7 DMA Address Register - hcdma7
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma7
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA7_HCDMA7 field value from a register. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA7_HCDMA7 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA7.
 */
struct ALT_USB_HOST_HCDMA7_s
{
    uint32_t  hcdma7 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA7. */
typedef volatile struct ALT_USB_HOST_HCDMA7_s  ALT_USB_HOST_HCDMA7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA7 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA7_OFST        0x1f4
/* The address of the ALT_USB_HOST_HCDMA7 register. */
#define ALT_USB_HOST_HCDMA7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA7_OFST))

/*
 * Register : Host Channel 7 DMA Buffer Address Register - hcdmab7
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 7 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 7 DMA Buffer Address - hcdmab7
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB7_HCDMAB7 field value from a register. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB7.
 */
struct ALT_USB_HOST_HCDMAB7_s
{
    uint32_t  hcdmab7 : 32;  /* Host Channel 7 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB7. */
typedef volatile struct ALT_USB_HOST_HCDMAB7_s  ALT_USB_HOST_HCDMAB7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB7 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB7_OFST        0x1f8
/* The address of the ALT_USB_HOST_HCDMAB7 register. */
#define ALT_USB_HOST_HCDMAB7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB7_OFST))

/*
 * Register : Host Channel 8 Characteristics Register - hcchar8
 * 
 * Host Channel 8 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR8_MPS register field value. */
#define ALT_USB_HOST_HCCHAR8_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_MPS register field value. */
#define ALT_USB_HOST_HCCHAR8_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR8_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR8_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description  
 * :---------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR8_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR8_EPDIR_E_IN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR8_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                            
 * :------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR8_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR8_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR8_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR8_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EC register field value. */
#define ALT_USB_HOST_HCCHAR8_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EC register field value. */
#define ALT_USB_HOST_HCCHAR8_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR8_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR8_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR8_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR8_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                   |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR8_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                   |       | data  buffer  with data is setup and this       
 * :                                   |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR8_CHENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR8_CHENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR8_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR8_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR8_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR8_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR8.
 */
struct ALT_USB_HOST_HCCHAR8_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR8. */
typedef volatile struct ALT_USB_HOST_HCCHAR8_s  ALT_USB_HOST_HCCHAR8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR8 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR8_OFST        0x200
/* The address of the ALT_USB_HOST_HCCHAR8 register. */
#define ALT_USB_HOST_HCCHAR8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR8_OFST))

/*
 * Register : Host Channel 8 Split Control Register - hcsplt8
 * 
 * Channel_number 8
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT8_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT8_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT8_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT8_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT8_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT8_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT8_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT8.
 */
struct ALT_USB_HOST_HCSPLT8_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT8. */
typedef volatile struct ALT_USB_HOST_HCSPLT8_s  ALT_USB_HOST_HCSPLT8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT8 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT8_OFST        0x204
/* The address of the ALT_USB_HOST_HCSPLT8 register. */
#define ALT_USB_HOST_HCSPLT8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT8_OFST))

/*
 * Register : Host Channel 8 Interrupt Register - hcint8
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT8_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT8_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT8_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT8_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT8_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT8_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT8_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT8_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT8_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT8_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT8_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT8_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT8_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT8_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_AHBERR register field value. */
#define ALT_USB_HOST_HCINT8_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT8_AHBERR register field value. */
#define ALT_USB_HOST_HCINT8_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT8_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT8_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT8_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT8_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT8_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_STALL register field value. */
#define ALT_USB_HOST_HCINT8_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT8_STALL register field value. */
#define ALT_USB_HOST_HCINT8_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_STALL field value from a register. */
#define ALT_USB_HOST_HCINT8_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT8_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT8_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT8_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT8_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT8_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_NAK register field value. */
#define ALT_USB_HOST_HCINT8_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT8_NAK register field value. */
#define ALT_USB_HOST_HCINT8_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_NAK field value from a register. */
#define ALT_USB_HOST_HCINT8_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT8_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT8_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT8_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT8_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT8_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_ACK register field value. */
#define ALT_USB_HOST_HCINT8_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT8_ACK register field value. */
#define ALT_USB_HOST_HCINT8_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_ACK field value from a register. */
#define ALT_USB_HOST_HCINT8_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT8_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT8_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT8_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT8_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT8_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_NYET register field value. */
#define ALT_USB_HOST_HCINT8_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT8_NYET register field value. */
#define ALT_USB_HOST_HCINT8_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_NYET field value from a register. */
#define ALT_USB_HOST_HCINT8_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT8_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT8_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT8_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT8_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT8_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_XACTERR register field value. */
#define ALT_USB_HOST_HCINT8_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT8_XACTERR register field value. */
#define ALT_USB_HOST_HCINT8_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT8_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT8_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT8_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT8_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT8_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT8_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_BBLERR register field value. */
#define ALT_USB_HOST_HCINT8_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT8_BBLERR register field value. */
#define ALT_USB_HOST_HCINT8_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT8_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT8_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT8_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT8_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT8_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT8_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT8_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT8_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT8_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT8_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT8_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT8_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT8_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT8.
 */
struct ALT_USB_HOST_HCINT8_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT8. */
typedef volatile struct ALT_USB_HOST_HCINT8_s  ALT_USB_HOST_HCINT8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT8 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT8_OFST        0x208
/* The address of the ALT_USB_HOST_HCINT8 register. */
#define ALT_USB_HOST_HCINT8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT8_OFST))

/*
 * Register : Host Channel 8 Interrupt Mask Register - hcintmsk8
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK8.
 */
struct ALT_USB_HOST_HCINTMSK8_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK8. */
typedef volatile struct ALT_USB_HOST_HCINTMSK8_s  ALT_USB_HOST_HCINTMSK8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK8 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK8_OFST        0x20c
/* The address of the ALT_USB_HOST_HCINTMSK8 register. */
#define ALT_USB_HOST_HCINTMSK8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK8_OFST))

/*
 * Register : Host Channel 8 Transfer Size Register - hctsiz8
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ8_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ8_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ8_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_PID register field value. */
#define ALT_USB_HOST_HCTSIZ8_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PID register field value. */
#define ALT_USB_HOST_HCTSIZ8_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ8_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ8_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ8.
 */
struct ALT_USB_HOST_HCTSIZ8_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ8. */
typedef volatile struct ALT_USB_HOST_HCTSIZ8_s  ALT_USB_HOST_HCTSIZ8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ8 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ8_OFST        0x210
/* The address of the ALT_USB_HOST_HCTSIZ8 register. */
#define ALT_USB_HOST_HCTSIZ8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ8_OFST))

/*
 * Register : Host Channel 8 DMA Address Register - hcdma8
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma8
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA8_HCDMA8 field value from a register. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA8_HCDMA8 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA8.
 */
struct ALT_USB_HOST_HCDMA8_s
{
    uint32_t  hcdma8 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA8. */
typedef volatile struct ALT_USB_HOST_HCDMA8_s  ALT_USB_HOST_HCDMA8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA8 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA8_OFST        0x214
/* The address of the ALT_USB_HOST_HCDMA8 register. */
#define ALT_USB_HOST_HCDMA8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA8_OFST))

/*
 * Register : Host Channel 8 DMA Buffer Address Register - hcdmab8
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 8 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 8 DMA Buffer Address - hcdmab8
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB8_HCDMAB8 field value from a register. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB8.
 */
struct ALT_USB_HOST_HCDMAB8_s
{
    uint32_t  hcdmab8 : 32;  /* Host Channel 8 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB8. */
typedef volatile struct ALT_USB_HOST_HCDMAB8_s  ALT_USB_HOST_HCDMAB8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB8 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB8_OFST        0x218
/* The address of the ALT_USB_HOST_HCDMAB8 register. */
#define ALT_USB_HOST_HCDMAB8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB8_OFST))

/*
 * Register : Host Channel 9 Characteristics Register - hcchar9
 * 
 * Host Channel 9 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR9_MPS register field value. */
#define ALT_USB_HOST_HCCHAR9_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_MPS register field value. */
#define ALT_USB_HOST_HCCHAR9_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR9_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3     0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4     0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5     0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6     0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7     0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8     0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9     0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10    0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11    0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12    0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13    0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14    0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15    0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR9_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description  
 * :---------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR9_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR9_EPDIR_E_IN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR9_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                            
 * :------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR9_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL       0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR9_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                  
 * :-------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR9_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                     |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR9_EC_E_RSVD          0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO      0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EC register field value. */
#define ALT_USB_HOST_HCCHAR9_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EC register field value. */
#define ALT_USB_HOST_HCCHAR9_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR9_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR9_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR9_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR9_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                   |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR9_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                   |       | data  buffer  with data is setup and this       
 * :                                   |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR9_CHENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR9_CHENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR9_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR9_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR9_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR9_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR9.
 */
struct ALT_USB_HOST_HCCHAR9_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR9. */
typedef volatile struct ALT_USB_HOST_HCCHAR9_s  ALT_USB_HOST_HCCHAR9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR9 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR9_OFST        0x220
/* The address of the ALT_USB_HOST_HCCHAR9 register. */
#define ALT_USB_HOST_HCCHAR9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR9_OFST))

/*
 * Register : Host Channel 9 Split Control Register - hcsplt9
 * 
 * Channel_number 9
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT9_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT9_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT9_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                      |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                      |       | transaction (which is less than or equal to 188
 * :                                      |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_END      0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT9_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT9_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description      
 * :------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT9_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT9_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT9.
 */
struct ALT_USB_HOST_HCSPLT9_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT9. */
typedef volatile struct ALT_USB_HOST_HCSPLT9_s  ALT_USB_HOST_HCSPLT9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT9 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT9_OFST        0x224
/* The address of the ALT_USB_HOST_HCSPLT9 register. */
#define ALT_USB_HOST_HCSPLT9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT9_OFST))

/*
 * Register : Host Channel 9 Interrupt Register - hcint9
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT9_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT9_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT9_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT9_CHHLTD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT9_CHHLTD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT9_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT9_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT9_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT9_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT9_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT9_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT9_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT9_AHBERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT9_AHBERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_AHBERR register field value. */
#define ALT_USB_HOST_HCINT9_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT9_AHBERR register field value. */
#define ALT_USB_HOST_HCINT9_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT9_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT9_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT9_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT9_STALL_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT9_STALL_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_STALL register field value. */
#define ALT_USB_HOST_HCINT9_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT9_STALL register field value. */
#define ALT_USB_HOST_HCINT9_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_STALL field value from a register. */
#define ALT_USB_HOST_HCINT9_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT9_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT9_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT9_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT9_NAK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT9_NAK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_NAK register field value. */
#define ALT_USB_HOST_HCINT9_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT9_NAK register field value. */
#define ALT_USB_HOST_HCINT9_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_NAK field value from a register. */
#define ALT_USB_HOST_HCINT9_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT9_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                   
 * :--------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT9_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT9_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT9_ACK_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT9_ACK_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_ACK register field value. */
#define ALT_USB_HOST_HCINT9_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT9_ACK register field value. */
#define ALT_USB_HOST_HCINT9_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_ACK field value from a register. */
#define ALT_USB_HOST_HCINT9_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT9_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT9_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT9_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT9_NYET_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT9_NYET_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_NYET register field value. */
#define ALT_USB_HOST_HCINT9_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT9_NYET register field value. */
#define ALT_USB_HOST_HCINT9_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_NYET field value from a register. */
#define ALT_USB_HOST_HCINT9_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT9_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT9_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT9_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT9_XACTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT9_XACTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_XACTERR register field value. */
#define ALT_USB_HOST_HCINT9_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT9_XACTERR register field value. */
#define ALT_USB_HOST_HCINT9_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT9_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT9_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT9_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT9_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT9_BBLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT9_BBLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_BBLERR register field value. */
#define ALT_USB_HOST_HCINT9_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT9_BBLERR register field value. */
#define ALT_USB_HOST_HCINT9_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT9_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT9_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT9_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT9_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT9_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT9_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT9_BNAINTR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT9_BNAINTR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT9_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT9_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT9_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT9_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT9_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                   
 * :-------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                     
 * :----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT9.
 */
struct ALT_USB_HOST_HCINT9_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT9. */
typedef volatile struct ALT_USB_HOST_HCINT9_s  ALT_USB_HOST_HCINT9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT9 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT9_OFST        0x228
/* The address of the ALT_USB_HOST_HCINT9 register. */
#define ALT_USB_HOST_HCINT9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT9_OFST))

/*
 * Register : Host Channel 9 Interrupt Mask Register - hcintmsk9
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description
 * :-----------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK9.
 */
struct ALT_USB_HOST_HCINTMSK9_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK9. */
typedef volatile struct ALT_USB_HOST_HCINTMSK9_s  ALT_USB_HOST_HCINTMSK9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK9 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK9_OFST        0x22c
/* The address of the ALT_USB_HOST_HCINTMSK9 register. */
#define ALT_USB_HOST_HCINTMSK9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK9_OFST))

/*
 * Register : Host Channel 9 Transfer Size Register - hctsiz9
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ9_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ9_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA2    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA1    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ9_PID_E_MDATA    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_PID register field value. */
#define ALT_USB_HOST_HCTSIZ9_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PID register field value. */
#define ALT_USB_HOST_HCTSIZ9_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ9_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description     
 * :------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ9_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ9.
 */
struct ALT_USB_HOST_HCTSIZ9_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ9. */
typedef volatile struct ALT_USB_HOST_HCTSIZ9_s  ALT_USB_HOST_HCTSIZ9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ9 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ9_OFST        0x230
/* The address of the ALT_USB_HOST_HCTSIZ9 register. */
#define ALT_USB_HOST_HCTSIZ9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ9_OFST))

/*
 * Register : Host Channel DMA Address Register - hcdma9
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma9
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA9_HCDMA9 field value from a register. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA9_HCDMA9 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA9.
 */
struct ALT_USB_HOST_HCDMA9_s
{
    uint32_t  hcdma9 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA9. */
typedef volatile struct ALT_USB_HOST_HCDMA9_s  ALT_USB_HOST_HCDMA9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA9 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA9_OFST        0x234
/* The address of the ALT_USB_HOST_HCDMA9 register. */
#define ALT_USB_HOST_HCDMA9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA9_OFST))

/*
 * Register : Host Channel 9 DMA Buffer Address Register - hcdmab9
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 0 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 0 DMA Buffer Address - hcdmab9
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB9_HCDMAB9 field value from a register. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB9.
 */
struct ALT_USB_HOST_HCDMAB9_s
{
    uint32_t  hcdmab9 : 32;  /* Host Channel 0 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB9. */
typedef volatile struct ALT_USB_HOST_HCDMAB9_s  ALT_USB_HOST_HCDMAB9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB9 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB9_OFST        0x238
/* The address of the ALT_USB_HOST_HCDMAB9 register. */
#define ALT_USB_HOST_HCDMAB9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB9_OFST))

/*
 * Register : Host Channel 10 Characteristics Register - hcchar10
 * 
 * Host Channel 1 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR10_MPS register field value. */
#define ALT_USB_HOST_HCCHAR10_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_MPS register field value. */
#define ALT_USB_HOST_HCCHAR10_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR10_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5    0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6    0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7    0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8    0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9    0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10   0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11   0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12   0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13   0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14   0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15   0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR10_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description  
 * :----------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR10_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR10_EPDIR_E_IN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR10_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR10_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description
 * :--------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR10_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                  
 * :--------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR10_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR10_EC_E_RSVD         0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EC register field value. */
#define ALT_USB_HOST_HCCHAR10_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EC register field value. */
#define ALT_USB_HOST_HCCHAR10_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR10_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR10_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR10_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR10_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR10_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                    |       | data  buffer  with data is setup and this       
 * :                                    |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR10_CHENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR10_CHENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR10_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR10_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR10_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR10_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR10.
 */
struct ALT_USB_HOST_HCCHAR10_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR10. */
typedef volatile struct ALT_USB_HOST_HCCHAR10_s  ALT_USB_HOST_HCCHAR10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR10 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR10_OFST        0x240
/* The address of the ALT_USB_HOST_HCCHAR10 register. */
#define ALT_USB_HOST_HCCHAR10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR10_OFST))

/*
 * Register : Host Channel 10 Split Control Register - hcsplt10
 * 
 * Channel_number 1
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT10_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT10_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT10_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                       |       | transaction (which is less than or equal to 188
 * :                                       |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_END     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT10_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description         
 * :-----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT10_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT10_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT10_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT10.
 */
struct ALT_USB_HOST_HCSPLT10_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT10. */
typedef volatile struct ALT_USB_HOST_HCSPLT10_s  ALT_USB_HOST_HCSPLT10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT10 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT10_OFST        0x244
/* The address of the ALT_USB_HOST_HCSPLT10 register. */
#define ALT_USB_HOST_HCSPLT10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT10_OFST))

/*
 * Register : Host Channel 10 Interrupt Register - hcint10
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT10_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description       
 * :------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT10_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT10_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT10_CHHLTD_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT10_CHHLTD_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT10_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT10_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT10_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT10_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT10_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                    
 * :------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT10_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT10_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT10_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT10_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_AHBERR register field value. */
#define ALT_USB_HOST_HCINT10_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT10_AHBERR register field value. */
#define ALT_USB_HOST_HCINT10_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT10_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT10_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT10_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT10_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT10_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_STALL register field value. */
#define ALT_USB_HOST_HCINT10_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT10_STALL register field value. */
#define ALT_USB_HOST_HCINT10_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_STALL field value from a register. */
#define ALT_USB_HOST_HCINT10_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT10_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT10_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT10_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT10_NAK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT10_NAK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_NAK register field value. */
#define ALT_USB_HOST_HCINT10_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT10_NAK register field value. */
#define ALT_USB_HOST_HCINT10_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_NAK field value from a register. */
#define ALT_USB_HOST_HCINT10_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT10_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                                   
 * :---------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT10_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT10_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT10_ACK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT10_ACK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_ACK register field value. */
#define ALT_USB_HOST_HCINT10_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT10_ACK register field value. */
#define ALT_USB_HOST_HCINT10_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_ACK field value from a register. */
#define ALT_USB_HOST_HCINT10_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT10_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT10_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT10_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT10_NYET_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT10_NYET_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_NYET register field value. */
#define ALT_USB_HOST_HCINT10_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT10_NYET register field value. */
#define ALT_USB_HOST_HCINT10_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_NYET field value from a register. */
#define ALT_USB_HOST_HCINT10_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT10_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT10_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT10_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT10_XACTERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT10_XACTERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_XACTERR register field value. */
#define ALT_USB_HOST_HCINT10_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT10_XACTERR register field value. */
#define ALT_USB_HOST_HCINT10_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT10_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT10_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT10_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT10_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT10_BBLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT10_BBLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_BBLERR register field value. */
#define ALT_USB_HOST_HCINT10_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT10_BBLERR register field value. */
#define ALT_USB_HOST_HCINT10_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT10_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT10_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT10_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT10_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT10_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT10_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT10_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT10_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT10_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT10_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT10_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT10_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT10_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                   
 * :--------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                     
 * :-----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT10.
 */
struct ALT_USB_HOST_HCINT10_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT10. */
typedef volatile struct ALT_USB_HOST_HCINT10_s  ALT_USB_HOST_HCINT10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT10 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT10_OFST        0x248
/* The address of the ALT_USB_HOST_HCINT10 register. */
#define ALT_USB_HOST_HCINT10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT10_OFST))

/*
 * Register : Host Channel 10 Interrupt Mask Register - hcintmsk10
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description
 * :----------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK10.
 */
struct ALT_USB_HOST_HCINTMSK10_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK10. */
typedef volatile struct ALT_USB_HOST_HCINTMSK10_s  ALT_USB_HOST_HCINTMSK10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK10 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK10_OFST        0x24c
/* The address of the ALT_USB_HOST_HCINTMSK10 register. */
#define ALT_USB_HOST_HCINTMSK10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK10_OFST))

/*
 * Register : Host Channel 10 Transfer Size Register - hctsiz10
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ10_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ10_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ10_PID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_PID register field value. */
#define ALT_USB_HOST_HCTSIZ10_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PID register field value. */
#define ALT_USB_HOST_HCTSIZ10_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ10_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ10_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ10.
 */
struct ALT_USB_HOST_HCTSIZ10_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ10. */
typedef volatile struct ALT_USB_HOST_HCTSIZ10_s  ALT_USB_HOST_HCTSIZ10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ10 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ10_OFST        0x250
/* The address of the ALT_USB_HOST_HCTSIZ10 register. */
#define ALT_USB_HOST_HCTSIZ10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ10_OFST))

/*
 * Register : Host Channel 10 DMA Address Register - hcdma10
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma10
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA10_HCDMA10 field value from a register. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA10_HCDMA10 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA10.
 */
struct ALT_USB_HOST_HCDMA10_s
{
    uint32_t  hcdma10 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA10. */
typedef volatile struct ALT_USB_HOST_HCDMA10_s  ALT_USB_HOST_HCDMA10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA10 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA10_OFST        0x254
/* The address of the ALT_USB_HOST_HCDMA10 register. */
#define ALT_USB_HOST_HCDMA10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA10_OFST))

/*
 * Register : Host Channel 10 DMA Buffer Address Register - hcdmab10
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                       
 * :-------|:-------|:------|:-----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 10 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 10 DMA Buffer Address - hcdmab10
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB10_HCDMAB10 field value from a register. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB10.
 */
struct ALT_USB_HOST_HCDMAB10_s
{
    uint32_t  hcdmab10 : 32;  /* Host Channel 10 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB10. */
typedef volatile struct ALT_USB_HOST_HCDMAB10_s  ALT_USB_HOST_HCDMAB10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB10 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB10_OFST        0x258
/* The address of the ALT_USB_HOST_HCDMAB10 register. */
#define ALT_USB_HOST_HCDMAB10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB10_OFST))

/*
 * Register : Host Channel 11 Characteristics Register - hcchar11
 * 
 * Host Channel 11 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR11_MPS register field value. */
#define ALT_USB_HOST_HCCHAR11_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_MPS register field value. */
#define ALT_USB_HOST_HCCHAR11_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR11_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5    0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6    0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7    0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8    0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9    0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10   0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11   0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12   0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13   0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14   0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15   0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR11_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description  
 * :----------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR11_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR11_EPDIR_E_IN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR11_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR11_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description
 * :--------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR11_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                  
 * :--------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR11_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR11_EC_E_RSVD         0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EC register field value. */
#define ALT_USB_HOST_HCCHAR11_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EC register field value. */
#define ALT_USB_HOST_HCCHAR11_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR11_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR11_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR11_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR11_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR11_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                    |       | data  buffer  with data is setup and this       
 * :                                    |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR11_CHENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR11_CHENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR11_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR11_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR11_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR11_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR11.
 */
struct ALT_USB_HOST_HCCHAR11_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR11. */
typedef volatile struct ALT_USB_HOST_HCCHAR11_s  ALT_USB_HOST_HCCHAR11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR11 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR11_OFST        0x260
/* The address of the ALT_USB_HOST_HCCHAR11 register. */
#define ALT_USB_HOST_HCCHAR11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR11_OFST))

/*
 * Register : Host Channel 11 Split Control Register - HCSPLT11
 * 
 * Channel number 11.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT11_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT11_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT11_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                       |       | transaction (which is less than or equal to 188
 * :                                       |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_END     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT11_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description         
 * :-----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT11_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT11_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT11_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT11.
 */
struct ALT_USB_HOST_HCSPLT11_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT11. */
typedef volatile struct ALT_USB_HOST_HCSPLT11_s  ALT_USB_HOST_HCSPLT11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT11 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT11_OFST        0x264
/* The address of the ALT_USB_HOST_HCSPLT11 register. */
#define ALT_USB_HOST_HCSPLT11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT11_OFST))

/*
 * Register : Host Channel 11 Interrupt Register - hcint11
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT11_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description       
 * :------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT11_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT11_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT11_CHHLTD_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT11_CHHLTD_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT11_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT11_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT11_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT11_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT11_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                    
 * :------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT11_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT11_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT11_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT11_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_AHBERR register field value. */
#define ALT_USB_HOST_HCINT11_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT11_AHBERR register field value. */
#define ALT_USB_HOST_HCINT11_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT11_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT11_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT11_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT11_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT11_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_STALL register field value. */
#define ALT_USB_HOST_HCINT11_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT11_STALL register field value. */
#define ALT_USB_HOST_HCINT11_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_STALL field value from a register. */
#define ALT_USB_HOST_HCINT11_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT11_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT11_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT11_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT11_NAK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT11_NAK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_NAK register field value. */
#define ALT_USB_HOST_HCINT11_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT11_NAK register field value. */
#define ALT_USB_HOST_HCINT11_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_NAK field value from a register. */
#define ALT_USB_HOST_HCINT11_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT11_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                                   
 * :---------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT11_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT11_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT11_ACK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT11_ACK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_ACK register field value. */
#define ALT_USB_HOST_HCINT11_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT11_ACK register field value. */
#define ALT_USB_HOST_HCINT11_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_ACK field value from a register. */
#define ALT_USB_HOST_HCINT11_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT11_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT11_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT11_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT11_NYET_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT11_NYET_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_NYET register field value. */
#define ALT_USB_HOST_HCINT11_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT11_NYET register field value. */
#define ALT_USB_HOST_HCINT11_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_NYET field value from a register. */
#define ALT_USB_HOST_HCINT11_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT11_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT11_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT11_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT11_XACTERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT11_XACTERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_XACTERR register field value. */
#define ALT_USB_HOST_HCINT11_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT11_XACTERR register field value. */
#define ALT_USB_HOST_HCINT11_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT11_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT11_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT11_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT11_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT11_BBLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT11_BBLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_BBLERR register field value. */
#define ALT_USB_HOST_HCINT11_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT11_BBLERR register field value. */
#define ALT_USB_HOST_HCINT11_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT11_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT11_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT11_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT11_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT11_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT11_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT11_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT11_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT11_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT11_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT11_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT11_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT11_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                   
 * :--------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                     
 * :-----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT11.
 */
struct ALT_USB_HOST_HCINT11_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT11. */
typedef volatile struct ALT_USB_HOST_HCINT11_s  ALT_USB_HOST_HCINT11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT11 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT11_OFST        0x268
/* The address of the ALT_USB_HOST_HCINT11 register. */
#define ALT_USB_HOST_HCINT11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT11_OFST))

/*
 * Register : Channel 11 Interrupt Mask Register - hcintmsk11
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description
 * :----------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK11.
 */
struct ALT_USB_HOST_HCINTMSK11_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK11. */
typedef volatile struct ALT_USB_HOST_HCINTMSK11_s  ALT_USB_HOST_HCINTMSK11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK11 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK11_OFST        0x26c
/* The address of the ALT_USB_HOST_HCINTMSK11 register. */
#define ALT_USB_HOST_HCINTMSK11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK11_OFST))

/*
 * Register : Host Channel 11 Transfer Size Register - hctsiz11
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ11_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ11_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ11_PID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_PID register field value. */
#define ALT_USB_HOST_HCTSIZ11_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PID register field value. */
#define ALT_USB_HOST_HCTSIZ11_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ11_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ11_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ11.
 */
struct ALT_USB_HOST_HCTSIZ11_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ11. */
typedef volatile struct ALT_USB_HOST_HCTSIZ11_s  ALT_USB_HOST_HCTSIZ11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ11 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ11_OFST        0x270
/* The address of the ALT_USB_HOST_HCTSIZ11 register. */
#define ALT_USB_HOST_HCTSIZ11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ11_OFST))

/*
 * Register : Host Channel 11 DMA Address Register - hcdma11
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma11
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA11_HCDMA11 field value from a register. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA11_HCDMA11 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA11.
 */
struct ALT_USB_HOST_HCDMA11_s
{
    uint32_t  hcdma11 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA11. */
typedef volatile struct ALT_USB_HOST_HCDMA11_s  ALT_USB_HOST_HCDMA11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA11 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA11_OFST        0x274
/* The address of the ALT_USB_HOST_HCDMA11 register. */
#define ALT_USB_HOST_HCDMA11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA11_OFST))

/*
 * Register : Host Channel 11 DMA Buffer Address Register - hcdmab11
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers are implemented in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                       
 * :-------|:-------|:------|:-----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 11 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 11 DMA Buffer Address - hcdmab11
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB11_HCDMAB11 field value from a register. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB11.
 */
struct ALT_USB_HOST_HCDMAB11_s
{
    uint32_t  hcdmab11 : 32;  /* Host Channel 11 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB11. */
typedef volatile struct ALT_USB_HOST_HCDMAB11_s  ALT_USB_HOST_HCDMAB11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB11 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB11_OFST        0x278
/* The address of the ALT_USB_HOST_HCDMAB11 register. */
#define ALT_USB_HOST_HCDMAB11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB11_OFST))

/*
 * Register : Host Channel 12 Characteristics Register - hcchar12
 * 
 * Host Channel 1 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR12_MPS register field value. */
#define ALT_USB_HOST_HCCHAR12_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_MPS register field value. */
#define ALT_USB_HOST_HCCHAR12_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR12_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5    0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6    0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7    0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8    0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9    0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10   0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11   0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12   0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13   0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14   0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15   0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR12_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description  
 * :----------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR12_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR12_EPDIR_E_IN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR12_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR12_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description
 * :--------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR12_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                  
 * :--------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR12_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR12_EC_E_RSVD         0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EC register field value. */
#define ALT_USB_HOST_HCCHAR12_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EC register field value. */
#define ALT_USB_HOST_HCCHAR12_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR12_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR12_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR12_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR12_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR12_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                    |       | data  buffer  with data is setup and this       
 * :                                    |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR12_CHENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR12_CHENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR12_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR12_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR12_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR12_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR12.
 */
struct ALT_USB_HOST_HCCHAR12_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR12. */
typedef volatile struct ALT_USB_HOST_HCCHAR12_s  ALT_USB_HOST_HCCHAR12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR12 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR12_OFST        0x280
/* The address of the ALT_USB_HOST_HCCHAR12 register. */
#define ALT_USB_HOST_HCCHAR12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR12_OFST))

/*
 * Register : Host Channel 12 Split Control Register - hcsplt12
 * 
 * Channel_number 1
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT12_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT12_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT12_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                       |       | transaction (which is less than or equal to 188
 * :                                       |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_END     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT12_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description         
 * :-----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT12_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT12_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT12_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT12.
 */
struct ALT_USB_HOST_HCSPLT12_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT12. */
typedef volatile struct ALT_USB_HOST_HCSPLT12_s  ALT_USB_HOST_HCSPLT12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT12 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT12_OFST        0x284
/* The address of the ALT_USB_HOST_HCSPLT12 register. */
#define ALT_USB_HOST_HCSPLT12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT12_OFST))

/*
 * Register : Host Channel 12 Interrupt Register - hcint12
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT12_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description       
 * :------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT12_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT12_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT12_CHHLTD_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT12_CHHLTD_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT12_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT12_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT12_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT12_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT12_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                    
 * :------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT12_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT12_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT12_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT12_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_AHBERR register field value. */
#define ALT_USB_HOST_HCINT12_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT12_AHBERR register field value. */
#define ALT_USB_HOST_HCINT12_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT12_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT12_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT12_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT12_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT12_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_STALL register field value. */
#define ALT_USB_HOST_HCINT12_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT12_STALL register field value. */
#define ALT_USB_HOST_HCINT12_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_STALL field value from a register. */
#define ALT_USB_HOST_HCINT12_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT12_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT12_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT12_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT12_NAK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT12_NAK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_NAK register field value. */
#define ALT_USB_HOST_HCINT12_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT12_NAK register field value. */
#define ALT_USB_HOST_HCINT12_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_NAK field value from a register. */
#define ALT_USB_HOST_HCINT12_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT12_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                                   
 * :---------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT12_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT12_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT12_ACK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT12_ACK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_ACK register field value. */
#define ALT_USB_HOST_HCINT12_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT12_ACK register field value. */
#define ALT_USB_HOST_HCINT12_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_ACK field value from a register. */
#define ALT_USB_HOST_HCINT12_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT12_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT12_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT12_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT12_NYET_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT12_NYET_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_NYET register field value. */
#define ALT_USB_HOST_HCINT12_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT12_NYET register field value. */
#define ALT_USB_HOST_HCINT12_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_NYET field value from a register. */
#define ALT_USB_HOST_HCINT12_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT12_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT12_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT12_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT12_XACTERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT12_XACTERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_XACTERR register field value. */
#define ALT_USB_HOST_HCINT12_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT12_XACTERR register field value. */
#define ALT_USB_HOST_HCINT12_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT12_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT12_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT12_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT12_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT12_BBLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT12_BBLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_BBLERR register field value. */
#define ALT_USB_HOST_HCINT12_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT12_BBLERR register field value. */
#define ALT_USB_HOST_HCINT12_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT12_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT12_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT12_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT12_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT12_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT12_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT12_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT12_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT12_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT12_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT12_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT12_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT12_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                   
 * :--------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                     
 * :-----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT12.
 */
struct ALT_USB_HOST_HCINT12_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT12. */
typedef volatile struct ALT_USB_HOST_HCINT12_s  ALT_USB_HOST_HCINT12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT12 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT12_OFST        0x288
/* The address of the ALT_USB_HOST_HCINT12 register. */
#define ALT_USB_HOST_HCINT12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT12_OFST))

/*
 * Register : Host Channel 12 Interrupt Mask Register - hcintmsk12
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description
 * :----------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK12.
 */
struct ALT_USB_HOST_HCINTMSK12_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK12. */
typedef volatile struct ALT_USB_HOST_HCINTMSK12_s  ALT_USB_HOST_HCINTMSK12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK12 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK12_OFST        0x28c
/* The address of the ALT_USB_HOST_HCINTMSK12 register. */
#define ALT_USB_HOST_HCINTMSK12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK12_OFST))

/*
 * Register : Host Channel 12 Transfer Size Register - hctsiz12
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ12_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ12_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ12_PID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_PID register field value. */
#define ALT_USB_HOST_HCTSIZ12_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PID register field value. */
#define ALT_USB_HOST_HCTSIZ12_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ12_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ12_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ12.
 */
struct ALT_USB_HOST_HCTSIZ12_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ12. */
typedef volatile struct ALT_USB_HOST_HCTSIZ12_s  ALT_USB_HOST_HCTSIZ12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ12 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ12_OFST        0x290
/* The address of the ALT_USB_HOST_HCTSIZ12 register. */
#define ALT_USB_HOST_HCTSIZ12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ12_OFST))

/*
 * Register : Host Channel 12 DMA Address Register - hcdma12
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma12
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA12_HCDMA12 field value from a register. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA12_HCDMA12 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA12.
 */
struct ALT_USB_HOST_HCDMA12_s
{
    uint32_t  hcdma12 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA12. */
typedef volatile struct ALT_USB_HOST_HCDMA12_s  ALT_USB_HOST_HCDMA12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA12 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA12_OFST        0x294
/* The address of the ALT_USB_HOST_HCDMA12 register. */
#define ALT_USB_HOST_HCDMA12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA12_OFST))

/*
 * Register : Host Channel 12 DMA Buffer Address Register - hcdmab12
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register  is  updated  as  and when  the
 * data  transfer for the corresponding  end  point  is  in progress. This register
 * is  present  only  in  Scatter/Gather DMA mode. Otherwise this field is
 * reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 0 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 0 DMA Buffer Address - hcdmab12
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB12_HCDMAB12 field value from a register. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB12.
 */
struct ALT_USB_HOST_HCDMAB12_s
{
    uint32_t  hcdmab12 : 32;  /* Host Channel 0 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB12. */
typedef volatile struct ALT_USB_HOST_HCDMAB12_s  ALT_USB_HOST_HCDMAB12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB12 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB12_OFST        0x298
/* The address of the ALT_USB_HOST_HCDMAB12 register. */
#define ALT_USB_HOST_HCDMAB12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB12_OFST))

/*
 * Register : Host Channel 13 Characteristics Register - hcchar13
 * 
 * Host Channel 13 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR13_MPS register field value. */
#define ALT_USB_HOST_HCCHAR13_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_MPS register field value. */
#define ALT_USB_HOST_HCCHAR13_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR13_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5    0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6    0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7    0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8    0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9    0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10   0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11   0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12   0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13   0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14   0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15   0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR13_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description  
 * :----------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR13_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR13_EPDIR_E_IN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR13_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR13_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description
 * :--------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR13_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                  
 * :--------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR13_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR13_EC_E_RSVD         0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EC register field value. */
#define ALT_USB_HOST_HCCHAR13_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EC register field value. */
#define ALT_USB_HOST_HCCHAR13_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR13_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR13_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR13_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR13_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR13_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                    |       | data  buffer  with data is setup and this       
 * :                                    |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR13_CHENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR13_CHENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR13_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR13_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR13_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR13_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR13.
 */
struct ALT_USB_HOST_HCCHAR13_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR13. */
typedef volatile struct ALT_USB_HOST_HCCHAR13_s  ALT_USB_HOST_HCCHAR13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR13 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR13_OFST        0x2a0
/* The address of the ALT_USB_HOST_HCCHAR13 register. */
#define ALT_USB_HOST_HCCHAR13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR13_OFST))

/*
 * Register : Host Channel 13 Split Control Register - hcsplt13
 * 
 * Channel_number 13.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT13_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT13_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT13_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                       |       | transaction (which is less than or equal to 188
 * :                                       |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_END     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT13_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description         
 * :-----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT13_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT13_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT13_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT13.
 */
struct ALT_USB_HOST_HCSPLT13_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT13. */
typedef volatile struct ALT_USB_HOST_HCSPLT13_s  ALT_USB_HOST_HCSPLT13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT13 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT13_OFST        0x2a4
/* The address of the ALT_USB_HOST_HCSPLT13 register. */
#define ALT_USB_HOST_HCSPLT13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT13_OFST))

/*
 * Register : Host Channel 13 Interrupt Register - hcint13
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT13_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description       
 * :------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT13_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT13_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT13_CHHLTD_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT13_CHHLTD_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT13_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT13_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT13_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT13_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT13_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                    
 * :------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT13_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT13_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT13_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT13_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_AHBERR register field value. */
#define ALT_USB_HOST_HCINT13_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT13_AHBERR register field value. */
#define ALT_USB_HOST_HCINT13_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT13_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT13_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT13_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT13_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT13_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_STALL register field value. */
#define ALT_USB_HOST_HCINT13_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT13_STALL register field value. */
#define ALT_USB_HOST_HCINT13_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_STALL field value from a register. */
#define ALT_USB_HOST_HCINT13_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT13_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT13_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT13_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT13_NAK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT13_NAK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_NAK register field value. */
#define ALT_USB_HOST_HCINT13_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT13_NAK register field value. */
#define ALT_USB_HOST_HCINT13_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_NAK field value from a register. */
#define ALT_USB_HOST_HCINT13_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT13_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                                   
 * :---------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT13_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT13_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT13_ACK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT13_ACK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_ACK register field value. */
#define ALT_USB_HOST_HCINT13_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT13_ACK register field value. */
#define ALT_USB_HOST_HCINT13_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_ACK field value from a register. */
#define ALT_USB_HOST_HCINT13_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT13_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT13_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT13_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT13_NYET_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT13_NYET_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_NYET register field value. */
#define ALT_USB_HOST_HCINT13_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT13_NYET register field value. */
#define ALT_USB_HOST_HCINT13_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_NYET field value from a register. */
#define ALT_USB_HOST_HCINT13_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT13_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT13_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT13_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT13_XACTERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT13_XACTERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_XACTERR register field value. */
#define ALT_USB_HOST_HCINT13_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT13_XACTERR register field value. */
#define ALT_USB_HOST_HCINT13_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT13_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT13_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT13_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT13_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT13_BBLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT13_BBLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_BBLERR register field value. */
#define ALT_USB_HOST_HCINT13_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT13_BBLERR register field value. */
#define ALT_USB_HOST_HCINT13_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT13_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT13_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT13_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT13_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT13_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT13_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT13_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT13_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT13_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT13_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT13_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT13_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT13_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                   
 * :--------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                     
 * :-----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT13.
 */
struct ALT_USB_HOST_HCINT13_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT13. */
typedef volatile struct ALT_USB_HOST_HCINT13_s  ALT_USB_HOST_HCINT13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT13 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT13_OFST        0x2a8
/* The address of the ALT_USB_HOST_HCINT13 register. */
#define ALT_USB_HOST_HCINT13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT13_OFST))

/*
 * Register : Host Channel 13 Interrupt Mask Registe - hcintmsk13
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description
 * :----------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK13.
 */
struct ALT_USB_HOST_HCINTMSK13_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK13. */
typedef volatile struct ALT_USB_HOST_HCINTMSK13_s  ALT_USB_HOST_HCINTMSK13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK13 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK13_OFST        0x2ac
/* The address of the ALT_USB_HOST_HCINTMSK13 register. */
#define ALT_USB_HOST_HCINTMSK13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK13_OFST))

/*
 * Register : Host Channel 13 Transfer Size Register - hctsiz13
 * 
 * Buffer DMA Mode
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ13_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ13_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ13_PID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_PID register field value. */
#define ALT_USB_HOST_HCTSIZ13_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PID register field value. */
#define ALT_USB_HOST_HCTSIZ13_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ13_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ13_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ13.
 */
struct ALT_USB_HOST_HCTSIZ13_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ13. */
typedef volatile struct ALT_USB_HOST_HCTSIZ13_s  ALT_USB_HOST_HCTSIZ13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ13 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ13_OFST        0x2b0
/* The address of the ALT_USB_HOST_HCTSIZ13 register. */
#define ALT_USB_HOST_HCTSIZ13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ13_OFST))

/*
 * Register : Host Channel 13 DMA Address Register - hcdma13
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma13
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA13_HCDMA13 field value from a register. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA13_HCDMA13 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA13.
 */
struct ALT_USB_HOST_HCDMA13_s
{
    uint32_t  hcdma13 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA13. */
typedef volatile struct ALT_USB_HOST_HCDMA13_s  ALT_USB_HOST_HCDMA13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA13 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA13_OFST        0x2b4
/* The address of the ALT_USB_HOST_HCDMA13 register. */
#define ALT_USB_HOST_HCDMA13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA13_OFST))

/*
 * Register : Host Channel 13 DMA Buffer Address Register - hcdmab13
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                       
 * :-------|:-------|:------|:-----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 13 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 13 DMA Buffer Address - hcdmab13
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB13_HCDMAB13 field value from a register. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB13.
 */
struct ALT_USB_HOST_HCDMAB13_s
{
    uint32_t  hcdmab13 : 32;  /* Host Channel 13 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB13. */
typedef volatile struct ALT_USB_HOST_HCDMAB13_s  ALT_USB_HOST_HCDMAB13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB13 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB13_OFST        0x2b8
/* The address of the ALT_USB_HOST_HCDMAB13 register. */
#define ALT_USB_HOST_HCDMAB13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB13_OFST))

/*
 * Register : Host Channel 14 Characteristics Register - hcchar14
 * 
 * Host Channel 1 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR14_MPS register field value. */
#define ALT_USB_HOST_HCCHAR14_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_MPS register field value. */
#define ALT_USB_HOST_HCCHAR14_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR14_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5    0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6    0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7    0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8    0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9    0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10   0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11   0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12   0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13   0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14   0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15   0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR14_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description  
 * :----------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR14_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR14_EPDIR_E_IN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR14_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating
 * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host
 * core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR14_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description
 * :--------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR14_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                  
 * :--------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR14_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR14_EC_E_RSVD         0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EC register field value. */
#define ALT_USB_HOST_HCCHAR14_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EC register field value. */
#define ALT_USB_HOST_HCCHAR14_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR14_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR14_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR14_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR14_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR14_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                    |       | data  buffer  with data is setup and this       
 * :                                    |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR14_CHENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR14_CHENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR14_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR14_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR14_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR14_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR14.
 */
struct ALT_USB_HOST_HCCHAR14_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR14. */
typedef volatile struct ALT_USB_HOST_HCCHAR14_s  ALT_USB_HOST_HCCHAR14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR14 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR14_OFST        0x2c0
/* The address of the ALT_USB_HOST_HCCHAR14 register. */
#define ALT_USB_HOST_HCCHAR14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR14_OFST))

/*
 * Register : Host Channel 14 Split Control Register - hcsplt14
 * 
 * Channel_number 14
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT14_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT14_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT14_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                       |       | transaction (which is less than or equal to 188
 * :                                       |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_END     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT14_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description         
 * :-----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT14_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT14_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT14_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT14.
 */
struct ALT_USB_HOST_HCSPLT14_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT14. */
typedef volatile struct ALT_USB_HOST_HCSPLT14_s  ALT_USB_HOST_HCSPLT14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT14 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT14_OFST        0x2c4
/* The address of the ALT_USB_HOST_HCSPLT14 register. */
#define ALT_USB_HOST_HCSPLT14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT14_OFST))

/*
 * Register : Host Channel 14 Interrupt Register - hcint14
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT14_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description       
 * :------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT14_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT14_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT14_CHHLTD_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT14_CHHLTD_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT14_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT14_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT14_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT14_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT14_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                    
 * :------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT14_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT14_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT14_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT14_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_AHBERR register field value. */
#define ALT_USB_HOST_HCINT14_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT14_AHBERR register field value. */
#define ALT_USB_HOST_HCINT14_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT14_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT14_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT14_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT14_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT14_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_STALL register field value. */
#define ALT_USB_HOST_HCINT14_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT14_STALL register field value. */
#define ALT_USB_HOST_HCINT14_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_STALL field value from a register. */
#define ALT_USB_HOST_HCINT14_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT14_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT14_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT14_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT14_NAK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT14_NAK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_NAK register field value. */
#define ALT_USB_HOST_HCINT14_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT14_NAK register field value. */
#define ALT_USB_HOST_HCINT14_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_NAK field value from a register. */
#define ALT_USB_HOST_HCINT14_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT14_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                                   
 * :---------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT14_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT14_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT14_ACK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT14_ACK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_ACK register field value. */
#define ALT_USB_HOST_HCINT14_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT14_ACK register field value. */
#define ALT_USB_HOST_HCINT14_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_ACK field value from a register. */
#define ALT_USB_HOST_HCINT14_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT14_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT14_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT14_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT14_NYET_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT14_NYET_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_NYET register field value. */
#define ALT_USB_HOST_HCINT14_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT14_NYET register field value. */
#define ALT_USB_HOST_HCINT14_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_NYET field value from a register. */
#define ALT_USB_HOST_HCINT14_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT14_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT14_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT14_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT14_XACTERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT14_XACTERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_XACTERR register field value. */
#define ALT_USB_HOST_HCINT14_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT14_XACTERR register field value. */
#define ALT_USB_HOST_HCINT14_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT14_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT14_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT14_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT14_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT14_BBLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT14_BBLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_BBLERR register field value. */
#define ALT_USB_HOST_HCINT14_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT14_BBLERR register field value. */
#define ALT_USB_HOST_HCINT14_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT14_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT14_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT14_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT14_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT14_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT14_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT14_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT14_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT14_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT14_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT14_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT14_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT14_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                   
 * :--------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                     
 * :-----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT14.
 */
struct ALT_USB_HOST_HCINT14_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT14. */
typedef volatile struct ALT_USB_HOST_HCINT14_s  ALT_USB_HOST_HCINT14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT14 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT14_OFST        0x2c8
/* The address of the ALT_USB_HOST_HCINT14 register. */
#define ALT_USB_HOST_HCINT14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT14_OFST))

/*
 * Register : Host Channel 14 Interrupt Mask Register - hcintmsk14
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description
 * :----------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK14.
 */
struct ALT_USB_HOST_HCINTMSK14_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK14. */
typedef volatile struct ALT_USB_HOST_HCINTMSK14_s  ALT_USB_HOST_HCINTMSK14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK14 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK14_OFST        0x2cc
/* The address of the ALT_USB_HOST_HCINTMSK14 register. */
#define ALT_USB_HOST_HCINTMSK14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK14_OFST))

/*
 * Register : Host Channel 14 Transfer Size Register - hctsiz14
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic). The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ14_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ14_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ14_PID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_PID register field value. */
#define ALT_USB_HOST_HCTSIZ14_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PID register field value. */
#define ALT_USB_HOST_HCTSIZ14_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ14_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ14_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ14.
 */
struct ALT_USB_HOST_HCTSIZ14_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ14. */
typedef volatile struct ALT_USB_HOST_HCTSIZ14_s  ALT_USB_HOST_HCTSIZ14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ14 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ14_OFST        0x2d0
/* The address of the ALT_USB_HOST_HCTSIZ14 register. */
#define ALT_USB_HOST_HCTSIZ14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ14_OFST))

/*
 * Register : Host Channel 14 DMA Address Register - hcdma14
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma14
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA14_HCDMA14 field value from a register. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA14_HCDMA14 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA14.
 */
struct ALT_USB_HOST_HCDMA14_s
{
    uint32_t  hcdma14 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA14. */
typedef volatile struct ALT_USB_HOST_HCDMA14_s  ALT_USB_HOST_HCDMA14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA14 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA14_OFST        0x2d4
/* The address of the ALT_USB_HOST_HCDMA14 register. */
#define ALT_USB_HOST_HCDMA14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA14_OFST))

/*
 * Register : Host Channel 14 DMA Buffer Address Register - hcdmab14
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 0 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 0 DMA Buffer Address - hcdmab14
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB14_HCDMAB14 field value from a register. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB14.
 */
struct ALT_USB_HOST_HCDMAB14_s
{
    uint32_t  hcdmab14 : 32;  /* Host Channel 0 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB14. */
typedef volatile struct ALT_USB_HOST_HCDMAB14_s  ALT_USB_HOST_HCDMAB14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB14 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB14_OFST        0x2d8
/* The address of the ALT_USB_HOST_HCDMAB14 register. */
#define ALT_USB_HOST_HCDMAB14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB14_OFST))

/*
 * Register : Host Channel 15 Characteristics Register - hcchar15
 * 
 * Host Channel 15 Characteristics Register
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | RW     | 0x0   | Endpoint Number    
 *  [15]    | RW     | 0x0   | Endpoint Direction 
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | RW     | 0x0   | Low-Speed Device   
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [21:20] | RW     | 0x0   | Multi Count        
 *  [28:22] | RW     | 0x0   | Device Address     
 *  [29]    | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Channel Disable    
 *  [31]    | R      | 0x0   | Channel Enable     
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Indicates the maximum packet size of the associated endpoint.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_MSB        10
/* The width in bits of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_WIDTH      11
/* The mask used to set the ALT_USB_HOST_HCCHAR15_MPS register field value. */
#define ALT_USB_HOST_HCCHAR15_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_MPS register field value. */
#define ALT_USB_HOST_HCCHAR15_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR15_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : Endpoint Number - epnum
 * 
 * Indicates the endpoint number on the device serving as the data source or sink.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0  | 0x0   | End point  0 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1  | 0x1   | End point  1 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2  | 0x2   | End point  2 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3  | 0x3   | End point  3 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4  | 0x4   | End point  4 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5  | 0x5   | End point  5 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6  | 0x6   | End point  6 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7  | 0x7   | End point  7 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8  | 0x8   | End point  8 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9  | 0x9   | End point  9 
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 | 0xa   | End point  10
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 | 0xb   | End point  11
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 | 0xc   | End point  12
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 | 0xd   | End point  13
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 | 0xe   | End point  14
 *  ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 | 0xf   | End point  15
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  0
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  1
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1    0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  2
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2    0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  3
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3    0x3
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  4
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4    0x4
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  5
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5    0x5
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  6
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6    0x6
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  7
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7    0x7
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  8
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8    0x8
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  9
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9    0x9
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  10
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10   0xa
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  11
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11   0xb
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  12
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12   0xc
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  13
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13   0xd
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  14
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14   0xe
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
 * 
 * End point  15
 */
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15   0xf

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_MSB        14
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_WIDTH      4
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_SET_MSK    0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_CLR_MSK    0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR15_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_SET(value) (((value) << 11) & 0x00007800)

/*
 * Field : Endpoint Direction - epdir
 * 
 * Indicates whether the transaction is IN or OUT.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description  
 * :----------------------------------|:------|:--------------
 *  ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT | 0x0   | OUT Direction
 *  ALT_USB_HOST_HCCHAR15_EPDIR_E_IN  | 0x1   | IN Direction 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR
 * 
 * OUT Direction
 */
#define ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR
 * 
 * IN Direction
 */
#define ALT_USB_HOST_HCCHAR15_EPDIR_E_IN    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_MSB        15
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR15_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Low-Speed Device - lspddev
 * 
 * This field is set by the application to indicate that this channel is
 * communicating to a low-speed device. The application must program this bit when
 * a low speed device is connected to the host through an FS HUB. The HS OTG Host
 * core uses this field to drive the XCVR_SELECT signal to 2'b11 while
 * communicating to the LS Device through the FS hub. In a peer to peer setup, the
 * HS OTG Host core ignores this bit even if it is set by the application software
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                            
 * :-------------------------------------|:------|:----------------------------------------
 *  ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD | 0x0   | Not Communicating with low speed device
 *  ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END  | 0x1   | Communicating with low speed device    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV
 * 
 * Not Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV
 * 
 * Communicating with low speed device
 */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_MSB        17
/* The width in bits of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR15_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Indicates the transfer type selected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description
 * :--------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL    | 0x0   | Control    
 *  ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC   | 0x1   | Isochronous
 *  ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK   | 0x2   | Bulk       
 *  ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
 * 
 * Control
 */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR15_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Multi Count - ec
 * 
 * When the Split Enable bit of the Host Channel-n Split Control register
 * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of
 * transactions that must be executed per microframe for this periodic endpoint.
 * for non periodic transfers, this field is used only in DMA mode, and specifies
 * the number packets to be fetched for this channel before the internal DMA engine
 * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the
 * number of immediate retries to be performed for a periodic split transactions on
 * transaction errors. This field must be set to at least 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                  
 * :--------------------------------------|:------|:----------------------------------------------
 *  ALT_USB_HOST_HCCHAR15_EC_E_RSVD       | 0x0   | Reserved This field yields undefined result  
 *  ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE   | 0x1   | 1 transaction                                
 *  ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO   | 0x2   | 2 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 *  ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE | 0x3   | 3 transactions to be issued for this endpoint
 * :                                      |       | per microframe                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
 * 
 * Reserved This field yields undefined result
 */
#define ALT_USB_HOST_HCCHAR15_EC_E_RSVD         0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
 * 
 * 1 transaction
 */
#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
 * 
 * 2 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO     0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
 * 
 * 3 transactions to be issued for this endpoint per microframe
 */
#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_MSB        21
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EC register field value. */
#define ALT_USB_HOST_HCCHAR15_EC_SET_MSK    0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EC register field value. */
#define ALT_USB_HOST_HCCHAR15_EC_CLR_MSK    0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR15_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EC_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Device Address - devaddr
 * 
 * This field selects the specific device serving as the data source or sink.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_MSB        28
/* The width in bits of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_SET_MSK    0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_CLR_MSK    0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR15_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)

/*
 * Field : Channel Disable - chdis
 * 
 * The application sets this bit to stop transmitting/receiving data on a channel,
 * even before the transfer for that channel is complete. The application must wait
 * for the Channel Disabled interrupt before treating the channel as disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT | 0x0   | Transmit/Recieve normal    
 *  ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT   | 0x1   | Stop transmitting/receiving
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS
 * 
 * Transmit/Recieve normal
 */
#define ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS
 * 
 * Stop transmitting/receiving
 */
#define ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_MSB        30
/* The width in bits of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR15_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Channel Enable - chena
 * 
 * When Scatter/Gather mode is disabled This field is set by the application and
 * cleared by the OTG host.
 * 
 * 0: Channel disabled
 * 
 * 1: Channel enabled
 * 
 * When Scatter/Gather mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_HOST_HCCHAR15_CHENA_E_INACT | 0x0   | Indicates that the descriptor structure is not  
 * :                                    |       | yet ready                                       
 *  ALT_USB_HOST_HCCHAR15_CHENA_E_ACT   | 0x1   | Indicates  that  the  descriptor  structure  and
 * :                                    |       | data  buffer  with data is setup and this       
 * :                                    |       | channel can access the descriptor               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA
 * 
 * Indicates that the descriptor structure is not yet ready
 */
#define ALT_USB_HOST_HCCHAR15_CHENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA
 * 
 * Indicates  that  the  descriptor  structure  and  data  buffer  with data is
 * setup and this channel can access the descriptor
 */
#define ALT_USB_HOST_HCCHAR15_CHENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR15_CHENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR15_CHENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR15_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR15_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_CHENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCCHAR15.
 */
struct ALT_USB_HOST_HCCHAR15_s
{
    uint32_t        mps     : 11;  /* Maximum Packet Size */
    uint32_t        epnum   :  4;  /* Endpoint Number */
    uint32_t        epdir   :  1;  /* Endpoint Direction */
    uint32_t                :  1;  /* *UNDEFINED* */
    uint32_t        lspddev :  1;  /* Low-Speed Device */
    uint32_t        eptype  :  2;  /* Endpoint Type */
    uint32_t        ec      :  2;  /* Multi Count */
    uint32_t        devaddr :  7;  /* Device Address */
    uint32_t                :  1;  /* *UNDEFINED* */
    const uint32_t  chdis   :  1;  /* Channel Disable */
    const uint32_t  chena   :  1;  /* Channel Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCCHAR15. */
typedef volatile struct ALT_USB_HOST_HCCHAR15_s  ALT_USB_HOST_HCCHAR15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCCHAR15 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR15_OFST        0x2e0
/* The address of the ALT_USB_HOST_HCCHAR15 register. */
#define ALT_USB_HOST_HCCHAR15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR15_OFST))

/*
 * Register : Host Channel 15 Split Control Register - hcsplt15
 * 
 * Channel_number 15.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description         
 * :--------|:-------|:------|:---------------------
 *  [6:0]   | RW     | 0x0   | Port Address        
 *  [13:7]  | RW     | 0x0   | Hub Address         
 *  [15:14] | RW     | 0x0   | Transaction Position
 *  [16]    | RW     | 0x0   | Do Complete Split   
 *  [30:17] | ???    | 0x0   | *UNDEFINED*         
 *  [31]    | RW     | 0x0   | Split Enable        
 * 
 */
/*
 * Field : Port Address - prtaddr
 * 
 * This field is the port number of the recipient transactiontranslator.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_MSB        6
/* The width in bits of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT15_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Hub Address - hubaddr
 * 
 * This field holds the device address of the transaction translator's hub.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_WIDTH      7
/* The mask used to set the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_SET_MSK    0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_CLR_MSK    0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT15_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)

/*
 * Field : Transaction Position - xactpos
 * 
 * This field is used to determine whether to send all, first, middle, or last
 * payloads with each OUT transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                    
 * :---------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE | 0x0   | Mid. This is the middle payload of this        
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT15_XACTPOS_E_END    | 0x1   | End. This is the last payload of this          
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN  | 0x2   | Begin. This is the first data payload of this  
 * :                                       |       | transaction (which is larger than 188 bytes)   
 *  ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL    | 0x3   | All. This is the entire data payload is of this
 * :                                       |       | transaction (which is less than or equal to 188
 * :                                       |       | bytes)                                         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
 * 
 * Mid. This is the middle payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
 * 
 * End. This is the last payload of this transaction (which is larger than 188
 * bytes)
 */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_END     0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
 * 
 * Begin. This is the first data payload of this transaction (which is larger than
 * 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
 * 
 * All. This is the entire data payload is of this transaction (which is less than
 * or equal to 188 bytes)
 */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_MSB        15
/* The width in bits of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_SET_MSK    0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_CLR_MSK    0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT15_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)

/*
 * Field : Do Complete Split - compsplt
 * 
 * The application sets this field to request the OTG host to perform a complete
 * split transaction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description         
 * :-----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT | 0x0   | No split transaction
 *  ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT   | 0x1   | Split transaction   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT
 * 
 * No split transaction
 */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT
 * 
 * Split transaction
 */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_MSB        16
/* The width in bits of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT15_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Split Enable - spltena
 * 
 * The application sets this field to indicate that this channel is enabled to
 * perform split transactions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD | 0x0   | Split not enabled
 *  ALT_USB_HOST_HCSPLT15_SPLTENA_E_END  | 0x1   | Split enabled    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA
 * 
 * Split not enabled
 */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA
 * 
 * Split enabled
 */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_MSB        31
/* The width in bits of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_RESET      0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT15_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCSPLT15.
 */
struct ALT_USB_HOST_HCSPLT15_s
{
    uint32_t  prtaddr  :  7;  /* Port Address */
    uint32_t  hubaddr  :  7;  /* Hub Address */
    uint32_t  xactpos  :  2;  /* Transaction Position */
    uint32_t  compsplt :  1;  /* Do Complete Split */
    uint32_t           : 14;  /* *UNDEFINED* */
    uint32_t  spltena  :  1;  /* Split Enable */
};

/* The typedef declaration for register ALT_USB_HOST_HCSPLT15. */
typedef volatile struct ALT_USB_HOST_HCSPLT15_s  ALT_USB_HOST_HCSPLT15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCSPLT15 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT15_OFST        0x2e4
/* The address of the ALT_USB_HOST_HCSPLT15 register. */
#define ALT_USB_HOST_HCSPLT15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT15_OFST))

/*
 * Register : Host Channel 15 Interrupt Register - hcint15
 * 
 * This register indicates the status of a channel with respect to USB- and AHB-
 * related events. The application must read this register when the Host Channels
 * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the
 * application can read this register, it must first read the Host All Channels
 * Interrupt (HAINT) register to get the exact channel number for the Host
 * Channel-n Interrupt register. The application must clear the appropriate bit in
 * this register to clear the corresponding bits in the HAINT and GINTSTS
 * registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                
 * :--------|:-------|:------|:--------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed                         
 *  [1]     | R      | 0x0   | Channel Halted                             
 *  [2]     | R      | 0x0   | AHB Error                                  
 *  [3]     | R      | 0x0   | STALL Response Received Interrupt          
 *  [4]     | R      | 0x0   | NAK Response Received Interrupt            
 *  [5]     | R      | 0x0   | ACK Response Received Transmitted Interrupt
 *  [6]     | R      | 0x0   | NYET Response Received Interrupt           
 *  [7]     | R      | 0x0   | Transaction Error                          
 *  [8]     | R      | 0x0   | Babble Error                               
 *  [9]     | R      | 0x0   | Frame Overrun                              
 *  [10]    | R      | 0x0   | Data Toggle Error                          
 *  [11]    | R      | 0x0   | BNA Interrupt                              
 *  [12]    | R      | 0x0   | Excessive Transaction Error                
 *  [13]    | R      | 0x0   | Descriptor rollover interrupt              
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                                
 * 
 */
/*
 * Field : Transfer Completed - xfercompl
 * 
 * Transfer completed normally without any errors. This bit can be set only by the
 * core and the application should write 1 to clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                                   
 * :---------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT | 0x0   | No transfer                                   
 *  ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT   | 0x1   | Transfer completed normally without any errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL
 * 
 * No transfer
 */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL
 * 
 * Transfer completed normally without any errors
 */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT15_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted - chhltd
 * 
 * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
 * either because of any USB transaction error or in response to disable request by
 * the application or because of a completed transfer. In Scatter/gather DMA mode,
 * this indicates that transfer completed due to any of the following
 * 
 * . EOL being set in descriptor
 * 
 * . AHB error
 * 
 * . Excessive transaction errors
 * 
 * . Babble
 * 
 * . Stall
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description       
 * :------------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT15_CHHLTD_E_INACT | 0x0   | Channel not halted
 *  ALT_USB_HOST_HCINT15_CHHLTD_E_ACT   | 0x1   | Channel Halted    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD
 * 
 * Channel not halted
 */
#define ALT_USB_HOST_HCINT15_CHHLTD_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD
 * 
 * Channel Halted
 */
#define ALT_USB_HOST_HCINT15_CHHLTD_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT15_CHHLTD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT15_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT15_CHHLTD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT15_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT15_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_CHHLTD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * This is generated only in Internal DMA mode when there is an AHB error during
 * AHB read/write. The application can read the corresponding channel's DMA address
 * register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                    
 * :------------------------------------|:------|:--------------------------------
 *  ALT_USB_HOST_HCINT15_AHBERR_E_INACT | 0x0   | No AHB error                   
 *  ALT_USB_HOST_HCINT15_AHBERR_E_ACT   | 0x1   | AHB error during AHB read/write
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR
 * 
 * No AHB error
 */
#define ALT_USB_HOST_HCINT15_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR
 * 
 * AHB error during AHB read/write
 */
#define ALT_USB_HOST_HCINT15_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_AHBERR register field value. */
#define ALT_USB_HOST_HCINT15_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT15_AHBERR register field value. */
#define ALT_USB_HOST_HCINT15_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT15_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : STALL Response Received Interrupt - stall
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_USB_HOST_HCINT15_STALL_E_INACT | 0x0   | No Stall Interrupt
 *  ALT_USB_HOST_HCINT15_STALL_E_ACT   | 0x1   | Stall Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_STALL
 * 
 * No Stall Interrupt
 */
#define ALT_USB_HOST_HCINT15_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_STALL
 * 
 * Stall Interrupt
 */
#define ALT_USB_HOST_HCINT15_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_MSB        3
/* The width in bits of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_STALL register field value. */
#define ALT_USB_HOST_HCINT15_STALL_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT15_STALL register field value. */
#define ALT_USB_HOST_HCINT15_STALL_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_STALL field value from a register. */
#define ALT_USB_HOST_HCINT15_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT15_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_STALL_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : NAK Response Received Interrupt - nak
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_HOST_HCINT15_NAK_E_INACT | 0x0   | No NAK Response Received Interrupt
 *  ALT_USB_HOST_HCINT15_NAK_E_ACT   | 0x1   | NAK Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_NAK
 * 
 * No NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT15_NAK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_NAK
 * 
 * NAK Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT15_NAK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_MSB        4
/* The width in bits of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_NAK register field value. */
#define ALT_USB_HOST_HCINT15_NAK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT15_NAK register field value. */
#define ALT_USB_HOST_HCINT15_NAK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_NAK field value from a register. */
#define ALT_USB_HOST_HCINT15_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT15_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_NAK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : ACK Response Received Transmitted Interrupt - ack
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                                   
 * :---------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_HOST_HCINT15_ACK_E_INACT | 0x0   | No ACK Response Received Transmitted Interrupt
 *  ALT_USB_HOST_HCINT15_ACK_E_ACT   | 0x1   | ACK Response Received Transmitted Interrup    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_ACK
 * 
 * No ACK Response Received Transmitted Interrupt
 */
#define ALT_USB_HOST_HCINT15_ACK_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_ACK
 * 
 * ACK Response Received Transmitted Interrup
 */
#define ALT_USB_HOST_HCINT15_ACK_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_MSB        5
/* The width in bits of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_ACK register field value. */
#define ALT_USB_HOST_HCINT15_ACK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT15_ACK register field value. */
#define ALT_USB_HOST_HCINT15_ACK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_ACK field value from a register. */
#define ALT_USB_HOST_HCINT15_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT15_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_ACK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : NYET Response Received Interrupt - nyet
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCINT15_NYET_E_INACT | 0x0   | No NYET Response Received Interrupt
 *  ALT_USB_HOST_HCINT15_NYET_E_ACT   | 0x1   | NYET Response Received Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_NYET
 * 
 * No NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT15_NYET_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_NYET
 * 
 * NYET Response Received Interrupt
 */
#define ALT_USB_HOST_HCINT15_NYET_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_MSB        6
/* The width in bits of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_NYET register field value. */
#define ALT_USB_HOST_HCINT15_NYET_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT15_NYET register field value. */
#define ALT_USB_HOST_HCINT15_NYET_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_NYET field value from a register. */
#define ALT_USB_HOST_HCINT15_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT15_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_NYET_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transaction Error - xacterr
 * 
 * Indicates one of the following errors occurred on the USB.-CRC check failure
 * 
 * * Timeout
 * 
 * * Bit stuff error
 * 
 * * False EOP
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT15_XACTERR_E_INACT | 0x0   | No Transaction Error
 *  ALT_USB_HOST_HCINT15_XACTERR_E_ACT   | 0x1   | Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR
 * 
 * No Transaction Error
 */
#define ALT_USB_HOST_HCINT15_XACTERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR
 * 
 * Transaction Error
 */
#define ALT_USB_HOST_HCINT15_XACTERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_MSB        7
/* The width in bits of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_XACTERR register field value. */
#define ALT_USB_HOST_HCINT15_XACTERR_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT15_XACTERR register field value. */
#define ALT_USB_HOST_HCINT15_XACTERR_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT15_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT15_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_XACTERR_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Babble Error - bblerr
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core..This bit can be set only by the core and the application should write 1 to
 * clear it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_USB_HOST_HCINT15_BBLERR_E_INACT | 0x0   | No Babble Error
 *  ALT_USB_HOST_HCINT15_BBLERR_E_ACT   | 0x1   | Babble Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR
 * 
 * No Babble Error
 */
#define ALT_USB_HOST_HCINT15_BBLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR
 * 
 * Babble Error
 */
#define ALT_USB_HOST_HCINT15_BBLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_MSB        8
/* The width in bits of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_BBLERR register field value. */
#define ALT_USB_HOST_HCINT15_BBLERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT15_BBLERR register field value. */
#define ALT_USB_HOST_HCINT15_BBLERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT15_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT15_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_BBLERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Frame Overrun - frmovrun
 * 
 * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.
 * This bit can be set only by the core and the application should write 1 to clear
 * it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description     
 * :--------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT | 0x0   | No Frame Overrun
 *  ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT   | 0x1   | Frame Overrun   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN
 * 
 * No Frame Overrun
 */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN
 * 
 * Frame Overrun
 */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_MSB        9
/* The width in bits of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT15_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Data Toggle Error - datatglerr
 * 
 * This bit can be set only by the core and the application should write 1 to clear
 * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the
 * core.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description         
 * :----------------------------------------|:------|:---------------------
 *  ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT | 0x0   | No Data Toggle Error
 *  ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT   | 0x1   | Data Toggle Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR
 * 
 * No Data Toggle Error
 */
#define ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR
 * 
 * Data Toggle Error
 */
#define ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_MSB        10
/* The width in bits of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT15_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process. BNA will not be generated for Isochronous channels. for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCINT15_BNAINTR_E_INACT | 0x0   | No BNA Interrupt
 *  ALT_USB_HOST_HCINT15_BNAINTR_E_ACT   | 0x1   | BNA Interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR
 * 
 * No BNA Interrupt
 */
#define ALT_USB_HOST_HCINT15_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR
 * 
 * BNA Interrupt
 */
#define ALT_USB_HOST_HCINT15_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT15_BNAINTR_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT15_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT15_BNAINTR_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT15_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT15_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_BNAINTR_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Excessive Transaction Error - xcs_xact_err
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
 * this bit when 3 consecutive transaction errors occurred on the USB bus.
 * XCS_XACT_ERR will not be generated for Isochronous channels.for non
 * Scatter/Gather DMA mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                   
 * :--------------------------------------------|:------|:-------------------------------
 *  ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT   | 0x0   | No Excessive Transaction Error
 *  ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE | 0x1   | Excessive Transaction Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR
 * 
 * No Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR
 * 
 * Excessive Transaction Error
 */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_MSB        12
/* The width in bits of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Descriptor rollover interrupt - desc_lst_rollintr
 * 
 * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when
 * Scatter/Gather DMA mode is enabled. The core sets this bit when the
 * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA
 * mode, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                     
 * :-----------------------------------------------|:------|:---------------------------------
 *  ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT | 0x0   | No Descriptor rollover interrupt
 *  ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT   | 0x1   | Descriptor rollover interrupt   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
 * 
 * No Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
 * 
 * Descriptor rollover interrupt
 */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINT15.
 */
struct ALT_USB_HOST_HCINT15_s
{
    const uint32_t  xfercompl         :  1;  /* Transfer Completed */
    const uint32_t  chhltd            :  1;  /* Channel Halted */
    const uint32_t  ahberr            :  1;  /* AHB Error */
    const uint32_t  stall             :  1;  /* STALL Response Received Interrupt */
    const uint32_t  nak               :  1;  /* NAK Response Received Interrupt */
    const uint32_t  ack               :  1;  /* ACK Response Received Transmitted Interrupt */
    const uint32_t  nyet              :  1;  /* NYET Response Received Interrupt */
    const uint32_t  xacterr           :  1;  /* Transaction Error */
    const uint32_t  bblerr            :  1;  /* Babble Error */
    const uint32_t  frmovrun          :  1;  /* Frame Overrun */
    const uint32_t  datatglerr        :  1;  /* Data Toggle Error */
    const uint32_t  bnaintr           :  1;  /* BNA Interrupt */
    const uint32_t  xcs_xact_err      :  1;  /* Excessive Transaction Error */
    const uint32_t  desc_lst_rollintr :  1;  /* Descriptor rollover interrupt */
    uint32_t                          : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINT15. */
typedef volatile struct ALT_USB_HOST_HCINT15_s  ALT_USB_HOST_HCINT15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINT15 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT15_OFST        0x2e8
/* The address of the ALT_USB_HOST_HCINT15 register. */
#define ALT_USB_HOST_HCINT15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT15_OFST))

/*
 * Register : Host Channel 15 Interrupt Mask Register - hcintmsk15
 * 
 * This register reflects the mask for each channel status described in the
 * previous section.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Mask          
 *  [1]     | RW     | 0x0   | Channel Halted Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                   
 *  [10:3]  | ???    | 0x0   | *UNDEFINED*                      
 *  [11]    | RW     | 0x0   | BNA Interrupt  mask              
 *  [12]    | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Framelist Rollover Interrupt Mask
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transfer Completed Mask - xfercomplmsk
 * 
 * Transfer complete.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Channel Halted Mask - chhltdmsk
 * 
 * Channel Halted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_MSB        1
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * In  scatter/gather DMA  mode  for  host, interrupts will not be generated due to
 * the corresponding bits set in HCINTn.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : BNA Interrupt  mask - bnaintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_MSB        11
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description
 * :----------------------------------------------------|:------|:------------
 *  ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK   | 0x0   | Mask       
 *  ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1   | No mask    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
 * 
 * Mask
 */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
 * 
 * No mask
 */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_MSB        13
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_RESET      0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCINTMSK15.
 */
struct ALT_USB_HOST_HCINTMSK15_s
{
    uint32_t  xfercomplmsk        :  1;  /* Transfer Completed Mask */
    uint32_t  chhltdmsk           :  1;  /* Channel Halted Mask */
    uint32_t  ahberrmsk           :  1;  /* AHB Error Mask */
    uint32_t                      :  8;  /* *UNDEFINED* */
    uint32_t  bnaintrmsk          :  1;  /* BNA Interrupt  mask */
    uint32_t                      :  1;  /* *UNDEFINED* */
    uint32_t  frm_lst_rollintrmsk :  1;  /* Framelist Rollover Interrupt Mask */
    uint32_t                      : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_HOST_HCINTMSK15. */
typedef volatile struct ALT_USB_HOST_HCINTMSK15_s  ALT_USB_HOST_HCINTMSK15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCINTMSK15 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK15_OFST        0x2ec
/* The address of the ALT_USB_HOST_HCINTMSK15 register. */
#define ALT_USB_HOST_HCINTMSK15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK15_OFST))

/*
 * Register : Host Channel 15 Transfer Size Register - hctsiz15
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [18:0]  | RW     | 0x0   | Transfer Size
 *  [28:19] | RW     | 0x0   | Packet Count 
 *  [30:29] | RW     | 0x0   | PID          
 *  [31]    | RW     | 0x0   | Do Ping      
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * for an OUT, this field is the number of data bytes the host sends during the
 * transfer. for an IN, this field is the buffer size that the application has
 * Reserved for the transfer. The application is expected to program this field as
 * an integer multiple of the maximum packet size for IN transactions (periodic and
 * non-periodic).The width of this counter is specified as 19 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is programmed by the application with the expected number of packets
 * to be transmitted (OUT) or received (IN). The host decrements this count on
 * every successful transmission or reception of an OUT/IN packet. Once this count
 * reaches zero, the application is interrupted to indicate normal completion. The
 * width of this counter is specified as 10 bits.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ15_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : PID - pid
 * 
 * The application programs this field with the type of PID to use forthe initial
 * transaction. The host maintains this field for the rest of the transfer.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                        
 * :----------------------------------|:------|:------------------------------------
 *  ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 | 0x0   | DATA0                              
 *  ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 | 0x1   | DATA2                              
 *  ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 | 0x2   | DATA1                              
 *  ALT_USB_HOST_HCTSIZ15_PID_E_MDATA | 0x3   | MDATA (non-control)/SETUP (control)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
 * 
 * DATA0
 */
#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA0   0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
 * 
 * DATA2
 */
#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA2   0x1
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
 * 
 * DATA1
 */
#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA1   0x2
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
 * 
 * MDATA (non-control)/SETUP (control)
 */
#define ALT_USB_HOST_HCTSIZ15_PID_E_MDATA   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_MSB        30
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_WIDTH      2
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_PID register field value. */
#define ALT_USB_HOST_HCTSIZ15_PID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PID register field value. */
#define ALT_USB_HOST_HCTSIZ15_PID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ15_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_PID_SET(value) (((value) << 29) & 0x60000000)

/*
 * Field : Do Ping - dopng
 * 
 * This bit is used only for OUT transfers.Setting this field to 1 directs the host
 * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set
 * for IN transfers it disables the channel.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING | 0x0   | No ping protocol
 *  ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING   | 0x1   | Ping protocol   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG
 * 
 * No ping protocol
 */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING    0x0
/*
 * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG
 * 
 * Ping protocol
 */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_MSB        31
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_WIDTH      1
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_RESET      0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ15_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCTSIZ15.
 */
struct ALT_USB_HOST_HCTSIZ15_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  pid      :  2;  /* PID */
    uint32_t  dopng    :  1;  /* Do Ping */
};

/* The typedef declaration for register ALT_USB_HOST_HCTSIZ15. */
typedef volatile struct ALT_USB_HOST_HCTSIZ15_s  ALT_USB_HOST_HCTSIZ15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCTSIZ15 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ15_OFST        0x2f0
/* The address of the ALT_USB_HOST_HCTSIZ15 register. */
#define ALT_USB_HOST_HCTSIZ15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ15_OFST))

/*
 * Register : Host Channel 15 DMA Address Register - hcdma15
 * 
 * This register is used by the OTG host in the internal DMA mode to maintain the
 * current buffer pointer for IN/OUT transactions. The starting DMA address must be
 * DWORD-aligned.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | RW     | 0x0   | DMA Address
 * 
 */
/*
 * Field : DMA Address - hcdma15
 * 
 * Non-Isochronous: This field holds the start address of the 512 bytes  page.  The
 * first descriptor in the list should be located in this address. The first
 * descriptor may be or may not be ready. The core starts processing the list from
 * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations
 * in which the isochronous descriptors are present where N is based on nTD as per
 * Table below
 * 
 * [31:N]  Base Address [N-1:3]  Offset  [2:0]  000
 * 
 * HS ISOC                           FS ISOC
 * 
 * nTD   N                          nTD     N
 * 
 * 7     6                           1       4
 * 
 * 15    7                           3      5
 * 
 * 31    8                           7      6
 * 
 * 63    9                           15     7
 * 
 * 127  10                           31     8
 * 
 * 255  11                           63     9
 * 
 * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD):  Non Isochronous:
 * This value is in terms of number of descriptors. The values can be from 0 to 63.
 * 0 -  1 descriptor. 63 - 64 descriptors. This field indicates the current
 * descriptor processed in the list. This field is updated both by application and
 * the core. for example, if the application enables the channel after programming
 * CTD=5, then the core will start processing the 6th descriptor. The address is
 * obtained by adding a value of (8bytes*5=) 40(decimal)  to DMAAddr.  Isochronous:
 * CTD for isochronous is based on the current frame/microframe value. Need to be
 * set to zero by application.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMA15_HCDMA15 field value from a register. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA15_HCDMA15 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMA15.
 */
struct ALT_USB_HOST_HCDMA15_s
{
    uint32_t  hcdma15 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMA15. */
typedef volatile struct ALT_USB_HOST_HCDMA15_s  ALT_USB_HOST_HCDMA15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMA15 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA15_OFST        0x2f4
/* The address of the ALT_USB_HOST_HCDMA15 register. */
#define ALT_USB_HOST_HCDMA15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA15_OFST))

/*
 * Register : Host Channel 15 DMA Buffer Address Register - hcdmab15
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather  DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address.  This  register  is  updated  as  and when  the
 * data  transfer  for  the corresponding  end  point  is  in progress.  This
 * register  is  present  only  in  Scatter/Gather  DMA mode. Otherwise this field
 * is reserved.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                       
 * :-------|:-------|:------|:-----------------------------------
 *  [31:0] | RW     | 0x0   | Host Channel 15 DMA Buffer Address
 * 
 */
/*
 * Field : Host Channel 15 DMA Buffer Address - hcdmab15
 * 
 * These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These
 * registers  are  implemented  in RAM instead of flop-based implementation. Holds
 * the  current  buffer  address. This register is updated as and when  the  data
 * transfer for the corresponding  end  point  is  in progress. This register  is
 * present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_MSB        31
/* The width in bits of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_WIDTH      32
/* The mask used to set the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_RESET      0x0
/* Extracts the ALT_USB_HOST_HCDMAB15_HCDMAB15 field value from a register. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_HOST_HCDMAB15.
 */
struct ALT_USB_HOST_HCDMAB15_s
{
    uint32_t  hcdmab15 : 32;  /* Host Channel 15 DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_HOST_HCDMAB15. */
typedef volatile struct ALT_USB_HOST_HCDMAB15_s  ALT_USB_HOST_HCDMAB15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_HOST_HCDMAB15 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB15_OFST        0x2f8
/* The address of the ALT_USB_HOST_HCDMAB15 register. */
#define ALT_USB_HOST_HCDMAB15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB15_OFST))

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_USB_HOST.
 */
struct ALT_USB_HOST_s
{
    volatile ALT_USB_HOST_HCFG_t        hcfg;                /* ALT_USB_HOST_HCFG */
    volatile ALT_USB_HOST_HFIR_t        hfir;                /* ALT_USB_HOST_HFIR */
    volatile ALT_USB_HOST_HFNUM_t       hfnum;               /* ALT_USB_HOST_HFNUM */
    volatile uint32_t                   _pad_0xc_0xf;        /* *UNDEFINED* */
    volatile ALT_USB_HOST_HPTXSTS_t     hptxsts;             /* ALT_USB_HOST_HPTXSTS */
    volatile ALT_USB_HOST_HAINT_t       haint;               /* ALT_USB_HOST_HAINT */
    volatile ALT_USB_HOST_HAINTMSK_t    haintmsk;            /* ALT_USB_HOST_HAINTMSK */
    volatile ALT_USB_HOST_HFLBADDR_t    hflbaddr;            /* ALT_USB_HOST_HFLBADDR */
    volatile uint32_t                   _pad_0x20_0x3f[8];   /* *UNDEFINED* */
    volatile ALT_USB_HOST_HPRT_t        hprt;                /* ALT_USB_HOST_HPRT */
    volatile uint32_t                   _pad_0x44_0xff[47];  /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR0_t     hcchar0;             /* ALT_USB_HOST_HCCHAR0 */
    volatile ALT_USB_HOST_HCSPLT0_t     hcsplt0;             /* ALT_USB_HOST_HCSPLT0 */
    volatile ALT_USB_HOST_HCINT0_t      hcint0;              /* ALT_USB_HOST_HCINT0 */
    volatile ALT_USB_HOST_HCINTMSK0_t   hcintmsk0;           /* ALT_USB_HOST_HCINTMSK0 */
    volatile ALT_USB_HOST_HCTSIZ0_t     hctsiz0;             /* ALT_USB_HOST_HCTSIZ0 */
    volatile ALT_USB_HOST_HCDMA0_t      hcdma0;              /* ALT_USB_HOST_HCDMA0 */
    volatile ALT_USB_HOST_HCDMAB0_t     hcdmab0;             /* ALT_USB_HOST_HCDMAB0 */
    volatile uint32_t                   _pad_0x11c_0x11f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR1_t     hcchar1;             /* ALT_USB_HOST_HCCHAR1 */
    volatile ALT_USB_HOST_HCSPLT1_t     hcsplt1;             /* ALT_USB_HOST_HCSPLT1 */
    volatile ALT_USB_HOST_HCINT1_t      hcint1;              /* ALT_USB_HOST_HCINT1 */
    volatile ALT_USB_HOST_HCINTMSK1_t   hcintmsk1;           /* ALT_USB_HOST_HCINTMSK1 */
    volatile ALT_USB_HOST_HCTSIZ1_t     hctsiz1;             /* ALT_USB_HOST_HCTSIZ1 */
    volatile ALT_USB_HOST_HCDMA1_t      hcdma1;              /* ALT_USB_HOST_HCDMA1 */
    volatile ALT_USB_HOST_HCDMAB1_t     hcdmab1;             /* ALT_USB_HOST_HCDMAB1 */
    volatile uint32_t                   _pad_0x13c_0x13f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR2_t     hcchar2;             /* ALT_USB_HOST_HCCHAR2 */
    volatile ALT_USB_HOST_HCSPLT2_t     hcsplt2;             /* ALT_USB_HOST_HCSPLT2 */
    volatile ALT_USB_HOST_HCINT2_t      hcint2;              /* ALT_USB_HOST_HCINT2 */
    volatile ALT_USB_HOST_HCINTMSK2_t   hcintmsk2;           /* ALT_USB_HOST_HCINTMSK2 */
    volatile ALT_USB_HOST_HCTSIZ2_t     hctsiz2;             /* ALT_USB_HOST_HCTSIZ2 */
    volatile ALT_USB_HOST_HCDMA2_t      hcdma2;              /* ALT_USB_HOST_HCDMA2 */
    volatile ALT_USB_HOST_HCDMAB2_t     hcdmab2;             /* ALT_USB_HOST_HCDMAB2 */
    volatile uint32_t                   _pad_0x15c_0x15f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR3_t     hcchar3;             /* ALT_USB_HOST_HCCHAR3 */
    volatile ALT_USB_HOST_HCSPLT3_t     hcsplt3;             /* ALT_USB_HOST_HCSPLT3 */
    volatile ALT_USB_HOST_HCINT3_t      hcint3;              /* ALT_USB_HOST_HCINT3 */
    volatile ALT_USB_HOST_HCINTMSK3_t   hcintmsk3;           /* ALT_USB_HOST_HCINTMSK3 */
    volatile ALT_USB_HOST_HCTSIZ3_t     hctsiz3;             /* ALT_USB_HOST_HCTSIZ3 */
    volatile ALT_USB_HOST_HCDMA3_t      hcdma3;              /* ALT_USB_HOST_HCDMA3 */
    volatile ALT_USB_HOST_HCDMAB3_t     hcdmab3;             /* ALT_USB_HOST_HCDMAB3 */
    volatile uint32_t                   _pad_0x17c_0x17f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR4_t     hcchar4;             /* ALT_USB_HOST_HCCHAR4 */
    volatile ALT_USB_HOST_HCSPLT4_t     hcsplt4;             /* ALT_USB_HOST_HCSPLT4 */
    volatile ALT_USB_HOST_HCINT4_t      hcint4;              /* ALT_USB_HOST_HCINT4 */
    volatile ALT_USB_HOST_HCINTMSK4_t   hcintmsk4;           /* ALT_USB_HOST_HCINTMSK4 */
    volatile ALT_USB_HOST_HCTSIZ4_t     hctsiz4;             /* ALT_USB_HOST_HCTSIZ4 */
    volatile ALT_USB_HOST_HCDMA4_t      hcdma4;              /* ALT_USB_HOST_HCDMA4 */
    volatile ALT_USB_HOST_HCDMAB4_t     hcdmab4;             /* ALT_USB_HOST_HCDMAB4 */
    volatile uint32_t                   _pad_0x19c_0x19f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR5_t     hcchar5;             /* ALT_USB_HOST_HCCHAR5 */
    volatile ALT_USB_HOST_HCSPLT5_t     hcsplt5;             /* ALT_USB_HOST_HCSPLT5 */
    volatile ALT_USB_HOST_HCINT5_t      hcint5;              /* ALT_USB_HOST_HCINT5 */
    volatile ALT_USB_HOST_HCINTMSK5_t   hcintmsk5;           /* ALT_USB_HOST_HCINTMSK5 */
    volatile ALT_USB_HOST_HCTSIZ5_t     hctsiz5;             /* ALT_USB_HOST_HCTSIZ5 */
    volatile ALT_USB_HOST_HCDMA5_t      hcdma5;              /* ALT_USB_HOST_HCDMA5 */
    volatile ALT_USB_HOST_HCDMAB5_t     hcdmab5;             /* ALT_USB_HOST_HCDMAB5 */
    volatile uint32_t                   _pad_0x1bc_0x1bf;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR6_t     hcchar6;             /* ALT_USB_HOST_HCCHAR6 */
    volatile ALT_USB_HOST_HCSPLT6_t     hcsplt6;             /* ALT_USB_HOST_HCSPLT6 */
    volatile ALT_USB_HOST_HCINT6_t      hcint6;              /* ALT_USB_HOST_HCINT6 */
    volatile ALT_USB_HOST_HCINTMSK6_t   hcintmsk6;           /* ALT_USB_HOST_HCINTMSK6 */
    volatile ALT_USB_HOST_HCTSIZ6_t     hctsiz6;             /* ALT_USB_HOST_HCTSIZ6 */
    volatile ALT_USB_HOST_HCDMA6_t      hcdma6;              /* ALT_USB_HOST_HCDMA6 */
    volatile ALT_USB_HOST_HCDMAB6_t     hcdmab6;             /* ALT_USB_HOST_HCDMAB6 */
    volatile uint32_t                   _pad_0x1dc_0x1df;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR7_t     hcchar7;             /* ALT_USB_HOST_HCCHAR7 */
    volatile ALT_USB_HOST_HCSPLT7_t     hcsplt7;             /* ALT_USB_HOST_HCSPLT7 */
    volatile ALT_USB_HOST_HCINT7_t      hcint7;              /* ALT_USB_HOST_HCINT7 */
    volatile ALT_USB_HOST_HCINTMSK7_t   hcintmsk7;           /* ALT_USB_HOST_HCINTMSK7 */
    volatile ALT_USB_HOST_HCTSIZ7_t     hctsiz7;             /* ALT_USB_HOST_HCTSIZ7 */
    volatile ALT_USB_HOST_HCDMA7_t      hcdma7;              /* ALT_USB_HOST_HCDMA7 */
    volatile ALT_USB_HOST_HCDMAB7_t     hcdmab7;             /* ALT_USB_HOST_HCDMAB7 */
    volatile uint32_t                   _pad_0x1fc_0x1ff;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR8_t     hcchar8;             /* ALT_USB_HOST_HCCHAR8 */
    volatile ALT_USB_HOST_HCSPLT8_t     hcsplt8;             /* ALT_USB_HOST_HCSPLT8 */
    volatile ALT_USB_HOST_HCINT8_t      hcint8;              /* ALT_USB_HOST_HCINT8 */
    volatile ALT_USB_HOST_HCINTMSK8_t   hcintmsk8;           /* ALT_USB_HOST_HCINTMSK8 */
    volatile ALT_USB_HOST_HCTSIZ8_t     hctsiz8;             /* ALT_USB_HOST_HCTSIZ8 */
    volatile ALT_USB_HOST_HCDMA8_t      hcdma8;              /* ALT_USB_HOST_HCDMA8 */
    volatile ALT_USB_HOST_HCDMAB8_t     hcdmab8;             /* ALT_USB_HOST_HCDMAB8 */
    volatile uint32_t                   _pad_0x21c_0x21f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR9_t     hcchar9;             /* ALT_USB_HOST_HCCHAR9 */
    volatile ALT_USB_HOST_HCSPLT9_t     hcsplt9;             /* ALT_USB_HOST_HCSPLT9 */
    volatile ALT_USB_HOST_HCINT9_t      hcint9;              /* ALT_USB_HOST_HCINT9 */
    volatile ALT_USB_HOST_HCINTMSK9_t   hcintmsk9;           /* ALT_USB_HOST_HCINTMSK9 */
    volatile ALT_USB_HOST_HCTSIZ9_t     hctsiz9;             /* ALT_USB_HOST_HCTSIZ9 */
    volatile ALT_USB_HOST_HCDMA9_t      hcdma9;              /* ALT_USB_HOST_HCDMA9 */
    volatile ALT_USB_HOST_HCDMAB9_t     hcdmab9;             /* ALT_USB_HOST_HCDMAB9 */
    volatile uint32_t                   _pad_0x23c_0x23f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR10_t    hcchar10;            /* ALT_USB_HOST_HCCHAR10 */
    volatile ALT_USB_HOST_HCSPLT10_t    hcsplt10;            /* ALT_USB_HOST_HCSPLT10 */
    volatile ALT_USB_HOST_HCINT10_t     hcint10;             /* ALT_USB_HOST_HCINT10 */
    volatile ALT_USB_HOST_HCINTMSK10_t  hcintmsk10;          /* ALT_USB_HOST_HCINTMSK10 */
    volatile ALT_USB_HOST_HCTSIZ10_t    hctsiz10;            /* ALT_USB_HOST_HCTSIZ10 */
    volatile ALT_USB_HOST_HCDMA10_t     hcdma10;             /* ALT_USB_HOST_HCDMA10 */
    volatile ALT_USB_HOST_HCDMAB10_t    hcdmab10;            /* ALT_USB_HOST_HCDMAB10 */
    volatile uint32_t                   _pad_0x25c_0x25f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR11_t    hcchar11;            /* ALT_USB_HOST_HCCHAR11 */
    volatile ALT_USB_HOST_HCSPLT11_t    HCSPLT11;            /* ALT_USB_HOST_HCSPLT11 */
    volatile ALT_USB_HOST_HCINT11_t     hcint11;             /* ALT_USB_HOST_HCINT11 */
    volatile ALT_USB_HOST_HCINTMSK11_t  hcintmsk11;          /* ALT_USB_HOST_HCINTMSK11 */
    volatile ALT_USB_HOST_HCTSIZ11_t    hctsiz11;            /* ALT_USB_HOST_HCTSIZ11 */
    volatile ALT_USB_HOST_HCDMA11_t     hcdma11;             /* ALT_USB_HOST_HCDMA11 */
    volatile ALT_USB_HOST_HCDMAB11_t    hcdmab11;            /* ALT_USB_HOST_HCDMAB11 */
    volatile uint32_t                   _pad_0x27c_0x27f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR12_t    hcchar12;            /* ALT_USB_HOST_HCCHAR12 */
    volatile ALT_USB_HOST_HCSPLT12_t    hcsplt12;            /* ALT_USB_HOST_HCSPLT12 */
    volatile ALT_USB_HOST_HCINT12_t     hcint12;             /* ALT_USB_HOST_HCINT12 */
    volatile ALT_USB_HOST_HCINTMSK12_t  hcintmsk12;          /* ALT_USB_HOST_HCINTMSK12 */
    volatile ALT_USB_HOST_HCTSIZ12_t    hctsiz12;            /* ALT_USB_HOST_HCTSIZ12 */
    volatile ALT_USB_HOST_HCDMA12_t     hcdma12;             /* ALT_USB_HOST_HCDMA12 */
    volatile ALT_USB_HOST_HCDMAB12_t    hcdmab12;            /* ALT_USB_HOST_HCDMAB12 */
    volatile uint32_t                   _pad_0x29c_0x29f;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR13_t    hcchar13;            /* ALT_USB_HOST_HCCHAR13 */
    volatile ALT_USB_HOST_HCSPLT13_t    hcsplt13;            /* ALT_USB_HOST_HCSPLT13 */
    volatile ALT_USB_HOST_HCINT13_t     hcint13;             /* ALT_USB_HOST_HCINT13 */
    volatile ALT_USB_HOST_HCINTMSK13_t  hcintmsk13;          /* ALT_USB_HOST_HCINTMSK13 */
    volatile ALT_USB_HOST_HCTSIZ13_t    hctsiz13;            /* ALT_USB_HOST_HCTSIZ13 */
    volatile ALT_USB_HOST_HCDMA13_t     hcdma13;             /* ALT_USB_HOST_HCDMA13 */
    volatile ALT_USB_HOST_HCDMAB13_t    hcdmab13;            /* ALT_USB_HOST_HCDMAB13 */
    volatile uint32_t                   _pad_0x2bc_0x2bf;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR14_t    hcchar14;            /* ALT_USB_HOST_HCCHAR14 */
    volatile ALT_USB_HOST_HCSPLT14_t    hcsplt14;            /* ALT_USB_HOST_HCSPLT14 */
    volatile ALT_USB_HOST_HCINT14_t     hcint14;             /* ALT_USB_HOST_HCINT14 */
    volatile ALT_USB_HOST_HCINTMSK14_t  hcintmsk14;          /* ALT_USB_HOST_HCINTMSK14 */
    volatile ALT_USB_HOST_HCTSIZ14_t    hctsiz14;            /* ALT_USB_HOST_HCTSIZ14 */
    volatile ALT_USB_HOST_HCDMA14_t     hcdma14;             /* ALT_USB_HOST_HCDMA14 */
    volatile ALT_USB_HOST_HCDMAB14_t    hcdmab14;            /* ALT_USB_HOST_HCDMAB14 */
    volatile uint32_t                   _pad_0x2dc_0x2df;    /* *UNDEFINED* */
    volatile ALT_USB_HOST_HCCHAR15_t    hcchar15;            /* ALT_USB_HOST_HCCHAR15 */
    volatile ALT_USB_HOST_HCSPLT15_t    hcsplt15;            /* ALT_USB_HOST_HCSPLT15 */
    volatile ALT_USB_HOST_HCINT15_t     hcint15;             /* ALT_USB_HOST_HCINT15 */
    volatile ALT_USB_HOST_HCINTMSK15_t  hcintmsk15;          /* ALT_USB_HOST_HCINTMSK15 */
    volatile ALT_USB_HOST_HCTSIZ15_t    hctsiz15;            /* ALT_USB_HOST_HCTSIZ15 */
    volatile ALT_USB_HOST_HCDMA15_t     hcdma15;             /* ALT_USB_HOST_HCDMA15 */
    volatile ALT_USB_HOST_HCDMAB15_t    hcdmab15;            /* ALT_USB_HOST_HCDMAB15 */
};

/* The typedef declaration for register group ALT_USB_HOST. */
typedef volatile struct ALT_USB_HOST_s  ALT_USB_HOST_t;
/* The struct declaration for the raw register contents of register group ALT_USB_HOST. */
struct ALT_USB_HOST_raw_s
{
    volatile uint32_t  hcfg;                /* ALT_USB_HOST_HCFG */
    volatile uint32_t  hfir;                /* ALT_USB_HOST_HFIR */
    volatile uint32_t  hfnum;               /* ALT_USB_HOST_HFNUM */
    volatile uint32_t  _pad_0xc_0xf;        /* *UNDEFINED* */
    volatile uint32_t  hptxsts;             /* ALT_USB_HOST_HPTXSTS */
    volatile uint32_t  haint;               /* ALT_USB_HOST_HAINT */
    volatile uint32_t  haintmsk;            /* ALT_USB_HOST_HAINTMSK */
    volatile uint32_t  hflbaddr;            /* ALT_USB_HOST_HFLBADDR */
    volatile uint32_t  _pad_0x20_0x3f[8];   /* *UNDEFINED* */
    volatile uint32_t  hprt;                /* ALT_USB_HOST_HPRT */
    volatile uint32_t  _pad_0x44_0xff[47];  /* *UNDEFINED* */
    volatile uint32_t  hcchar0;             /* ALT_USB_HOST_HCCHAR0 */
    volatile uint32_t  hcsplt0;             /* ALT_USB_HOST_HCSPLT0 */
    volatile uint32_t  hcint0;              /* ALT_USB_HOST_HCINT0 */
    volatile uint32_t  hcintmsk0;           /* ALT_USB_HOST_HCINTMSK0 */
    volatile uint32_t  hctsiz0;             /* ALT_USB_HOST_HCTSIZ0 */
    volatile uint32_t  hcdma0;              /* ALT_USB_HOST_HCDMA0 */
    volatile uint32_t  hcdmab0;             /* ALT_USB_HOST_HCDMAB0 */
    volatile uint32_t  _pad_0x11c_0x11f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar1;             /* ALT_USB_HOST_HCCHAR1 */
    volatile uint32_t  hcsplt1;             /* ALT_USB_HOST_HCSPLT1 */
    volatile uint32_t  hcint1;              /* ALT_USB_HOST_HCINT1 */
    volatile uint32_t  hcintmsk1;           /* ALT_USB_HOST_HCINTMSK1 */
    volatile uint32_t  hctsiz1;             /* ALT_USB_HOST_HCTSIZ1 */
    volatile uint32_t  hcdma1;              /* ALT_USB_HOST_HCDMA1 */
    volatile uint32_t  hcdmab1;             /* ALT_USB_HOST_HCDMAB1 */
    volatile uint32_t  _pad_0x13c_0x13f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar2;             /* ALT_USB_HOST_HCCHAR2 */
    volatile uint32_t  hcsplt2;             /* ALT_USB_HOST_HCSPLT2 */
    volatile uint32_t  hcint2;              /* ALT_USB_HOST_HCINT2 */
    volatile uint32_t  hcintmsk2;           /* ALT_USB_HOST_HCINTMSK2 */
    volatile uint32_t  hctsiz2;             /* ALT_USB_HOST_HCTSIZ2 */
    volatile uint32_t  hcdma2;              /* ALT_USB_HOST_HCDMA2 */
    volatile uint32_t  hcdmab2;             /* ALT_USB_HOST_HCDMAB2 */
    volatile uint32_t  _pad_0x15c_0x15f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar3;             /* ALT_USB_HOST_HCCHAR3 */
    volatile uint32_t  hcsplt3;             /* ALT_USB_HOST_HCSPLT3 */
    volatile uint32_t  hcint3;              /* ALT_USB_HOST_HCINT3 */
    volatile uint32_t  hcintmsk3;           /* ALT_USB_HOST_HCINTMSK3 */
    volatile uint32_t  hctsiz3;             /* ALT_USB_HOST_HCTSIZ3 */
    volatile uint32_t  hcdma3;              /* ALT_USB_HOST_HCDMA3 */
    volatile uint32_t  hcdmab3;             /* ALT_USB_HOST_HCDMAB3 */
    volatile uint32_t  _pad_0x17c_0x17f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar4;             /* ALT_USB_HOST_HCCHAR4 */
    volatile uint32_t  hcsplt4;             /* ALT_USB_HOST_HCSPLT4 */
    volatile uint32_t  hcint4;              /* ALT_USB_HOST_HCINT4 */
    volatile uint32_t  hcintmsk4;           /* ALT_USB_HOST_HCINTMSK4 */
    volatile uint32_t  hctsiz4;             /* ALT_USB_HOST_HCTSIZ4 */
    volatile uint32_t  hcdma4;              /* ALT_USB_HOST_HCDMA4 */
    volatile uint32_t  hcdmab4;             /* ALT_USB_HOST_HCDMAB4 */
    volatile uint32_t  _pad_0x19c_0x19f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar5;             /* ALT_USB_HOST_HCCHAR5 */
    volatile uint32_t  hcsplt5;             /* ALT_USB_HOST_HCSPLT5 */
    volatile uint32_t  hcint5;              /* ALT_USB_HOST_HCINT5 */
    volatile uint32_t  hcintmsk5;           /* ALT_USB_HOST_HCINTMSK5 */
    volatile uint32_t  hctsiz5;             /* ALT_USB_HOST_HCTSIZ5 */
    volatile uint32_t  hcdma5;              /* ALT_USB_HOST_HCDMA5 */
    volatile uint32_t  hcdmab5;             /* ALT_USB_HOST_HCDMAB5 */
    volatile uint32_t  _pad_0x1bc_0x1bf;    /* *UNDEFINED* */
    volatile uint32_t  hcchar6;             /* ALT_USB_HOST_HCCHAR6 */
    volatile uint32_t  hcsplt6;             /* ALT_USB_HOST_HCSPLT6 */
    volatile uint32_t  hcint6;              /* ALT_USB_HOST_HCINT6 */
    volatile uint32_t  hcintmsk6;           /* ALT_USB_HOST_HCINTMSK6 */
    volatile uint32_t  hctsiz6;             /* ALT_USB_HOST_HCTSIZ6 */
    volatile uint32_t  hcdma6;              /* ALT_USB_HOST_HCDMA6 */
    volatile uint32_t  hcdmab6;             /* ALT_USB_HOST_HCDMAB6 */
    volatile uint32_t  _pad_0x1dc_0x1df;    /* *UNDEFINED* */
    volatile uint32_t  hcchar7;             /* ALT_USB_HOST_HCCHAR7 */
    volatile uint32_t  hcsplt7;             /* ALT_USB_HOST_HCSPLT7 */
    volatile uint32_t  hcint7;              /* ALT_USB_HOST_HCINT7 */
    volatile uint32_t  hcintmsk7;           /* ALT_USB_HOST_HCINTMSK7 */
    volatile uint32_t  hctsiz7;             /* ALT_USB_HOST_HCTSIZ7 */
    volatile uint32_t  hcdma7;              /* ALT_USB_HOST_HCDMA7 */
    volatile uint32_t  hcdmab7;             /* ALT_USB_HOST_HCDMAB7 */
    volatile uint32_t  _pad_0x1fc_0x1ff;    /* *UNDEFINED* */
    volatile uint32_t  hcchar8;             /* ALT_USB_HOST_HCCHAR8 */
    volatile uint32_t  hcsplt8;             /* ALT_USB_HOST_HCSPLT8 */
    volatile uint32_t  hcint8;              /* ALT_USB_HOST_HCINT8 */
    volatile uint32_t  hcintmsk8;           /* ALT_USB_HOST_HCINTMSK8 */
    volatile uint32_t  hctsiz8;             /* ALT_USB_HOST_HCTSIZ8 */
    volatile uint32_t  hcdma8;              /* ALT_USB_HOST_HCDMA8 */
    volatile uint32_t  hcdmab8;             /* ALT_USB_HOST_HCDMAB8 */
    volatile uint32_t  _pad_0x21c_0x21f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar9;             /* ALT_USB_HOST_HCCHAR9 */
    volatile uint32_t  hcsplt9;             /* ALT_USB_HOST_HCSPLT9 */
    volatile uint32_t  hcint9;              /* ALT_USB_HOST_HCINT9 */
    volatile uint32_t  hcintmsk9;           /* ALT_USB_HOST_HCINTMSK9 */
    volatile uint32_t  hctsiz9;             /* ALT_USB_HOST_HCTSIZ9 */
    volatile uint32_t  hcdma9;              /* ALT_USB_HOST_HCDMA9 */
    volatile uint32_t  hcdmab9;             /* ALT_USB_HOST_HCDMAB9 */
    volatile uint32_t  _pad_0x23c_0x23f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar10;            /* ALT_USB_HOST_HCCHAR10 */
    volatile uint32_t  hcsplt10;            /* ALT_USB_HOST_HCSPLT10 */
    volatile uint32_t  hcint10;             /* ALT_USB_HOST_HCINT10 */
    volatile uint32_t  hcintmsk10;          /* ALT_USB_HOST_HCINTMSK10 */
    volatile uint32_t  hctsiz10;            /* ALT_USB_HOST_HCTSIZ10 */
    volatile uint32_t  hcdma10;             /* ALT_USB_HOST_HCDMA10 */
    volatile uint32_t  hcdmab10;            /* ALT_USB_HOST_HCDMAB10 */
    volatile uint32_t  _pad_0x25c_0x25f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar11;            /* ALT_USB_HOST_HCCHAR11 */
    volatile uint32_t  HCSPLT11;            /* ALT_USB_HOST_HCSPLT11 */
    volatile uint32_t  hcint11;             /* ALT_USB_HOST_HCINT11 */
    volatile uint32_t  hcintmsk11;          /* ALT_USB_HOST_HCINTMSK11 */
    volatile uint32_t  hctsiz11;            /* ALT_USB_HOST_HCTSIZ11 */
    volatile uint32_t  hcdma11;             /* ALT_USB_HOST_HCDMA11 */
    volatile uint32_t  hcdmab11;            /* ALT_USB_HOST_HCDMAB11 */
    volatile uint32_t  _pad_0x27c_0x27f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar12;            /* ALT_USB_HOST_HCCHAR12 */
    volatile uint32_t  hcsplt12;            /* ALT_USB_HOST_HCSPLT12 */
    volatile uint32_t  hcint12;             /* ALT_USB_HOST_HCINT12 */
    volatile uint32_t  hcintmsk12;          /* ALT_USB_HOST_HCINTMSK12 */
    volatile uint32_t  hctsiz12;            /* ALT_USB_HOST_HCTSIZ12 */
    volatile uint32_t  hcdma12;             /* ALT_USB_HOST_HCDMA12 */
    volatile uint32_t  hcdmab12;            /* ALT_USB_HOST_HCDMAB12 */
    volatile uint32_t  _pad_0x29c_0x29f;    /* *UNDEFINED* */
    volatile uint32_t  hcchar13;            /* ALT_USB_HOST_HCCHAR13 */
    volatile uint32_t  hcsplt13;            /* ALT_USB_HOST_HCSPLT13 */
    volatile uint32_t  hcint13;             /* ALT_USB_HOST_HCINT13 */
    volatile uint32_t  hcintmsk13;          /* ALT_USB_HOST_HCINTMSK13 */
    volatile uint32_t  hctsiz13;            /* ALT_USB_HOST_HCTSIZ13 */
    volatile uint32_t  hcdma13;             /* ALT_USB_HOST_HCDMA13 */
    volatile uint32_t  hcdmab13;            /* ALT_USB_HOST_HCDMAB13 */
    volatile uint32_t  _pad_0x2bc_0x2bf;    /* *UNDEFINED* */
    volatile uint32_t  hcchar14;            /* ALT_USB_HOST_HCCHAR14 */
    volatile uint32_t  hcsplt14;            /* ALT_USB_HOST_HCSPLT14 */
    volatile uint32_t  hcint14;             /* ALT_USB_HOST_HCINT14 */
    volatile uint32_t  hcintmsk14;          /* ALT_USB_HOST_HCINTMSK14 */
    volatile uint32_t  hctsiz14;            /* ALT_USB_HOST_HCTSIZ14 */
    volatile uint32_t  hcdma14;             /* ALT_USB_HOST_HCDMA14 */
    volatile uint32_t  hcdmab14;            /* ALT_USB_HOST_HCDMAB14 */
    volatile uint32_t  _pad_0x2dc_0x2df;    /* *UNDEFINED* */
    volatile uint32_t  hcchar15;            /* ALT_USB_HOST_HCCHAR15 */
    volatile uint32_t  hcsplt15;            /* ALT_USB_HOST_HCSPLT15 */
    volatile uint32_t  hcint15;             /* ALT_USB_HOST_HCINT15 */
    volatile uint32_t  hcintmsk15;          /* ALT_USB_HOST_HCINTMSK15 */
    volatile uint32_t  hctsiz15;            /* ALT_USB_HOST_HCTSIZ15 */
    volatile uint32_t  hcdma15;             /* ALT_USB_HOST_HCDMA15 */
    volatile uint32_t  hcdmab15;            /* ALT_USB_HOST_HCDMAB15 */
};

/* The typedef declaration for the raw register contents of register group ALT_USB_HOST. */
typedef volatile struct ALT_USB_HOST_raw_s  ALT_USB_HOST_raw_t;
#endif  /* __ASSEMBLY__ */


/*
 * Register Group : Device Mode Registers - ALT_USB_DEV
 * Device Mode Registers
 * 
 * These registers must be programmed every time the USB OTG Controller changes to
 * Device mode.
 * 
 */
/*
 * Register : Device Configuration Register - dcfg
 * 
 * This register configures the core in Device mode after power-on or after certain
 * control commands or enumeration. Do not make changes to this register after
 * initial programming.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                             
 * :--------|:-------|:------|:-----------------------------------------
 *  [1:0]   | RW     | 0x0   | Device Speed                            
 *  [2]     | RW     | 0x0   | Non-Zero-Length Status OUT Handshak     
 *  [3]     | RW     | 0x0   | Enable 32 KHz Suspend mode              
 *  [10:4]  | RW     | 0x0   | Device Address                          
 *  [12:11] | RW     | 0x0   | Periodic Frame Interval                 
 *  [13]    | RW     | 0x0   | Enable Device OUT NA                    
 *  [22:14] | ???    | 0x0   | *UNDEFINED*                             
 *  [23]    | RW     | 0x0   | Enable Scatter gather DMA in device mode
 *  [25:24] | RW     | 0x0   | Periodic Scheduling Interva             
 *  [31:26] | RW     | 0x2   | Resume Validation Period                
 * 
 */
/*
 * Field : Device Speed - devspd
 * 
 * Indicates the speed at which the application requires the core to enumerate, or
 * the maximum speed the application can support. However, the actual bus speed is
 * determined only after the chirp sequence is completed, and is based on the speed
 * of the USB host to which the core is connected.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20   | 0x0   | High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
 *  ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20   | 0x1   | Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
 *  ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116  | 0x2   | Low speed USB 1.1 transceiver clock is 6 MHz    
 *  ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 | 0x3   | Full speed USB 1.1 transceiver clock is 48 MHz  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
 * 
 * High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
 */
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
 * 
 * Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
 */
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
 * 
 * Low speed USB 1.1 transceiver clock is 6 MHz
 */
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116  0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
 * 
 * Full speed USB 1.1 transceiver clock is 48 MHz
 */
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_MSB        1
/* The width in bits of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DCFG_DEVSPD register field value. */
#define ALT_USB_DEV_DCFG_DEVSPD_SET_MSK    0x00000003
/* The mask used to clear the ALT_USB_DEV_DCFG_DEVSPD register field value. */
#define ALT_USB_DEV_DCFG_DEVSPD_CLR_MSK    0xfffffffc
/* The reset value of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_DEVSPD field value from a register. */
#define ALT_USB_DEV_DCFG_DEVSPD_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_DEV_DCFG_DEVSPD register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_DEVSPD_SET(value) (((value) << 0) & 0x00000003)

/*
 * Field : Non-Zero-Length Status OUT Handshak - nzstsouthshk
 * 
 * The application can use this field to select the handshake the core sends on
 * receiving a nonzero-length data packet during the OUT transaction of a control
 * transfer's Status stage. 1: Send a STALL handshake on a nonzero-length statusOUT
 * transaction and do not send the received OUT packet tothe application. 0: Send
 * the received OUT packet to the application (zerolengthor nonzero-length) and
 * send a handshake based onthe NAK and STALL bits for the endpoint in the
 * DeviceEndpoint Control register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                    
 * :------------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT   | 0x0   | Send the received OUT packet to the application
 * :                                          |       | zerolength                                     
 *  ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL | 0x1   | Send a STALL handshake on a nonzero-length     
 * :                                          |       | status OUT transaction and do not send the     
 * :                                          |       | received OUT packet to the application         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK
 * 
 * Send the received OUT packet to the application zerolength
 */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK
 * 
 * Send a STALL handshake on a nonzero-length status OUT transaction and do not
 * send the received OUT packet to the application
 */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_MSB        2
/* The width in bits of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_NZSTSOUTHSHK field value from a register. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Enable 32 KHz Suspend mode - ena32khzsusp
 * 
 * When the USB 1.1 Full-Speed Serial Transceiver Interface is chosen and this bit
 * is set, the core expects the 48-MHz PHY clock to be switched to 32 KHz during a
 * suspend. This bit can only be set if USB 1.1 Full-Speed Serial Transceiver
 * Interface has been selected. If USB 1.1 Full-Speed Serial Transceiver Interface
 * has not been selected, this bit must be zero.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD | 0x0   | USB 1.1 Full-Speed Serial Transceiver not      
 * :                                     |       | selected                                       
 *  ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END  | 0x1   | USB 1.1 Full-Speed Serial Transceiver Interface
 * :                                     |       | selected                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP
 * 
 * USB 1.1 Full-Speed Serial Transceiver not selected
 */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP
 * 
 * USB 1.1 Full-Speed Serial Transceiver Interface selected
 */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_MSB        3
/* The width in bits of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_ENA32KHZSUSP field value from a register. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Device Address - devaddr
 * 
 * The application must program this field after every SetAddress control command.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_MSB        10
/* The width in bits of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_WIDTH      7
/* The mask used to set the ALT_USB_DEV_DCFG_DEVADDR register field value. */
#define ALT_USB_DEV_DCFG_DEVADDR_SET_MSK    0x000007f0
/* The mask used to clear the ALT_USB_DEV_DCFG_DEVADDR register field value. */
#define ALT_USB_DEV_DCFG_DEVADDR_CLR_MSK    0xfffff80f
/* The reset value of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_DEVADDR field value from a register. */
#define ALT_USB_DEV_DCFG_DEVADDR_GET(value) (((value) & 0x000007f0) >> 4)
/* Produces a ALT_USB_DEV_DCFG_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_DEVADDR_SET(value) (((value) << 4) & 0x000007f0)

/*
 * Field : Periodic Frame Interval - perfrint
 * 
 * Indicates the time within a (micro)frame at which the application must be
 * notified using the End Of Periodic Frame Interrupt. This can be used to
 * determine If all the isochronous traffic for that (micro)frame is complete. 0x0:
 * 80% of the (micro)frame interval 0x1: 85% 0x2: 90% 0x3: 95%
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                     
 * :-----------------------------------|:------|:---------------------------------
 *  ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 | 0x0   | 80% of the (micro)frame interval
 *  ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 | 0x1   | 85% of the (micro)frame interval
 *  ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 | 0x2   | 90% of the (micro)frame interval
 *  ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 | 0x3   | 95% of the (micro)frame interval
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
 * 
 * 80% of the (micro)frame interval
 */
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
 * 
 * 85% of the (micro)frame interval
 */
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
 * 
 * 90% of the (micro)frame interval
 */
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90  0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
 * 
 * 95% of the (micro)frame interval
 */
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95  0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_MSB        12
/* The width in bits of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DCFG_PERFRINT register field value. */
#define ALT_USB_DEV_DCFG_PERFRINT_SET_MSK    0x00001800
/* The mask used to clear the ALT_USB_DEV_DCFG_PERFRINT register field value. */
#define ALT_USB_DEV_DCFG_PERFRINT_CLR_MSK    0xffffe7ff
/* The reset value of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_PERFRINT field value from a register. */
#define ALT_USB_DEV_DCFG_PERFRINT_GET(value) (((value) & 0x00001800) >> 11)
/* Produces a ALT_USB_DEV_DCFG_PERFRINT register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_PERFRINT_SET(value) (((value) << 11) & 0x00001800)

/*
 * Field : Enable Device OUT NA - endevoutnak
 * 
 * This bit enables setting NAK for Bulk OUT endpoints after the transfer is
 * completed for Device mode Descriptor DMA It is one time programmable after reset
 * like any other DCFG register bits.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                              
 * :------------------------------------|:------|:------------------------------------------
 *  ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD | 0x0   | The core does not set NAK after Bulk OUT 
 * :                                    |       | transfer complete                        
 *  ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END  | 0x1   | The core sets NAK after Bulk OUT transfer
 * :                                    |       | complete                                 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK
 * 
 * The core does not set NAK after Bulk OUT transfer complete
 */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK
 * 
 * The core sets NAK after Bulk OUT transfer complete
 */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_MSB        13
/* The width in bits of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_ENDEVOUTNAK field value from a register. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Enable Scatter gather DMA in device mode - descdma
 * 
 * When the Scatter/Gather DMA option selected during configuration of the RTL, the
 * application can Set this bit during initialization to enable the Scatter/Gather
 * DMA operation. This bit must be modified only once after a reset.The following
 * combinations are available for programming:
 * 
 * GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode
 * 
 * GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid
 * 
 * GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA
 * 
 * mode GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description               
 * :--------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DCFG_DESCDMA_E_DISD | 0x0   | Disable Scatter gather DMA
 *  ALT_USB_DEV_DCFG_DESCDMA_E_END  | 0x1   | Enable Scatter gather DMA 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA
 * 
 * Disable Scatter gather DMA
 */
#define ALT_USB_DEV_DCFG_DESCDMA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA
 * 
 * Enable Scatter gather DMA
 */
#define ALT_USB_DEV_DCFG_DESCDMA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_MSB        23
/* The width in bits of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCFG_DESCDMA register field value. */
#define ALT_USB_DEV_DCFG_DESCDMA_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_DEV_DCFG_DESCDMA register field value. */
#define ALT_USB_DEV_DCFG_DESCDMA_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_DESCDMA field value from a register. */
#define ALT_USB_DEV_DCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_DEV_DCFG_DESCDMA register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Periodic Scheduling Interva - perschintvl
 * 
 * PerSchIntvl must be programmed only for Scatter/Gather DMAmode. Description:
 * This field specifies the amount of time the Internal DMA engine must allocate
 * for fetching periodic IN endpoint data. Based on the number of periodic
 * endpoints, this value must be specified as 25,50 or 75% of (micro)frame. When
 * any periodic endpoints are active, the internal DMA engine allocates the
 * specified amount of time in fetching periodic IN endpoint data . When no
 * periodic endpoints are active, Then the internal DMA engine services non-
 * periodic endpoints, ignoring this field. After the specified time within a
 * (micro)frame, the DMA switches to fetching for non-periodic endpoints. 2'b00:
 * 25% of (micro)frame. 2'b01: 50% of (micro)frame. 2'b10: 75% of (micro)frame.
 * 2'b11: Reserved.Reset: 2'b00Access: read-write
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 | 0x0   | 25% of (micro)frame
 *  ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 | 0x1   | 50% of (micro)frame
 *  ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 | 0x2   | 75% of (micro)frame
 *  ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD | 0x3   | Reserved           
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
 * 
 * 25% of (micro)frame
 */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
 * 
 * 50% of (micro)frame
 */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
 * 
 * 75% of (micro)frame
 */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
 * 
 * Reserved
 */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_MSB        25
/* The width in bits of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET_MSK    0x03000000
/* The mask used to clear the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_CLR_MSK    0xfcffffff
/* The reset value of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_RESET      0x0
/* Extracts the ALT_USB_DEV_DCFG_PERSCHINTVL field value from a register. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_GET(value) (((value) & 0x03000000) >> 24)
/* Produces a ALT_USB_DEV_DCFG_PERSCHINTVL register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET(value) (((value) << 24) & 0x03000000)

/*
 * Field : Resume Validation Period - resvalid
 * 
 * This field is effective only when DCFG.Ena32KHzSusp is set. It will control the
 * resume period when the core resumes from suspend. The core counts for ResValid
 * number of clock cycles to detect a valid resume when this is set
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_MSB        31
/* The width in bits of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_WIDTH      6
/* The mask used to set the ALT_USB_DEV_DCFG_RESVALID register field value. */
#define ALT_USB_DEV_DCFG_RESVALID_SET_MSK    0xfc000000
/* The mask used to clear the ALT_USB_DEV_DCFG_RESVALID register field value. */
#define ALT_USB_DEV_DCFG_RESVALID_CLR_MSK    0x03ffffff
/* The reset value of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_RESET      0x2
/* Extracts the ALT_USB_DEV_DCFG_RESVALID field value from a register. */
#define ALT_USB_DEV_DCFG_RESVALID_GET(value) (((value) & 0xfc000000) >> 26)
/* Produces a ALT_USB_DEV_DCFG_RESVALID register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_RESVALID_SET(value) (((value) << 26) & 0xfc000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DCFG.
 */
struct ALT_USB_DEV_DCFG_s
{
    uint32_t  devspd       :  2;  /* Device Speed */
    uint32_t  nzstsouthshk :  1;  /* Non-Zero-Length Status OUT Handshak */
    uint32_t  ena32khzsusp :  1;  /* Enable 32 KHz Suspend mode */
    uint32_t  devaddr      :  7;  /* Device Address */
    uint32_t  perfrint     :  2;  /* Periodic Frame Interval */
    uint32_t  endevoutnak  :  1;  /* Enable Device OUT NA */
    uint32_t               :  9;  /* *UNDEFINED* */
    uint32_t  descdma      :  1;  /* Enable Scatter gather DMA in device mode */
    uint32_t  perschintvl  :  2;  /* Periodic Scheduling Interva */
    uint32_t  resvalid     :  6;  /* Resume Validation Period */
};

/* The typedef declaration for register ALT_USB_DEV_DCFG. */
typedef volatile struct ALT_USB_DEV_DCFG_s  ALT_USB_DEV_DCFG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DCFG register from the beginning of the component. */
#define ALT_USB_DEV_DCFG_OFST        0x0
/* The address of the ALT_USB_DEV_DCFG register. */
#define ALT_USB_DEV_DCFG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCFG_OFST))

/*
 * Register : Device Control Register - dctl
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                  
 * :--------|:-------|:------|:----------------------------------------------
 *  [0]     | RW     | 0x0   | Remote Wakeup Signaling                      
 *  [1]     | RW     | 0x0   | Soft Disconnect                              
 *  [2]     | R      | 0x0   | Global Non-periodic IN NAK Status            
 *  [3]     | R      | 0x0   | Global OUT NAK Status                        
 *  [6:4]   | RW     | 0x0   | Test Control                                 
 *  [7]     | W      | 0x0   | Set Global Non-periodic IN NAK               
 *  [8]     | W      | 0x0   | Clear Global Non-periodic IN NAK             
 *  [9]     | W      | 0x0   | Set Global OUT NAK                           
 *  [10]    | W      | 0x0   | Clear Global OUT NAK                         
 *  [11]    | RW     | 0x0   | Power-On Programming Done                    
 *  [12]    | ???    | 0x0   | *UNDEFINED*                                  
 *  [14:13] | RW     | 0x0   | Global Multi Count                           
 *  [15]    | RW     | 0x0   | Ignore Frame number for Isochronous Endpoints
 *  [16]    | RW     | 0x0   | NAK on Babble Error                          
 *  [31:17] | ???    | 0x0   | *UNDEFINED*                                  
 * 
 */
/*
 * Field : Remote Wakeup Signaling - rmtwkupsig
 * 
 * When the application sets this bit, the core initiates remote signaling to wake
 * up the USB host. The application must Set this bit to instruct the core to exit
 * the Suspend state. As specified in the USB 2.0 specification, the application
 * must clear this bit 115 ms after setting it. Remote Wakeup Signaling
 * (RmtWkUpSig) When LPM is enabled, In L1 state the behavior of this bit is as
 * follows: When the application sets this bit, the core initiates L1 remote
 * signaling to wake up the USB host. The application must set this bit to instruct
 * the core to exit the Sleep state. As specified in the LPM specification, the
 * hardware will automatically clear this bit after a time of 50us
 * (TL1DevDrvResume) after set by application. Application should not set this bit
 * when GLPMCFG bRemoteWake from the previous LPM transaction was zero.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description          
 * :-------------------------------------|:------|:----------------------
 *  ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT | 0x0   | No exit suspend state
 *  ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT   | 0x1   | Exit Suspend State   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG
 * 
 * No exit suspend state
 */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG
 * 
 * Exit Suspend State
 */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_MSB        0
/* The width in bits of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_RMTWKUPSIG field value from a register. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DCTL_RMTWKUPSIG register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Soft Disconnect - sftdiscon
 * 
 * The application uses this bit to signal the otg core to do a soft disconnect. As
 * long as this bit is Set, the host does not see that the device is connected, and
 * the device does not receive signals on the USB. The core stays in the
 * disconnected state until the application clears this bit. There is a  minimum
 * duration for which the core must keep this bit set. When this bit is cleared
 * after a soft disconnect, the core drives the phy_opmode_o signal on the ULPI,
 * which generates a device connect event to the USB host. When the device is
 * reconnected, the USB host restarts device enumeration.;
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                   
 * :------------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT | 0x0   | Normal operation                              
 *  ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT   | 0x1   | The core drives the phy_opmode_o signal on the
 * :                                          |       | ULPI                                          
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON
 * 
 * Normal operation
 */
#define ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON
 * 
 * The core drives the phy_opmode_o signal on the ULPI
 */
#define ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_MSB        1
/* The width in bits of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_SFTDISCON register field value. */
#define ALT_USB_DEV_DCTL_SFTDISCON_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DCTL_SFTDISCON register field value. */
#define ALT_USB_DEV_DCTL_SFTDISCON_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_SFTDISCON field value from a register. */
#define ALT_USB_DEV_DCTL_SFTDISCON_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DCTL_SFTDISCON register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_SFTDISCON_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Global Non-periodic IN NAK Status - gnpinnaksts
 * 
 * Defines IN NAK conditions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT | 0x0   | A handshake is sent out based on the data      
 * :                                     |       | availability in the transmit FIFO              
 *  ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT   | 0x1   | A NAK handshake is sent out on all non-periodic
 * :                                     |       | IN endpoints, irrespective of the data         
 * :                                     |       | availability in the transmit FIFO.             
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS
 * 
 * A handshake is sent out based on the data availability in the transmit FIFO
 */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS
 * 
 * A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of
 * the data availability in the transmit FIFO.
 */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_MSB        2
/* The width in bits of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_GNPINNAKSTS field value from a register. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DCTL_GNPINNAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Global OUT NAK Status - goutnaksts
 * 
 * Reports NAK status. All isochronous OUT packets aredropped.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                     
 * :------------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT | 0x0   | A handshake is sent based on the FIFO Status and
 * :                                    |       | the NAK and STALL bit settings.                 
 *  ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT   | 0x1   | No data is written to the RxFIFO, irrespective  
 * :                                    |       | of space availability. Sends a NAK handshake on 
 * :                                    |       | all packets, except on SETUP transactions. All  
 * :                                    |       | isochronous OUT packets are dropped.            
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS
 * 
 * A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
 */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS
 * 
 * No data is written to the RxFIFO, irrespective of space availability. Sends a
 * NAK handshake on all packets, except on SETUP transactions. All isochronous OUT
 * packets are dropped.
 */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_MSB        3
/* The width in bits of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_GOUTNAKSTS field value from a register. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DCTL_GOUTNAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Test Control - tstctl
 * 
 * Others: Reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description       
 * :---------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DCTL_TSTCTL_E_DISD   | 0x0   | Test mode disabled
 *  ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ  | 0x1   | Test_J mode       
 *  ALT_USB_DEV_DCTL_TSTCTL_E_TESTK  | 0x2   | Test_K mode       
 *  ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN | 0x3   | Test_SE0_NAK mode 
 *  ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM | 0x4   | Test_Packet mode  
 *  ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE | 0x5   | Test_force_Enable 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
 * 
 * Test mode disabled
 */
#define ALT_USB_DEV_DCTL_TSTCTL_E_DISD      0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
 * 
 * Test_J mode
 */
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ     0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
 * 
 * Test_K mode
 */
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTK     0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
 * 
 * Test_SE0_NAK mode
 */
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN    0x3
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
 * 
 * Test_Packet mode
 */
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM    0x4
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
 * 
 * Test_force_Enable
 */
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE    0x5

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_MSB        6
/* The width in bits of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_WIDTH      3
/* The mask used to set the ALT_USB_DEV_DCTL_TSTCTL register field value. */
#define ALT_USB_DEV_DCTL_TSTCTL_SET_MSK    0x00000070
/* The mask used to clear the ALT_USB_DEV_DCTL_TSTCTL register field value. */
#define ALT_USB_DEV_DCTL_TSTCTL_CLR_MSK    0xffffff8f
/* The reset value of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_TSTCTL field value from a register. */
#define ALT_USB_DEV_DCTL_TSTCTL_GET(value) (((value) & 0x00000070) >> 4)
/* Produces a ALT_USB_DEV_DCTL_TSTCTL register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_TSTCTL_SET(value) (((value) << 4) & 0x00000070)

/*
 * Field : Set Global Non-periodic IN NAK - sgnpinnak
 * 
 * A write to this field sets the Global Non-periodic IN NAK. The application uses
 * this bit to send a NAK handshake on all  nonperiodic IN endpoints. The core can
 * also Set this bit when a timeout condition is detected on a non-periodic
 * endpoint in shared FIFO operation. The application must Set this bit only after
 * making sure that the Global IN NAK Effective bit in the Core Interrupt Register
 * (GINTSTS.GINNakEff) is cleared
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                       
 * :----------------------------------|:------|:-----------------------------------
 *  ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD | 0x0   | Disable Global Non-periodic IN NAK
 *  ALT_USB_DEV_DCTL_SGNPINNAK_E_END  | 0x1   | Global Non-periodic IN NAK        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK
 * 
 * Disable Global Non-periodic IN NAK
 */
#define ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK
 * 
 * Global Non-periodic IN NAK
 */
#define ALT_USB_DEV_DCTL_SGNPINNAK_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_MSB        7
/* The width in bits of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_SGNPINNAK field value from a register. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DCTL_SGNPINNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Clear Global Non-periodic IN NAK - CGNPInNak
 * 
 * A write to this field clears the Global Non-periodic IN NAK.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                       
 * :---------------------------------|:------|:-----------------------------------
 *  ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS | 0x0   | Disable Global Non-periodic IN NAK
 *  ALT_USB_DEV_DCTL_CGNPINNAK_E_EN  | 0x1   | Clear Global Non-periodic IN NAK  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK
 * 
 * Disable Global Non-periodic IN NAK
 */
#define ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK
 * 
 * Clear Global Non-periodic IN NAK
 */
#define ALT_USB_DEV_DCTL_CGNPINNAK_E_EN     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_MSB        8
/* The width in bits of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_CGNPINNAK field value from a register. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DCTL_CGNPINNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Set Global OUT NAK - sgoutnak
 * 
 * A write to this field sets the Global OUT NAK.The application uses this bit to
 * send a NAK handshake on all OUT endpoints. The application must Set the this bit
 * only after making sure that the Global OUT NAK Effective bit in the Core
 * Interrupt Register GINTSTS.GOUTNakEff) is cleared.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description           
 * :---------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD | 0x0   | Disable Global OUT NAK
 *  ALT_USB_DEV_DCTL_SGOUTNAK_E_END  | 0x1   | Global OUT NAK        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK
 * 
 * Disable Global OUT NAK
 */
#define ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK
 * 
 * Global OUT NAK
 */
#define ALT_USB_DEV_DCTL_SGOUTNAK_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_MSB        9
/* The width in bits of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_SGOUTNAK field value from a register. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DCTL_SGOUTNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Clear Global OUT NAK - cgoutnak
 * 
 * A write to this field clears the Global OUT NAK.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                 
 * :---------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD | 0x0   | Disable Clear Global OUT NAK
 *  ALT_USB_DEV_DCTL_CGOUTNAK_E_END  | 0x1   | Clear Global OUT NAK        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK
 * 
 * Disable Clear Global OUT NAK
 */
#define ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK
 * 
 * Clear Global OUT NAK
 */
#define ALT_USB_DEV_DCTL_CGOUTNAK_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_MSB        10
/* The width in bits of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_CGOUTNAK field value from a register. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DCTL_CGOUTNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Power-On Programming Done - pwronprgdone
 * 
 * The application uses this bit to indicate that registerprogramming is completed
 * after a wake-up from Power Downmode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                  
 * :----------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE | 0x0   | Power-On Programming not done
 *  ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE    | 0x1   | Power-On Programming Done    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE
 * 
 * Power-On Programming not done
 */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE
 * 
 * Power-On Programming Done
 */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_MSB        11
/* The width in bits of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_PWRONPRGDONE field value from a register. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DCTL_PWRONPRGDONE register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Global Multi Count - gmc
 * 
 * GMC must be programmed only once after initialization.Applicable only for
 * Scatter/Gather DMA mode. This indicates the number of packets to be serviced for
 * that end point before moving to the next end point. It is only for non-periodic
 * end points. When Scatter/Gather DMA mode is disabled, this field isreserved. and
 * reads 0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description
 * :--------------------------------|:------|:------------
 *  ALT_USB_DEV_DCTL_GMC_E_NOTVALID | 0x0   | Invalid    
 *  ALT_USB_DEV_DCTL_GMC_E_ONEPKT   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DCTL_GMC_E_TWOPKT   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DCTL_GMC_E_THREEPKT | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
 * 
 * Invalid
 */
#define ALT_USB_DEV_DCTL_GMC_E_NOTVALID 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DCTL_GMC_E_ONEPKT   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DCTL_GMC_E_TWOPKT   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DCTL_GMC_E_THREEPKT 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_MSB        14
/* The width in bits of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DCTL_GMC register field value. */
#define ALT_USB_DEV_DCTL_GMC_SET_MSK    0x00006000
/* The mask used to clear the ALT_USB_DEV_DCTL_GMC register field value. */
#define ALT_USB_DEV_DCTL_GMC_CLR_MSK    0xffff9fff
/* The reset value of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_GMC field value from a register. */
#define ALT_USB_DEV_DCTL_GMC_GET(value) (((value) & 0x00006000) >> 13)
/* Produces a ALT_USB_DEV_DCTL_GMC register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_GMC_SET(value) (((value) << 13) & 0x00006000)

/*
 * Field : Ignore Frame number for Isochronous Endpoints - ignrfrmnum
 * 
 * Do NOT program IgnrFrmNum bit to 1'b1 when the core is operating in threshold
 * mode. When Scatter/Gather DMA mode is enabled this feature is not applicable to
 * High Speed, High bandwidth transfers. When this bit is enabled, there must be
 * only one packet per descriptor. In Scatter/Gather DMA mode, if this bit is
 * enabled, the packets are not flushed when a ISOC IN token is received for an
 * elapsed frame. When Scatter/Gather DMA mode is disabled, this field is used by
 * the application to enable periodic transfer interrupt. The application can
 * program periodic endpoint transfers for multiple (micro)frames.  0: periodic
 * transfer interrupt feature is disabled, application needs to program transfers
 * for periodic endpoints every (micro)frame  1: periodic transfer interrupt
 * feature is enabled, application can program transfers for multiple (micro)frames
 * for periodic endpoints. In non Scatter/Gather DMA mode the application will
 * receive transfer complete interrupt after transfers for multiple (micro)frames
 * are completed.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD | 0x0   | The core transmits the packets only in the frame
 * :                                   |       | number in which they are intended to be         
 * :                                   |       | transmitted                                     
 *  ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END  | 0x1   | The core ignores the frame number, sending      
 * :                                   |       | packets immediately as the packets are ready    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM
 * 
 * The core transmits the packets only in the frame number in which they are
 * intended to be transmitted
 */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM
 * 
 * The core ignores the frame number, sending packets immediately as the packets
 * are ready
 */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_MSB        15
/* The width in bits of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_IGNRFRMNUM field value from a register. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DCTL_IGNRFRMNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : NAK on Babble Error - nakonbble
 * 
 * Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for
 * the endpoint on which babble is received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                
 * :----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD | 0x0   | Disable NAK on Babble Error
 *  ALT_USB_DEV_DCTL_NAKONBBLE_E_END  | 0x1   | NAK on Babble Error        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE
 * 
 * Disable NAK on Babble Error
 */
#define ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE
 * 
 * NAK on Babble Error
 */
#define ALT_USB_DEV_DCTL_NAKONBBLE_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_MSB        16
/* The width in bits of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_RESET      0x0
/* Extracts the ALT_USB_DEV_DCTL_NAKONBBLE field value from a register. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DCTL_NAKONBBLE register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_SET(value) (((value) << 16) & 0x00010000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DCTL.
 */
struct ALT_USB_DEV_DCTL_s
{
    uint32_t        rmtwkupsig   :  1;  /* Remote Wakeup Signaling */
    uint32_t        sftdiscon    :  1;  /* Soft Disconnect */
    const uint32_t  gnpinnaksts  :  1;  /* Global Non-periodic IN NAK Status */
    const uint32_t  goutnaksts   :  1;  /* Global OUT NAK Status */
    uint32_t        tstctl       :  3;  /* Test Control */
    uint32_t        sgnpinnak    :  1;  /* Set Global Non-periodic IN NAK */
    uint32_t        CGNPInNak    :  1;  /* Clear Global Non-periodic IN NAK */
    uint32_t        sgoutnak     :  1;  /* Set Global OUT NAK */
    uint32_t        cgoutnak     :  1;  /* Clear Global OUT NAK */
    uint32_t        pwronprgdone :  1;  /* Power-On Programming Done */
    uint32_t                     :  1;  /* *UNDEFINED* */
    uint32_t        gmc          :  2;  /* Global Multi Count */
    uint32_t        ignrfrmnum   :  1;  /* Ignore Frame number for Isochronous Endpoints */
    uint32_t        nakonbble    :  1;  /* NAK on Babble Error */
    uint32_t                     : 15;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DCTL. */
typedef volatile struct ALT_USB_DEV_DCTL_s  ALT_USB_DEV_DCTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DCTL register from the beginning of the component. */
#define ALT_USB_DEV_DCTL_OFST        0x4
/* The address of the ALT_USB_DEV_DCTL register. */
#define ALT_USB_DEV_DCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCTL_OFST))

/*
 * Register : Device Status Register - dsts
 * 
 * This register indicates the status of the core with respect to USB-related
 * events. It must be read on interrupts from Device All Interrupts (DAINT)
 * register.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                   
 * :--------|:-------|:------|:-----------------------------------------------
 *  [0]     | R      | 0x0   | Suspend Status                                
 *  [2:1]   | R      | 0x1   | Enumerated Speed                              
 *  [3]     | R      | 0x0   | Erratic Error                                 
 *  [7:4]   | ???    | 0x0   | *UNDEFINED*                                   
 *  [21:8]  | R      | 0x0   | Frame or Microframe Number of the Received SOF
 *  [31:22] | ???    | 0x0   | *UNDEFINED*                                   
 * 
 */
/*
 * Field : Suspend Status - suspsts
 * 
 * In Device mode, this bit is Set as long as a Suspend condition is detected on
 * the USB. The core enters the Suspended state when there is no activity on the
 * phy_line_state_i signal for an extended period of time. The core comes out of
 * the suspend:
 * 
 * * When there is any activity on the phy_line_state_i signal
 * 
 * * When the application writes to the Remote Wakeup Signaling bit in the Device
 *   Control register (DCTL.RmtWkUpSig).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description     
 * :---------------------------------|:------|:-----------------
 *  ALT_USB_DEV_DSTS_SUSPSTS_E_INACT | 0x0   | No suspend state
 *  ALT_USB_DEV_DSTS_SUSPSTS_E_ACT   | 0x1   | Suspend state   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS
 * 
 * No suspend state
 */
#define ALT_USB_DEV_DSTS_SUSPSTS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS
 * 
 * Suspend state
 */
#define ALT_USB_DEV_DSTS_SUSPSTS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_MSB        0
/* The width in bits of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DSTS_SUSPSTS register field value. */
#define ALT_USB_DEV_DSTS_SUSPSTS_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DSTS_SUSPSTS register field value. */
#define ALT_USB_DEV_DSTS_SUSPSTS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DSTS_SUSPSTS field value from a register. */
#define ALT_USB_DEV_DSTS_SUSPSTS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DSTS_SUSPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_SUSPSTS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Enumerated Speed - enumspd
 * 
 * Indicates the speed at which the otg core has come up after speed detection
 * through a chirp sequence.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                                 
 * :----------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 | 0x0   | High speed (PHY clock is running at 30 or 60
 * :                                  |       | MHz)                                        
 *  ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 | 0x1   | Full speed (PHY clock is running at 30 or 60
 * :                                  |       | MHz)                                        
 *  ALT_USB_DEV_DSTS_ENUMSPD_E_LS6    | 0x2   | Low speed (PHY clock is running at 6 MHz)   
 *  ALT_USB_DEV_DSTS_ENUMSPD_E_FS48   | 0x3   | Full speed (PHY clock is running at 48 MHz) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
 * 
 * High speed (PHY clock is running at 30 or 60 MHz)
 */
#define ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
 * 
 * Full speed (PHY clock is running at 30 or 60 MHz)
 */
#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
 * 
 * Low speed (PHY clock is running at 6 MHz)
 */
#define ALT_USB_DEV_DSTS_ENUMSPD_E_LS6      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
 * 
 * Full speed (PHY clock is running at 48 MHz)
 */
#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS48     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_MSB        2
/* The width in bits of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DSTS_ENUMSPD register field value. */
#define ALT_USB_DEV_DSTS_ENUMSPD_SET_MSK    0x00000006
/* The mask used to clear the ALT_USB_DEV_DSTS_ENUMSPD register field value. */
#define ALT_USB_DEV_DSTS_ENUMSPD_CLR_MSK    0xfffffff9
/* The reset value of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_RESET      0x1
/* Extracts the ALT_USB_DEV_DSTS_ENUMSPD field value from a register. */
#define ALT_USB_DEV_DSTS_ENUMSPD_GET(value) (((value) & 0x00000006) >> 1)
/* Produces a ALT_USB_DEV_DSTS_ENUMSPD register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_ENUMSPD_SET(value) (((value) << 1) & 0x00000006)

/*
 * Field : Erratic Error - errticerr
 * 
 * The core sets this bit to report any erratic errors (phy_rxvalid_i/phy_rxvldh_i
 * or phy_rxactive_i is asserted for at least 2 ms, due to PHY error) seen on the
 * UTMI+ . Due to erratic errors, the otg core goes into Suspended state and an
 * interrupt is generated to the application with Early Suspend bit of the Core
 * Interrupt register (GINTSTS.ErlySusp). If the early suspend is asserted due to
 * an erratic error, the application can only perform a soft disconnect recover.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description     
 * :-----------------------------------|:------|:-----------------
 *  ALT_USB_DEV_DSTS_ERRTICERR_E_INACT | 0x0   | No Erratic Error
 *  ALT_USB_DEV_DSTS_ERRTICERR_E_ACT   | 0x1   | Erratic Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR
 * 
 * No Erratic Error
 */
#define ALT_USB_DEV_DSTS_ERRTICERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR
 * 
 * Erratic Error
 */
#define ALT_USB_DEV_DSTS_ERRTICERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_MSB        3
/* The width in bits of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DSTS_ERRTICERR register field value. */
#define ALT_USB_DEV_DSTS_ERRTICERR_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DSTS_ERRTICERR register field value. */
#define ALT_USB_DEV_DSTS_ERRTICERR_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DSTS_ERRTICERR field value from a register. */
#define ALT_USB_DEV_DSTS_ERRTICERR_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DSTS_ERRTICERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_ERRTICERR_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Frame or Microframe Number of the Received SOF - soffn
 * 
 * When the core is operating at high speed, this field contains a microframe
 * number. When the core is operating at full or low speed, this field contains a
 * Frame number.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_MSB        21
/* The width in bits of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_WIDTH      14
/* The mask used to set the ALT_USB_DEV_DSTS_SOFFN register field value. */
#define ALT_USB_DEV_DSTS_SOFFN_SET_MSK    0x003fff00
/* The mask used to clear the ALT_USB_DEV_DSTS_SOFFN register field value. */
#define ALT_USB_DEV_DSTS_SOFFN_CLR_MSK    0xffc000ff
/* The reset value of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_RESET      0x0
/* Extracts the ALT_USB_DEV_DSTS_SOFFN field value from a register. */
#define ALT_USB_DEV_DSTS_SOFFN_GET(value) (((value) & 0x003fff00) >> 8)
/* Produces a ALT_USB_DEV_DSTS_SOFFN register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_SOFFN_SET(value) (((value) << 8) & 0x003fff00)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DSTS.
 */
struct ALT_USB_DEV_DSTS_s
{
    const uint32_t  suspsts   :  1;  /* Suspend Status */
    const uint32_t  enumspd   :  2;  /* Enumerated Speed */
    const uint32_t  errticerr :  1;  /* Erratic Error */
    uint32_t                  :  4;  /* *UNDEFINED* */
    const uint32_t  soffn     : 14;  /* Frame or Microframe Number of the Received SOF */
    uint32_t                  : 10;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DSTS. */
typedef volatile struct ALT_USB_DEV_DSTS_s  ALT_USB_DEV_DSTS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DSTS register from the beginning of the component. */
#define ALT_USB_DEV_DSTS_OFST        0x8
/* The address of the ALT_USB_DEV_DSTS register. */
#define ALT_USB_DEV_DSTS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DSTS_OFST))

/*
 * Register : Device IN Endpoint Common Interrupt Mask Register - diepmsk
 * 
 * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn)
 * registers for all endpoints to generate an interrupt per IN endpoint. The IN
 * endpoint interrupt for a specific status in the DIEPINTn register can be masked
 * by writing to the corresponding bit in this register. Status bits are masked by
 * default.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                             
 * :--------|:-------|:------|:-----------------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Interrupt Mask       
 *  [1]     | RW     | 0x0   | Endpoint Disabled Interrupt Mask        
 *  [2]     | RW     | 0x0   | AHB Error Mask                          
 *  [3]     | RW     | 0x0   | Timeout Condition Mask                  
 *  [4]     | RW     | 0x0   | IN Token Received When TxFIFO Empty Mask
 *  [5]     | RW     | 0x0   | IN Token received with EP Mismatch Mask 
 *  [6]     | RW     | 0x0   | IN Endpoint NAK Effective Mask          
 *  [7]     | ???    | 0x0   | *UNDEFINED*                             
 *  [8]     | RW     | 0x0   | Fifo Underrun Mask                      
 *  [9]     | RW     | 0x0   | BNA interrupt Mask                      
 *  [12:10] | ???    | 0x0   | *UNDEFINED*                             
 *  [13]    | RW     | 0x0   | NAK interrupt Mask                      
 *  [31:14] | ???    | 0x0   | *UNDEFINED*                             
 * 
 */
/*
 * Field : Transfer Completed Interrupt Mask - xfercomplmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                         
 * :-----------------------------------------|:------|:-------------------------------------
 *  ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK   | 0x0   | Mask Transfer Completed Interrupt   
 *  ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1   | No Mask Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
 * 
 * Mask Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
 * 
 * No Mask Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt Mask - epdisbldmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK   | 0x0   | Mask Endpoint Disabled Interrupt   
 *  ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK | 0x1   | No Mask Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
 * 
 * Mask Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
 * 
 * No Mask Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK   | 0x0   | Mask AHB Error Interrupt    
 *  ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK | 0x1   | No Mask  AHB Error Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK
 * 
 * Mask AHB Error Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK
 * 
 * No Mask  AHB Error Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_AHBERRMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition Mask - timeoutmsk
 * 
 * Non-isochronous endpoints
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                        
 * :-----------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK   | 0x0   | Mask Timeout Condition Interrupt   
 *  ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK | 0x1   | No Mask Timeout Condition Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK
 * 
 * Mask Timeout Condition Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK
 * 
 * No Mask Timeout Condition Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_TMOMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPMSK_TMOMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO Empty Mask - intkntxfempmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                
 * :-------------------------------------------|:------|:--------------------------------------------
 *  ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK   | 0x0   | Mask IN Token Received When TxFIFO Empty   
 * :                                           |       | Interrupt                                  
 *  ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK | 0x1   | No Mask IN Token Received When TxFIFO Empty
 * :                                           |       | Interrupt                                  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
 * 
 * Mask IN Token Received When TxFIFO Empty Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
 * 
 * No Mask IN Token Received When TxFIFO Empty  Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token received with EP Mismatch Mask - intknepmismsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK   | 0x0   | Mask IN Token received with EP Mismatch   
 * :                                          |       | Interrupt                                 
 *  ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK | 0x1   | No Mask IN Token received with EP Mismatch
 * :                                          |       | Interrupt                                 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
 * 
 * Mask IN Token received with EP Mismatch Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
 * 
 * No Mask IN Token received with EP Mismatch Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective Mask - inepnakeffmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                
 * :------------------------------------------|:------|:--------------------------------------------
 *  ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK   | 0x0   | Mask IN Endpoint NAK Effective Interrupt   
 *  ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK | 0x1   | No Mask IN Endpoint NAK Effective Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
 * 
 * Mask IN Endpoint NAK Effective Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
 * 
 * No Mask IN Endpoint NAK Effective Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Fifo Underrun Mask - txfifoundrnmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                    
 * :-------------------------------------------|:------|:--------------------------------
 *  ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK   | 0x0   | Mask Fifo Underrun Interrupt   
 *  ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK | 0x1   | No Mask Fifo Underrun Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
 * 
 * Mask Fifo Underrun Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
 * 
 * No Mask Fifo Underrun Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA interrupt Mask - bnainintrmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description          
 * :-----------------------------------------|:------|:----------------------
 *  ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK   | 0x0   | Mask BNA Interrupt   
 *  ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK | 0x1   | No Mask BNA Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK
 * 
 * Mask BNA Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK
 * 
 * No Mask BNA Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_BNAININTRMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : NAK interrupt Mask - nakmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description          
 * :-----------------------------------|:------|:----------------------
 *  ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK   | 0x0   | Mask NAK Interrupt   
 *  ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK | 0x1   | No Mask NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK
 * 
 * Mask NAK Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK
 * 
 * No Mask NAK Interrupt
 */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_NAKMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPMSK_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPMSK.
 */
struct ALT_USB_DEV_DIEPMSK_s
{
    uint32_t  xfercomplmsk   :  1;  /* Transfer Completed Interrupt Mask */
    uint32_t  epdisbldmsk    :  1;  /* Endpoint Disabled Interrupt Mask */
    uint32_t  ahberrmsk      :  1;  /* AHB Error Mask */
    uint32_t  timeoutmsk     :  1;  /* Timeout Condition Mask */
    uint32_t  intkntxfempmsk :  1;  /* IN Token Received When TxFIFO Empty Mask */
    uint32_t  intknepmismsk  :  1;  /* IN Token received with EP Mismatch Mask */
    uint32_t  inepnakeffmsk  :  1;  /* IN Endpoint NAK Effective Mask */
    uint32_t                 :  1;  /* *UNDEFINED* */
    uint32_t  txfifoundrnmsk :  1;  /* Fifo Underrun Mask */
    uint32_t  bnainintrmsk   :  1;  /* BNA interrupt Mask */
    uint32_t                 :  3;  /* *UNDEFINED* */
    uint32_t  nakmsk         :  1;  /* NAK interrupt Mask */
    uint32_t                 : 18;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPMSK. */
typedef volatile struct ALT_USB_DEV_DIEPMSK_s  ALT_USB_DEV_DIEPMSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPMSK register from the beginning of the component. */
#define ALT_USB_DEV_DIEPMSK_OFST        0x10
/* The address of the ALT_USB_DEV_DIEPMSK register. */
#define ALT_USB_DEV_DIEPMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPMSK_OFST))

/*
 * Register : Device OUT Endpoint Common Interrupt Mask Register - doepmsk
 * 
 * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn)
 * registers for all endpoints to generate an interrupt per OUT endpoint. The OUT
 * endpoint interrupt for a specific status in the DOEPINTn register can be masked
 * by writing into the corresponding bit in this register. Status bits are masked
 * by default
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                   
 * :--------|:-------|:------|:-----------------------------------------------
 *  [0]     | RW     | 0x0   | Transfer Completed Interrupt Mask             
 *  [1]     | RW     | 0x0   | Endpoint Disabled Interrupt Mask              
 *  [2]     | RW     | 0x0   | AHB Error Mask                                
 *  [3]     | RW     | 0x0   | SETUP Phase Done Mask                         
 *  [4]     | RW     | 0x0   | OUT Token Received when Endpoint Disabled Mask
 *  [5]     | ???    | 0x0   | *UNDEFINED*                                   
 *  [6]     | RW     | 0x0   | Back-to-Back SETUP Packets Received Mask      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                                   
 *  [8]     | RW     | 0x0   | OUT Packet Error Mask                         
 *  [9]     | RW     | 0x0   | BNA interrupt Mask                            
 *  [11:10] | ???    | 0x0   | *UNDEFINED*                                   
 *  [12]    | RW     | 0x0   | Babble Error interrupt Mask                   
 *  [13]    | RW     | 0x0   | NAK interrupt Mask                            
 *  [14]    | RW     | 0x0   | NYET interrupt Mask                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                                   
 * 
 */
/*
 * Field : Transfer Completed Interrupt Mask - xfercomplmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                         
 * :-----------------------------------------|:------|:-------------------------------------
 *  ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK   | 0x0   | Mask Transfer Completed Interrupt   
 *  ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1   | No Mask Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
 * 
 * Mask Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
 * 
 * No Mask Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt Mask - epdisbldmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK   | 0x0   | Mask Endpoint Disabled Interrupt   
 *  ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK | 0x1   | No Mask Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
 * 
 * Mask Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
 * 
 * No Mask Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error Mask - ahberrmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK   | 0x0   | Mask AHB Error Interrupt    
 *  ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK | 0x1   | No Mask  AHB Error Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK
 * 
 * Mask AHB Error Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK
 * 
 * No Mask  AHB Error Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_AHBERRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done Mask - setupmsk
 * 
 * Applies to control endpoints only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                       
 * :-------------------------------------|:------|:-----------------------------------
 *  ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK   | 0x0   | Mask SETUP Phase Done Interrupt   
 *  ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK | 0x1   | No Mask SETUP Phase Done Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK
 * 
 * Mask SETUP Phase Done Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK
 * 
 * No Mask SETUP Phase Done Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_SETUPMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPMSK_SETUPMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received when Endpoint Disabled Mask - outtknepdismsk
 * 
 * Applies to control OUT endpoints only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                   
 * :-------------------------------------------|:------|:-----------------------------------------------
 *  ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK   | 0x0   | Mask OUT Token Received when Endpoint Disabled
 * :                                           |       | Interrupt                                     
 *  ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK | 0x1   | No Mask OUT Token Received when Endpoint      
 * :                                           |       | Disabled Interrupt                            
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
 * 
 * Mask OUT Token Received when Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
 * 
 * No Mask OUT Token Received when Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Back-to-Back SETUP Packets Received Mask - back2backsetup
 * 
 * Applies to control OUT endpoints only.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                
 * :-------------------------------------------|:------|:--------------------------------------------
 *  ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK   | 0x0   | Mask Back-to-Back SETUP Packets Received   
 * :                                           |       | Interrupt                                  
 *  ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK | 0x1   | No Mask Back-to-Back SETUP Packets Received
 * :                                           |       | Interrupt                                  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
 * 
 * Mask Back-to-Back SETUP Packets Received Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
 * 
 * No Mask Back-to-Back SETUP Packets Received Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error Mask - outpkterrmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                       
 * :-----------------------------------------|:------|:-----------------------------------
 *  ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK   | 0x0   | Mask OUT Packet Error Interrupt   
 *  ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK | 0x1   | No Mask OUT Packet Error Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
 * 
 * Mask OUT Packet Error Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK      0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
 * 
 * No Mask OUT Packet Error Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA interrupt Mask - bnaoutintrmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description          
 * :------------------------------------------|:------|:----------------------
 *  ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK   | 0x0   | Mask BNA Interrupt   
 *  ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK | 0x1   | No Mask BNA Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
 * 
 * Mask BNA Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
 * 
 * No Mask BNA Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Babble Error interrupt Mask - bbleerrmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                   
 * :---------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK   | 0x0   | Mask Babble Error Interrupt   
 *  ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK | 0x1   | No Mask Babble Error Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK
 * 
 * Mask Babble Error Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK
 * 
 * No Mask Babble Error Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_BBLEERRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK interrupt Mask - nakmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description          
 * :-----------------------------------|:------|:----------------------
 *  ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK   | 0x0   | Mask NAK Interrupt   
 *  ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK | 0x1   | No Mask NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK
 * 
 * Mask NAK Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK
 * 
 * No Mask NAK Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_NAKMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPMSK_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET interrupt Mask - nyetmsk
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description           
 * :------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK   | 0x0   | Mask NYET Interrupt   
 *  ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK | 0x1   | No Mask NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK
 * 
 * Mask NYET Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK
 * 
 * No Mask NYET Interrupt
 */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_NYETMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPMSK_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPMSK.
 */
struct ALT_USB_DEV_DOEPMSK_s
{
    uint32_t  xfercomplmsk   :  1;  /* Transfer Completed Interrupt Mask */
    uint32_t  epdisbldmsk    :  1;  /* Endpoint Disabled Interrupt Mask */
    uint32_t  ahberrmsk      :  1;  /* AHB Error Mask */
    uint32_t  setupmsk       :  1;  /* SETUP Phase Done Mask */
    uint32_t  outtknepdismsk :  1;  /* OUT Token Received when Endpoint Disabled Mask */
    uint32_t                 :  1;  /* *UNDEFINED* */
    uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received Mask */
    uint32_t                 :  1;  /* *UNDEFINED* */
    uint32_t  outpkterrmsk   :  1;  /* OUT Packet Error Mask */
    uint32_t  bnaoutintrmsk  :  1;  /* BNA interrupt Mask */
    uint32_t                 :  2;  /* *UNDEFINED* */
    uint32_t  bbleerrmsk     :  1;  /* Babble Error interrupt Mask */
    uint32_t  nakmsk         :  1;  /* NAK interrupt Mask */
    uint32_t  nyetmsk        :  1;  /* NYET interrupt Mask */
    uint32_t                 : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPMSK. */
typedef volatile struct ALT_USB_DEV_DOEPMSK_s  ALT_USB_DEV_DOEPMSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPMSK register from the beginning of the component. */
#define ALT_USB_DEV_DOEPMSK_OFST        0x14
/* The address of the ALT_USB_DEV_DOEPMSK register. */
#define ALT_USB_DEV_DOEPMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPMSK_OFST))

/*
 * Register : Device All Endpoints Interrupt Register - daint
 * 
 * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt
 * register interrupts the application using the Device OUT Endpoints Interrupt bit
 * or Device IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). This is shown in Figure 5-2.
 * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT
 * endpoints and 16 bits for IN endpoints. for a bidirectional endpoint, the
 * corresponding IN and OUT interrupt bits are used. Bits in this register are set
 * and cleared when the application sets and clears bits in the corresponding
 * Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
 * 
 * Register Layout
 * 
 *  Bits | Access | Reset | Description                  
 * :-----|:-------|:------|:------------------------------
 *  [0]  | R      | 0x0   | IN Endpoint 0 Interrupt Bit  
 *  [1]  | R      | 0x0   | IN Endpoint 1 Interrupt Bit  
 *  [2]  | R      | 0x0   | IN Endpoint 2 Interrupt Bit  
 *  [3]  | R      | 0x0   | IN Endpoint 3 Interrupt Bit  
 *  [4]  | R      | 0x0   | IN Endpoint 4 Interrupt Bit  
 *  [5]  | R      | 0x0   | IN Endpoint 5 Interrupt Bit  
 *  [6]  | R      | 0x0   | IN Endpoint 6 Interrupt Bit  
 *  [7]  | R      | 0x0   | IN Endpoint 7 Interrupt Bit  
 *  [8]  | R      | 0x0   | IN Endpoint 8 Interrupt Bit  
 *  [9]  | R      | 0x0   | IN Endpoint 9 Interrupt Bit  
 *  [10] | R      | 0x0   | IN Endpoint 10 Interrupt Bit 
 *  [11] | R      | 0x0   | IN Endpoint 11 Interrupt Bit 
 *  [12] | R      | 0x0   | IN Endpoint 12 Interrupt Bit 
 *  [13] | R      | 0x0   | IN Endpoint 13 Interrupt Bit 
 *  [14] | R      | 0x0   | IN Endpoint 14 Interrupt Bit 
 *  [15] | R      | 0x0   | IN Endpoint 15 Interrupt Bit 
 *  [16] | R      | 0x0   | OUT Endpoint 0 Interrupt Bit 
 *  [17] | R      | 0x0   | OUT Endpoint 1 Interrupt Bi  
 *  [18] | R      | 0x0   | OUT Endpoint 2 Interrupt Bit 
 *  [19] | R      | 0x0   | OUT Endpoint 3 Interrupt Bit 
 *  [20] | R      | 0x0   | OUT Endpoint 4 Interrupt Bit 
 *  [21] | R      | 0x0   | OUT Endpoint 5 Interrupt Bit 
 *  [22] | R      | 0x0   | OUT Endpoint 6 Interrupt Bi  
 *  [23] | R      | 0x0   | OUT Endpoint 7 Interrupt Bit 
 *  [24] | R      | 0x0   | OUT Endpoint 8 Interrupt Bit 
 *  [25] | R      | 0x0   | OUT Endpoint 9 Interrupt Bit 
 *  [26] | R      | 0x0   | OUT Endpoint 10 Interrupt Bit
 *  [27] | R      | 0x0   | OUT Endpoint 11 Interrupt Bit
 *  [28] | R      | 0x0   | OUT Endpoint 12 Interrupt Bit
 *  [29] | R      | 0x0   | OUT Endpoint 13 Interrupt Bit
 *  [30] | R      | 0x0   | OUT Endpoint 14 Interrupt Bi 
 *  [31] | R      | 0x0   | OUT Endpoint 15 Interrupt Bit
 * 
 */
/*
 * Field : IN Endpoint 0 Interrupt Bit - inepint0
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT0_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT0_E_ACT   | 0x1   | IN Endpoint 0 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT0_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0
 * 
 * IN Endpoint 0 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT0_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_MSB        0
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT0_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT0_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT0 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DAINT_INEPINT0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT0_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : IN Endpoint 1 Interrupt Bit - inepint1
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT1_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT1_E_ACT   | 0x1   | IN Endpoint 1 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT1_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1
 * 
 * IN Endpoint 1 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT1_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_MSB        1
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT1_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT1_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT1 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DAINT_INEPINT1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT1_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : IN Endpoint 2 Interrupt Bit - inepint2
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT2_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT2_E_ACT   | 0x1   | IN Endpoint 2 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT2_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2
 * 
 * IN Endpoint 2 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT2_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_MSB        2
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT2_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT2_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT2 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DAINT_INEPINT2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT2_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : IN Endpoint 3 Interrupt Bit - inepint3
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT3_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT3_E_ACT   | 0x1   | IN Endpoint 3 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT3_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3
 * 
 * IN Endpoint 3 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT3_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_MSB        3
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT3_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT3_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT3 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DAINT_INEPINT3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT3_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Endpoint 4 Interrupt Bit - inepint4
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT4_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT4_E_ACT   | 0x1   | IN Endpoint 4 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT4_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4
 * 
 * IN Endpoint 4 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT4_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_MSB        4
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT4_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT4_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT4 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT4_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DAINT_INEPINT4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT4_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Endpoint 5 Interrupt Bit - inepint5
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT5_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT5_E_ACT   | 0x1   | IN Endpoint 5 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT5_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5
 * 
 * IN Endpoint 5 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT5_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_MSB        5
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT5_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT5_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT5 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT5_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DAINT_INEPINT5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT5_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint 6 Interrupt Bit - inepint6
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT6_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT6_E_ACT   | 0x1   | IN Endpoint 6 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT6_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6
 * 
 * IN Endpoint 6 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT6_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_MSB        6
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT6_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT6_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT6 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT6_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DAINT_INEPINT6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT6_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : IN Endpoint 7 Interrupt Bit - inepint7
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT7_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT7_E_ACT   | 0x1   | IN Endpoint 7 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT7_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7
 * 
 * IN Endpoint 7 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT7_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_MSB        7
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT7_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT7_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT7 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT7_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DAINT_INEPINT7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT7_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : IN Endpoint 8 Interrupt Bit - inepint8
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT8_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT8_E_ACT   | 0x1   | IN Endpoint 8 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT8_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8
 * 
 * IN Endpoint 8 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT8_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_MSB        8
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT8_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT8_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT8 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT8_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DAINT_INEPINT8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT8_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : IN Endpoint 9 Interrupt Bit - inepint9
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description            
 * :-----------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DAINT_INEPINT9_E_INACT | 0x0   | No Interrupt           
 *  ALT_USB_DEV_DAINT_INEPINT9_E_ACT   | 0x1   | IN Endpoint 9 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT9_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9
 * 
 * IN Endpoint 9 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT9_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_MSB        9
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT9_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT9_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT9 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT9_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DAINT_INEPINT9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT9_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : IN Endpoint 10 Interrupt Bit - inepint10
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_INEPINT10_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_INEPINT10_E_ACT   | 0x1   | IN Endpoint 10 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT10_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10
 * 
 * IN Endpoint 10 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT10_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_MSB        10
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT10_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT10_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT10 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT10_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DAINT_INEPINT10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT10_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : IN Endpoint 11 Interrupt Bit - inepint11
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_INEPINT11_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_INEPINT11_E_ACT   | 0x1   | IN Endpoint 11 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT11_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11
 * 
 * IN Endpoint 11 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT11_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_MSB        11
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT11_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT11_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT11 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT11_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DAINT_INEPINT11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT11_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : IN Endpoint 12 Interrupt Bit - inepint12
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_INEPINT12_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_INEPINT12_E_ACT   | 0x1   | IN Endpoint 12 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT12_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12
 * 
 * IN Endpoint 12 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT12_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_MSB        12
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT12_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT12_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT12 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT12_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DAINT_INEPINT12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT12_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : IN Endpoint 13 Interrupt Bit - inepint13
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_INEPINT13_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_INEPINT13_E_ACT   | 0x1   | IN Endpoint 13 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT13_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13
 * 
 * IN Endpoint 13 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT13_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_MSB        13
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT13_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT13_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT13 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT13_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DAINT_INEPINT13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT13_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : IN Endpoint 14 Interrupt Bit - inepint14
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_INEPINT14_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_INEPINT14_E_ACT   | 0x1   | IN Endpoint 14 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT14_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14
 * 
 * IN Endpoint 14 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT14_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_MSB        14
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT14_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT14_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT14 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT14_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DAINT_INEPINT14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT14_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : IN Endpoint 15 Interrupt Bit - inepint15
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_INEPINT15_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_INEPINT15_E_ACT   | 0x1   | IN Endpoint 15 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT15_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15
 * 
 * IN Endpoint 15 Interrupt
 */
#define ALT_USB_DEV_DAINT_INEPINT15_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_MSB        15
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT15_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT15_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT15 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT15_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DAINT_INEPINT15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT15_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : OUT Endpoint 0 Interrupt Bit - outepint0
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT   | 0x1   | OUT Endpoint 0 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0
 * 
 * OUT Endpoint 0 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_MSB        16
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT0 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : OUT Endpoint 1 Interrupt Bi - outepint1
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT   | 0x1   | OUT Endpoint 1 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1
 * 
 * OUT Endpoint 1 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_MSB        17
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT1 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : OUT Endpoint 2 Interrupt Bit - outepint2
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT   | 0x1   | OUT Endpoint 2 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2
 * 
 * OUT Endpoint 2 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_MSB        18
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT2 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : OUT Endpoint 3 Interrupt Bit - outepint3
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT   | 0x1   | OUT Endpoint 3 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3
 * 
 * OUT Endpoint 3 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_MSB        19
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT3 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : OUT Endpoint 4 Interrupt Bit - outepint4
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT   | 0x1   | OUT Endpoint 4 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4
 * 
 * OUT Endpoint 4 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_MSB        20
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT4 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : OUT Endpoint 5 Interrupt Bit - outepint5
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT   | 0x1   | OUT Endpoint 5 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5
 * 
 * OUT Endpoint 5 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_MSB        21
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT5 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : OUT Endpoint 6 Interrupt Bi - outepint6
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT   | 0x1   | OUT Endpoint 6 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6
 * 
 * OUT Endpoint 6 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_MSB        22
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT6 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : OUT Endpoint 7 Interrupt Bit - outepint7
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT   | 0x1   | OUT Endpoint 7 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7
 * 
 * OUT Endpoint 7 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_MSB        23
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT7 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : OUT Endpoint 8 Interrupt Bit - outepint8
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT   | 0x1   | OUT Endpoint 8 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8
 * 
 * OUT Endpoint 8 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_MSB        24
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT8 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : OUT Endpoint 9 Interrupt Bit - outepint9
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT | 0x0   | No Interrupt            
 *  ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT   | 0x1   | OUT Endpoint 9 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9
 * 
 * OUT Endpoint 9 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_MSB        25
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT9 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : OUT Endpoint 10 Interrupt Bit - outepint10
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description              
 * :-------------------------------------|:------|:--------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT | 0x0   | No Interrupt             
 *  ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT   | 0x1   | OUT Endpoint 10 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10
 * 
 * OUT Endpoint 10 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_MSB        26
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT10 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : OUT Endpoint 11 Interrupt Bit - outepint11
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description              
 * :-------------------------------------|:------|:--------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT | 0x0   | No Interrupt             
 *  ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT   | 0x1   | OUT Endpoint 11 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11
 * 
 * OUT Endpoint 11 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_MSB        27
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT11 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : OUT Endpoint 12 Interrupt Bit - outepint12
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description              
 * :-------------------------------------|:------|:--------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT | 0x0   | No Interrupt             
 *  ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT   | 0x1   | OUT Endpoint 12 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12
 * 
 * OUT Endpoint 12 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_MSB        28
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT12 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : OUT Endpoint 13 Interrupt Bit - outepint13
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description              
 * :-------------------------------------|:------|:--------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT | 0x0   | No Interrupt             
 *  ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT   | 0x1   | OUT Endpoint 13 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13
 * 
 * OUT Endpoint 13 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_MSB        29
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT13 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : OUT Endpoint 14 Interrupt Bi - outepint14
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description              
 * :-------------------------------------|:------|:--------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT | 0x0   | No Interrupt             
 *  ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT   | 0x1   | OUT Endpoint 14 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14
 * 
 * OUT Endpoint 14 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_MSB        30
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT14 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : OUT Endpoint 15 Interrupt Bit - outepint15
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description              
 * :-------------------------------------|:------|:--------------------------
 *  ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT | 0x0   | No Interrupt             
 *  ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT   | 0x1   | OUT Endpoint 15 Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15
 * 
 * OUT Endpoint 15 Interrupt
 */
#define ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_MSB        31
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT15 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DAINT.
 */
struct ALT_USB_DEV_DAINT_s
{
    const uint32_t  inepint0   :  1;  /* IN Endpoint 0 Interrupt Bit */
    const uint32_t  inepint1   :  1;  /* IN Endpoint 1 Interrupt Bit */
    const uint32_t  inepint2   :  1;  /* IN Endpoint 2 Interrupt Bit */
    const uint32_t  inepint3   :  1;  /* IN Endpoint 3 Interrupt Bit */
    const uint32_t  inepint4   :  1;  /* IN Endpoint 4 Interrupt Bit */
    const uint32_t  inepint5   :  1;  /* IN Endpoint 5 Interrupt Bit */
    const uint32_t  inepint6   :  1;  /* IN Endpoint 6 Interrupt Bit */
    const uint32_t  inepint7   :  1;  /* IN Endpoint 7 Interrupt Bit */
    const uint32_t  inepint8   :  1;  /* IN Endpoint 8 Interrupt Bit */
    const uint32_t  inepint9   :  1;  /* IN Endpoint 9 Interrupt Bit */
    const uint32_t  inepint10  :  1;  /* IN Endpoint 10 Interrupt Bit */
    const uint32_t  inepint11  :  1;  /* IN Endpoint 11 Interrupt Bit */
    const uint32_t  inepint12  :  1;  /* IN Endpoint 12 Interrupt Bit */
    const uint32_t  inepint13  :  1;  /* IN Endpoint 13 Interrupt Bit */
    const uint32_t  inepint14  :  1;  /* IN Endpoint 14 Interrupt Bit */
    const uint32_t  inepint15  :  1;  /* IN Endpoint 15 Interrupt Bit */
    const uint32_t  outepint0  :  1;  /* OUT Endpoint 0 Interrupt Bit */
    const uint32_t  outepint1  :  1;  /* OUT Endpoint 1 Interrupt Bi */
    const uint32_t  outepint2  :  1;  /* OUT Endpoint 2 Interrupt Bit */
    const uint32_t  outepint3  :  1;  /* OUT Endpoint 3 Interrupt Bit */
    const uint32_t  outepint4  :  1;  /* OUT Endpoint 4 Interrupt Bit */
    const uint32_t  outepint5  :  1;  /* OUT Endpoint 5 Interrupt Bit */
    const uint32_t  outepint6  :  1;  /* OUT Endpoint 6 Interrupt Bi */
    const uint32_t  outepint7  :  1;  /* OUT Endpoint 7 Interrupt Bit */
    const uint32_t  outepint8  :  1;  /* OUT Endpoint 8 Interrupt Bit */
    const uint32_t  outepint9  :  1;  /* OUT Endpoint 9 Interrupt Bit */
    const uint32_t  outepint10 :  1;  /* OUT Endpoint 10 Interrupt Bit */
    const uint32_t  outepint11 :  1;  /* OUT Endpoint 11 Interrupt Bit */
    const uint32_t  outepint12 :  1;  /* OUT Endpoint 12 Interrupt Bit */
    const uint32_t  outepint13 :  1;  /* OUT Endpoint 13 Interrupt Bit */
    const uint32_t  outepint14 :  1;  /* OUT Endpoint 14 Interrupt Bi */
    const uint32_t  outepint15 :  1;  /* OUT Endpoint 15 Interrupt Bit */
};

/* The typedef declaration for register ALT_USB_DEV_DAINT. */
typedef volatile struct ALT_USB_DEV_DAINT_s  ALT_USB_DEV_DAINT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DAINT register from the beginning of the component. */
#define ALT_USB_DEV_DAINT_OFST        0x18
/* The address of the ALT_USB_DEV_DAINT register. */
#define ALT_USB_DEV_DAINT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINT_OFST))

/*
 * Register : Device All Endpoints Interrupt Mask Register - daintmsk
 * 
 * The Device Endpoint Interrupt Mask register works with the Device Endpoint
 * Interrupt register to interrupt the application when an event occurs on a device
 * endpoint. However, the Device All Endpoints Interrupt (DAINT) register bit
 * corresponding to that interrupt is still set.
 * 
 * Register Layout
 * 
 *  Bits | Access | Reset | Description                       
 * :-----|:-------|:------|:-----------------------------------
 *  [0]  | RW     | 0x0   | IN Endpoint 0 Interrupt mask Bit  
 *  [1]  | RW     | 0x0   | IN Endpoint 1 Interrupt mask Bit  
 *  [2]  | RW     | 0x0   | N Endpoint 2 Interrupt mask Bit   
 *  [3]  | RW     | 0x0   | ALT_USB_DEV_DAINTMSK_INEPMSK3     
 *  [4]  | RW     | 0x0   | IN Endpoint 4 Interrupt mask Bit  
 *  [5]  | RW     | 0x0   | IN Endpoint 5 Interrupt mask Bit  
 *  [6]  | RW     | 0x0   | IN Endpoint 6 Interrupt mask Bit  
 *  [7]  | RW     | 0x0   | IN Endpoint 7 Interrupt mask Bit  
 *  [8]  | RW     | 0x0   | IN Endpoint 8 Interrupt mask Bit  
 *  [9]  | RW     | 0x0   | IN Endpoint 9 Interrupt mask Bit  
 *  [10] | RW     | 0x0   | IN Endpoint 10 Interrupt mask Bit 
 *  [11] | RW     | 0x0   | IN Endpoint 11 Interrupt mask Bit 
 *  [12] | RW     | 0x0   | IN Endpoint 12 Interrupt mask Bit 
 *  [13] | RW     | 0x0   | IN Endpoint 13 Interrupt mask Bit 
 *  [14] | RW     | 0x0   | IN Endpoint 14 Interrupt mask Bit 
 *  [15] | RW     | 0x0   | ALT_USB_DEV_DAINTMSK_INEPMSK15    
 *  [16] | RW     | 0x0   | OUT Endpoint 0 Interrupt mask Bit 
 *  [17] | RW     | 0x0   | OUT Endpoint 1 Interrupt mask Bit 
 *  [18] | RW     | 0x0   | OUT Endpoint 2 Interrupt mask Bi  
 *  [19] | RW     | 0x0   | OUT Endpoint 3 Interrupt mask Bi  
 *  [20] | RW     | 0x0   | OUT Endpoint 4 Interrupt mask Bit 
 *  [21] | RW     | 0x0   | OUT Endpoint 5 Interrupt mask Bit 
 *  [22] | RW     | 0x0   | OUT Endpoint 6 Interrupt mask Bit 
 *  [23] | RW     | 0x0   | OUT Endpoint 7 Interrupt mask Bit 
 *  [24] | RW     | 0x0   | ALT_USB_DEV_DAINTMSK_OUTEPMSK8    
 *  [25] | RW     | 0x0   | OUT Endpoint 9 Interrupt mask Bit 
 *  [26] | RW     | 0x0   | OUT Endpoint 10 Interrupt mask Bi 
 *  [27] | RW     | 0x0   | OUT Endpoint 11 Interrupt mask Bit
 *  [28] | RW     | 0x0   | OUT Endpoint 12 Interrupt mask Bit
 *  [29] | RW     | 0x0   | OUT Endpoint 13 Interrupt mask Bit
 *  [30] | RW     | 0x0   | OUT Endpoint 14 Interrupt mask Bit
 *  [31] | RW     | 0x0   | OUT Endpoint 15 Interrupt mask Bit
 * 
 */
/*
 * Field : IN Endpoint 0 Interrupt mask Bit - inepmsk0
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK   | 0x0   | IN Endpoint 0 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0
 * 
 * IN Endpoint 0 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_MSB        0
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK0 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : IN Endpoint 1 Interrupt mask Bit - inepmsk1
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK   | 0x0   | IN Endpoint 1 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1
 * 
 * IN Endpoint 1 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_MSB        1
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK1 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : N Endpoint 2 Interrupt mask Bit - inepmsk2
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK   | 0x0   | IN Endpoint 2 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2
 * 
 * IN Endpoint 2 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_MSB        2
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK2 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : inepmsk3
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK   | 0x0   | IN Endpoint 3 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3
 * 
 * IN Endpoint 3 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_MSB        3
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK3 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Endpoint 4 Interrupt mask Bit - inepmsk4
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK   | 0x0   | IN Endpoint 4 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4
 * 
 * IN Endpoint 4 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_MSB        4
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK4 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Endpoint 5 Interrupt mask Bit - inepmsk5
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK   | 0x0   | IN Endpoint 5 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5
 * 
 * IN Endpoint 5 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_MSB        5
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK5 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint 6 Interrupt mask Bit - inepmsk6
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK   | 0x0   | IN Endpoint 6 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6
 * 
 * IN Endpoint 6 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_MSB        6
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK6 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : IN Endpoint 7 Interrupt mask Bit - inepmsk7
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK   | 0x0   | IN Endpoint 7 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7
 * 
 * IN Endpoint 7 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_MSB        7
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK7 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : IN Endpoint 8 Interrupt mask Bit - inepmsk8
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK   | 0x0   | IN Endpoint 8 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8
 * 
 * IN Endpoint 8 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_MSB        8
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK8 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : IN Endpoint 9 Interrupt mask Bit - inepmsk9
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK | 0x1   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK   | 0x0   | IN Endpoint 0 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9
 * 
 * IN Endpoint 0 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK     0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_MSB        9
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK9 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : IN Endpoint 10 Interrupt mask Bit - inepmsk10
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK   | 0x0   | IN Endpoint 10 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10
 * 
 * IN Endpoint 10 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_MSB        10
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK10 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : IN Endpoint 11 Interrupt mask Bit - inepmsk11
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK   | 0x0   | IN Endpoint 11 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11
 * 
 * IN Endpoint 11 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_MSB        11
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK11 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : IN Endpoint 12 Interrupt mask Bit - inepmsk12
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK   | 0x0   | IN Endpoint 12 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12
 * 
 * IN Endpoint 12 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_MSB        12
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK12 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : IN Endpoint 13 Interrupt mask Bit - InEpMsk13
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK   | 0x0   | IN Endpoint 13 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13
 * 
 * IN Endpoint 13 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_MSB        13
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK13 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : IN Endpoint 14 Interrupt mask Bit - inepmsk14
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK   | 0x0   | IN Endpoint 14 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14
 * 
 * IN Endpoint 14 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_MSB        14
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK14 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : InEpMsk15
 * 
 * IN Endpoint 15 Interrupt mask Bit
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT | 0x0   | No Interrupt mask           
 *  ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT   | 0x1   | IN Endpoint 0 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15
 * 
 * IN Endpoint 0 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_MSB        15
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK15 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : OUT Endpoint 0 Interrupt mask Bit - outepmsk0
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK   | 0x0   | OUT Endpoint 0 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0
 * 
 * OUT Endpoint 0 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_MSB        16
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : OUT Endpoint 1 Interrupt mask Bit - outepmsk1
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK   | 0x0   | OUT Endpoint 1 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1
 * 
 * OUT Endpoint 1 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_MSB        17
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : OUT Endpoint 2 Interrupt mask Bi - outepmsk2
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK   | 0x0   | OUT Endpoint 2 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2
 * 
 * OUT Endpoint 2 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_MSB        18
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET_MSK    0x00040000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_CLR_MSK    0xfffbffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : OUT Endpoint 3 Interrupt mask Bi - OutEPMsk3
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK   | 0x0   | OUT Endpoint 3 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3
 * 
 * OUT Endpoint 3 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_MSB        19
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : OUT Endpoint 4 Interrupt mask Bit - outepmsk4
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK   | 0x0   | OUT Endpoint 4 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4
 * 
 * OUT Endpoint 4 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_MSB        20
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : OUT Endpoint 5 Interrupt mask Bit - outepmsk5
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK   | 0x0   | OUT Endpoint 5 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5
 * 
 * OUT Endpoint 5 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_MSB        21
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : OUT Endpoint 6 Interrupt mask Bit - outepmsk6
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK   | 0x0   | OUT Endpoint 6 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6
 * 
 * OUT Endpoint 6 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_MSB        22
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET_MSK    0x00400000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_CLR_MSK    0xffbfffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : OUT Endpoint 7 Interrupt mask Bit - outepmsk7
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK   | 0x0   | OUT Endpoint 7 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7
 * 
 * OUT Endpoint 7 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_MSB        23
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET_MSK    0x00800000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_CLR_MSK    0xff7fffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : outepmsk8
 * 
 * OUT Endpoint 8 Interrupt mask Bit
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK   | 0x0   | OUT Endpoint 8 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8
 * 
 * OUT Endpoint 8 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_MSB        24
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET_MSK    0x01000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_CLR_MSK    0xfeffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : OUT Endpoint 9 Interrupt mask Bit - outepmsk9
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                  
 * :---------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK | 0x1   | No Interrupt mask            
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK   | 0x0   | OUT Endpoint 9 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9
 * 
 * OUT Endpoint 9 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK    0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_MSB        25
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET_MSK    0x02000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_CLR_MSK    0xfdffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : OUT Endpoint 10 Interrupt mask Bi - outepmsk10
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK | 0x1   | No Interrupt mask             
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK   | 0x0   | OUT Endpoint 10 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10
 * 
 * OUT Endpoint 10 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_MSB        26
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : OUT Endpoint 11 Interrupt mask Bit - outepmsk11
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK | 0x1   | No Interrupt mask             
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK   | 0x0   | OUT Endpoint 11 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11
 * 
 * OUT Endpoint 11 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_MSB        27
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : OUT Endpoint 12 Interrupt mask Bit - outepmsk12
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK | 0x1   | No Interrupt mask             
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK   | 0x0   | OUT Endpoint 12 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12
 * 
 * OUT Endpoint 12 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_MSB        28
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : OUT Endpoint 13 Interrupt mask Bit - outepmsk13
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK | 0x1   | No Interrupt mask             
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK   | 0x0   | OUT Endpoint 13 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13
 * 
 * OUT Endpoint 13 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_MSB        29
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : OUT Endpoint 14 Interrupt mask Bit - OutEPMsk14
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK | 0x1   | No Interrupt mask             
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK   | 0x0   | OUT Endpoint 14 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14
 * 
 * OUT Endpoint 14 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_MSB        30
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : OUT Endpoint 15 Interrupt mask Bit - outepmsk15
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                   
 * :----------------------------------------|:------|:-------------------------------
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK | 0x1   | No Interrupt mask             
 *  ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK   | 0x0   | OUT Endpoint 15 Interrupt mask
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15
 * 
 * No Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK 0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15
 * 
 * OUT Endpoint 15 Interrupt mask
 */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_MSB        31
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_RESET      0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DAINTMSK.
 */
struct ALT_USB_DEV_DAINTMSK_s
{
    uint32_t  inepmsk0   :  1;  /* IN Endpoint 0 Interrupt mask Bit */
    uint32_t  inepmsk1   :  1;  /* IN Endpoint 1 Interrupt mask Bit */
    uint32_t  inepmsk2   :  1;  /* N Endpoint 2 Interrupt mask Bit */
    uint32_t  inepmsk3   :  1;  /* ALT_USB_DEV_DAINTMSK_INEPMSK3 */
    uint32_t  inepmsk4   :  1;  /* IN Endpoint 4 Interrupt mask Bit */
    uint32_t  inepmsk5   :  1;  /* IN Endpoint 5 Interrupt mask Bit */
    uint32_t  inepmsk6   :  1;  /* IN Endpoint 6 Interrupt mask Bit */
    uint32_t  inepmsk7   :  1;  /* IN Endpoint 7 Interrupt mask Bit */
    uint32_t  inepmsk8   :  1;  /* IN Endpoint 8 Interrupt mask Bit */
    uint32_t  inepmsk9   :  1;  /* IN Endpoint 9 Interrupt mask Bit */
    uint32_t  inepmsk10  :  1;  /* IN Endpoint 10 Interrupt mask Bit */
    uint32_t  inepmsk11  :  1;  /* IN Endpoint 11 Interrupt mask Bit */
    uint32_t  inepmsk12  :  1;  /* IN Endpoint 12 Interrupt mask Bit */
    uint32_t  InEpMsk13  :  1;  /* IN Endpoint 13 Interrupt mask Bit */
    uint32_t  inepmsk14  :  1;  /* IN Endpoint 14 Interrupt mask Bit */
    uint32_t  InEpMsk15  :  1;  /* ALT_USB_DEV_DAINTMSK_INEPMSK15 */
    uint32_t  outepmsk0  :  1;  /* OUT Endpoint 0 Interrupt mask Bit */
    uint32_t  outepmsk1  :  1;  /* OUT Endpoint 1 Interrupt mask Bit */
    uint32_t  outepmsk2  :  1;  /* OUT Endpoint 2 Interrupt mask Bi */
    uint32_t  OutEPMsk3  :  1;  /* OUT Endpoint 3 Interrupt mask Bi */
    uint32_t  outepmsk4  :  1;  /* OUT Endpoint 4 Interrupt mask Bit */
    uint32_t  outepmsk5  :  1;  /* OUT Endpoint 5 Interrupt mask Bit */
    uint32_t  outepmsk6  :  1;  /* OUT Endpoint 6 Interrupt mask Bit */
    uint32_t  outepmsk7  :  1;  /* OUT Endpoint 7 Interrupt mask Bit */
    uint32_t  outepmsk8  :  1;  /* ALT_USB_DEV_DAINTMSK_OUTEPMSK8 */
    uint32_t  outepmsk9  :  1;  /* OUT Endpoint 9 Interrupt mask Bit */
    uint32_t  outepmsk10 :  1;  /* OUT Endpoint 10 Interrupt mask Bi */
    uint32_t  outepmsk11 :  1;  /* OUT Endpoint 11 Interrupt mask Bit */
    uint32_t  outepmsk12 :  1;  /* OUT Endpoint 12 Interrupt mask Bit */
    uint32_t  outepmsk13 :  1;  /* OUT Endpoint 13 Interrupt mask Bit */
    uint32_t  OutEPMsk14 :  1;  /* OUT Endpoint 14 Interrupt mask Bit */
    uint32_t  outepmsk15 :  1;  /* OUT Endpoint 15 Interrupt mask Bit */
};

/* The typedef declaration for register ALT_USB_DEV_DAINTMSK. */
typedef volatile struct ALT_USB_DEV_DAINTMSK_s  ALT_USB_DEV_DAINTMSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DAINTMSK register from the beginning of the component. */
#define ALT_USB_DEV_DAINTMSK_OFST        0x1c
/* The address of the ALT_USB_DEV_DAINTMSK register. */
#define ALT_USB_DEV_DAINTMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINTMSK_OFST))

/*
 * Register : Device VBUS Discharge Time Register - dvbusdis
 * 
 * This register specifies the VBUS discharge time after VBUS pulsing during SRP.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description               
 * :--------|:-------|:-------|:---------------------------
 *  [15:0]  | RW     | 0x17d7 | Device VBUS Discharge Time
 *  [31:16] | ???    | 0x0    | *UNDEFINED*               
 * 
 */
/*
 * Field : Device VBUS Discharge Time - dvbusdis
 * 
 * This value equals:
 * 
 * VBUS discharge time in PHY clocks/1,024 The value you use depends whether the
 * PHY is operating at 30 MHz (16-bit data width) or 60 MHz (8-bit data width).
 * Depending on your VBUS load, this value can need adjustment.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_MSB        15
/* The width in bits of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_RESET      0x17d7
/* Extracts the ALT_USB_DEV_DVBUSDIS_DVBUSDIS field value from a register. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DVBUSDIS.
 */
struct ALT_USB_DEV_DVBUSDIS_s
{
    uint32_t  dvbusdis : 16;  /* Device VBUS Discharge Time */
    uint32_t           : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DVBUSDIS. */
typedef volatile struct ALT_USB_DEV_DVBUSDIS_s  ALT_USB_DEV_DVBUSDIS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DVBUSDIS register from the beginning of the component. */
#define ALT_USB_DEV_DVBUSDIS_OFST        0x28
/* The address of the ALT_USB_DEV_DVBUSDIS register. */
#define ALT_USB_DEV_DVBUSDIS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSDIS_OFST))

/*
 * Register : Device VBUS Pulsing Time Register - dvbuspulse
 * 
 * This register specifies the VBUS pulsing time during SRP.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description             
 * :--------|:-------|:------|:-------------------------
 *  [11:0]  | RW     | 0x5b8 | Device VBUS Pulsing Time
 *  [31:12] | ???    | 0x0   | *UNDEFINED*             
 * 
 */
/*
 * Field : Device VBUS Pulsing Time - dvbuspulse
 * 
 * Specifies the VBUS pulsing time during SRP. This value equals:
 * 
 * VBUS pulsing time in PHY clocks/1,024
 * 
 * The value you use depends whether the PHY is operating at 30MHz (16-bit data
 * width) or 60 MHz (8-bit data width).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_MSB        11
/* The width in bits of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_WIDTH      12
/* The mask used to set the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET_MSK    0x00000fff
/* The mask used to clear the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_CLR_MSK    0xfffff000
/* The reset value of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_RESET      0x5b8
/* Extracts the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE field value from a register. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_GET(value) (((value) & 0x00000fff) >> 0)
/* Produces a ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value suitable for setting the register. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET(value) (((value) << 0) & 0x00000fff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DVBUSPULSE.
 */
struct ALT_USB_DEV_DVBUSPULSE_s
{
    uint32_t  dvbuspulse : 12;  /* Device VBUS Pulsing Time */
    uint32_t             : 20;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DVBUSPULSE. */
typedef volatile struct ALT_USB_DEV_DVBUSPULSE_s  ALT_USB_DEV_DVBUSPULSE_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DVBUSPULSE register from the beginning of the component. */
#define ALT_USB_DEV_DVBUSPULSE_OFST        0x2c
/* The address of the ALT_USB_DEV_DVBUSPULSE register. */
#define ALT_USB_DEV_DVBUSPULSE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSPULSE_OFST))

/*
 * Register : Device Threshold Control Register - dthrctl
 * 
 * Thresholding is not supported in Slave mode and so this register must not be
 * programmed in Slave mode. for threshold support, the AHB must be run at 60 MHz
 * or higher.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                          
 * :--------|:-------|:------|:--------------------------------------
 *  [0]     | RW     | 0x0   | Non-ISO IN Endpoints Threshold Enable
 *  [1]     | RW     | 0x0   | ISO IN Endpoints Threshold Enable    
 *  [10:2]  | RW     | 0x8   | Transmit Threshold                   
 *  [12:11] | RW     | 0x0   | AHB Threshold Ratio                  
 *  [15:13] | ???    | 0x0   | *UNDEFINED*                          
 *  [16]    | RW     | 0x0   | Receive Threshold Enable             
 *  [25:17] | RW     | 0x8   | Receive Threshold Length             
 *  [26]    | ???    | 0x0   | *UNDEFINED*                          
 *  [27]    | RW     | 0x1   | Arbiter Parking Enable               
 *  [31:28] | ???    | 0x0   | *UNDEFINED*                          
 * 
 */
/*
 * Field : Non-ISO IN Endpoints Threshold Enable - nonisothren
 * 
 * When this bit is Set, the core enables thresholding for Non Isochronous IN
 * endpoints.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD | 0x0   | No thresholding    
 *  ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END  | 0x1   | Enable thresholding
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN
 * 
 * No thresholding
 */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN
 * 
 * Enable thresholding
 */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_MSB        0
/* The width in bits of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_RESET      0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_NONISOTHREN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : ISO IN Endpoints Threshold Enable - isothren
 * 
 * When this bit is Set, the core enables thresholding for isochronous IN
 * endpoints.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description         
 * :------------------------------------|:------|:---------------------
 *  ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD | 0x0   | No thresholding     
 *  ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END  | 0x1   | Enables thresholding
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN
 * 
 * No thresholding
 */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN
 * 
 * Enables thresholding
 */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_MSB        1
/* The width in bits of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_RESET      0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_ISOTHREN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DTHRCTL_ISOTHREN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Transmit Threshold - txthrlen
 * 
 * This field specifies Transmit thresholding size in DWORDS. This also forms the
 * MAC threshold and specifies the amount of data in bytes to be in the
 * corresponding endpoint transmit FIFO, before the core can start transmit on the
 * USB. The threshold length has to be at least eight DWORDS when the value of
 * AHBThrRatio is 0. In case the AHBThrRatio is non zero the application needs to
 * ensure that the AHB Threshold value does not go below the recommended eight
 * DWORD.  This field controls both isochronous and non-isochronous IN endpoint
 * thresholds. The recommended value for ThrLen is to be the same as the programmed
 * AHB Burst Length (GAHBCFG.HBstLen).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_MSB        10
/* The width in bits of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_WIDTH      9
/* The mask used to set the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET_MSK    0x000007fc
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_CLR_MSK    0xfffff803
/* The reset value of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_RESET      0x8
/* Extracts the ALT_USB_DEV_DTHRCTL_TXTHRLEN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_GET(value) (((value) & 0x000007fc) >> 2)
/* Produces a ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET(value) (((value) << 2) & 0x000007fc)

/*
 * Field : AHB Threshold Ratio - ahbthrratio
 * 
 * These bits define the ratio between the AHB threshold and the MAC threshold for
 * the transmit path only. The AHB threshold always remains less than or equal to
 * the USB threshold, because this does not increase overhead. Both the AHB and the
 * MAC threshold must be DWORD-aligned. The application needs to program TxThrLen
 * and the AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB
 * threshold value is not DWORD aligned, the core might not behave correctly. When
 * programming the TxThrLen and AHBThrRatio, the application must ensure that the
 * minimum AHB threshold value does not go below 8 DWORDS to meet the USB
 * turnaround time requirements.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                     
 * :---------------------------------------------|:------|:---------------------------------
 *  ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO  | 0x0   | AHB threshold = MAC threshold   
 *  ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE   | 0x1   | AHB threshold = MAC threshold /2
 *  ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO   | 0x2   | AHB threshold = MAC threshold /4
 *  ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE | 0x3   | AHB threshold = MAC threshold / 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
 * 
 * AHB threshold = MAC threshold
 */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
 * 
 * AHB threshold = MAC threshold /2
 */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
 * 
 * AHB threshold = MAC threshold /4
 */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
 * 
 * AHB threshold = MAC threshold /
 */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_MSB        12
/* The width in bits of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET_MSK    0x00001800
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_CLR_MSK    0xffffe7ff
/* The reset value of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_RESET      0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO field value from a register. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_GET(value) (((value) & 0x00001800) >> 11)
/* Produces a ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET(value) (((value) << 11) & 0x00001800)

/*
 * Field : Receive Threshold Enable - rxthren
 * 
 * When this bit is Set, the core enables thresholding in the receive direction.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                 
 * :-----------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD | 0x0   | Disable thresholding                        
 *  ALT_USB_DEV_DTHRCTL_RXTHREN_E_END  | 0x1   | Enable thresholding in the receive direction
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN
 * 
 * Disable thresholding
 */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN
 * 
 * Enable thresholding in the receive direction
 */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_MSB        16
/* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_RESET      0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_RXTHREN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DTHRCTL_RXTHREN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Receive Threshold Length - rxthrlen
 * 
 * This field specifies Receive thresholding size in DWORDS.This field also
 * specifies the amount of data received on the USB before the core can start
 * transmitting on the AHB. The threshold length has to be at least eight DWORDS.
 * The recommended value for ThrLen is to be the same as the programmed AHB Burst
 * Length (GAHBCFG.HBstLen).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_MSB        25
/* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_WIDTH      9
/* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET_MSK    0x03fe0000
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_CLR_MSK    0xfc01ffff
/* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_RESET      0x8
/* Extracts the ALT_USB_DEV_DTHRCTL_RXTHRLEN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_GET(value) (((value) & 0x03fe0000) >> 17)
/* Produces a ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET(value) (((value) << 17) & 0x03fe0000)

/*
 * Field : Arbiter Parking Enable - arbprken
 * 
 * This bit controls internal DMA arbiter parking for IN endpoints. When
 * thresholding is enabled and this bit is Set to one, Then the arbiter parks on
 * the IN endpoint for which there is a token received on the USB. This is done to
 * avoid getting into underrun conditions. By Default the parking is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                
 * :------------------------------------|:------|:--------------------------------------------
 *  ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD | 0x0   | Disable DMA arbiter parking                
 *  ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END  | 0x1   | Enable DMA arbiter parking for IN endpoints
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN
 * 
 * Disable DMA arbiter parking
 */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN
 * 
 * Enable DMA arbiter parking for IN endpoints
 */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_MSB        27
/* The width in bits of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_RESET      0x1
/* Extracts the ALT_USB_DEV_DTHRCTL_ARBPRKEN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET(value) (((value) << 27) & 0x08000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTHRCTL.
 */
struct ALT_USB_DEV_DTHRCTL_s
{
    uint32_t  nonisothren :  1;  /* Non-ISO IN Endpoints Threshold Enable */
    uint32_t  isothren    :  1;  /* ISO IN Endpoints Threshold Enable */
    uint32_t  txthrlen    :  9;  /* Transmit Threshold */
    uint32_t  ahbthrratio :  2;  /* AHB Threshold Ratio */
    uint32_t              :  3;  /* *UNDEFINED* */
    uint32_t  rxthren     :  1;  /* Receive Threshold Enable */
    uint32_t  rxthrlen    :  9;  /* Receive Threshold Length */
    uint32_t              :  1;  /* *UNDEFINED* */
    uint32_t  arbprken    :  1;  /* Arbiter Parking Enable */
    uint32_t              :  4;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTHRCTL. */
typedef volatile struct ALT_USB_DEV_DTHRCTL_s  ALT_USB_DEV_DTHRCTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTHRCTL register from the beginning of the component. */
#define ALT_USB_DEV_DTHRCTL_OFST        0x30
/* The address of the ALT_USB_DEV_DTHRCTL register. */
#define ALT_USB_DEV_DTHRCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTHRCTL_OFST))

/*
 * Register : Device IN Endpoint FIFO Empty Interrupt Mask Register - diepempmsk
 * 
 * This register is used to control the IN endpoint FIFO empty interrupt generation
 * (DIEPINTn.TxfEmp).
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                               
 * :--------|:-------|:------|:-------------------------------------------
 *  [0]     | RW     | 0x0   | IN EP 0 Tx FIFO Empty Interrupt Mask Bits 
 *  [1]     | RW     | 0x0   | IN EP 1 Tx FIFO Empty Interrupt Mask Bits 
 *  [2]     | RW     | 0x0   | IN EP 2 Tx FIFO Empty Interrupt Mask Bits 
 *  [3]     | RW     | 0x0   | IN EP 3 Tx FIFO Empty Interrupt Mask Bits 
 *  [4]     | RW     | 0x0   | IN EP 4 Tx FIFO Empty Interrupt Mask Bits 
 *  [5]     | RW     | 0x0   | IN EP 5 Tx FIFO Empty Interrupt Mask Bits 
 *  [6]     | RW     | 0x0   | IN EP 6 Tx FIFO Empty Interrupt Mask Bits 
 *  [7]     | RW     | 0x0   | IN EP 7 Tx FIFO Empty Interrupt Mask Bits 
 *  [8]     | RW     | 0x0   | IN EP 8 Tx FIFO Empty Interrupt Mask Bits 
 *  [9]     | RW     | 0x0   | IN EP 9 Tx FIFO Empty Interrupt Mask Bits 
 *  [10]    | RW     | 0x0   | IN EP 10 Tx FIFO Empty Interrupt Mask Bits
 *  [11]    | RW     | 0x0   | IN EP 11 Tx FIFO Empty Interrupt Mask Bits
 *  [12]    | RW     | 0x0   | IN EP 12 Tx FIFO Empty Interrupt Mask Bits
 *  [13]    | RW     | 0x0   | IN EP 13 Tx FIFO Empty Interrupt Mask Bits
 *  [14]    | RW     | 0x0   | IN EP 14 Tx FIFO Empty Interrupt Mask Bits
 *  [15]    | RW     | 0x0   | IN EP 15 Tx FIFO Empty Interrupt Mask Bits
 *  [31:16] | ???    | 0x0   | *UNDEFINED*                               
 * 
 */
/*
 * Field : IN EP 0 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk0
 * 
 * This bit acts as mask bits for DIEPINT0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK   | 0x0   | Mask End point 0 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0
 * 
 * Mask End point 0 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : IN EP 1 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk1
 * 
 * This bit acts as mask bits for DIEPINT1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK   | 0x0   | Mask End point 1 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1
 * 
 * Mask End point 1 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : IN EP 2 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk2
 * 
 * This bit acts as mask bits for DIEPINT2.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK   | 0x0   | Mask End point 2 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2
 * 
 * Mask End point 2 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : IN EP 3 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk3
 * 
 * This bit acts as mask bits for DIEPINT3.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK   | 0x0   | Mask End point 3 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3
 * 
 * Mask End point 3 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN EP 4 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk4
 * 
 * This bit acts as mask bits for DIEPINT4.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK   | 0x0   | Mask End point 4 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4
 * 
 * Mask End point 4 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN EP 5 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk5
 * 
 * This bit acts as mask bits for DIEPINT5.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK   | 0x0   | Mask End point 5 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5
 * 
 * Mask End point 5 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN EP 6 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk6
 * 
 * This bit acts as mask bits for DIEPINT6.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK   | 0x0   | Mask End point 6 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6
 * 
 * Mask End point 6 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : IN EP 7 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk7
 * 
 * This bit acts as mask bits for DIEPINT7.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK   | 0x0   | Mask End point 7 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7
 * 
 * Mask End point 7 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : IN EP 8 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk8
 * 
 * This bit acts as mask bits for DIEPINT8.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK   | 0x0   | Mask End point 8 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8
 * 
 * Mask End point 8 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : IN EP 9 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk9
 * 
 * This bit acts as mask bits for DIEPINT9.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description               
 * :----------------------------------------------|:------|:---------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK   | 0x0   | Mask End point 9 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK | 0x1   | No mask                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9
 * 
 * Mask End point 9 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK     0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : IN EP 10 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk10
 * 
 * This bit acts as mask bits for DIEPINT10.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                
 * :-----------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK   | 0x0   | Mask End point 10 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK | 0x1   | No mask                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10
 * 
 * Mask End point 10 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET_MSK    0x00000400
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_CLR_MSK    0xfffffbff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : IN EP 11 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk11
 * 
 * This bit acts as mask bits for DIEPINT11.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                
 * :-----------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK   | 0x0   | Mask End point 11 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK | 0x1   | No mask                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11
 * 
 * Mask End point 11 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : IN EP 12 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk12
 * 
 * This bit acts as mask bits for DIEPINT12.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                
 * :-----------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK   | 0x0   | Mask End point 12 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK | 0x1   | No mask                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12
 * 
 * Mask End point 12 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : IN EP 13 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk13
 * 
 * This bit acts as mask bits for DIEPINT13.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                
 * :-----------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK   | 0x0   | Mask End point 12 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK | 0x1   | No mask                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13
 * 
 * Mask End point 12 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : IN EP 14 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk14
 * 
 * This bit acts as mask bits for DIEPINT14.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                
 * :-----------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK   | 0x0   | Mask End point 14 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK | 0x1   | No mask                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14
 * 
 * Mask End point 14 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : IN EP 15 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk15
 * 
 * This bit acts as mask bits for DIEPINT15.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                
 * :-----------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK   | 0x0   | Mask End point 15 interrupt
 *  ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK | 0x1   | No mask                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15
 * 
 * Mask End point 15 interrupt
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15
 * 
 * No mask
 */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET(value) (((value) << 15) & 0x00008000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPEMPMSK.
 */
struct ALT_USB_DEV_DIEPEMPMSK_s
{
    uint32_t  ineptxfempmsk0  :  1;  /* IN EP 0 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk1  :  1;  /* IN EP 1 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk2  :  1;  /* IN EP 2 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk3  :  1;  /* IN EP 3 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk4  :  1;  /* IN EP 4 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk5  :  1;  /* IN EP 5 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk6  :  1;  /* IN EP 6 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk7  :  1;  /* IN EP 7 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk8  :  1;  /* IN EP 8 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk9  :  1;  /* IN EP 9 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk10 :  1;  /* IN EP 10 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk11 :  1;  /* IN EP 11 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk12 :  1;  /* IN EP 12 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk13 :  1;  /* IN EP 13 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk14 :  1;  /* IN EP 14 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t  ineptxfempmsk15 :  1;  /* IN EP 15 Tx FIFO Empty Interrupt Mask Bits */
    uint32_t                  : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPEMPMSK. */
typedef volatile struct ALT_USB_DEV_DIEPEMPMSK_s  ALT_USB_DEV_DIEPEMPMSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPEMPMSK register from the beginning of the component. */
#define ALT_USB_DEV_DIEPEMPMSK_OFST        0x34
/* The address of the ALT_USB_DEV_DIEPEMPMSK register. */
#define ALT_USB_DEV_DIEPEMPMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPEMPMSK_OFST))

/*
 * Register : Device Control IN Endpoint 0 Control Register - diepctl0
 * 
 * This register covers Device Control IN Endpoint 0.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [1:0]   | RW     | 0x0   | Maximum Packet Size
 *  [14:2]  | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | R      | 0x1   | USB Active Endpoint
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | R      | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [29:28] | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints.The application must program this field with the
 * maximum packet size for the current logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 | 0x0   | 64 bytes   
 *  ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 | 0x1   | 32 bytes   
 *  ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 | 0x2   | 16 bytes   
 *  ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8  | 0x3   | 8 bytes    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
 * 
 * 64 bytes
 */
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
 * 
 * 32 bytes
 */
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
 * 
 * 16 bytes
 */
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16  0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
 * 
 * 8 bytes
 */
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL0_MPS_SET_MSK    0x00000003
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL0_MPS_CLR_MSK    0xfffffffc
/* The reset value of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL0_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * This bit is always SET to 1, indicating that control endpoint 0 is always active
 * in all configurations and interfaces.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                      
 * :-------------------------------------|:------|:----------------------------------
 *  ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 | 0x1   | Control endpoint is always active
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_USBACTEP
 * 
 * Control endpoint is always active
 */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPCTL0_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL0_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : NAK Status - naksts
 * 
 * When this bit is Set, either by the application or core, the core stops
 * transmitting data, even If there is data available in the TxFIFO. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                    
 * :------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                    |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT   | 0x1   | The core is transmitting NAK handshakes on this
 * :                                    |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL0_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Hardcoded to 00 for control.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT | 0x0   | Endpoint Control 0
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPTYPE
 * 
 * Endpoint Control 0
 */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL0_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * The application can only Set this bit, and the core clears it, when a SETUP
 * token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or
 * Global OUT NAK is Set along with this bit, the STALL bit takes priority.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_DEV_DIEPCTL0_STALL_E_INACT | 0x0   | No Stall       
 *  ALT_USB_DEV_DIEPCTL0_STALL_E_ACT   | 0x1   | Stall Handshake
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL
 * 
 * No Stall
 */
#define ALT_USB_DEV_DIEPCTL0_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL
 * 
 * Stall Handshake
 */
#define ALT_USB_DEV_DIEPCTL0_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL0_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL0_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL0_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * for Shared FIFO operation, this value is always Set to 0, indicating that
 * control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO.
 * for Dedicated FIFO operation, this value is Set to the FIFO number that is
 * assigned to IN Endpoint 0.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL0_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR | 0x0   | No action  
 *  ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR   | 0x1   | Clear NAK  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK
 * 
 * No action
 */
#define ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL0_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET | 0x0   | No action  
 *  ALT_USB_DEV_DIEPCTL0_SNAK_E_SET   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK
 * 
 * No action
 */
#define ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL0_SNAK_E_SET     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL0_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * The application sets this bit to stop transmitting data on an endpoint, even
 * before the transfer for that endpoint is complete. The application must wait for
 * the Endpoint Disabled interrupt before treating the endpoint as disabled. The
 * core clears this bit before setting the Endpoint Disabled Interrupt. The
 * application must Set this bit only If Endpoint Enable is already Set for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                       
 * :-----------------------------------|:------|:-----------------------------------
 *  ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT | 0x0   | No action                         
 *  ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT   | 0x1   | Stop transmitting data on endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS
 * 
 * No action
 */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS
 * 
 * Stop transmitting data on endpoint
 */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL0_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * When Scatter/Gather DMA mode is enabled, for IN endpoints this bit indicates
 * that the descriptor structure and data buffer with data ready to transmit is
 * setup. When Scatter/Gather DMA mode is disabled such as in bufferpointer based
 * DMA mode this bit indicates that data is ready to be transmitted on the
 * endpoint. The core clears this bit before setting the following interrupts on
 * this endpoint:
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description     
 * :-----------------------------------|:------|:-----------------
 *  ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT | 0x0   | No action       
 *  ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT   | 0x1   | Endpoint Enabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA
 * 
 * No action
 */
#define ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA
 * 
 * Endpoint Enabled
 */
#define ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL0_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL0.
 */
struct ALT_USB_DEV_DIEPCTL0_s
{
    uint32_t        mps      :  2;  /* Maximum Packet Size */
    uint32_t                 : 13;  /* *UNDEFINED* */
    const uint32_t  usbactep :  1;  /* USB Active Endpoint */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  naksts   :  1;  /* NAK Status */
    const uint32_t  eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t                 :  2;  /* *UNDEFINED* */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL0. */
typedef volatile struct ALT_USB_DEV_DIEPCTL0_s  ALT_USB_DEV_DIEPCTL0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL0_OFST        0x100
/* The address of the ALT_USB_DEV_DIEPCTL0 register. */
#define ALT_USB_DEV_DIEPCTL0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL0_OFST))

/*
 * Register : Device IN Endpoint 0 Interrupt Register - diepint0
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT0_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT0_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT0_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT0_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT0_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_TMO register field value. */
#define ALT_USB_DEV_DIEPINT0_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TMO register field value. */
#define ALT_USB_DEV_DIEPINT0_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT0_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT0_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT0_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT0_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT0_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT0_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT0.
 */
struct ALT_USB_DEV_DIEPINT0_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT0. */
typedef volatile struct ALT_USB_DEV_DIEPINT0_s  ALT_USB_DEV_DIEPINT0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT0_OFST        0x108
/* The address of the ALT_USB_DEV_DIEPINT0 register. */
#define ALT_USB_DEV_DIEPINT0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT0_OFST))

/*
 * Register : Device IN Endpoint 0 Transfer Size Register - dieptsiz0
 * 
 * The application must modify this register before enabling endpoint 0. Once
 * endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0
 * Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this
 * register. The application can only read this register once the core has cleared
 * the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to
 * 15. When Scatter/Gather DMA mode is enabled, this register must not be
 * programmed by the application. If the application reads this register when
 * Scatter/Gather DMA mode is enabled, the core returns all zeros.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description  
 * :--------|:-------|:------|:--------------
 *  [6:0]   | RW     | 0x0   | Transfer Size
 *  [18:7]  | ???    | 0x0   | *UNDEFINED*  
 *  [20:19] | RW     | 0x0   | Packet Count 
 *  [31:21] | ???    | 0x0   | *UNDEFINED*  
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_WIDTH      7
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0. This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_MSB        20
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET_MSK    0x00180000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_CLR_MSK    0xffe7ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ0_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00180000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00180000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ0.
 */
struct ALT_USB_DEV_DIEPTSIZ0_s
{
    uint32_t  xfersize :  7;  /* Transfer Size */
    uint32_t           : 12;  /* *UNDEFINED* */
    uint32_t  pktcnt   :  2;  /* Packet Count */
    uint32_t           : 11;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ0. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ0_s  ALT_USB_DEV_DIEPTSIZ0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ0_OFST        0x110
/* The address of the ALT_USB_DEV_DIEPTSIZ0 register. */
#define ALT_USB_DEV_DIEPTSIZ0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ0_OFST))

/*
 * Register : Device IN Endpoint 0 DMA Address Register - diepdma0
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma0
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 field value from a register. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA0.
 */
struct ALT_USB_DEV_DIEPDMA0_s
{
    uint32_t  diepdma0 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA0. */
typedef volatile struct ALT_USB_DEV_DIEPDMA0_s  ALT_USB_DEV_DIEPDMA0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA0_OFST        0x114
/* The address of the ALT_USB_DEV_DIEPDMA0 register. */
#define ALT_USB_DEV_DIEPDMA0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA0_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 0 - dtxfsts0
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS0.
 */
struct ALT_USB_DEV_DTXFSTS0_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS0. */
typedef volatile struct ALT_USB_DEV_DTXFSTS0_s  ALT_USB_DEV_DTXFSTS0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS0 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS0_OFST        0x118
/* The address of the ALT_USB_DEV_DTXFSTS0 register. */
#define ALT_USB_DEV_DTXFSTS0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS0_OFST))

/*
 * Register : Device IN Endpoint 0 DMA Buffer Address Register - diepdmab0
 * 
 * Endpoint 16.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab0
 * 
 * Used with Scatter/Gather DMA.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB0.
 */
struct ALT_USB_DEV_DIEPDMAB0_s
{
    const uint32_t  diepdmab0 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB0. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB0_s  ALT_USB_DEV_DIEPDMAB0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB0_OFST        0x11c
/* The address of the ALT_USB_DEV_DIEPDMAB0 register. */
#define ALT_USB_DEV_DIEPDMAB0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB0_OFST))

/*
 * Register : Device Control IN Endpoint 1 Control Register - diepctl1
 * 
 * Endpoint_number: 1
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL1_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL1_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL1_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL1_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL1_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL1_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL1_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL1_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL1_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL1_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL1_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL1_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL1_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL1_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL1_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL1_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL1_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL1_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL1_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL1_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL1_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL1_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL1_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL1_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL1_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL1_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL1_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL1.
 */
struct ALT_USB_DEV_DIEPCTL1_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL1. */
typedef volatile struct ALT_USB_DEV_DIEPCTL1_s  ALT_USB_DEV_DIEPCTL1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL1_OFST        0x120
/* The address of the ALT_USB_DEV_DIEPCTL1 register. */
#define ALT_USB_DEV_DIEPCTL1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL1_OFST))

/*
 * Register : Device IN Endpoint 1 Interrupt Register - diepint1
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA Interrupt                         
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt (                   
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT1_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT1_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT1_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT1_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT1_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_TMO register field value. */
#define ALT_USB_DEV_DIEPINT1_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TMO register field value. */
#define ALT_USB_DEV_DIEPINT1_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT1_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT1_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT1_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT1_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT1_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt ( - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT1_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT1.
 */
struct ALT_USB_DEV_DIEPINT1_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt ( */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT1. */
typedef volatile struct ALT_USB_DEV_DIEPINT1_s  ALT_USB_DEV_DIEPINT1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT1_OFST        0x128
/* The address of the ALT_USB_DEV_DIEPINT1 register. */
#define ALT_USB_DEV_DIEPINT1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT1_OFST))

/*
 * Register : Device IN Endpoint 1 Transfer Size Register - dieptsiz1
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ1_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ1_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ1_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ1.
 */
struct ALT_USB_DEV_DIEPTSIZ1_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ1. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ1_s  ALT_USB_DEV_DIEPTSIZ1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ1_OFST        0x130
/* The address of the ALT_USB_DEV_DIEPTSIZ1 register. */
#define ALT_USB_DEV_DIEPTSIZ1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ1_OFST))

/*
 * Register : Device IN Endpoint 1 DMA Address Registe - diepdma1
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma1
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 field value from a register. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA1.
 */
struct ALT_USB_DEV_DIEPDMA1_s
{
    uint32_t  diepdma1 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA1. */
typedef volatile struct ALT_USB_DEV_DIEPDMA1_s  ALT_USB_DEV_DIEPDMA1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA1_OFST        0x134
/* The address of the ALT_USB_DEV_DIEPDMA1 register. */
#define ALT_USB_DEV_DIEPDMA1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA1_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 1 - dtxfsts1
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS1.
 */
struct ALT_USB_DEV_DTXFSTS1_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS1. */
typedef volatile struct ALT_USB_DEV_DTXFSTS1_s  ALT_USB_DEV_DTXFSTS1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS1 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS1_OFST        0x138
/* The address of the ALT_USB_DEV_DTXFSTS1 register. */
#define ALT_USB_DEV_DTXFSTS1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS1_OFST))

/*
 * Register : Device IN Endpoint 1 DMA Buffer Address Register - diepdmab1
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab1
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB1.
 */
struct ALT_USB_DEV_DIEPDMAB1_s
{
    const uint32_t  diepdmab1 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB1. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB1_s  ALT_USB_DEV_DIEPDMAB1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB1_OFST        0x13c
/* The address of the ALT_USB_DEV_DIEPDMAB1 register. */
#define ALT_USB_DEV_DIEPDMAB1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB1_OFST))

/*
 * Register : Device Control IN Endpoint 2 Control Register - diepctl2
 * 
 * Endpoint_number: 2
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL2_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL2_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL2_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL2_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL2_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL2_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL2_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL2_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL2_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL2_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL2_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL2_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL2_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL2_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL2_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL2_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL2_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL2_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL2_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL2_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL2_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL2_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL2_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL2_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL2_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL2_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL2_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL2.
 */
struct ALT_USB_DEV_DIEPCTL2_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL2. */
typedef volatile struct ALT_USB_DEV_DIEPCTL2_s  ALT_USB_DEV_DIEPCTL2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL2_OFST        0x140
/* The address of the ALT_USB_DEV_DIEPCTL2 register. */
#define ALT_USB_DEV_DIEPCTL2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL2_OFST))

/*
 * Register : Device IN Endpoint 2 Interrupt Register - diepint2
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT2_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT2_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT2_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT2_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT2_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_TMO register field value. */
#define ALT_USB_DEV_DIEPINT2_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TMO register field value. */
#define ALT_USB_DEV_DIEPINT2_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT2_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT2_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT2_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT2_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT2_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT2_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT2.
 */
struct ALT_USB_DEV_DIEPINT2_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT2. */
typedef volatile struct ALT_USB_DEV_DIEPINT2_s  ALT_USB_DEV_DIEPINT2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT2_OFST        0x148
/* The address of the ALT_USB_DEV_DIEPINT2 register. */
#define ALT_USB_DEV_DIEPINT2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT2_OFST))

/*
 * Register : Device IN Endpoint 2 Transfer Size Register - dieptsiz2
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ2_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ2_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ2_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ2.
 */
struct ALT_USB_DEV_DIEPTSIZ2_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ2. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ2_s  ALT_USB_DEV_DIEPTSIZ2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ2_OFST        0x150
/* The address of the ALT_USB_DEV_DIEPTSIZ2 register. */
#define ALT_USB_DEV_DIEPTSIZ2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ2_OFST))

/*
 * Register : Device IN Endpoint 2 DMA Address Register - diepdma2
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma2
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 field value from a register. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA2.
 */
struct ALT_USB_DEV_DIEPDMA2_s
{
    uint32_t  diepdma2 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA2. */
typedef volatile struct ALT_USB_DEV_DIEPDMA2_s  ALT_USB_DEV_DIEPDMA2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA2_OFST        0x154
/* The address of the ALT_USB_DEV_DIEPDMA2 register. */
#define ALT_USB_DEV_DIEPDMA2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA2_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 2 - DTXFSTS2
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS2.
 */
struct ALT_USB_DEV_DTXFSTS2_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS2. */
typedef volatile struct ALT_USB_DEV_DTXFSTS2_s  ALT_USB_DEV_DTXFSTS2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS2 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS2_OFST        0x158
/* The address of the ALT_USB_DEV_DTXFSTS2 register. */
#define ALT_USB_DEV_DTXFSTS2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS2_OFST))

/*
 * Register : Device IN Endpoint 2 DMA Buffer Address Register - diepdmab2
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab2
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB2.
 */
struct ALT_USB_DEV_DIEPDMAB2_s
{
    const uint32_t  diepdmab2 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB2. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB2_s  ALT_USB_DEV_DIEPDMAB2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB2_OFST        0x15c
/* The address of the ALT_USB_DEV_DIEPDMAB2 register. */
#define ALT_USB_DEV_DIEPDMAB2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB2_OFST))

/*
 * Register : Device Control IN Endpoint 3 Control Register - diepctl3
 * 
 * Endpoint_number: 3
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL3_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL3_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL3_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL3_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL3_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL3_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL3_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL3_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL3_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL3_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL3_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL3_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL3_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL3_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL3_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL3_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL3_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL3_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL3_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL3_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL3_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL3_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL3_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL3_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL3_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL3_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL3_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL3.
 */
struct ALT_USB_DEV_DIEPCTL3_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL3. */
typedef volatile struct ALT_USB_DEV_DIEPCTL3_s  ALT_USB_DEV_DIEPCTL3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL3_OFST        0x160
/* The address of the ALT_USB_DEV_DIEPCTL3 register. */
#define ALT_USB_DEV_DIEPCTL3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL3_OFST))

/*
 * Register : Device IN Endpoint 3 Interrupt Register - diepint3
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT3_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT3_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT3_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT3_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT3_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_TMO register field value. */
#define ALT_USB_DEV_DIEPINT3_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TMO register field value. */
#define ALT_USB_DEV_DIEPINT3_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT3_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT3_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT3_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT3_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT3_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT3_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT3.
 */
struct ALT_USB_DEV_DIEPINT3_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT3. */
typedef volatile struct ALT_USB_DEV_DIEPINT3_s  ALT_USB_DEV_DIEPINT3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT3_OFST        0x168
/* The address of the ALT_USB_DEV_DIEPINT3 register. */
#define ALT_USB_DEV_DIEPINT3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT3_OFST))

/*
 * Register : Device IN Endpoint 3 Transfer Size Registe - dieptsiz3
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ3_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ3_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ3_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ3.
 */
struct ALT_USB_DEV_DIEPTSIZ3_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ3. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ3_s  ALT_USB_DEV_DIEPTSIZ3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ3_OFST        0x170
/* The address of the ALT_USB_DEV_DIEPTSIZ3 register. */
#define ALT_USB_DEV_DIEPTSIZ3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ3_OFST))

/*
 * Register : Device IN Endpoint 3 DMA Address Registe - diepdma3
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma3
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 field value from a register. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA3.
 */
struct ALT_USB_DEV_DIEPDMA3_s
{
    uint32_t  diepdma3 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA3. */
typedef volatile struct ALT_USB_DEV_DIEPDMA3_s  ALT_USB_DEV_DIEPDMA3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA3_OFST        0x174
/* The address of the ALT_USB_DEV_DIEPDMA3 register. */
#define ALT_USB_DEV_DIEPDMA3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA3_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 3 - dtxfsts3
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS3.
 */
struct ALT_USB_DEV_DTXFSTS3_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS3. */
typedef volatile struct ALT_USB_DEV_DTXFSTS3_s  ALT_USB_DEV_DTXFSTS3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS3 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS3_OFST        0x178
/* The address of the ALT_USB_DEV_DTXFSTS3 register. */
#define ALT_USB_DEV_DTXFSTS3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS3_OFST))

/*
 * Register : Device IN Endpoint 3 DMA Buffer Address Register - diepdmab3
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab3
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB3.
 */
struct ALT_USB_DEV_DIEPDMAB3_s
{
    const uint32_t  diepdmab3 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB3. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB3_s  ALT_USB_DEV_DIEPDMAB3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB3_OFST        0x17c
/* The address of the ALT_USB_DEV_DIEPDMAB3 register. */
#define ALT_USB_DEV_DIEPDMAB3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB3_OFST))

/*
 * Register : Device Control IN Endpoint 4 Control Register - diepctl4
 * 
 * Endpoint_number: 4
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL4_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL4_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL4_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL4_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL4_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL4_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL4_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL4_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL4_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL4_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL4_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL4_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL4_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL4_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL4_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL4_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL4_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL4_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL4_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL4_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL4_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL4_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL4_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL4_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL4_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL4_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL4_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL4.
 */
struct ALT_USB_DEV_DIEPCTL4_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL4. */
typedef volatile struct ALT_USB_DEV_DIEPCTL4_s  ALT_USB_DEV_DIEPCTL4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL4_OFST        0x180
/* The address of the ALT_USB_DEV_DIEPCTL4 register. */
#define ALT_USB_DEV_DIEPCTL4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL4_OFST))

/*
 * Register : Device IN Endpoint 4 Interrupt Register - diepint4
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT4_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT4_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT4_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT4_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT4_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_TMO register field value. */
#define ALT_USB_DEV_DIEPINT4_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TMO register field value. */
#define ALT_USB_DEV_DIEPINT4_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT4_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT4_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT4_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT4_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT4_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT4_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT4.
 */
struct ALT_USB_DEV_DIEPINT4_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT4. */
typedef volatile struct ALT_USB_DEV_DIEPINT4_s  ALT_USB_DEV_DIEPINT4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT4_OFST        0x188
/* The address of the ALT_USB_DEV_DIEPINT4 register. */
#define ALT_USB_DEV_DIEPINT4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT4_OFST))

/*
 * Register : Device IN Endpoint 4 Transfer Size Register - dieptsiz4
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ4_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ4_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ4_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ4.
 */
struct ALT_USB_DEV_DIEPTSIZ4_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ4. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ4_s  ALT_USB_DEV_DIEPTSIZ4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ4_OFST        0x190
/* The address of the ALT_USB_DEV_DIEPTSIZ4 register. */
#define ALT_USB_DEV_DIEPTSIZ4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ4_OFST))

/*
 * Register : Device IN Endpoint 4 DMA Address Register - diepdma4
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma4
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 field value from a register. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA4.
 */
struct ALT_USB_DEV_DIEPDMA4_s
{
    uint32_t  diepdma4 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA4. */
typedef volatile struct ALT_USB_DEV_DIEPDMA4_s  ALT_USB_DEV_DIEPDMA4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA4_OFST        0x194
/* The address of the ALT_USB_DEV_DIEPDMA4 register. */
#define ALT_USB_DEV_DIEPDMA4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA4_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 4 - dtxfsts4
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS4.
 */
struct ALT_USB_DEV_DTXFSTS4_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS4. */
typedef volatile struct ALT_USB_DEV_DTXFSTS4_s  ALT_USB_DEV_DTXFSTS4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS4 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS4_OFST        0x198
/* The address of the ALT_USB_DEV_DTXFSTS4 register. */
#define ALT_USB_DEV_DTXFSTS4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS4_OFST))

/*
 * Register : Device IN Endpoint 4 DMA Buffer Address Register - diepdmab4
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab4
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB4.
 */
struct ALT_USB_DEV_DIEPDMAB4_s
{
    const uint32_t  diepdmab4 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB4. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB4_s  ALT_USB_DEV_DIEPDMAB4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB4_OFST        0x19c
/* The address of the ALT_USB_DEV_DIEPDMAB4 register. */
#define ALT_USB_DEV_DIEPDMAB4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB4_OFST))

/*
 * Register : Device Control IN Endpoint 5 Control Register - diepctl5
 * 
 * Endpoint_number: 5
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL5_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL5_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL5_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL5_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL5_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL5_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL5_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL5_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL5_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL5_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL5_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL5_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL5_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL5_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL5_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL5_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL5_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL5_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL5_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL5_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL5_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL5_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL5_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL5_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL5_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL5_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL5_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL5.
 */
struct ALT_USB_DEV_DIEPCTL5_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL5. */
typedef volatile struct ALT_USB_DEV_DIEPCTL5_s  ALT_USB_DEV_DIEPCTL5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL5_OFST        0x1a0
/* The address of the ALT_USB_DEV_DIEPCTL5 register. */
#define ALT_USB_DEV_DIEPCTL5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL5_OFST))

/*
 * Register : Device IN Endpoint 5 Interrupt Register - diepint5
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt (                   
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT5_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT5_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT5_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT5_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT5_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_TMO register field value. */
#define ALT_USB_DEV_DIEPINT5_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TMO register field value. */
#define ALT_USB_DEV_DIEPINT5_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT5_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT5_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT5_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT5_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT5_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt ( - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT5_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT5.
 */
struct ALT_USB_DEV_DIEPINT5_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt ( */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT5. */
typedef volatile struct ALT_USB_DEV_DIEPINT5_s  ALT_USB_DEV_DIEPINT5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT5_OFST        0x1a8
/* The address of the ALT_USB_DEV_DIEPINT5 register. */
#define ALT_USB_DEV_DIEPINT5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT5_OFST))

/*
 * Register : Device IN Endpoint 5 Transfer Size Register - dieptsiz5
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ5_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ5_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ5_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ5.
 */
struct ALT_USB_DEV_DIEPTSIZ5_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ5. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ5_s  ALT_USB_DEV_DIEPTSIZ5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ5_OFST        0x1b0
/* The address of the ALT_USB_DEV_DIEPTSIZ5 register. */
#define ALT_USB_DEV_DIEPTSIZ5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ5_OFST))

/*
 * Register : Device IN Endpoint 5 DMA Address Register - diepdma5
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma5
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 field value from a register. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA5.
 */
struct ALT_USB_DEV_DIEPDMA5_s
{
    uint32_t  diepdma5 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA5. */
typedef volatile struct ALT_USB_DEV_DIEPDMA5_s  ALT_USB_DEV_DIEPDMA5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA5_OFST        0x1b4
/* The address of the ALT_USB_DEV_DIEPDMA5 register. */
#define ALT_USB_DEV_DIEPDMA5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA5_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 5 - dtxfsts5
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS5.
 */
struct ALT_USB_DEV_DTXFSTS5_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS5. */
typedef volatile struct ALT_USB_DEV_DTXFSTS5_s  ALT_USB_DEV_DTXFSTS5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS5 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS5_OFST        0x1b8
/* The address of the ALT_USB_DEV_DTXFSTS5 register. */
#define ALT_USB_DEV_DTXFSTS5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS5_OFST))

/*
 * Register : Device IN Endpoint 5 DMA Buffer Address Register - diepdmab5
 * 
 * Device IN Endpoint 1 Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description                        
 * :-------|:-------|:--------|:------------------------------------
 *  [31:0] | R      | Unknown | Device IN Endpoint 1 Buffer Address
 * 
 */
/*
 * Field : Device IN Endpoint 1 Buffer Address - diepdmab5
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB5.
 */
struct ALT_USB_DEV_DIEPDMAB5_s
{
    const uint32_t  diepdmab5 : 32;  /* Device IN Endpoint 1 Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB5. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB5_s  ALT_USB_DEV_DIEPDMAB5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB5_OFST        0x1bc
/* The address of the ALT_USB_DEV_DIEPDMAB5 register. */
#define ALT_USB_DEV_DIEPDMAB5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB5_OFST))

/*
 * Register : Device Control IN Endpoint 6 Control Register - diepctl6
 * 
 * Endpoint_number: 6
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL6_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL6_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL6_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL6_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL6_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL6_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL6_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL6_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL6_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL6_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL6_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL6_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL6_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL6_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL6_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL6_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL6_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL6_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL6_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL6_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL6_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL6_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL6_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL6_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL6_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL6_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL6_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL6.
 */
struct ALT_USB_DEV_DIEPCTL6_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL6. */
typedef volatile struct ALT_USB_DEV_DIEPCTL6_s  ALT_USB_DEV_DIEPCTL6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL6_OFST        0x1c0
/* The address of the ALT_USB_DEV_DIEPCTL6 register. */
#define ALT_USB_DEV_DIEPCTL6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL6_OFST))

/*
 * Register : Device IN Endpoint 6 Interrupt Register - diepint6
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT6_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT6_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT6_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT6_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT6_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_TMO register field value. */
#define ALT_USB_DEV_DIEPINT6_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TMO register field value. */
#define ALT_USB_DEV_DIEPINT6_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT6_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT6_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT6_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT6_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT6_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT6_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT6.
 */
struct ALT_USB_DEV_DIEPINT6_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT6. */
typedef volatile struct ALT_USB_DEV_DIEPINT6_s  ALT_USB_DEV_DIEPINT6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT6_OFST        0x1c8
/* The address of the ALT_USB_DEV_DIEPINT6 register. */
#define ALT_USB_DEV_DIEPINT6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT6_OFST))

/*
 * Register : Device IN Endpoint 6 Transfer Size Register - dieptsiz6
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ6_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ6_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ6_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ6.
 */
struct ALT_USB_DEV_DIEPTSIZ6_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ6. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ6_s  ALT_USB_DEV_DIEPTSIZ6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ6_OFST        0x1d0
/* The address of the ALT_USB_DEV_DIEPTSIZ6 register. */
#define ALT_USB_DEV_DIEPTSIZ6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ6_OFST))

/*
 * Register : Device IN Endpoint 6 DMA Address Register - diepdma6
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma6
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 field value from a register. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA6.
 */
struct ALT_USB_DEV_DIEPDMA6_s
{
    uint32_t  diepdma6 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA6. */
typedef volatile struct ALT_USB_DEV_DIEPDMA6_s  ALT_USB_DEV_DIEPDMA6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA6_OFST        0x1d4
/* The address of the ALT_USB_DEV_DIEPDMA6 register. */
#define ALT_USB_DEV_DIEPDMA6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA6_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 6 - dtxfsts6
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS6.
 */
struct ALT_USB_DEV_DTXFSTS6_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS6. */
typedef volatile struct ALT_USB_DEV_DTXFSTS6_s  ALT_USB_DEV_DTXFSTS6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS6 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS6_OFST        0x1d8
/* The address of the ALT_USB_DEV_DTXFSTS6 register. */
#define ALT_USB_DEV_DTXFSTS6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS6_OFST))

/*
 * Register : Device IN Endpoint 6 DMA Buffer Address Register - diepdmab6
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab6
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB6.
 */
struct ALT_USB_DEV_DIEPDMAB6_s
{
    const uint32_t  diepdmab6 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB6. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB6_s  ALT_USB_DEV_DIEPDMAB6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB6_OFST        0x1dc
/* The address of the ALT_USB_DEV_DIEPDMAB6 register. */
#define ALT_USB_DEV_DIEPDMAB6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB6_OFST))

/*
 * Register : Device Control IN Endpoint 7 Control Register - diepctl7
 * 
 * Endpoint_number: 7
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL7_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL7_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL7_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL7_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL7_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL7_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL7_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL7_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL7_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL7_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL7_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL7_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL7_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL7_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL7_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL7_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL7_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL7_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL7_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL7_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL7_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL7_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL7_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL7_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL7_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL7_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL7_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL7.
 */
struct ALT_USB_DEV_DIEPCTL7_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL7. */
typedef volatile struct ALT_USB_DEV_DIEPCTL7_s  ALT_USB_DEV_DIEPCTL7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL7_OFST        0x1e0
/* The address of the ALT_USB_DEV_DIEPCTL7 register. */
#define ALT_USB_DEV_DIEPCTL7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL7_OFST))

/*
 * Register : Device IN Endpoint 7 Interrupt Register - diepint7
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT7_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT7_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT7_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT7_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT7_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_TMO register field value. */
#define ALT_USB_DEV_DIEPINT7_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TMO register field value. */
#define ALT_USB_DEV_DIEPINT7_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT7_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT7_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT7_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT7_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT7_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT7_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT7.
 */
struct ALT_USB_DEV_DIEPINT7_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT7. */
typedef volatile struct ALT_USB_DEV_DIEPINT7_s  ALT_USB_DEV_DIEPINT7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT7_OFST        0x1e8
/* The address of the ALT_USB_DEV_DIEPINT7 register. */
#define ALT_USB_DEV_DIEPINT7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT7_OFST))

/*
 * Register : Device IN Endpoint 7 Transfer Size Register - dieptsiz7
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ7_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ7_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ7_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ7.
 */
struct ALT_USB_DEV_DIEPTSIZ7_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ7. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ7_s  ALT_USB_DEV_DIEPTSIZ7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ7_OFST        0x1f0
/* The address of the ALT_USB_DEV_DIEPTSIZ7 register. */
#define ALT_USB_DEV_DIEPTSIZ7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ7_OFST))

/*
 * Register : Device IN Endpoint 7 DMA Address Register - diepdma7
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma7
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 field value from a register. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA7.
 */
struct ALT_USB_DEV_DIEPDMA7_s
{
    uint32_t  diepdma7 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA7. */
typedef volatile struct ALT_USB_DEV_DIEPDMA7_s  ALT_USB_DEV_DIEPDMA7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA7_OFST        0x1f4
/* The address of the ALT_USB_DEV_DIEPDMA7 register. */
#define ALT_USB_DEV_DIEPDMA7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA7_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 7 - dtxfsts7
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS7.
 */
struct ALT_USB_DEV_DTXFSTS7_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS7. */
typedef volatile struct ALT_USB_DEV_DTXFSTS7_s  ALT_USB_DEV_DTXFSTS7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS7 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS7_OFST        0x1f8
/* The address of the ALT_USB_DEV_DTXFSTS7 register. */
#define ALT_USB_DEV_DTXFSTS7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS7_OFST))

/*
 * Register : Device IN Endpoint 7 DMA Buffer Address Register - diepdmab7
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab7
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB7.
 */
struct ALT_USB_DEV_DIEPDMAB7_s
{
    const uint32_t  diepdmab7 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB7. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB7_s  ALT_USB_DEV_DIEPDMAB7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB7_OFST        0x1fc
/* The address of the ALT_USB_DEV_DIEPDMAB7 register. */
#define ALT_USB_DEV_DIEPDMAB7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB7_OFST))

/*
 * Register : Device Control IN Endpoint 8 Control Register - diepctl8
 * 
 * Endpoint_number: 8
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL8_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL8_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL8_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL8_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL8_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL8_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL8_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL8_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL8_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL8_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL8_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL8_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL8_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL8_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL8_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL8_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL8_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL8_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL8_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL8_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL8_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL8_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL8_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL8_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL8_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL8_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL8_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL8.
 */
struct ALT_USB_DEV_DIEPCTL8_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL8. */
typedef volatile struct ALT_USB_DEV_DIEPCTL8_s  ALT_USB_DEV_DIEPCTL8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL8_OFST        0x200
/* The address of the ALT_USB_DEV_DIEPCTL8 register. */
#define ALT_USB_DEV_DIEPCTL8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL8_OFST))

/*
 * Register : Device IN Endpoint 8 Interrupt Register - diepint8
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt (                   
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT8_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT8_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT8_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT8_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT8_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_TMO register field value. */
#define ALT_USB_DEV_DIEPINT8_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TMO register field value. */
#define ALT_USB_DEV_DIEPINT8_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT8_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT8_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT8_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT8_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT8_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt ( - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT8_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT8.
 */
struct ALT_USB_DEV_DIEPINT8_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt ( */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT8. */
typedef volatile struct ALT_USB_DEV_DIEPINT8_s  ALT_USB_DEV_DIEPINT8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT8_OFST        0x208
/* The address of the ALT_USB_DEV_DIEPINT8 register. */
#define ALT_USB_DEV_DIEPINT8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT8_OFST))

/*
 * Register : Device IN Endpoint 8 Transfer Size Register - dieptsiz8
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                 
 * :--------|:-------|:------|:-----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size               
 *  [28:19] | RW     | 0x0   | Packet Count                
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints only
 *  [31]    | ???    | 0x0   | *UNDEFINED*                 
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ8_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints only - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ8_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ8_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ8.
 */
struct ALT_USB_DEV_DIEPTSIZ8_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints only */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ8. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ8_s  ALT_USB_DEV_DIEPTSIZ8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ8_OFST        0x210
/* The address of the ALT_USB_DEV_DIEPTSIZ8 register. */
#define ALT_USB_DEV_DIEPTSIZ8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ8_OFST))

/*
 * Register : Device IN Endpoint 8 DMA Address Register - diepdma8
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma8
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 field value from a register. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA8.
 */
struct ALT_USB_DEV_DIEPDMA8_s
{
    uint32_t  diepdma8 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA8. */
typedef volatile struct ALT_USB_DEV_DIEPDMA8_s  ALT_USB_DEV_DIEPDMA8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA8_OFST        0x214
/* The address of the ALT_USB_DEV_DIEPDMA8 register. */
#define ALT_USB_DEV_DIEPDMA8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA8_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 8 - dtxfsts8
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS8.
 */
struct ALT_USB_DEV_DTXFSTS8_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS8. */
typedef volatile struct ALT_USB_DEV_DTXFSTS8_s  ALT_USB_DEV_DTXFSTS8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS8 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS8_OFST        0x218
/* The address of the ALT_USB_DEV_DTXFSTS8 register. */
#define ALT_USB_DEV_DTXFSTS8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS8_OFST))

/*
 * Register : Device IN Endpoint 8 DMA Buffer Address Register - diepdmab8
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab8
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB8.
 */
struct ALT_USB_DEV_DIEPDMAB8_s
{
    const uint32_t  diepdmab8 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB8. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB8_s  ALT_USB_DEV_DIEPDMAB8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB8_OFST        0x21c
/* The address of the ALT_USB_DEV_DIEPDMAB8 register. */
#define ALT_USB_DEV_DIEPDMAB8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB8_OFST))

/*
 * Register : Device Control IN Endpoint 9 Control Register - diepctl9
 * 
 * Endpoint_number: 9
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL9_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL9_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL9_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL9_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL9_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL9_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL9_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL9_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL9_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL9_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL9_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL9_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL9_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL9_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL9_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL9_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL9_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL9_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL9_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL9_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL9_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL9_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL9_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL9_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL9_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL9_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL9_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL9.
 */
struct ALT_USB_DEV_DIEPCTL9_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL9. */
typedef volatile struct ALT_USB_DEV_DIEPCTL9_s  ALT_USB_DEV_DIEPCTL9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL9_OFST        0x220
/* The address of the ALT_USB_DEV_DIEPCTL9 register. */
#define ALT_USB_DEV_DIEPCTL9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL9_OFST))

/*
 * Register : Device IN Endpoint 9 Interrupt Register - diepint9
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT9_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT9_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT9_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT9_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_TMO_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT9_TMO_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_TMO register field value. */
#define ALT_USB_DEV_DIEPINT9_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TMO register field value. */
#define ALT_USB_DEV_DIEPINT9_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT9_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT9_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                 
 * :----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                        
 * :----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                  
 * :------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT9_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT9_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT9_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT9_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT9.
 */
struct ALT_USB_DEV_DIEPINT9_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT9. */
typedef volatile struct ALT_USB_DEV_DIEPINT9_s  ALT_USB_DEV_DIEPINT9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT9_OFST        0x228
/* The address of the ALT_USB_DEV_DIEPINT9 register. */
#define ALT_USB_DEV_DIEPINT9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT9_OFST))

/*
 * Register : Device IN Endpoint 9 Transfer Size Register - dieptsiz9
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ9_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description
 * :------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ9_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ9_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ9.
 */
struct ALT_USB_DEV_DIEPTSIZ9_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ9. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ9_s  ALT_USB_DEV_DIEPTSIZ9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ9_OFST        0x230
/* The address of the ALT_USB_DEV_DIEPTSIZ9 register. */
#define ALT_USB_DEV_DIEPTSIZ9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ9_OFST))

/*
 * Register : Device IN Endpoint 9 DMA Address Register - diepdma9
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma9
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 field value from a register. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA9.
 */
struct ALT_USB_DEV_DIEPDMA9_s
{
    uint32_t  diepdma9 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA9. */
typedef volatile struct ALT_USB_DEV_DIEPDMA9_s  ALT_USB_DEV_DIEPDMA9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA9_OFST        0x234
/* The address of the ALT_USB_DEV_DIEPDMA9 register. */
#define ALT_USB_DEV_DIEPDMA9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA9_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 9 - dtxfsts9
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS9.
 */
struct ALT_USB_DEV_DTXFSTS9_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS9. */
typedef volatile struct ALT_USB_DEV_DTXFSTS9_s  ALT_USB_DEV_DTXFSTS9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS9 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS9_OFST        0x238
/* The address of the ALT_USB_DEV_DTXFSTS9 register. */
#define ALT_USB_DEV_DTXFSTS9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS9_OFST))

/*
 * Register : Device IN Endpoint 9 DMA Buffer Address Register - diepdmab9
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab9
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB9.
 */
struct ALT_USB_DEV_DIEPDMAB9_s
{
    const uint32_t  diepdmab9 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB9. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB9_s  ALT_USB_DEV_DIEPDMAB9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB9_OFST        0x23c
/* The address of the ALT_USB_DEV_DIEPDMAB9 register. */
#define ALT_USB_DEV_DIEPDMAB9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB9_OFST))

/*
 * Register : Device Control IN Endpoint 10 Control Register - diepctl10
 * 
 * Endpoint_number: 10
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL10_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL10_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL10_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL10_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL10_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL10_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL10_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL10_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL10_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL10_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL10_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL10_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL10_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL10_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL10_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL10_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL10_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL10_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL10_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL10_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL10_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL10_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL10_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL10_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL10_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL10_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL10_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL10.
 */
struct ALT_USB_DEV_DIEPCTL10_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL10. */
typedef volatile struct ALT_USB_DEV_DIEPCTL10_s  ALT_USB_DEV_DIEPCTL10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL10_OFST        0x240
/* The address of the ALT_USB_DEV_DIEPCTL10 register. */
#define ALT_USB_DEV_DIEPCTL10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL10_OFST))

/*
 * Register : Device IN Endpoint 10 Interrupt Register - diepint10
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT10_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT10_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description      
 * :----------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT10_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT10_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_TMO_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT10_TMO_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_TMO register field value. */
#define ALT_USB_DEV_DIEPINT10_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TMO register field value. */
#define ALT_USB_DEV_DIEPINT10_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT10_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT10_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT10_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT10_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description            
 * :------------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT10_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT10_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT10.
 */
struct ALT_USB_DEV_DIEPINT10_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT10. */
typedef volatile struct ALT_USB_DEV_DIEPINT10_s  ALT_USB_DEV_DIEPINT10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT10_OFST        0x248
/* The address of the ALT_USB_DEV_DIEPINT10 register. */
#define ALT_USB_DEV_DIEPINT10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT10_OFST))

/*
 * Register : Device IN Endpoint 10 Transfer Size Register - dieptsiz10
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ10_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ10_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ10_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ10.
 */
struct ALT_USB_DEV_DIEPTSIZ10_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ10. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ10_s  ALT_USB_DEV_DIEPTSIZ10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ10_OFST        0x250
/* The address of the ALT_USB_DEV_DIEPTSIZ10 register. */
#define ALT_USB_DEV_DIEPTSIZ10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ10_OFST))

/*
 * Register : Device IN Endpoint 10 DMA Address Register - diepdma10
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma10
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 field value from a register. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA10.
 */
struct ALT_USB_DEV_DIEPDMA10_s
{
    uint32_t  diepdma10 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA10. */
typedef volatile struct ALT_USB_DEV_DIEPDMA10_s  ALT_USB_DEV_DIEPDMA10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA10_OFST        0x254
/* The address of the ALT_USB_DEV_DIEPDMA10 register. */
#define ALT_USB_DEV_DIEPDMA10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA10_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 10 - dtxfsts10
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS10.
 */
struct ALT_USB_DEV_DTXFSTS10_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS10. */
typedef volatile struct ALT_USB_DEV_DTXFSTS10_s  ALT_USB_DEV_DTXFSTS10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS10 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS10_OFST        0x258
/* The address of the ALT_USB_DEV_DTXFSTS10 register. */
#define ALT_USB_DEV_DTXFSTS10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS10_OFST))

/*
 * Register : Device IN Endpoint 10 DMA Buffer Address Register - diepdmab10
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab10
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB10.
 */
struct ALT_USB_DEV_DIEPDMAB10_s
{
    const uint32_t  diepdmab10 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB10. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB10_s  ALT_USB_DEV_DIEPDMAB10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB10_OFST        0x25c
/* The address of the ALT_USB_DEV_DIEPDMAB10 register. */
#define ALT_USB_DEV_DIEPDMAB10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB10_OFST))

/*
 * Register : Device Control IN Endpoint 11 Control Register - diepctl11
 * 
 * Endpoint_number: 11
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL11_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL11_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL11_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL11_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL11_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL11_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL11_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL11_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL11_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL11_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL11_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL11_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL11_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL11_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL11_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL11_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL11_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL11_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL11_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL11_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL11_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL11_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL11_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL11_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL11_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL11_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL11_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL11.
 */
struct ALT_USB_DEV_DIEPCTL11_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL11. */
typedef volatile struct ALT_USB_DEV_DIEPCTL11_s  ALT_USB_DEV_DIEPCTL11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL11_OFST        0x260
/* The address of the ALT_USB_DEV_DIEPCTL11 register. */
#define ALT_USB_DEV_DIEPCTL11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL11_OFST))

/*
 * Register : Device IN Endpoint 11 Interrupt Register - diepint11
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT11_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT11_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description      
 * :----------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT11_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT11_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_TMO_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT11_TMO_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_TMO register field value. */
#define ALT_USB_DEV_DIEPINT11_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TMO register field value. */
#define ALT_USB_DEV_DIEPINT11_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT11_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT11_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT11_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT11_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description            
 * :------------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT11_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT11_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT11.
 */
struct ALT_USB_DEV_DIEPINT11_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT11. */
typedef volatile struct ALT_USB_DEV_DIEPINT11_s  ALT_USB_DEV_DIEPINT11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT11_OFST        0x268
/* The address of the ALT_USB_DEV_DIEPINT11 register. */
#define ALT_USB_DEV_DIEPINT11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT11_OFST))

/*
 * Register : Device IN Endpoint 11 Transfer Size Register - dieptsiz11
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ11_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ11_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ11_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ11.
 */
struct ALT_USB_DEV_DIEPTSIZ11_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ11. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ11_s  ALT_USB_DEV_DIEPTSIZ11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ11_OFST        0x270
/* The address of the ALT_USB_DEV_DIEPTSIZ11 register. */
#define ALT_USB_DEV_DIEPTSIZ11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ11_OFST))

/*
 * Register : Device IN Endpoint 11 DMA Address Register - diepdma11
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma11
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 field value from a register. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA11.
 */
struct ALT_USB_DEV_DIEPDMA11_s
{
    uint32_t  diepdma11 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA11. */
typedef volatile struct ALT_USB_DEV_DIEPDMA11_s  ALT_USB_DEV_DIEPDMA11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA11_OFST        0x274
/* The address of the ALT_USB_DEV_DIEPDMA11 register. */
#define ALT_USB_DEV_DIEPDMA11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA11_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 11 - dtxfsts11
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS11.
 */
struct ALT_USB_DEV_DTXFSTS11_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS11. */
typedef volatile struct ALT_USB_DEV_DTXFSTS11_s  ALT_USB_DEV_DTXFSTS11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS11 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS11_OFST        0x278
/* The address of the ALT_USB_DEV_DTXFSTS11 register. */
#define ALT_USB_DEV_DTXFSTS11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS11_OFST))

/*
 * Register : Device IN Endpoint 11 DMA Buffer Address Register - diepdmab11
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab11
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB11.
 */
struct ALT_USB_DEV_DIEPDMAB11_s
{
    const uint32_t  diepdmab11 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB11. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB11_s  ALT_USB_DEV_DIEPDMAB11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB11_OFST        0x27c
/* The address of the ALT_USB_DEV_DIEPDMAB11 register. */
#define ALT_USB_DEV_DIEPDMAB11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB11_OFST))

/*
 * Register : Device Control IN Endpoint 12 Control Register - diepctl12
 * 
 * Endpoint_number: 12
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL12_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL12_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL12_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL12_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL12_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL12_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL12_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL12_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL12_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL12_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL12_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL12_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL12_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL12_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL12_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL12_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL12_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL12_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL12_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL12_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL12_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL12_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL12_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL12_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL12_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL12_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL12_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL12.
 */
struct ALT_USB_DEV_DIEPCTL12_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL12. */
typedef volatile struct ALT_USB_DEV_DIEPCTL12_s  ALT_USB_DEV_DIEPCTL12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL12_OFST        0x280
/* The address of the ALT_USB_DEV_DIEPCTL12 register. */
#define ALT_USB_DEV_DIEPCTL12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL12_OFST))

/*
 * Register : Device IN Endpoint 12 Interrupt Register - diepint12
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt (                   
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT12_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT12_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description      
 * :----------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT12_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT12_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_TMO_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT12_TMO_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_TMO register field value. */
#define ALT_USB_DEV_DIEPINT12_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TMO register field value. */
#define ALT_USB_DEV_DIEPINT12_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT12_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT12_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT12_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT12_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description            
 * :------------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT12_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt ( - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT12_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT12.
 */
struct ALT_USB_DEV_DIEPINT12_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt ( */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT12. */
typedef volatile struct ALT_USB_DEV_DIEPINT12_s  ALT_USB_DEV_DIEPINT12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT12_OFST        0x288
/* The address of the ALT_USB_DEV_DIEPINT12 register. */
#define ALT_USB_DEV_DIEPINT12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT12_OFST))

/*
 * Register : Device IN Endpoint 12 Transfer Size Register - dieptsiz12
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ12_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ12_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ12_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ12.
 */
struct ALT_USB_DEV_DIEPTSIZ12_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  pktcnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ12. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ12_s  ALT_USB_DEV_DIEPTSIZ12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ12_OFST        0x290
/* The address of the ALT_USB_DEV_DIEPTSIZ12 register. */
#define ALT_USB_DEV_DIEPTSIZ12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ12_OFST))

/*
 * Register : Device IN Endpoint 12 DMA Address Register - diepdma12
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma12
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 field value from a register. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA12.
 */
struct ALT_USB_DEV_DIEPDMA12_s
{
    uint32_t  diepdma12 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA12. */
typedef volatile struct ALT_USB_DEV_DIEPDMA12_s  ALT_USB_DEV_DIEPDMA12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA12_OFST        0x294
/* The address of the ALT_USB_DEV_DIEPDMA12 register. */
#define ALT_USB_DEV_DIEPDMA12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA12_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 12 - dtxfsts12
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS12.
 */
struct ALT_USB_DEV_DTXFSTS12_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS12. */
typedef volatile struct ALT_USB_DEV_DTXFSTS12_s  ALT_USB_DEV_DTXFSTS12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS12 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS12_OFST        0x298
/* The address of the ALT_USB_DEV_DTXFSTS12 register. */
#define ALT_USB_DEV_DTXFSTS12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS12_OFST))

/*
 * Register : Device IN Endpoint 12 DMA Buffer Address Register - diepdmab12
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab12
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB12.
 */
struct ALT_USB_DEV_DIEPDMAB12_s
{
    const uint32_t  diepdmab12 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB12. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB12_s  ALT_USB_DEV_DIEPDMAB12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB12_OFST        0x29c
/* The address of the ALT_USB_DEV_DIEPDMAB12 register. */
#define ALT_USB_DEV_DIEPDMAB12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB12_OFST))

/*
 * Register : Device Control IN Endpoint 13 Control Register - diepctl13
 * 
 * Endpoint_number: 13
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL13_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL13_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL13_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL13_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL13_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL13_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL13_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL13_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL13_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL13_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL13_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL13_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL13_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL13_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL13_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL13_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL13_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL13_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL13_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL13_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL13_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL13_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL13_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL13_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL13_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL13_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL13_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL13.
 */
struct ALT_USB_DEV_DIEPCTL13_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL13. */
typedef volatile struct ALT_USB_DEV_DIEPCTL13_s  ALT_USB_DEV_DIEPCTL13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL13_OFST        0x2a0
/* The address of the ALT_USB_DEV_DIEPCTL13 register. */
#define ALT_USB_DEV_DIEPCTL13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL13_OFST))

/*
 * Register : Device IN Endpoint 13 Interrupt Register - diepint13
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT13_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT13_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description      
 * :----------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT13_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT13_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_TMO_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT13_TMO_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_TMO register field value. */
#define ALT_USB_DEV_DIEPINT13_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TMO register field value. */
#define ALT_USB_DEV_DIEPINT13_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT13_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT13_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT13_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT13_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description            
 * :------------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT13_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT13_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT13.
 */
struct ALT_USB_DEV_DIEPINT13_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT13. */
typedef volatile struct ALT_USB_DEV_DIEPINT13_s  ALT_USB_DEV_DIEPINT13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT13_OFST        0x2a8
/* The address of the ALT_USB_DEV_DIEPINT13 register. */
#define ALT_USB_DEV_DIEPINT13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT13_OFST))

/*
 * Register : Device IN Endpoint 13 Transfer Size Register - dieptsiz13
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ13_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ13_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ13_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ13.
 */
struct ALT_USB_DEV_DIEPTSIZ13_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ13. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ13_s  ALT_USB_DEV_DIEPTSIZ13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ13_OFST        0x2b0
/* The address of the ALT_USB_DEV_DIEPTSIZ13 register. */
#define ALT_USB_DEV_DIEPTSIZ13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ13_OFST))

/*
 * Register : Device IN Endpoint 13 DMA Address Register - diepdma13
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma13
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 field value from a register. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA13.
 */
struct ALT_USB_DEV_DIEPDMA13_s
{
    uint32_t  diepdma13 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA13. */
typedef volatile struct ALT_USB_DEV_DIEPDMA13_s  ALT_USB_DEV_DIEPDMA13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA13_OFST        0x2b4
/* The address of the ALT_USB_DEV_DIEPDMA13 register. */
#define ALT_USB_DEV_DIEPDMA13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA13_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 13 - dtxfsts13
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS13.
 */
struct ALT_USB_DEV_DTXFSTS13_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS13. */
typedef volatile struct ALT_USB_DEV_DTXFSTS13_s  ALT_USB_DEV_DTXFSTS13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS13 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS13_OFST        0x2b8
/* The address of the ALT_USB_DEV_DTXFSTS13 register. */
#define ALT_USB_DEV_DTXFSTS13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS13_OFST))

/*
 * Register : Device IN Endpoint 13 DMA Buffer Address Register - diepdmab13
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab13
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB13.
 */
struct ALT_USB_DEV_DIEPDMAB13_s
{
    const uint32_t  diepdmab13 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB13. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB13_s  ALT_USB_DEV_DIEPDMAB13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB13_OFST        0x2bc
/* The address of the ALT_USB_DEV_DIEPDMAB13 register. */
#define ALT_USB_DEV_DIEPDMAB13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB13_OFST))

/*
 * Register : Device Control IN Endpoint 14 Control Register - diepctl14
 * 
 * Endpoint_number: 14
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL14_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL14_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL14_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL14_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL14_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL14_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL14_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL14_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL14_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL14_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL14_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL14_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL14_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL14_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL14_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL14_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL14_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL14_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL14_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL14_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL14_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL14_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL14_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL14_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL14_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL14_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL14_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL14.
 */
struct ALT_USB_DEV_DIEPCTL14_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL14. */
typedef volatile struct ALT_USB_DEV_DIEPCTL14_s  ALT_USB_DEV_DIEPCTL14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL14_OFST        0x2c0
/* The address of the ALT_USB_DEV_DIEPCTL14 register. */
#define ALT_USB_DEV_DIEPCTL14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL14_OFST))

/*
 * Register : Device IN Endpoint 14 Interrupt Register - diepint14
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt (                   
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT14_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT14_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description      
 * :----------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT14_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT14_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_TMO_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT14_TMO_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_TMO register field value. */
#define ALT_USB_DEV_DIEPINT14_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TMO register field value. */
#define ALT_USB_DEV_DIEPINT14_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT14_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT14_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT14_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT14_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description            
 * :------------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT14_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt ( - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT14_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT14.
 */
struct ALT_USB_DEV_DIEPINT14_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt ( */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT14. */
typedef volatile struct ALT_USB_DEV_DIEPINT14_s  ALT_USB_DEV_DIEPINT14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT14_OFST        0x2c8
/* The address of the ALT_USB_DEV_DIEPINT14 register. */
#define ALT_USB_DEV_DIEPINT14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT14_OFST))

/*
 * Register : Device IN Endpoint 14 Transfer Size Register - dieptsiz14
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                 
 * :--------|:-------|:------|:-----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size               
 *  [28:19] | RW     | 0x0   | Packet Count                
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints only
 *  [31]    | ???    | 0x0   | *UNDEFINED*                 
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ14_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints only - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ14_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ14_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ14.
 */
struct ALT_USB_DEV_DIEPTSIZ14_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints only */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ14. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ14_s  ALT_USB_DEV_DIEPTSIZ14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ14_OFST        0x2d0
/* The address of the ALT_USB_DEV_DIEPTSIZ14 register. */
#define ALT_USB_DEV_DIEPTSIZ14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ14_OFST))

/*
 * Register : Device IN Endpoint 14 DMA Address Register - diepdma14
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma14
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 field value from a register. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA14.
 */
struct ALT_USB_DEV_DIEPDMA14_s
{
    uint32_t  diepdma14 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA14. */
typedef volatile struct ALT_USB_DEV_DIEPDMA14_s  ALT_USB_DEV_DIEPDMA14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA14_OFST        0x2d4
/* The address of the ALT_USB_DEV_DIEPDMA14 register. */
#define ALT_USB_DEV_DIEPDMA14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA14_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 14 - dtxfsts14
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS14.
 */
struct ALT_USB_DEV_DTXFSTS14_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS14. */
typedef volatile struct ALT_USB_DEV_DTXFSTS14_s  ALT_USB_DEV_DTXFSTS14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS14 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS14_OFST        0x2d8
/* The address of the ALT_USB_DEV_DTXFSTS14 register. */
#define ALT_USB_DEV_DTXFSTS14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS14_OFST))

/*
 * Register : Device IN Endpoint 14 DMA Buffer Address Register - diepdmab14
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab14
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB14.
 */
struct ALT_USB_DEV_DIEPDMAB14_s
{
    const uint32_t  diepdmab14 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB14. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB14_s  ALT_USB_DEV_DIEPDMAB14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB14_OFST        0x2dc
/* The address of the ALT_USB_DEV_DIEPDMAB14 register. */
#define ALT_USB_DEV_DIEPDMAB14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB14_OFST))

/*
 * Register : Device Control IN Endpoint 15 Control Registe - diepctl15
 * 
 * Endpoint_number: 15
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL15_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL15_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL15_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL15_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPCTL15_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DIEPCTL15_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DIEPCTL15_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DIEPCTL15_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL15_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL15_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL15_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL15_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL15_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL15_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DIEPCTL15_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DIEPCTL15_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DIEPCTL15_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL15_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL15_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL15_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL15_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL15_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL15_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL15_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL15_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL15_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL15_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPCTL15.
 */
struct ALT_USB_DEV_DIEPCTL15_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPCTL15. */
typedef volatile struct ALT_USB_DEV_DIEPCTL15_s  ALT_USB_DEV_DIEPCTL15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPCTL15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL15_OFST        0x2e0
/* The address of the ALT_USB_DEV_DIEPCTL15 register. */
#define ALT_USB_DEV_DIEPCTL15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL15_OFST))

/*
 * Register : Device IN Endpoint 15 Interrupt Register - diepint15
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt          
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt           
 *  [2]     | R      | 0x0   | AHB Error                             
 *  [3]     | R      | 0x0   | Timeout Condition                     
 *  [4]     | R      | 0x0   | IN Token Received When TxFIFO is Empty
 *  [5]     | R      | 0x0   | IN Token Received with EP Mismatch    
 *  [6]     | R      | 0x0   | IN Endpoint NAK Effective             
 *  [7]     | R      | 0x1   | Transmit FIFO Empty                   
 *  [8]     | R      | 0x0   | Fifo Underrun                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                        
 *  [10]    | ???    | 0x0   | *UNDEFINED*                           
 *  [11]    | R      | 0x0   | Packet Drop Status                    
 *  [12]    | R      | 0x0   | BbleErr Interrupt                     
 *  [13]    | R      | 0x0   | NAK Interrupt                         
 *  [14]    | R      | 0x0   | NYET Interrupt                        
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled
 * 
 * * for IN endpoint this field indicates that the requested data from the
 *   descriptor is moved from external system memory to internal FIFO.
 * 
 * * for OUT endpoint this field indicates that the requested data from the
 *   internal FIFO is moved to external system memory. This interrupt is generated
 *   only when the corresponding endpoint descriptor is closed, and the IOC bit for
 *   the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled,
 *   this field indicates that the programmed transfer is complete on the AHB as
 *   well as on the USB, for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT15_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AHB Error - ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT15_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timeout Condition - timeout
 * 
 * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In
 * dedicated FIFO mode, applies only to Control IN endpoints.  In Scatter/Gather
 * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has
 * detected a timeout condition on the USB for the last IN token on this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description      
 * :----------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT15_TMO_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT15_TMO_E_ACT   | 0x1   | Timeout interrupy
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_TMO_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO
 * 
 * Timeout interrupy
 */
#define ALT_USB_DEV_DIEPINT15_TMO_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_MSB        3
/* The width in bits of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_TMO register field value. */
#define ALT_USB_DEV_DIEPINT15_TMO_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TMO register field value. */
#define ALT_USB_DEV_DIEPINT15_TMO_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT15_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT15_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_TMO_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : IN Token Received When TxFIFO is Empty - intkntxfemp
 * 
 * Applies to non-periodic IN endpoints only. Indicates that an IN token was
 * received when the associated TxFIFO (periodic/non-periodic) was empty. This
 * interrupt is asserted on the endpoint for which the IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT | 0x0   | No interrupt               
 *  ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT   | 0x1   | IN Token Received Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
 * 
 * IN Token Received Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_MSB        4
/* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : IN Token Received with EP Mismatch - intknepmis
 * 
 * Applies to non-periodic IN endpoints only. Indicates that the data in the top of
 * the non-periodic TxFIFO belongs to an endpoint other than the one for which the
 * IN token was received. This interrupt is asserted on the endpoint for which the
 * IN token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT | 0x0   | No interrupt                                
 *  ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT   | 0x1   | IN Token Received with EP Mismatch interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS
 * 
 * IN Token Received with EP Mismatch interrupt
 */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_MSB        5
/* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : IN Endpoint NAK Effective - inepnakeff
 * 
 * Applies to periodic IN endpoints only. This bit can be cleared when the
 * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This
 * interrupt indicates that the core has sampled the NAK bit Set (either by the
 * application or by the core). The interrupt indicates that the IN endpoint NAK
 * bit Set by the application has taken effect in the core.This interrupt does not
 * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority
 * over a NAK bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT | 0x0   | No interrupt                       
 *  ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT   | 0x1   | IN Endpoint NAK Effective interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF
 * 
 * IN Endpoint NAK Effective interrupt
 */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_MSB        6
/* The width in bits of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Transmit FIFO Empty - txfemp
 * 
 * This bit is valid only for IN Endpoints This interrupt is asserted when the
 * TxFIFO for this endpoint is either half or completely empty. The half or
 * completely empty status is determined by the TxFIFO Empty Level bit in the Core
 * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT | 0x0   | No interrupt                 
 *  ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT   | 0x1   | Transmit FIFO Empty interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP
 * 
 * Transmit FIFO Empty interrupt
 */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_MSB        7
/* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_RESET      0x1
/* Extracts the ALT_USB_DEV_DIEPINT15_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT15_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Fifo Underrun - txfifoundrn
 * 
 * Applies to IN endpoints Only. The core generates this interrupt when it detects
 * a transmit FIFO underrun condition for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description            
 * :------------------------------------------|:------|:------------------------
 *  ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT | 0x0   | No interrupt           
 *  ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT   | 0x1   | Fifo Underrun interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
 * 
 * Fifo Underrun interrupt
 */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_MSB        8
/* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core
 * generates this interrupt when the descriptor accessed is not ready for the Core
 * to process, such as Host busy or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT15_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT15_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPINT15.
 */
struct ALT_USB_DEV_DIEPINT15_s
{
    const uint32_t  xfercompl   :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld    :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr      :  1;  /* AHB Error */
    const uint32_t  timeout     :  1;  /* Timeout Condition */
    const uint32_t  intkntxfemp :  1;  /* IN Token Received When TxFIFO is Empty */
    const uint32_t  intknepmis  :  1;  /* IN Token Received with EP Mismatch */
    const uint32_t  inepnakeff  :  1;  /* IN Endpoint NAK Effective */
    const uint32_t  txfemp      :  1;  /* Transmit FIFO Empty */
    const uint32_t  txfifoundrn :  1;  /* Fifo Underrun */
    const uint32_t  bnaintr     :  1;  /* BNA  Interrupt */
    uint32_t                    :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts   :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr     :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt   :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt  :  1;  /* NYET Interrupt */
    uint32_t                    : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPINT15. */
typedef volatile struct ALT_USB_DEV_DIEPINT15_s  ALT_USB_DEV_DIEPINT15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPINT15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT15_OFST        0x2e8
/* The address of the ALT_USB_DEV_DIEPINT15 register. */
#define ALT_USB_DEV_DIEPINT15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT15_OFST))

/*
 * Register : Device IN Endpoint 15 Transfer Size Register - dieptsiz15
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                
 * :--------|:-------|:------|:----------------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size              
 *  [28:19] | RW     | 0x0   | Packet Count               
 *  [30:29] | RW     | 0x0   | Applies to IN endpoints onl
 *  [31]    | ???    | 0x0   | *UNDEFINED*                
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - PktCnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the TxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ15_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : Applies to IN endpoints onl - mc
 * 
 * for periodic IN endpoints, this field indicates the number of packets that must
 * be transmitted per microframe on the USB. The core uses this field to calculate
 * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this
 * field is valid only in Internal DMA mode. It specifies the number of packets the
 * core must fetchfor an IN endpoint before it switches to the endpoint pointed to
 * by the Next Endpoint field of the Device Endpoint-n Control register
 * (DIEPCTLn.NextEp)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description
 * :-------------------------------------|:------|:------------
 *  ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE      0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO      0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_MSB        30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ15_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ15_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPTSIZ15.
 */
struct ALT_USB_DEV_DIEPTSIZ15_s
{
    uint32_t  xfersize : 19;  /* Transfer Size */
    uint32_t  PktCnt   : 10;  /* Packet Count */
    uint32_t  mc       :  2;  /* Applies to IN endpoints onl */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ15. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ15_s  ALT_USB_DEV_DIEPTSIZ15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPTSIZ15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ15_OFST        0x2f0
/* The address of the ALT_USB_DEV_DIEPTSIZ15 register. */
#define ALT_USB_DEV_DIEPTSIZ15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ15_OFST))

/*
 * Register : Device IN Endpoint 15 DMA Address Register - diepdma15
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - diepdma15
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 field value from a register. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMA15.
 */
struct ALT_USB_DEV_DIEPDMA15_s
{
    uint32_t  diepdma15 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMA15. */
typedef volatile struct ALT_USB_DEV_DIEPDMA15_s  ALT_USB_DEV_DIEPDMA15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMA15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA15_OFST        0x2f4
/* The address of the ALT_USB_DEV_DIEPDMA15 register. */
#define ALT_USB_DEV_DIEPDMA15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA15_OFST))

/*
 * Register : Device IN Endpoint Transmit FIFO Status Register 15 - dtxfsts15
 * 
 * This register contains the free space information for the Device IN endpoint
 * TxFIFO.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description                   
 * :--------|:-------|:-------|:-------------------------------
 *  [15:0]  | R      | 0x2000 | IN Endpoint TxFIFO Space Avail
 *  [31:16] | ???    | 0x0    | *UNDEFINED*                   
 * 
 */
/*
 * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail
 * 
 * Indicates the amount of free space available in the Endpoint TxFIFO. Values are
 * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available
 * 16'h2: 2 words available 16'hn: n words available (where 0  n  32,768) 16'h8000:
 * 32,768 words available Others: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_MSB        15
/* The width in bits of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_WIDTH      16
/* The mask used to set the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_CLR_MSK    0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_RESET      0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DTXFSTS15.
 */
struct ALT_USB_DEV_DTXFSTS15_s
{
    const uint32_t  ineptxfspcavail : 16;  /* IN Endpoint TxFIFO Space Avail */
    uint32_t                        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DTXFSTS15. */
typedef volatile struct ALT_USB_DEV_DTXFSTS15_s  ALT_USB_DEV_DTXFSTS15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DTXFSTS15 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS15_OFST        0x2f8
/* The address of the ALT_USB_DEV_DTXFSTS15 register. */
#define ALT_USB_DEV_DTXFSTS15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS15_OFST))

/*
 * Register : Device IN Endpoint 15 DMA Buffer Address Register - diepdmab15
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - diepdmab15
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_MSB        31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_RESET      0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DIEPDMAB15.
 */
struct ALT_USB_DEV_DIEPDMAB15_s
{
    const uint32_t  diepdmab15 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB15. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB15_s  ALT_USB_DEV_DIEPDMAB15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DIEPDMAB15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB15_OFST        0x2fc
/* The address of the ALT_USB_DEV_DIEPDMAB15 register. */
#define ALT_USB_DEV_DIEPDMAB15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB15_OFST))

/*
 * Register : Device Control OUT Endpoint 0 Control Register - doepctl0
 * 
 * This is Control OUT Endpoint 0 Control register.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [1:0]   | R      | 0x0   | Maximum Packet Size
 *  [14:2]  | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | R      | 0x1   | USB Active Endpoint
 *  [16]    | ???    | 0x0   | *UNDEFINED*        
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | R      | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [29:28] | ???    | 0x0   | *UNDEFINED*        
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * The maximum packet size for control OUT endpoint 0 is thesame as what is
 * programmed in control IN Endpoint 0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 | 0x0   | 64 bytes   
 *  ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 | 0x1   | 32 bytes   
 *  ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 | 0x2   | 16 bytes   
 *  ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8  | 0x3   | 8 bytes    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
 * 
 * 64 bytes
 */
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
 * 
 * 32 bytes
 */
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
 * 
 * 16 bytes
 */
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
 * 
 * 8 bytes
 */
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL0_MPS_SET_MSK    0x00000003
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL0_MPS_CLR_MSK    0xfffffffc
/* The reset value of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL0_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * This bit is always Set to 1, indicating that a control endpoint 0 is always
 * active in all configurations and interfaces.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description          
 * :------------------------------------|:------|:----------------------
 *  ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT | 0x1   | USB Active Endpoint 0
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_USBACTEP
 * 
 * USB Active Endpoint 0
 */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT 0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_RESET      0x1
/* Extracts the ALT_USB_DEV_DOEPCTL0_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL0_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit, the core stops receiving
 * data, even If there is space in the RxFIFO to accommodate the incoming packet.
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                                    
 * :------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                    |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT   | 0x1   | The core is transmitting NAK handshakes on this
 * :                                    |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL0_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * Hardcoded to 0 for control.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description       
 * :----------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT | 0x0   | Endpoint Control 0
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPTYPE
 * 
 * Endpoint Control 0
 */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT   0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL0_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
 * check the correctness of OUT packets before transferring them to application
 * memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description        
 * :--------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL0_SNP_E_DISD | 0x0   | Snoop Mode disabled
 *  ALT_USB_DEV_DOEPCTL0_SNP_E_END  | 0x1   | Snoop Mode enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP
 * 
 * Snoop Mode disabled
 */
#define ALT_USB_DEV_DOEPCTL0_SNP_E_DISD 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP
 * 
 * Snoop Mode enabled
 */
#define ALT_USB_DEV_DOEPCTL0_SNP_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL0_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * The application can only Set this bit, and the core clears it, when a SETUP
 * token is received for this endpoint. If a NAK bit or Global OUT NAK is Set along
 * with this bit, the STALL bit takes priority. Irrespective of this bit's setting,
 * the core always responds to SETUP data packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description    
 * :-----------------------------------|:------|:----------------
 *  ALT_USB_DEV_DOEPCTL0_STALL_E_INACT | 0x0   | No Stall       
 *  ALT_USB_DEV_DOEPCTL0_STALL_E_ACT   | 0x1   | Stall Handshake
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL
 * 
 * No Stall
 */
#define ALT_USB_DEV_DOEPCTL0_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL
 * 
 * Stall Handshake
 */
#define ALT_USB_DEV_DOEPCTL0_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL0_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL0_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL0_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR | 0x0   | No action  
 *  ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR   | 0x1   | Clear NAK  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK
 * 
 * No action
 */
#define ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL0_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint.Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set bit on a Transfer Completed interrupt, or after a SETUP is
 * received on the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET | 0x0   | No action  
 *  ALT_USB_DEV_DOEPCTL0_SNAK_E_SET   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK
 * 
 * No action
 */
#define ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL0_SNAK_E_SET     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL0_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * The application cannot disable control OUT endpoint 0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT | 0x0   | No Endpoint disable
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPDIS
 * 
 * No Endpoint disable
 */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT  0x0

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL0_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates
 * that the descriptor structure and data buffer to receive data is setup. When
 * Scatter/Gather DMA mode is disabled(such as for buffer-pointer based DMA
 * mode)this bit indicates that the application has allocated the memory to start
 * receiving data from the USB.The core clears this bit before setting any of the
 * following interrupts on this endpoint:
 * 
 * SETUP Phase Done
 * 
 * Endpoint Disabled
 * 
 * Transfer Completed
 * 
 * In DMA mode, this bit must be Set for the core to transfer SETUP data packets
 * into memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description     
 * :-----------------------------------|:------|:-----------------
 *  ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT | 0x0   | No action       
 *  ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT   | 0x1   | Endpoint Enabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA
 * 
 * No action
 */
#define ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA
 * 
 * Endpoint Enabled
 */
#define ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL0_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL0.
 */
struct ALT_USB_DEV_DOEPCTL0_s
{
    const uint32_t  mps      :  2;  /* Maximum Packet Size */
    uint32_t                 : 13;  /* *UNDEFINED* */
    const uint32_t  usbactep :  1;  /* USB Active Endpoint */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  naksts   :  1;  /* NAK Status */
    const uint32_t  eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t                 :  2;  /* *UNDEFINED* */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL0. */
typedef volatile struct ALT_USB_DEV_DOEPCTL0_s  ALT_USB_DEV_DOEPCTL0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL0_OFST        0x300
/* The address of the ALT_USB_DEV_DOEPCTL0 register. */
#define ALT_USB_DEV_DOEPCTL0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL0_OFST))

/*
 * Register : Device OUT Endpoint 0 Interrupt Register - doepint0
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT0_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT0_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT0_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT0_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT0_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT0_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT0_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT0_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT0_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT0_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT0_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT0.
 */
struct ALT_USB_DEV_DOEPINT0_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT0_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT0. */
typedef volatile struct ALT_USB_DEV_DOEPINT0_s  ALT_USB_DEV_DOEPINT0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT0_OFST        0x308
/* The address of the ALT_USB_DEV_DOEPINT0 register. */
#define ALT_USB_DEV_DOEPINT0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT0_OFST))

/*
 * Register : Device OUT Endpoint 0 Transfer Size Register - doeptsiz0
 * 
 * The application must modify this register before enabling endpoint 0. Once
 * endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0
 * Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this
 * register. The application can only read this register once the core has cleared
 * the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to
 * 15. When Scatter/Gather DMA mode is enabled, this register must not be
 * programmed by the application. If the application reads this register when
 * Scatter/Gather DMA mode is enabled, the core returns all zeros.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                 
 * :--------|:-------|:------|:-----------------------------
 *  [6:0]   | RW     | 0x0   | Transfer Size               
 *  [18:7]  | ???    | 0x0   | *UNDEFINED*                 
 *  [19]    | RW     | 0x0   | Packet Count                
 *  [28:20] | ???    | 0x0   | *UNDEFINED*                 
 *  [30:29] | RW     | 0x0   | ALT_USB_DEV_DOEPTSIZ0_SUPCNT
 *  [31]    | ???    | 0x0   | *UNDEFINED*                 
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_WIDTH      7
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET_MSK    0x0000007f
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_CLR_MSK    0xffffff80
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f)

/*
 * Field : Packet Count - pktcnt
 * 
 * This field is decremented to zero after a packet is written into the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET_MSK    0x00080000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ0_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : supcnt
 * 
 * SETUP Packet Count (SUPCnt)This field specifies the number of back-to-back SETUP
 * datapackets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description
 * :----------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT   | 0x1   | 1 packet   
 *  ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT   | 0x2   | 2 packets  
 *  ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT | 0x3   | 3 packets  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
 * 
 * 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
 * 
 * 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
 * 
 * 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT 0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ0_SUPCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ0.
 */
struct ALT_USB_DEV_DOEPTSIZ0_s
{
    uint32_t  xfersize :  7;  /* Transfer Size */
    uint32_t           : 12;  /* *UNDEFINED* */
    uint32_t  pktcnt   :  1;  /* Packet Count */
    uint32_t           :  9;  /* *UNDEFINED* */
    uint32_t  supcnt   :  2;  /* ALT_USB_DEV_DOEPTSIZ0_SUPCNT */
    uint32_t           :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ0. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ0_s  ALT_USB_DEV_DOEPTSIZ0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ0_OFST        0x310
/* The address of the ALT_USB_DEV_DOEPTSIZ0 register. */
#define ALT_USB_DEV_DOEPTSIZ0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ0_OFST))

/*
 * Register : Device OUT Endpoint 0 DMA Address Register - doepdma0
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma0
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 field value from a register. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA0.
 */
struct ALT_USB_DEV_DOEPDMA0_s
{
    uint32_t  doepdma0 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA0. */
typedef volatile struct ALT_USB_DEV_DOEPDMA0_s  ALT_USB_DEV_DOEPDMA0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA0_OFST        0x314
/* The address of the ALT_USB_DEV_DOEPDMA0 register. */
#define ALT_USB_DEV_DOEPDMA0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA0_OFST))

/*
 * Register : Device OUT Endpoint 16 DMA Buffer Address Register - doepdmab0
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab0
 * 
 * Used with Scatter/Gather DMA.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB0.
 */
struct ALT_USB_DEV_DOEPDMAB0_s
{
    const uint32_t  doepdmab0 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB0. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB0_s  ALT_USB_DEV_DOEPDMAB0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB0_OFST        0x31c
/* The address of the ALT_USB_DEV_DOEPDMAB0 register. */
#define ALT_USB_DEV_DOEPDMAB0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB0_OFST))

/*
 * Register : Device Control OUT Endpoint 1 Control Register - doepctl1
 * 
 * Out Endpoint 1.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL1_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL1_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL1_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL1_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * h 1'b0'b0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL1_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL1_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL1_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL1_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL1_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL1_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL1_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL1_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL1_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL1_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL1_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL1_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL1_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL1_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL1_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL1_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL1_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL1_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL1_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL1_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL1_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL1_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL1_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL1_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL1_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL1_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL1_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL1.
 */
struct ALT_USB_DEV_DOEPCTL1_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL1. */
typedef volatile struct ALT_USB_DEV_DOEPCTL1_s  ALT_USB_DEV_DOEPCTL1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL1_OFST        0x320
/* The address of the ALT_USB_DEV_DOEPCTL1 register. */
#define ALT_USB_DEV_DOEPCTL1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL1_OFST))

/*
 * Register : Device OUT Endpoint 1 Interrupt Register - doepint1
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT1_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA  Interrupt                           
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT1_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT1_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT1_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT1_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT1_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT1_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT1_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT1_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA  Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT1_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT1_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT1.
 */
struct ALT_USB_DEV_DOEPINT1_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT1_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA  Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT1. */
typedef volatile struct ALT_USB_DEV_DOEPINT1_s  ALT_USB_DEV_DOEPINT1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT1_OFST        0x328
/* The address of the ALT_USB_DEV_DOEPINT1 register. */
#define ALT_USB_DEV_DOEPINT1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT1_OFST))

/*
 * Register : Device OUT Endpoint 1 Transfer Size Register - doeptsiz1
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ1_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ1_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ1.
 */
struct ALT_USB_DEV_DOEPTSIZ1_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ1. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ1_s  ALT_USB_DEV_DOEPTSIZ1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ1_OFST        0x330
/* The address of the ALT_USB_DEV_DOEPTSIZ1 register. */
#define ALT_USB_DEV_DOEPTSIZ1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ1_OFST))

/*
 * Register : Device OUT Endpoint 1 DMA Address Register - doepdma1
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma1
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 field value from a register. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA1.
 */
struct ALT_USB_DEV_DOEPDMA1_s
{
    uint32_t  doepdma1 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA1. */
typedef volatile struct ALT_USB_DEV_DOEPDMA1_s  ALT_USB_DEV_DOEPDMA1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA1_OFST        0x334
/* The address of the ALT_USB_DEV_DOEPDMA1 register. */
#define ALT_USB_DEV_DOEPDMA1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA1_OFST))

/*
 * Register : Device OUT Endpoint 1 DMA Buffer Address Register - doepdmab1
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab1
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB1.
 */
struct ALT_USB_DEV_DOEPDMAB1_s
{
    const uint32_t  doepdmab1 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB1. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB1_s  ALT_USB_DEV_DOEPDMAB1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB1_OFST        0x33c
/* The address of the ALT_USB_DEV_DOEPDMAB1 register. */
#define ALT_USB_DEV_DOEPDMAB1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB1_OFST))

/*
 * Register : Device Control OUT Endpoint 2 Control Register - DOEPCTL2
 * 
 * Out Endpoint 2.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL2_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL2_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL2_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL2_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL2_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL2_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL2_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL2_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL2_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL2_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL2_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL2_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL2_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL2_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL2_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL2_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL2_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL2_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL2_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL2_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL2_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL2_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL2_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL2_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL2_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL2_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL2_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL2_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL2_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL2_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL2_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL2.
 */
struct ALT_USB_DEV_DOEPCTL2_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL2. */
typedef volatile struct ALT_USB_DEV_DOEPCTL2_s  ALT_USB_DEV_DOEPCTL2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL2_OFST        0x340
/* The address of the ALT_USB_DEV_DOEPCTL2 register. */
#define ALT_USB_DEV_DOEPCTL2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL2_OFST))

/*
 * Register : Device OUT Endpoint 2 Interrupt Register - doepint2
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT2_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT2_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT2_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT2_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT2_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT2_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT2_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT2_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT2_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT2_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT2_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT2.
 */
struct ALT_USB_DEV_DOEPINT2_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT2_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT2. */
typedef volatile struct ALT_USB_DEV_DOEPINT2_s  ALT_USB_DEV_DOEPINT2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT2_OFST        0x348
/* The address of the ALT_USB_DEV_DOEPINT2 register. */
#define ALT_USB_DEV_DOEPINT2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT2_OFST))

/*
 * Register : Device OUT Endpoint 2 Transfer Size Register - doeptsiz2
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ2_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ2_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ2.
 */
struct ALT_USB_DEV_DOEPTSIZ2_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ2. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ2_s  ALT_USB_DEV_DOEPTSIZ2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ2_OFST        0x350
/* The address of the ALT_USB_DEV_DOEPTSIZ2 register. */
#define ALT_USB_DEV_DOEPTSIZ2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ2_OFST))

/*
 * Register : Device OUT Endpoint 2 DMA Address Register - doepdma2
 * 
 * DMA Addressing.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma2
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 field value from a register. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA2.
 */
struct ALT_USB_DEV_DOEPDMA2_s
{
    uint32_t  doepdma2 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA2. */
typedef volatile struct ALT_USB_DEV_DOEPDMA2_s  ALT_USB_DEV_DOEPDMA2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA2_OFST        0x354
/* The address of the ALT_USB_DEV_DOEPDMA2 register. */
#define ALT_USB_DEV_DOEPDMA2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA2_OFST))

/*
 * Register : Device OUT Endpoint 2 DMA Buffer Address Register - doepdmab2
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description                        
 * :-------|:-------|:--------|:------------------------------------
 *  [31:0] | R      | Unknown | Device IN Endpoint 1 Buffer Address
 * 
 */
/*
 * Field : Device IN Endpoint 1 Buffer Address - doepdmab2
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB2.
 */
struct ALT_USB_DEV_DOEPDMAB2_s
{
    const uint32_t  doepdmab2 : 32;  /* Device IN Endpoint 1 Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB2. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB2_s  ALT_USB_DEV_DOEPDMAB2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB2_OFST        0x35c
/* The address of the ALT_USB_DEV_DOEPDMAB2 register. */
#define ALT_USB_DEV_DOEPDMAB2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB2_OFST))

/*
 * Register : Device Control OUT Endpoint 3 Control Register - DOEPCTL3
 * 
 * Out Endpoint 3.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL3_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL3_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL3_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL3_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL3_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL3_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL3_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL3_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL3_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL3_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL3_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL3_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL3_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL3_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL3_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL3_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL3_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL3_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL3_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL3_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL3_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL3_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL3_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL3_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL3_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL3_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL3_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL3_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL3_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL3_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL3_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL3.
 */
struct ALT_USB_DEV_DOEPCTL3_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL3. */
typedef volatile struct ALT_USB_DEV_DOEPCTL3_s  ALT_USB_DEV_DOEPCTL3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL3_OFST        0x360
/* The address of the ALT_USB_DEV_DOEPCTL3 register. */
#define ALT_USB_DEV_DOEPCTL3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL3_OFST))

/*
 * Register : Device OUT Endpoint 3 Interrupt Register - doepint3
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT3_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT3_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT3_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT3_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT3_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT3_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT3_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT3_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT3_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT3_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT3_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT3.
 */
struct ALT_USB_DEV_DOEPINT3_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT3_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT3. */
typedef volatile struct ALT_USB_DEV_DOEPINT3_s  ALT_USB_DEV_DOEPINT3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT3_OFST        0x368
/* The address of the ALT_USB_DEV_DOEPINT3 register. */
#define ALT_USB_DEV_DOEPINT3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT3_OFST))

/*
 * Register : Device OUT Endpoint 3 Transfer Size Register - doeptsiz3
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ3_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ3_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ3.
 */
struct ALT_USB_DEV_DOEPTSIZ3_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ3. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ3_s  ALT_USB_DEV_DOEPTSIZ3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ3_OFST        0x370
/* The address of the ALT_USB_DEV_DOEPTSIZ3 register. */
#define ALT_USB_DEV_DOEPTSIZ3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ3_OFST))

/*
 * Register : Device OUT Endpoint 3 DMA Address Register - doepdma3
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma3
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 field value from a register. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA3.
 */
struct ALT_USB_DEV_DOEPDMA3_s
{
    uint32_t  doepdma3 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA3. */
typedef volatile struct ALT_USB_DEV_DOEPDMA3_s  ALT_USB_DEV_DOEPDMA3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA3_OFST        0x374
/* The address of the ALT_USB_DEV_DOEPDMA3 register. */
#define ALT_USB_DEV_DOEPDMA3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA3_OFST))

/*
 * Register : Device OUT Endpoint 3 DMA Buffer Address Register - doepdmab3
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab3
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB3.
 */
struct ALT_USB_DEV_DOEPDMAB3_s
{
    const uint32_t  doepdmab3 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB3. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB3_s  ALT_USB_DEV_DOEPDMAB3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB3_OFST        0x37c
/* The address of the ALT_USB_DEV_DOEPDMAB3 register. */
#define ALT_USB_DEV_DOEPDMAB3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB3_OFST))

/*
 * Register : Device Control OUT Endpoint 4 Control Register - doepctl4
 * 
 * Out Endpoint 4.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL4_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL4_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL4_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL4_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL4_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL4_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL4_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL4_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL4_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL4_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL4_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL4_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL4_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL4_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL4_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL4_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL4_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL4_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL4_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL4_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL4_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL4_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL4_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL4_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL4_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL4_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL4_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL4_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL4_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL4_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL4_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL4.
 */
struct ALT_USB_DEV_DOEPCTL4_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL4. */
typedef volatile struct ALT_USB_DEV_DOEPCTL4_s  ALT_USB_DEV_DOEPCTL4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL4_OFST        0x380
/* The address of the ALT_USB_DEV_DOEPCTL4 register. */
#define ALT_USB_DEV_DOEPCTL4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL4_OFST))

/*
 * Register : Device OUT Endpoint 4 Interrupt Register - Doepint4
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT4_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT4_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT4_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT4_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT4_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT4_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT4_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT4_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT4_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT4_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT4_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT4.
 */
struct ALT_USB_DEV_DOEPINT4_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT4_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT4. */
typedef volatile struct ALT_USB_DEV_DOEPINT4_s  ALT_USB_DEV_DOEPINT4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT4_OFST        0x388
/* The address of the ALT_USB_DEV_DOEPINT4 register. */
#define ALT_USB_DEV_DOEPINT4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT4_OFST))

/*
 * Register : Device OUT Endpoint 4 Transfer Size Register - doeptsiz4
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ4_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ4_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ4.
 */
struct ALT_USB_DEV_DOEPTSIZ4_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ4. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ4_s  ALT_USB_DEV_DOEPTSIZ4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ4_OFST        0x390
/* The address of the ALT_USB_DEV_DOEPTSIZ4 register. */
#define ALT_USB_DEV_DOEPTSIZ4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ4_OFST))

/*
 * Register : Device OUT Endpoint 4 DMA Address Register - doepdma4
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma4
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 field value from a register. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA4.
 */
struct ALT_USB_DEV_DOEPDMA4_s
{
    uint32_t  doepdma4 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA4. */
typedef volatile struct ALT_USB_DEV_DOEPDMA4_s  ALT_USB_DEV_DOEPDMA4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA4_OFST        0x394
/* The address of the ALT_USB_DEV_DOEPDMA4 register. */
#define ALT_USB_DEV_DOEPDMA4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA4_OFST))

/*
 * Register : Device OUT Endpoint 4 Buffer Address Register - doepdmab4
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab4
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB4.
 */
struct ALT_USB_DEV_DOEPDMAB4_s
{
    const uint32_t  doepdmab4 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB4. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB4_s  ALT_USB_DEV_DOEPDMAB4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB4_OFST        0x39c
/* The address of the ALT_USB_DEV_DOEPDMAB4 register. */
#define ALT_USB_DEV_DOEPDMAB4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB4_OFST))

/*
 * Register : Device Control OUT Endpoint 5 Control Register - doepctl5
 * 
 * Out Endpoint 5.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL5_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL5_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL5_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL5_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and
 * non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-
 * Scatter/Gather DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL5_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL5_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL5_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL5_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL5_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL5_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL5_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL5_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL5_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL5_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL5_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL5_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL5_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL5_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL5_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL5_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL5_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL5_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL5_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL5_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL5_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL5_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL5_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL5_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL5_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL5_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL5_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL5.
 */
struct ALT_USB_DEV_DOEPCTL5_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL5. */
typedef volatile struct ALT_USB_DEV_DOEPCTL5_s  ALT_USB_DEV_DOEPCTL5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL5_OFST        0x3a0
/* The address of the ALT_USB_DEV_DOEPCTL5 register. */
#define ALT_USB_DEV_DOEPCTL5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL5_OFST))

/*
 * Register : Device OUT Endpoint 5 Interrupt Register - doepint5
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT5_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT5_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT5_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT5_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT5_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT5_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT5_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT5_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT5_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT5_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT5_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT5.
 */
struct ALT_USB_DEV_DOEPINT5_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT5_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT5. */
typedef volatile struct ALT_USB_DEV_DOEPINT5_s  ALT_USB_DEV_DOEPINT5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT5_OFST        0x3a8
/* The address of the ALT_USB_DEV_DOEPINT5 register. */
#define ALT_USB_DEV_DOEPINT5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT5_OFST))

/*
 * Register : Device OUT Endpoint 5 Transfer Size Register - doeptsiz5
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ5_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ5_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ5.
 */
struct ALT_USB_DEV_DOEPTSIZ5_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ5. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ5_s  ALT_USB_DEV_DOEPTSIZ5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ5_OFST        0x3b0
/* The address of the ALT_USB_DEV_DOEPTSIZ5 register. */
#define ALT_USB_DEV_DOEPTSIZ5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ5_OFST))

/*
 * Register : Device OUT Endpoint 5 DMA Address Register - doepdma5
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma5
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 field value from a register. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA5.
 */
struct ALT_USB_DEV_DOEPDMA5_s
{
    uint32_t  doepdma5 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA5. */
typedef volatile struct ALT_USB_DEV_DOEPDMA5_s  ALT_USB_DEV_DOEPDMA5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA5_OFST        0x3b4
/* The address of the ALT_USB_DEV_DOEPDMA5 register. */
#define ALT_USB_DEV_DOEPDMA5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA5_OFST))

/*
 * Register : Device OUT Endpoint 5 DMA Buffer Address Register - doepdmab5
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab5
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB5.
 */
struct ALT_USB_DEV_DOEPDMAB5_s
{
    const uint32_t  doepdmab5 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB5. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB5_s  ALT_USB_DEV_DOEPDMAB5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB5_OFST        0x3bc
/* The address of the ALT_USB_DEV_DOEPDMAB5 register. */
#define ALT_USB_DEV_DOEPDMAB5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB5_OFST))

/*
 * Register : Device Control OUT Endpoint 6 Control Register - doepctl6
 * 
 * Out Endpoint 6.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL6_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL6_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL6_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL6_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0  1: DATA1This field is applicable both for Scatter/Gather DMA mode and
 * non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-
 * Scatter/Gather DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL6_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL6_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL6_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL6_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL6_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL6_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL6_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL6_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL6_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL6_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL6_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL6_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL6_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL6_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL6_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL6_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL6_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL6_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL6_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL6_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL6_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL6_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL6_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL6_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL6_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL6_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL6_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL6.
 */
struct ALT_USB_DEV_DOEPCTL6_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL6. */
typedef volatile struct ALT_USB_DEV_DOEPCTL6_s  ALT_USB_DEV_DOEPCTL6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL6_OFST        0x3c0
/* The address of the ALT_USB_DEV_DOEPCTL6 register. */
#define ALT_USB_DEV_DOEPCTL6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL6_OFST))

/*
 * Register : Device OUT Endpoint 6 Interrupt Register - doepint6
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT6_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT6_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT6_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT6_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT6_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT6_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT6_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT6_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT6_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT6_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT6_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT6.
 */
struct ALT_USB_DEV_DOEPINT6_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT6_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT6. */
typedef volatile struct ALT_USB_DEV_DOEPINT6_s  ALT_USB_DEV_DOEPINT6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT6_OFST        0x3c8
/* The address of the ALT_USB_DEV_DOEPINT6 register. */
#define ALT_USB_DEV_DOEPINT6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT6_OFST))

/*
 * Register : Device OUT Endpoint 6 Transfer Size Register - doeptsiz6
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ6_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ6_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ6.
 */
struct ALT_USB_DEV_DOEPTSIZ6_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ6. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ6_s  ALT_USB_DEV_DOEPTSIZ6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ6_OFST        0x3d0
/* The address of the ALT_USB_DEV_DOEPTSIZ6 register. */
#define ALT_USB_DEV_DOEPTSIZ6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ6_OFST))

/*
 * Register : Device OUT Endpoint 6 DMA Address Register - doepdma6
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma6
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 field value from a register. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA6.
 */
struct ALT_USB_DEV_DOEPDMA6_s
{
    uint32_t  doepdma6 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA6. */
typedef volatile struct ALT_USB_DEV_DOEPDMA6_s  ALT_USB_DEV_DOEPDMA6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA6_OFST        0x3d4
/* The address of the ALT_USB_DEV_DOEPDMA6 register. */
#define ALT_USB_DEV_DOEPDMA6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA6_OFST))

/*
 * Register : Device OUT Endpoint 6 DMA Buffer Address Register - doepdmab6
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab6
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB6.
 */
struct ALT_USB_DEV_DOEPDMAB6_s
{
    const uint32_t  doepdmab6 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB6. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB6_s  ALT_USB_DEV_DOEPDMAB6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB6_OFST        0x3dc
/* The address of the ALT_USB_DEV_DOEPDMAB6 register. */
#define ALT_USB_DEV_DOEPDMAB6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB6_OFST))

/*
 * Register : Device Control OUT Endpoint 7 Control Register - doepctl7
 * 
 * Endpoint_number: 7
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | ???    | 0x0   | *UNDEFINED*        
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | RW     | 0x0   | TxFIFO Number      
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL7_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL7_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL7_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL7_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and
 * non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-
 * Scatter/Gather DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL7_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL7_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL7_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL7_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL7_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL7_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL7_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL7_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL7_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL7_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL7_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL7_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL7_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL7_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL7_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL7_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : TxFIFO Number - txfnum
 * 
 * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic
 * endpoints must map this to the corresponding Periodic TxFIFO number.
 * 
 * 4'h0: Non-Periodic TxFIFO
 * 
 * Others: Specified Periodic TxFIFO.number
 * 
 * An interrupt IN endpoint can be configured as a non-periodic endpoint for
 * applications such as mass storage. The core treats an IN endpoint as a non-
 * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN
 * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
 * Dedicated FIFO Operation-these bits specify the FIFO number associated with this
 * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
 * This field is valid only for IN endpoints.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_MSB        25
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_WIDTH      4
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_TXFNUM register field value. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_SET_MSK    0x03c00000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_TXFNUM register field value. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_CLR_MSK    0xfc3fffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_TXFNUM field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DOEPCTL7_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL7_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL7_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID     
 *  ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END  | 0x1   | Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID
 * 
 * Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL7_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL7_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL7_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL7_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL7.
 */
struct ALT_USB_DEV_DOEPCTL7_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t                 :  1;  /* *UNDEFINED* */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t        txfnum   :  4;  /* TxFIFO Number */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL7. */
typedef volatile struct ALT_USB_DEV_DOEPCTL7_s  ALT_USB_DEV_DOEPCTL7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL7_OFST        0x3e0
/* The address of the ALT_USB_DEV_DOEPCTL7 register. */
#define ALT_USB_DEV_DOEPCTL7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL7_OFST))

/*
 * Register : Device OUT Endpoint 7 Interrupt Register - doepint7
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT7_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT7_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT7_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT7_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT7_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT7_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT7_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT7_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT7_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT7_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT7_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT7.
 */
struct ALT_USB_DEV_DOEPINT7_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT7_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT7. */
typedef volatile struct ALT_USB_DEV_DOEPINT7_s  ALT_USB_DEV_DOEPINT7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT7_OFST        0x3e8
/* The address of the ALT_USB_DEV_DOEPINT7 register. */
#define ALT_USB_DEV_DOEPINT7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT7_OFST))

/*
 * Register : Device OUT Endpoint 7 Transfer Size Register - doeptsiz7
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ7_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ7_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ7.
 */
struct ALT_USB_DEV_DOEPTSIZ7_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ7. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ7_s  ALT_USB_DEV_DOEPTSIZ7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ7_OFST        0x3f0
/* The address of the ALT_USB_DEV_DOEPTSIZ7 register. */
#define ALT_USB_DEV_DOEPTSIZ7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ7_OFST))

/*
 * Register : Device OUT Endpoint 7 DMA Address Register - doepdma7
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma7
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 field value from a register. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA7.
 */
struct ALT_USB_DEV_DOEPDMA7_s
{
    uint32_t  doepdma7 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA7. */
typedef volatile struct ALT_USB_DEV_DOEPDMA7_s  ALT_USB_DEV_DOEPDMA7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA7_OFST        0x3f4
/* The address of the ALT_USB_DEV_DOEPDMA7 register. */
#define ALT_USB_DEV_DOEPDMA7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA7_OFST))

/*
 * Register : Device OUT Endpoint 7 Buffer Address - doepdmab7
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab7
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB7.
 */
struct ALT_USB_DEV_DOEPDMAB7_s
{
    const uint32_t  doepdmab7 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB7. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB7_s  ALT_USB_DEV_DOEPDMAB7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB7_OFST        0x3fc
/* The address of the ALT_USB_DEV_DOEPDMAB7 register. */
#define ALT_USB_DEV_DOEPDMAB7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB7_OFST))

/*
 * Register : Device Control OUT Endpoint 8 Control Register - doepctl8
 * 
 * Out Endpoint 8.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL8_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL8_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL8_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL8_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL8_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL8_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL8_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL8_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL8_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL8_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL8_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL8_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL8_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL8_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL8_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL8_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL8_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL8_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL8_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL8_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL8_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL8_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL8_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL8_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL8_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL8_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL8_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL8_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL8_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL8_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL8_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL8.
 */
struct ALT_USB_DEV_DOEPCTL8_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL8. */
typedef volatile struct ALT_USB_DEV_DOEPCTL8_s  ALT_USB_DEV_DOEPCTL8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL8_OFST        0x400
/* The address of the ALT_USB_DEV_DOEPCTL8 register. */
#define ALT_USB_DEV_DOEPCTL8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL8_OFST))

/*
 * Register : Device OUT Endpoint 8 Interrupt Register - doepint8
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT8_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT8_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT8_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT8_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT8_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT8_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT8_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT8_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT8_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT8_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT8_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT8.
 */
struct ALT_USB_DEV_DOEPINT8_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT8_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT8. */
typedef volatile struct ALT_USB_DEV_DOEPINT8_s  ALT_USB_DEV_DOEPINT8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT8_OFST        0x408
/* The address of the ALT_USB_DEV_DOEPINT8 register. */
#define ALT_USB_DEV_DOEPINT8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT8_OFST))

/*
 * Register : Device OUT Endpoint 8 Transfer Size Register - doeptsiz8
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ8_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ8_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ8.
 */
struct ALT_USB_DEV_DOEPTSIZ8_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ8. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ8_s  ALT_USB_DEV_DOEPTSIZ8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ8_OFST        0x410
/* The address of the ALT_USB_DEV_DOEPTSIZ8 register. */
#define ALT_USB_DEV_DOEPTSIZ8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ8_OFST))

/*
 * Register : Device OUT Endpoint 8 DMA Address Register - doepdma8
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma8
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 field value from a register. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA8.
 */
struct ALT_USB_DEV_DOEPDMA8_s
{
    uint32_t  doepdma8 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA8. */
typedef volatile struct ALT_USB_DEV_DOEPDMA8_s  ALT_USB_DEV_DOEPDMA8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA8_OFST        0x414
/* The address of the ALT_USB_DEV_DOEPDMA8 register. */
#define ALT_USB_DEV_DOEPDMA8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA8_OFST))

/*
 * Register : Device OUT Endpoint 8 DMA Buffer Address Register - doepdmab8
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab8
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB8.
 */
struct ALT_USB_DEV_DOEPDMAB8_s
{
    const uint32_t  doepdmab8 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB8. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB8_s  ALT_USB_DEV_DOEPDMAB8_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB8_OFST        0x41c
/* The address of the ALT_USB_DEV_DOEPDMAB8 register. */
#define ALT_USB_DEV_DOEPDMAB8_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB8_OFST))

/*
 * Register : Device Control OUT Endpoint 9 Control Register - doepctl9
 * 
 * Out Endpoint 9.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL9_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL9_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL9_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL9_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                 
 * :----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL9_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL9_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL9_DPID_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL9_DPID_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL9_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL9_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL9_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                    
 * :-------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                     |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                     |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK       0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL9_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description
 * :------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL           0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK          0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP      0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL9_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL9_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL9_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL9_SNP_E_DIS  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL9_SNP_E_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL9_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL9_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL9_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL9_STALL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL9_STALL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL9_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL9_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL9_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description 
 * :----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL9_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL9_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL9_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description           
 * :-------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL9_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL9_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description             
 * :-----------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL9_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL9.
 */
struct ALT_USB_DEV_DOEPCTL9_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL9. */
typedef volatile struct ALT_USB_DEV_DOEPCTL9_s  ALT_USB_DEV_DOEPCTL9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL9_OFST        0x420
/* The address of the ALT_USB_DEV_DOEPCTL9 register. */
#define ALT_USB_DEV_DOEPCTL9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL9_OFST))

/*
 * Register : Device OUT Endpoint 9 Interrupt Register - doepint9
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT9_AHBERR              
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT9_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT9_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT9_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT9_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT9_SETUP_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT9_SETUP_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT9_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT9_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                 
 * :-----------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                               
 * :-----------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description        
 * :---------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT9_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description      
 * :-------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT9_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description  
 * :---------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT9.
 */
struct ALT_USB_DEV_DOEPINT9_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT9_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT9. */
typedef volatile struct ALT_USB_DEV_DOEPINT9_s  ALT_USB_DEV_DOEPINT9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT9_OFST        0x428
/* The address of the ALT_USB_DEV_DOEPINT9 register. */
#define ALT_USB_DEV_DOEPINT9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT9_OFST))

/*
 * Register : Device OUT Endpoint 9 Transfer Size Register - doeptsiz9
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ9_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description       
 * :-----------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0        0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1    0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2    0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3    0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ9_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ9.
 */
struct ALT_USB_DEV_DOEPTSIZ9_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ9. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ9_s  ALT_USB_DEV_DOEPTSIZ9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ9_OFST        0x430
/* The address of the ALT_USB_DEV_DOEPTSIZ9 register. */
#define ALT_USB_DEV_DOEPTSIZ9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ9_OFST))

/*
 * Register : Device OUT Endpoint 9 DMA Address Register - doepdma9
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma9
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 field value from a register. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA9.
 */
struct ALT_USB_DEV_DOEPDMA9_s
{
    uint32_t  doepdma9 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA9. */
typedef volatile struct ALT_USB_DEV_DOEPDMA9_s  ALT_USB_DEV_DOEPDMA9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA9_OFST        0x434
/* The address of the ALT_USB_DEV_DOEPDMA9 register. */
#define ALT_USB_DEV_DOEPDMA9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA9_OFST))

/*
 * Register : Device OUT Endpoint 9 DMA Buffer Address Register - doepdmab9
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab9
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB9.
 */
struct ALT_USB_DEV_DOEPDMAB9_s
{
    const uint32_t  doepdmab9 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB9. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB9_s  ALT_USB_DEV_DOEPDMAB9_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB9_OFST        0x43c
/* The address of the ALT_USB_DEV_DOEPDMAB9 register. */
#define ALT_USB_DEV_DOEPDMAB9_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB9_OFST))

/*
 * Register : Device Control OUT Endpoint 10 Control Register - doepctl10
 * 
 * Out Endpoint 10.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL10_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL10_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL10_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL10_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL10_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL10_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL10_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL10_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL10_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL10_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL10_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL10_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL10_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description       
 * :--------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL10_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL10_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL10_SNP_E_DIS 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL10_SNP_E_EN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL10_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL10_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL10_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL10_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL10_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL10_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL10_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL10_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL10_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL10_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL10_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL10_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL10_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL10_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL10.
 */
struct ALT_USB_DEV_DOEPCTL10_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL10. */
typedef volatile struct ALT_USB_DEV_DOEPCTL10_s  ALT_USB_DEV_DOEPCTL10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL10_OFST        0x440
/* The address of the ALT_USB_DEV_DOEPCTL10 register. */
#define ALT_USB_DEV_DOEPCTL10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL10_OFST))

/*
 * Register : Device OUT Endpoint 10 Interrupt Register - doepint10
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT10_AHBERR             
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT10_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT10_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT10_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT10_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT10_SETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT10_SETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT10_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT10_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description        
 * :----------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT10_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT10_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT10.
 */
struct ALT_USB_DEV_DOEPINT10_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT10_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT10. */
typedef volatile struct ALT_USB_DEV_DOEPINT10_s  ALT_USB_DEV_DOEPINT10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT10_OFST        0x448
/* The address of the ALT_USB_DEV_DOEPINT10 register. */
#define ALT_USB_DEV_DOEPINT10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT10_OFST))

/*
 * Register : Device OUT Endpoint 10 Transfer Size Register - doeptsiz10
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ10_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description       
 * :------------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0       0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ10_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ10.
 */
struct ALT_USB_DEV_DOEPTSIZ10_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ10. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ10_s  ALT_USB_DEV_DOEPTSIZ10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ10_OFST        0x450
/* The address of the ALT_USB_DEV_DOEPTSIZ10 register. */
#define ALT_USB_DEV_DOEPTSIZ10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ10_OFST))

/*
 * Register : Device OUT Endpoint 10 DMA Address Register - doepdma10
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma10
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 field value from a register. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA10.
 */
struct ALT_USB_DEV_DOEPDMA10_s
{
    uint32_t  doepdma10 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA10. */
typedef volatile struct ALT_USB_DEV_DOEPDMA10_s  ALT_USB_DEV_DOEPDMA10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA10_OFST        0x454
/* The address of the ALT_USB_DEV_DOEPDMA10 register. */
#define ALT_USB_DEV_DOEPDMA10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA10_OFST))

/*
 * Register : Device OUT Endpoint 10 DMA Buffer Address Register - doepdmab10
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab10
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB10.
 */
struct ALT_USB_DEV_DOEPDMAB10_s
{
    const uint32_t  doepdmab10 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB10. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB10_s  ALT_USB_DEV_DOEPDMAB10_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB10_OFST        0x45c
/* The address of the ALT_USB_DEV_DOEPDMAB10 register. */
#define ALT_USB_DEV_DOEPDMAB10_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB10_OFST))

/*
 * Register : Device Control OUT Endpoint 11 Control Register - doepctl11
 * 
 * Out Endpoint 11.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL11_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL11_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL11_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL11_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL11_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL11_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL11_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL11_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL11_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL11_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL11_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL11_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL11_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description       
 * :--------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL11_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL11_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL11_SNP_E_DIS 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL11_SNP_E_EN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL11_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL11_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL11_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL11_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL11_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL11_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL11_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL11_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL11_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL11_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL11_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL11_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL11_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL11_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL11.
 */
struct ALT_USB_DEV_DOEPCTL11_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL11. */
typedef volatile struct ALT_USB_DEV_DOEPCTL11_s  ALT_USB_DEV_DOEPCTL11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL11_OFST        0x460
/* The address of the ALT_USB_DEV_DOEPCTL11 register. */
#define ALT_USB_DEV_DOEPCTL11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL11_OFST))

/*
 * Register : Device OUT Endpoint 11 Interrupt Register - doepint11
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT11_AHBERR             
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT11_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT11_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT11_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT11_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT11_SETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT11_SETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT11_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT11_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description        
 * :----------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT11_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT11_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT11.
 */
struct ALT_USB_DEV_DOEPINT11_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT11_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT11. */
typedef volatile struct ALT_USB_DEV_DOEPINT11_s  ALT_USB_DEV_DOEPINT11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT11_OFST        0x468
/* The address of the ALT_USB_DEV_DOEPINT11 register. */
#define ALT_USB_DEV_DOEPINT11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT11_OFST))

/*
 * Register : Device OUT Endpoint 11 Transfer Size Register - doeptsiz11
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ11_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description       
 * :------------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0       0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ11_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ11.
 */
struct ALT_USB_DEV_DOEPTSIZ11_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ11. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ11_s  ALT_USB_DEV_DOEPTSIZ11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ11_OFST        0x470
/* The address of the ALT_USB_DEV_DOEPTSIZ11 register. */
#define ALT_USB_DEV_DOEPTSIZ11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ11_OFST))

/*
 * Register : Device OUT Endpoint 11 DMA Address Register - doepdma11
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma11
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 field value from a register. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA11.
 */
struct ALT_USB_DEV_DOEPDMA11_s
{
    uint32_t  doepdma11 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA11. */
typedef volatile struct ALT_USB_DEV_DOEPDMA11_s  ALT_USB_DEV_DOEPDMA11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA11_OFST        0x474
/* The address of the ALT_USB_DEV_DOEPDMA11 register. */
#define ALT_USB_DEV_DOEPDMA11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA11_OFST))

/*
 * Register : Device OUT Endpoint 11 DMA Buffer Address Register - doepdmab11
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab11
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB11.
 */
struct ALT_USB_DEV_DOEPDMAB11_s
{
    const uint32_t  doepdmab11 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB11. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB11_s  ALT_USB_DEV_DOEPDMAB11_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB11_OFST        0x47c
/* The address of the ALT_USB_DEV_DOEPDMAB11 register. */
#define ALT_USB_DEV_DOEPDMAB11_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB11_OFST))

/*
 * Register : Device Control OUT Endpoint 12 Control Register - doepctl12
 * 
 * Out Endpoint 12.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL12_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL12_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL12_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL12_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL12_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL12_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL12_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL12_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL12_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL12_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL12_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL12_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL12_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description       
 * :--------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL12_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL12_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL12_SNP_E_DIS 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL12_SNP_E_EN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL12_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL12_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL12_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL12_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL12_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL12_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL12_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL12_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL12_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL12_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL12_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL12_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL12_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL12_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL12.
 */
struct ALT_USB_DEV_DOEPCTL12_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL12. */
typedef volatile struct ALT_USB_DEV_DOEPCTL12_s  ALT_USB_DEV_DOEPCTL12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL12_OFST        0x480
/* The address of the ALT_USB_DEV_DOEPCTL12 register. */
#define ALT_USB_DEV_DOEPCTL12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL12_OFST))

/*
 * Register : Device OUT Endpoint 12 Interrupt Register - doepint12
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT12_AHBERR             
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT12_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT12_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT12_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT12_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT12_SETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT12_SETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT12_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT12_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description        
 * :----------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT12_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT12_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT12.
 */
struct ALT_USB_DEV_DOEPINT12_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT12_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT12. */
typedef volatile struct ALT_USB_DEV_DOEPINT12_s  ALT_USB_DEV_DOEPINT12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT12_OFST        0x488
/* The address of the ALT_USB_DEV_DOEPINT12 register. */
#define ALT_USB_DEV_DOEPINT12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT12_OFST))

/*
 * Register : Device OUT Endpoint 12 Transfer Size Register - doeptsiz12
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ12_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description       
 * :------------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0       0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ12_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ12.
 */
struct ALT_USB_DEV_DOEPTSIZ12_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ12. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ12_s  ALT_USB_DEV_DOEPTSIZ12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ12_OFST        0x490
/* The address of the ALT_USB_DEV_DOEPTSIZ12 register. */
#define ALT_USB_DEV_DOEPTSIZ12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ12_OFST))

/*
 * Register : Device OUT Endpoint 12 DMA Address Register - doepdma12
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma12
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 field value from a register. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA12.
 */
struct ALT_USB_DEV_DOEPDMA12_s
{
    uint32_t  doepdma12 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA12. */
typedef volatile struct ALT_USB_DEV_DOEPDMA12_s  ALT_USB_DEV_DOEPDMA12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA12_OFST        0x494
/* The address of the ALT_USB_DEV_DOEPDMA12 register. */
#define ALT_USB_DEV_DOEPDMA12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA12_OFST))

/*
 * Register : Device OUT Endpoint 12 DMA Buffer Address Register - doepdmab12
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab12
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB12.
 */
struct ALT_USB_DEV_DOEPDMAB12_s
{
    const uint32_t  doepdmab12 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB12. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB12_s  ALT_USB_DEV_DOEPDMAB12_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB12_OFST        0x49c
/* The address of the ALT_USB_DEV_DOEPDMAB12 register. */
#define ALT_USB_DEV_DOEPDMAB12_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB12_OFST))

/*
 * Register : Device Control OUT Endpoint 13 Control Register - doepctl13
 * 
 * Out Endpoint 13.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL13_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL13_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL13_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL13_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL13_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL13_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL13_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL13_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL13_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL13_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL13_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL13_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL13_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description       
 * :--------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL13_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL13_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL13_SNP_E_DIS 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL13_SNP_E_EN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL13_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL13_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL13_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL13_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL13_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL13_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL13_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL13_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL13_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL13_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL13_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL13_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL13_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL13_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL13.
 */
struct ALT_USB_DEV_DOEPCTL13_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL13. */
typedef volatile struct ALT_USB_DEV_DOEPCTL13_s  ALT_USB_DEV_DOEPCTL13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL13_OFST        0x4a0
/* The address of the ALT_USB_DEV_DOEPCTL13 register. */
#define ALT_USB_DEV_DOEPCTL13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL13_OFST))

/*
 * Register : Device OUT Endpoint 13 Interrupt Register - doepint13
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT13_AHBERR             
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT13_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT13_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT13_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT13_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT13_SETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT13_SETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT13_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT13_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description        
 * :----------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT13_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT13_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT13.
 */
struct ALT_USB_DEV_DOEPINT13_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT13_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT13. */
typedef volatile struct ALT_USB_DEV_DOEPINT13_s  ALT_USB_DEV_DOEPINT13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT13_OFST        0x4a8
/* The address of the ALT_USB_DEV_DOEPINT13 register. */
#define ALT_USB_DEV_DOEPINT13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT13_OFST))

/*
 * Register : Device OUT Endpoint 13 Transfer Size Register - doeptsiz13
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ13_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description       
 * :------------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0       0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ13_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ13.
 */
struct ALT_USB_DEV_DOEPTSIZ13_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ13. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ13_s  ALT_USB_DEV_DOEPTSIZ13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ13_OFST        0x4b0
/* The address of the ALT_USB_DEV_DOEPTSIZ13 register. */
#define ALT_USB_DEV_DOEPTSIZ13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ13_OFST))

/*
 * Register : Device OUT Endpoint 13 DMA Address Register - doepdma13
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma13
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 field value from a register. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA13.
 */
struct ALT_USB_DEV_DOEPDMA13_s
{
    uint32_t  doepdma13 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA13. */
typedef volatile struct ALT_USB_DEV_DOEPDMA13_s  ALT_USB_DEV_DOEPDMA13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA13_OFST        0x4b4
/* The address of the ALT_USB_DEV_DOEPDMA13 register. */
#define ALT_USB_DEV_DOEPDMA13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA13_OFST))

/*
 * Register : Device OUT Endpoint 13 DMA Buffer Address Register - doepdmab13
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab13
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB13.
 */
struct ALT_USB_DEV_DOEPDMAB13_s
{
    const uint32_t  doepdmab13 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB13. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB13_s  ALT_USB_DEV_DOEPDMAB13_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB13_OFST        0x4bc
/* The address of the ALT_USB_DEV_DOEPDMAB13 register. */
#define ALT_USB_DEV_DOEPDMAB13_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB13_OFST))

/*
 * Register : Device Control OUT Endpoint 14 Control Register - doepctl14
 * 
 * Out Endpoint 14.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL14_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL14_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL14_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL14_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL14_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL14_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL14_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL14_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL14_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL14_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL14_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL14_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL14_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description       
 * :--------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL14_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL14_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL14_SNP_E_DIS 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL14_SNP_E_EN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL14_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL14_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL14_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL14_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL14_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL14_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL14_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL14_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL14_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL14_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL14_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL14_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL14_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL14_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL14.
 */
struct ALT_USB_DEV_DOEPCTL14_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL14. */
typedef volatile struct ALT_USB_DEV_DOEPCTL14_s  ALT_USB_DEV_DOEPCTL14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL14_OFST        0x4c0
/* The address of the ALT_USB_DEV_DOEPCTL14 register. */
#define ALT_USB_DEV_DOEPCTL14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL14_OFST))

/*
 * Register : Device OUT Endpoint 14 Interrupt Register - doepint14
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT14_AHBERR             
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT14_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT14_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT14_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT14_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT14_SETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT14_SETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT14_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT14_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description        
 * :----------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT14_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT14_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT14.
 */
struct ALT_USB_DEV_DOEPINT14_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT14_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT14. */
typedef volatile struct ALT_USB_DEV_DOEPINT14_s  ALT_USB_DEV_DOEPINT14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT14_OFST        0x4c8
/* The address of the ALT_USB_DEV_DOEPINT14 register. */
#define ALT_USB_DEV_DOEPINT14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT14_OFST))

/*
 * Register : Device OUT Endpoint 14 Transfer Size Register - doeptsiz14
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ14_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description       
 * :------------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0       0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ14_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ14.
 */
struct ALT_USB_DEV_DOEPTSIZ14_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ14. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ14_s  ALT_USB_DEV_DOEPTSIZ14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ14_OFST        0x4d0
/* The address of the ALT_USB_DEV_DOEPTSIZ14 register. */
#define ALT_USB_DEV_DOEPTSIZ14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ14_OFST))

/*
 * Register : Device OUT Endpoint 14 DMA Address Register - doepdma14
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma14
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 field value from a register. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA14.
 */
struct ALT_USB_DEV_DOEPDMA14_s
{
    uint32_t  doepdma14 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA14. */
typedef volatile struct ALT_USB_DEV_DOEPDMA14_s  ALT_USB_DEV_DOEPDMA14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA14_OFST        0x4d4
/* The address of the ALT_USB_DEV_DOEPDMA14 register. */
#define ALT_USB_DEV_DOEPDMA14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA14_OFST))

/*
 * Register : Device OUT Endpoint 14 DMA Buffer Address Register - doepdmab14
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab14
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB14.
 */
struct ALT_USB_DEV_DOEPDMAB14_s
{
    const uint32_t  doepdmab14 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB14. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB14_s  ALT_USB_DEV_DOEPDMAB14_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB14_OFST        0x4dc
/* The address of the ALT_USB_DEV_DOEPDMAB14 register. */
#define ALT_USB_DEV_DOEPDMAB14_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB14_OFST))

/*
 * Register : Device Control OUT Endpoint 15 Control Register - doepctl15
 * 
 * Out Endpoint 15.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description        
 * :--------|:-------|:------|:--------------------
 *  [10:0]  | RW     | 0x0   | Maximum Packet Size
 *  [14:11] | ???    | 0x0   | *UNDEFINED*        
 *  [15]    | RW     | 0x0   | USB Active Endpoint
 *  [16]    | R      | 0x0   | Endpoint Data PID  
 *  [17]    | R      | 0x0   | NAK Status         
 *  [19:18] | RW     | 0x0   | Endpoint Type      
 *  [20]    | RW     | 0x0   | Snoop Mode         
 *  [21]    | R      | 0x0   | STALL Handshake    
 *  [25:22] | ???    | 0x0   | *UNDEFINED*        
 *  [26]    | W      | 0x0   | Clear NAK          
 *  [27]    | W      | 0x0   | Set NAK            
 *  [28]    | W      | 0x0   | Set DATA0 PID      
 *  [29]    | W      | 0x0   | Set DATA1 PID      
 *  [30]    | R      | 0x0   | Endpoint Disable   
 *  [31]    | R      | 0x0   | Endpoint Enable    
 * 
 */
/*
 * Field : Maximum Packet Size - mps
 * 
 * Applies to IN and OUT endpoints. The application must program this field with
 * the maximum packet size for the current logical endpoint. This value is in
 * bytes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_MSB        10
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_WIDTH      11
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL15_MPS_SET_MSK    0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL15_MPS_CLR_MSK    0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL15_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff)

/*
 * Field : USB Active Endpoint - usbactep
 * 
 * Indicates whether this endpoint is active in the current configuration and
 * interface. The core clears this bit for all endpoints (other than EP 0) after
 * detecting a USB reset. After receiving the SetConfiguration and SetInterface
 * commands, the application must program endpoint registers accordingly and set
 * this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD | 0x0   | Not Active         
 *  ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END  | 0x1   | USB Active Endpoint
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP
 * 
 * Not Active
 */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP
 * 
 * USB Active Endpoint
 */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_MSB        15
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET_MSK    0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_CLR_MSK    0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL15_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Endpoint Data PID - dpid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the
 * packet to be received or transmitted on this endpoint. The application must
 * program the PID of the first packet to be received or transmitted on this
 * endpoint, after the endpoint is activated. The applications use the SetD1PID and
 * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
 * 
 * 0: DATA0
 * 
 * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-
 * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather
 * DMA mode:
 * 
 * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame
 * number in which the core transmits/receives isochronous data for this endpoint.
 * The application must program the even/odd (micro) frame number in which it
 * intends to transmit/receive isochronous data for this endpoint using the
 * SetEvnFr and SetOddFr fields in this register.
 * 
 * 0: Even (micro)frame
 * 
 * 1: Odd (micro)frame
 * 
 * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
 * number in which to send data is provided in the transmit descriptor structure.
 * The frame in which data is received is updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                 
 * :-----------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPCTL15_DPID_E_INACT | 0x0   | Endpoint Data PID not active
 *  ALT_USB_DEV_DOEPCTL15_DPID_E_ACT   | 0x1   | Endpoint Data PID active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID
 * 
 * Endpoint Data PID not active
 */
#define ALT_USB_DEV_DOEPCTL15_DPID_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID
 * 
 * Endpoint Data PID active
 */
#define ALT_USB_DEV_DOEPCTL15_DPID_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_MSB        16
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL15_DPID_SET_MSK    0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL15_DPID_CLR_MSK    0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL15_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : NAK Status - naksts
 * 
 * When either the application or the core sets this bit:
 * 
 * * The core stops receiving any data on an OUT endpoint, even if there is space
 *   in the RxFIFO to accommodate the incoming packet.
 * 
 * * for non-isochronous IN endpoints: The core stops transmitting any data on an
 *   IN endpoint, even if there data is available in the TxFIFO.
 * 
 * * for isochronous IN endpoints: The core sends out a zero-length data packet,
 *   even if there data is available in the TxFIFO.
 * 
 * Irrespective of this bit's setting, the core always responds to SETUP data
 * packets with an ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                    
 * :--------------------------------------|:------|:------------------------------------------------
 *  ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK | 0x0   | The core is transmitting non-NAK handshakes    
 * :                                      |       | based on the FIFO status                       
 *  ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK    | 0x1   | The core is transmitting NAK handshakes on this
 * :                                      |       | endpoint                                       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS
 * 
 * The core is transmitting non-NAK handshakes based on the FIFO status
 */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS
 * 
 * The core is transmitting NAK handshakes on this endpoint
 */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_MSB        17
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET_MSK    0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL15_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Endpoint Type - eptype
 * 
 * This is the transfer type supported by this logical endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description
 * :-------------------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL         | 0x0   | Control    
 *  ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1   | Isochronous
 *  ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK        | 0x2   | Bulk       
 *  ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP    | 0x3   | Interrupt  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
 * 
 * Control
 */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL          0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
 * 
 * Isochronous
 */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS  0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
 * 
 * Bulk
 */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK         0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
 * 
 * Interrupt
 */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP     0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_MSB        19
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET_MSK    0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_CLR_MSK    0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL15_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)

/*
 * Field : Snoop Mode - snp
 * 
 * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode.
 * In Snoop mode, the core does not check the correctness of OUT packets before
 * transferring them to application memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description       
 * :--------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPCTL15_SNP_E_DIS | 0x0   | Disable Snoop Mode
 *  ALT_USB_DEV_DOEPCTL15_SNP_E_EN  | 0x1   | Enable Snoop Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP
 * 
 * Disable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL15_SNP_E_DIS 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP
 * 
 * Enable Snoop Mode
 */
#define ALT_USB_DEV_DOEPCTL15_SNP_E_EN  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_MSB        20
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNP_SET_MSK    0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNP_CLR_MSK    0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL15_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SNP_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : STALL Handshake - stall
 * 
 * Applies to non-control, non-isochronous IN and OUT endpoints only. The
 * application sets this bit to stall all tokens from the USB host to this
 * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set
 * along with this bit, the STALL bit takes priority. Only the application can
 * clear this bit, never the core. Applies to control endpoints only. The
 * application can only set this bit, and the core clears it, when a SETUP token is
 * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
 * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective
 * of this bit's setting, the core always responds to SETUP data packets with an
 * ACK handshake.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPCTL15_STALL_E_INACT | 0x0   | STALL All Tokens not active
 *  ALT_USB_DEV_DOEPCTL15_STALL_E_ACT   | 0x1   | STALL All Tokens active    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL
 * 
 * STALL All Tokens not active
 */
#define ALT_USB_DEV_DOEPCTL15_STALL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL
 * 
 * STALL All Tokens active
 */
#define ALT_USB_DEV_DOEPCTL15_STALL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_MSB        21
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL15_STALL_SET_MSK    0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL15_STALL_CLR_MSK    0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL15_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Clear NAK - cnak
 * 
 * A write to this bit clears the NAK bit for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description 
 * :-----------------------------------|:------|:-------------
 *  ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT | 0x0   | No Clear NAK
 *  ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT   | 0x1   | Clear NAK   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK
 * 
 * No Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK
 * 
 * Clear NAK
 */
#define ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_MSB        26
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_SET_MSK    0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_CLR_MSK    0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL15_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Set NAK - snak
 * 
 * A write to this bit sets the NAK bit for the endpoint. Using this bit, the
 * application can control the transmission of NAK handshakes on an endpoint. The
 * core can also Set this bit for an endpoint after a SETUP packet is received on
 * that endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description
 * :-----------------------------------|:------|:------------
 *  ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT | 0x0   | No Set NAK 
 *  ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT   | 0x1   | Set NAK    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK
 * 
 * No Set NAK
 */
#define ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK
 * 
 * Set NAK
 */
#define ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_MSB        27
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_SET_MSK    0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL15_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Set DATA0 PID - setd0pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA0. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In
 * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to
 * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
 * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA
 * mode is enabled, this field is reserved. The frame number in which to send data
 * is in the transmit descriptor structure. The frame in which to receive data is
 * updated in receive descriptor structure.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD | 0x0   | Disables Set DATA0 PID             
 *  ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END  | 0x1   | Enables Endpoint Data PID to DATA0)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID
 * 
 * Disables Set DATA0 PID
 */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID
 * 
 * Enables Endpoint Data PID to DATA0)
 */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET_MSK    0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_CLR_MSK    0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL15_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Set DATA1 PID - setd1pid
 * 
 * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets
 * the Endpoint Data PID (DPID) field in this register to DATA1. This field is
 * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
 * 
 * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints
 * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to
 * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description           
 * :--------------------------------------|:------|:-----------------------
 *  ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD | 0x0   | Disables Set DATA1 PID
 *  ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END  | 0x1   | Enables Set DATA1 PID 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID
 * 
 * Disables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID
 * 
 * Enables Set DATA1 PID
 */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_MSB        29
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET_MSK    0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_CLR_MSK    0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL15_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Endpoint Disable - epdis
 * 
 * Applies to IN and OUT endpoints. The application sets this bit to stop
 * transmitting/receiving data on an endpoint, even before the transfer for that
 * endpoint is complete. The application must wait for the Endpoint Disabled
 * interrupt before treating the endpoint as disabled. The core clears this bit
 * before setting the Endpoint Disabled interrupt. The application must set this
 * bit only if Endpoint Enable is already set for this endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT | 0x0   | No Endpoint Disable
 *  ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT   | 0x1   | Endpoint Disable   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS
 * 
 * No Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS
 * 
 * Endpoint Disable
 */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_SET_MSK    0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_CLR_MSK    0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL15_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Endpoint Enable - epena
 * 
 * Applies to IN and OUT endpoints.
 * 
 * * When Scatter/Gather DMA mode is enabled,
 * 
 * * for IN endpoints this bit indicates that the descriptor structure and data
 *   buffer with data ready to transmit is setup.
 * 
 * * for OUT endpoint it indicates that the descriptor structure and data buffer to
 *   receive data is setup.
 * 
 * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA
 *   mode:
 * 
 * * for IN endpoints, this bit indicates that data is ready to be transmitted on
 *   the endpoint.
 * 
 * * for OUT endpoints, this bit indicates that the application has allocated the
 *   memory to start receiving data from the USB.
 * 
 * * The core clears this bit before setting any of the following interrupts on
 *   this endpoint:
 * 
 * * SETUP Phase Done
 * 
 * * Endpoint Disabled
 * 
 * * Transfer Completed
 * 
 * for control endpoints in DMA mode, this bit must be set to be able to transfer
 * SETUP data packets in memory.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description             
 * :------------------------------------|:------|:-------------------------
 *  ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT | 0x0   | Endpoint Enable inactive
 *  ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT   | 0x1   | Endpoint Enable active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA
 * 
 * Endpoint Enable inactive
 */
#define ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA
 * 
 * Endpoint Enable active
 */
#define ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_SET_MSK    0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL15_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPCTL15.
 */
struct ALT_USB_DEV_DOEPCTL15_s
{
    uint32_t        mps      : 11;  /* Maximum Packet Size */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        usbactep :  1;  /* USB Active Endpoint */
    const uint32_t  dpid     :  1;  /* Endpoint Data PID */
    const uint32_t  naksts   :  1;  /* NAK Status */
    uint32_t        eptype   :  2;  /* Endpoint Type */
    uint32_t        snp      :  1;  /* Snoop Mode */
    const uint32_t  stall    :  1;  /* STALL Handshake */
    uint32_t                 :  4;  /* *UNDEFINED* */
    uint32_t        cnak     :  1;  /* Clear NAK */
    uint32_t        snak     :  1;  /* Set NAK */
    uint32_t        setd0pid :  1;  /* Set DATA0 PID */
    uint32_t        setd1pid :  1;  /* Set DATA1 PID */
    const uint32_t  epdis    :  1;  /* Endpoint Disable */
    const uint32_t  epena    :  1;  /* Endpoint Enable */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPCTL15. */
typedef volatile struct ALT_USB_DEV_DOEPCTL15_s  ALT_USB_DEV_DOEPCTL15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPCTL15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL15_OFST        0x4e0
/* The address of the ALT_USB_DEV_DOEPCTL15 register. */
#define ALT_USB_DEV_DOEPCTL15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL15_OFST))

/*
 * Register : Device OUT Endpoint 15 Interrupt Register - doepint15
 * 
 * This register indicates the status of an endpoint with respect to USB- and AHB-
 * related events. The application must read this register when the OUT Endpoints
 * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
 * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application
 * can read this register, it must first read the Device All Endpoints Interrupt
 * (DAINT) register to get the exact endpoint number for the Device Endpoint-n
 * Interrupt register. The application must clear the appropriate bit in this
 * register to clear the corresponding bits in the DAINT and GINTSTS registers.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                              
 * :--------|:-------|:------|:------------------------------------------
 *  [0]     | R      | 0x0   | Transfer Completed Interrupt             
 *  [1]     | R      | 0x0   | Endpoint Disabled Interrupt              
 *  [2]     | R      | 0x0   | ALT_USB_DEV_DOEPINT15_AHBERR             
 *  [3]     | R      | 0x0   | SETUP Phase Done                         
 *  [4]     | R      | 0x0   | OUT Token Received When Endpoint Disabled
 *  [5]     | R      | 0x0   | Status Phase Received for Control Write  
 *  [6]     | R      | 0x0   | Back-to-Back SETUP Packets Received      
 *  [7]     | ???    | 0x0   | *UNDEFINED*                              
 *  [8]     | R      | 0x0   | OUT Packet Error                         
 *  [9]     | R      | 0x0   | BNA (Buffer Not Available) Interrupt     
 *  [10]    | ???    | 0x0   | *UNDEFINED*                              
 *  [11]    | R      | 0x0   | Packet Drop Status                       
 *  [12]    | R      | 0x0   | BbleErr Interrupt                        
 *  [13]    | R      | 0x0   | NAK Interrupt                            
 *  [14]    | R      | 0x0   | NYET Interrupt                           
 *  [31:15] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : Transfer Completed Interrupt - xfercompl
 * 
 * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled
 * 
 * This field indicates that the requested data from the internal FIFO is moved to
 * external system memory. This interrupt is generated only when the corresponding
 * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor
 * is Set.
 * 
 * When Scatter/Gather DMA mode is disabled, this field indicates that the
 * programmed transfer is complete on the AHB as well as on the USB, for this
 * endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT | 0x0   | No Interrupt                
 *  ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT   | 0x1   | Transfer Completed Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL
 * 
 * Transfer Completed Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_MSB        0
/* The width in bits of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Endpoint Disabled Interrupt - epdisbld
 * 
 * Applies to IN and OUT endpoints. This bit indicates that the endpoint is
 * disabled per the application's request.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT | 0x0   | No Interrupt               
 *  ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT   | 0x1   | Endpoint Disabled Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD
 * 
 * Endpoint Disabled Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_MSB        1
/* The width in bits of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET_MSK    0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_CLR_MSK    0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT15_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : ahberr
 * 
 * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when
 * there is an AHB error during an AHB read/write. The application can read the
 * corresponding endpoint DMA address register to get the error address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT | 0x0   | No Interrupt       
 *  ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT   | 0x1   | AHB Error interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR
 * 
 * No Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR
 * 
 * AHB Error interrupt
 */
#define ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_MSB        2
/* The width in bits of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_SET_MSK    0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_CLR_MSK    0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT15_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : SETUP Phase Done - setup
 * 
 * Applies to control OUT endpoints only. Indicates that the SETUP phase for the
 * control endpoint is complete and no more back-to-back SETUP packets were
 * received for the current control transfer. On this interrupt, the application
 * can decode the received SETUP data packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description        
 * :------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT15_SETUP_E_INACT | 0x0   | No SETUP Phase Done
 *  ALT_USB_DEV_DOEPINT15_SETUP_E_ACT   | 0x1   | SETUP Phase Done   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP
 * 
 * No SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT15_SETUP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP
 * 
 * SETUP Phase Done
 */
#define ALT_USB_DEV_DOEPINT15_SETUP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_MSB        3
/* The width in bits of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_SETUP_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_SETUP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT15_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT15_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_SETUP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : OUT Token Received When Endpoint Disabled - outtknepdis
 * 
 * Applies only to control OUT endpoints. Indicates that an OUT token was received
 * when the endpoint was not yet enabled. This interrupt is asserted on the
 * endpoint for which the OUT token was received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                                 
 * :------------------------------------------|:------|:---------------------------------------------
 *  ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT | 0x0   | No OUT Token Received When Endpoint Disabled
 *  ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT   | 0x1   | OUT Token Received When Endpoint Disabled   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
 * 
 * No OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
 * 
 * OUT Token Received When Endpoint Disabled
 */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_MSB        4
/* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Status Phase Received for Control Write - stsphsercvd
 * 
 * This interrupt is valid only for Control OUT endpoints and only in Scatter
 * Gather DMA mode. This interrupt is generated only after the core has transferred
 * all the data that the host has sent during the data phase of a control write
 * transfer, to the system memory buffer. The interrupt indicates to the
 * application that the host has switched from data phase to the status phase of a
 * Control Write transfer. The application can use this interrupt to ACK or STALL
 * the Status phase, after it has decoded the data phase. This is applicable only
 * in Case of Scatter Gather DMA mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                               
 * :------------------------------------------|:------|:-------------------------------------------
 *  ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT | 0x0   | No Status Phase Received for Control Write
 *  ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT   | 0x1   | Status Phase Received for Control Write   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD
 * 
 * No Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD
 * 
 * Status Phase Received for Control Write
 */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_MSB        5
/* The width in bits of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET_MSK    0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_CLR_MSK    0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Back-to-Back SETUP Packets Received - back2backsetup
 * 
 * Applies to Control OUT endpoints only. This bit indicates that the core has
 * received more than three back-to-back SETUP packets for this particular
 * endpoint. for information about handling this interrupt,
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                           
 * :---------------------------------------------|:------|:---------------------------------------
 *  ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT | 0x0   | No Back-to-Back SETUP Packets Received
 *  ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT   | 0x1   | Back-to-Back SETUP Packets Received   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
 * 
 * No Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
 * 
 * Back-to-Back SETUP Packets Received
 */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_MSB        6
/* The width in bits of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : OUT Packet Error - outpkterr
 * 
 * Applies to OUT endpoints Only This interrupt is asserted when the core detects
 * an overflow or a CRC error for non-Isochronous OUT packet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description        
 * :----------------------------------------|:------|:--------------------
 *  ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT | 0x0   | No OUT Packet Error
 *  ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT   | 0x1   | OUT Packet Error   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR
 * 
 * No OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR
 * 
 * OUT Packet Error
 */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_MSB        8
/* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET_MSK    0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_CLR_MSK    0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : BNA (Buffer Not Available) Interrupt - bnaintr
 * 
 * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only
 * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when
 * the descriptor accessed is not ready for the Core to process, such as Host busy
 * or DMA done
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description  
 * :--------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT   | 0x1   | BNA interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR
 * 
 * BNA interrupt
 */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_MSB        9
/* The width in bits of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_SET_MSK    0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT15_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Packet Drop Status - pktdrpsts
 * 
 * This bit indicates to the application that an ISOC OUT packet has been dropped.
 * This bit does not have an associated mask bit and does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT | 0x0   | No interrupt                
 *  ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT   | 0x1   | Packet Drop Status interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS
 * 
 * Packet Drop Status interrupt
 */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_MSB        11
/* The width in bits of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET_MSK    0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : BbleErr Interrupt - bbleerr
 * 
 * The core generates this interrupt when babble is received for the endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description      
 * :--------------------------------------|:------|:------------------
 *  ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT | 0x0   | No interrupt     
 *  ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT   | 0x1   | BbleErr interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT   0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR
 * 
 * BbleErr interrupt
 */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_MSB        12
/* The width in bits of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_SET_MSK    0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_CLR_MSK    0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT15_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : NAK Interrupt - nakintrpt
 * 
 * The core generates this interrupt when a NAK is transmitted or received by the
 * device. In case of isochronous IN endpoints the interrupt gets generated when a
 * zero length packet is transmitted due to un-availability of data in the TXFifo.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description  
 * :----------------------------------------|:------|:--------------
 *  ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT | 0x0   | No interrupt 
 *  ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT   | 0x1   | NAK Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT
 * 
 * NAK Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_MSB        13
/* The width in bits of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET_MSK    0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_CLR_MSK    0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : NYET Interrupt - nyetintrpt
 * 
 * The core generates this interrupt when a NYET response is transmitted for a non
 * isochronous OUT endpoint.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description   
 * :-----------------------------------------|:------|:---------------
 *  ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT | 0x0   | No interrupt  
 *  ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT   | 0x1   | NYET Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT
 * 
 * No interrupt
 */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT    0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT
 * 
 * NYET Interrupt
 */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_MSB        14
/* The width in bits of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_WIDTH      1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET_MSK    0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_CLR_MSK    0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPINT15.
 */
struct ALT_USB_DEV_DOEPINT15_s
{
    const uint32_t  xfercompl      :  1;  /* Transfer Completed Interrupt */
    const uint32_t  epdisbld       :  1;  /* Endpoint Disabled Interrupt */
    const uint32_t  ahberr         :  1;  /* ALT_USB_DEV_DOEPINT15_AHBERR */
    const uint32_t  setup          :  1;  /* SETUP Phase Done */
    const uint32_t  outtknepdis    :  1;  /* OUT Token Received When Endpoint Disabled */
    const uint32_t  stsphsercvd    :  1;  /* Status Phase Received for Control Write */
    const uint32_t  back2backsetup :  1;  /* Back-to-Back SETUP Packets Received */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  outpkterr      :  1;  /* OUT Packet Error */
    const uint32_t  bnaintr        :  1;  /* BNA (Buffer Not Available) Interrupt */
    uint32_t                       :  1;  /* *UNDEFINED* */
    const uint32_t  pktdrpsts      :  1;  /* Packet Drop Status */
    const uint32_t  bbleerr        :  1;  /* BbleErr Interrupt */
    const uint32_t  nakintrpt      :  1;  /* NAK Interrupt */
    const uint32_t  nyetintrpt     :  1;  /* NYET Interrupt */
    uint32_t                       : 17;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPINT15. */
typedef volatile struct ALT_USB_DEV_DOEPINT15_s  ALT_USB_DEV_DOEPINT15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPINT15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT15_OFST        0x4e8
/* The address of the ALT_USB_DEV_DOEPINT15 register. */
#define ALT_USB_DEV_DOEPINT15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT15_OFST))

/*
 * Register : Device OUT Endpoint 15 Transfer Size Register - doeptsiz15
 * 
 * The application must modify this register before enabling the endpoint. Once the
 * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
 * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The
 * application can only read this register once the core has cleared the Endpoint
 * Enable bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description       
 * :--------|:-------|:------|:-------------------
 *  [18:0]  | RW     | 0x0   | Transfer Size     
 *  [28:19] | RW     | 0x0   | Packet Count      
 *  [30:29] | R      | 0x0   | SETUP Packet Count
 *  [31]    | ???    | 0x0   | *UNDEFINED*       
 * 
 */
/*
 * Field : Transfer Size - xfersize
 * 
 * Indicates the transfer size in bytes for endpoint 0. The core interrupts the
 * application only after it has exhausted the transfer size amount of data. The
 * transfer size can be Set to the maximum packet size of the endpoint, to be
 * interrupted at the end of each packet. The core decrements this field every time
 * a packet from the external memory is written to the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_MSB        18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_WIDTH      19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET_MSK    0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_CLR_MSK    0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)

/*
 * Field : Packet Count - pktcnt
 * 
 * Indicates the total number of USB packets that constitute the Transfer Size
 * amount of data for endpoint 0.This field is decremented every time a packet
 * (maximum size or short packet) is read from the RxFIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_MSB        28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_WIDTH      10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET_MSK    0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_CLR_MSK    0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ15_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)

/*
 * Field : SETUP Packet Count - rxdpid
 * 
 * Applies to isochronous OUT endpoints only.This is the data PID received in the
 * last packet for this endpoint. Use datax.
 * 
 * Applies to control OUT Endpoints only. Use packetx. This field specifies the
 * number of back-to-back SETUP data packets the endpoint can receive.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description       
 * :------------------------------------------|:------|:-------------------
 *  ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0     | 0x0   | DATA0             
 *  ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 | 0x1   | DATA2 or 1 packet 
 *  ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 | 0x2   | DATA1 or 2 packets
 *  ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 | 0x3   | MDATA or 3 packets
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
 * 
 * DATA0
 */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0       0x0
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
 * 
 * DATA2 or 1 packet
 */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1   0x1
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
 * 
 * DATA1 or 2 packets
 */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2   0x2
/*
 * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
 * 
 * MDATA or 3 packets
 */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3   0x3

/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_MSB        30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_WIDTH      2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET_MSK    0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_CLR_MSK    0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ15_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET(value) (((value) << 29) & 0x60000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPTSIZ15.
 */
struct ALT_USB_DEV_DOEPTSIZ15_s
{
    uint32_t        xfersize : 19;  /* Transfer Size */
    uint32_t        pktcnt   : 10;  /* Packet Count */
    const uint32_t  rxdpid   :  2;  /* SETUP Packet Count */
    uint32_t                 :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ15. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ15_s  ALT_USB_DEV_DOEPTSIZ15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPTSIZ15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ15_OFST        0x4f0
/* The address of the ALT_USB_DEV_DOEPTSIZ15 register. */
#define ALT_USB_DEV_DOEPTSIZ15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ15_OFST))

/*
 * Register : Device OUT Endpoint 15 DMA Address Register - doepdma15
 * 
 * DMA OUT Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description
 * :-------|:-------|:--------|:------------
 *  [31:0] | RW     | Unknown | DMA Address
 * 
 */
/*
 * Field : DMA Address - doepdma15
 * 
 * Holds the start address of the external memory for storing or fetching endpoint
 * data. for control endpoints, this field stores control OUT data packets as well
 * as SETUP transaction data packets. When more than three SETUP packets are
 * received back-to-back, the SETUP data packet in the memory is overwritten. This
 * register is incremented on every AHB transaction. The application can give only
 * a DWORD-aligned address.
 * 
 * When Scatter/Gather DMA mode is not enabled, the application programs the start
 * address value in this field.
 * 
 * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer
 * for the descriptor list.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 field value from a register. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMA15.
 */
struct ALT_USB_DEV_DOEPDMA15_s
{
    uint32_t  doepdma15 : 32;  /* DMA Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMA15. */
typedef volatile struct ALT_USB_DEV_DOEPDMA15_s  ALT_USB_DEV_DOEPDMA15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMA15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA15_OFST        0x4f4
/* The address of the ALT_USB_DEV_DOEPDMA15 register. */
#define ALT_USB_DEV_DOEPDMA15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA15_OFST))

/*
 * Register : Device OUT Endpoint 15 DMA Buffer Address Register - doepdmab15
 * 
 * DMA Buffer Address.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset   | Description       
 * :-------|:-------|:--------|:-------------------
 *  [31:0] | R      | Unknown | DMA Buffer Address
 * 
 */
/*
 * Field : DMA Buffer Address - doepdmab15
 * 
 * Holds the current buffer address. This register is updated as and when the data
 * transfer for the corresponding end point is in progress. This register is
 * present only in Scatter/Gather DMA mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_MSB        31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_WIDTH      32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET_MSK    0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_CLR_MSK    0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_RESET      0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_DEV_DOEPDMAB15.
 */
struct ALT_USB_DEV_DOEPDMAB15_s
{
    const uint32_t  doepdmab15 : 32;  /* DMA Buffer Address */
};

/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB15. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB15_s  ALT_USB_DEV_DOEPDMAB15_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_DEV_DOEPDMAB15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB15_OFST        0x4fc
/* The address of the ALT_USB_DEV_DOEPDMAB15 register. */
#define ALT_USB_DEV_DOEPDMAB15_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB15_OFST))

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_USB_DEV.
 */
struct ALT_USB_DEV_s
{
    volatile ALT_USB_DEV_DCFG_t        dcfg;                /* ALT_USB_DEV_DCFG */
    volatile ALT_USB_DEV_DCTL_t        dctl;                /* ALT_USB_DEV_DCTL */
    volatile ALT_USB_DEV_DSTS_t        dsts;                /* ALT_USB_DEV_DSTS */
    volatile uint32_t                  _pad_0xc_0xf;        /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPMSK_t     diepmsk;             /* ALT_USB_DEV_DIEPMSK */
    volatile ALT_USB_DEV_DOEPMSK_t     doepmsk;             /* ALT_USB_DEV_DOEPMSK */
    volatile ALT_USB_DEV_DAINT_t       daint;               /* ALT_USB_DEV_DAINT */
    volatile ALT_USB_DEV_DAINTMSK_t    daintmsk;            /* ALT_USB_DEV_DAINTMSK */
    volatile uint32_t                  _pad_0x20_0x27[2];   /* *UNDEFINED* */
    volatile ALT_USB_DEV_DVBUSDIS_t    dvbusdis;            /* ALT_USB_DEV_DVBUSDIS */
    volatile ALT_USB_DEV_DVBUSPULSE_t  dvbuspulse;          /* ALT_USB_DEV_DVBUSPULSE */
    volatile ALT_USB_DEV_DTHRCTL_t     dthrctl;             /* ALT_USB_DEV_DTHRCTL */
    volatile ALT_USB_DEV_DIEPEMPMSK_t  diepempmsk;          /* ALT_USB_DEV_DIEPEMPMSK */
    volatile uint32_t                  _pad_0x38_0xff[50];  /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPCTL0_t    diepctl0;            /* ALT_USB_DEV_DIEPCTL0 */
    volatile uint32_t                  _pad_0x104_0x107;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT0_t    diepint0;            /* ALT_USB_DEV_DIEPINT0 */
    volatile uint32_t                  _pad_0x10c_0x10f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ0_t   dieptsiz0;           /* ALT_USB_DEV_DIEPTSIZ0 */
    volatile ALT_USB_DEV_DIEPDMA0_t    diepdma0;            /* ALT_USB_DEV_DIEPDMA0 */
    volatile ALT_USB_DEV_DTXFSTS0_t    dtxfsts0;            /* ALT_USB_DEV_DTXFSTS0 */
    volatile ALT_USB_DEV_DIEPDMAB0_t   diepdmab0;           /* ALT_USB_DEV_DIEPDMAB0 */
    volatile ALT_USB_DEV_DIEPCTL1_t    diepctl1;            /* ALT_USB_DEV_DIEPCTL1 */
    volatile uint32_t                  _pad_0x124_0x127;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT1_t    diepint1;            /* ALT_USB_DEV_DIEPINT1 */
    volatile uint32_t                  _pad_0x12c_0x12f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ1_t   dieptsiz1;           /* ALT_USB_DEV_DIEPTSIZ1 */
    volatile ALT_USB_DEV_DIEPDMA1_t    diepdma1;            /* ALT_USB_DEV_DIEPDMA1 */
    volatile ALT_USB_DEV_DTXFSTS1_t    dtxfsts1;            /* ALT_USB_DEV_DTXFSTS1 */
    volatile ALT_USB_DEV_DIEPDMAB1_t   diepdmab1;           /* ALT_USB_DEV_DIEPDMAB1 */
    volatile ALT_USB_DEV_DIEPCTL2_t    diepctl2;            /* ALT_USB_DEV_DIEPCTL2 */
    volatile uint32_t                  _pad_0x144_0x147;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT2_t    diepint2;            /* ALT_USB_DEV_DIEPINT2 */
    volatile uint32_t                  _pad_0x14c_0x14f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ2_t   dieptsiz2;           /* ALT_USB_DEV_DIEPTSIZ2 */
    volatile ALT_USB_DEV_DIEPDMA2_t    diepdma2;            /* ALT_USB_DEV_DIEPDMA2 */
    volatile ALT_USB_DEV_DTXFSTS2_t    DTXFSTS2;            /* ALT_USB_DEV_DTXFSTS2 */
    volatile ALT_USB_DEV_DIEPDMAB2_t   diepdmab2;           /* ALT_USB_DEV_DIEPDMAB2 */
    volatile ALT_USB_DEV_DIEPCTL3_t    diepctl3;            /* ALT_USB_DEV_DIEPCTL3 */
    volatile uint32_t                  _pad_0x164_0x167;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT3_t    diepint3;            /* ALT_USB_DEV_DIEPINT3 */
    volatile uint32_t                  _pad_0x16c_0x16f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ3_t   dieptsiz3;           /* ALT_USB_DEV_DIEPTSIZ3 */
    volatile ALT_USB_DEV_DIEPDMA3_t    diepdma3;            /* ALT_USB_DEV_DIEPDMA3 */
    volatile ALT_USB_DEV_DTXFSTS3_t    dtxfsts3;            /* ALT_USB_DEV_DTXFSTS3 */
    volatile ALT_USB_DEV_DIEPDMAB3_t   diepdmab3;           /* ALT_USB_DEV_DIEPDMAB3 */
    volatile ALT_USB_DEV_DIEPCTL4_t    diepctl4;            /* ALT_USB_DEV_DIEPCTL4 */
    volatile uint32_t                  _pad_0x184_0x187;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT4_t    diepint4;            /* ALT_USB_DEV_DIEPINT4 */
    volatile uint32_t                  _pad_0x18c_0x18f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ4_t   dieptsiz4;           /* ALT_USB_DEV_DIEPTSIZ4 */
    volatile ALT_USB_DEV_DIEPDMA4_t    diepdma4;            /* ALT_USB_DEV_DIEPDMA4 */
    volatile ALT_USB_DEV_DTXFSTS4_t    dtxfsts4;            /* ALT_USB_DEV_DTXFSTS4 */
    volatile ALT_USB_DEV_DIEPDMAB4_t   diepdmab4;           /* ALT_USB_DEV_DIEPDMAB4 */
    volatile ALT_USB_DEV_DIEPCTL5_t    diepctl5;            /* ALT_USB_DEV_DIEPCTL5 */
    volatile uint32_t                  _pad_0x1a4_0x1a7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT5_t    diepint5;            /* ALT_USB_DEV_DIEPINT5 */
    volatile uint32_t                  _pad_0x1ac_0x1af;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ5_t   dieptsiz5;           /* ALT_USB_DEV_DIEPTSIZ5 */
    volatile ALT_USB_DEV_DIEPDMA5_t    diepdma5;            /* ALT_USB_DEV_DIEPDMA5 */
    volatile ALT_USB_DEV_DTXFSTS5_t    dtxfsts5;            /* ALT_USB_DEV_DTXFSTS5 */
    volatile ALT_USB_DEV_DIEPDMAB5_t   diepdmab5;           /* ALT_USB_DEV_DIEPDMAB5 */
    volatile ALT_USB_DEV_DIEPCTL6_t    diepctl6;            /* ALT_USB_DEV_DIEPCTL6 */
    volatile uint32_t                  _pad_0x1c4_0x1c7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT6_t    diepint6;            /* ALT_USB_DEV_DIEPINT6 */
    volatile uint32_t                  _pad_0x1cc_0x1cf;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ6_t   dieptsiz6;           /* ALT_USB_DEV_DIEPTSIZ6 */
    volatile ALT_USB_DEV_DIEPDMA6_t    diepdma6;            /* ALT_USB_DEV_DIEPDMA6 */
    volatile ALT_USB_DEV_DTXFSTS6_t    dtxfsts6;            /* ALT_USB_DEV_DTXFSTS6 */
    volatile ALT_USB_DEV_DIEPDMAB6_t   diepdmab6;           /* ALT_USB_DEV_DIEPDMAB6 */
    volatile ALT_USB_DEV_DIEPCTL7_t    diepctl7;            /* ALT_USB_DEV_DIEPCTL7 */
    volatile uint32_t                  _pad_0x1e4_0x1e7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT7_t    diepint7;            /* ALT_USB_DEV_DIEPINT7 */
    volatile uint32_t                  _pad_0x1ec_0x1ef;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ7_t   dieptsiz7;           /* ALT_USB_DEV_DIEPTSIZ7 */
    volatile ALT_USB_DEV_DIEPDMA7_t    diepdma7;            /* ALT_USB_DEV_DIEPDMA7 */
    volatile ALT_USB_DEV_DTXFSTS7_t    dtxfsts7;            /* ALT_USB_DEV_DTXFSTS7 */
    volatile ALT_USB_DEV_DIEPDMAB7_t   diepdmab7;           /* ALT_USB_DEV_DIEPDMAB7 */
    volatile ALT_USB_DEV_DIEPCTL8_t    diepctl8;            /* ALT_USB_DEV_DIEPCTL8 */
    volatile uint32_t                  _pad_0x204_0x207;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT8_t    diepint8;            /* ALT_USB_DEV_DIEPINT8 */
    volatile uint32_t                  _pad_0x20c_0x20f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ8_t   dieptsiz8;           /* ALT_USB_DEV_DIEPTSIZ8 */
    volatile ALT_USB_DEV_DIEPDMA8_t    diepdma8;            /* ALT_USB_DEV_DIEPDMA8 */
    volatile ALT_USB_DEV_DTXFSTS8_t    dtxfsts8;            /* ALT_USB_DEV_DTXFSTS8 */
    volatile ALT_USB_DEV_DIEPDMAB8_t   diepdmab8;           /* ALT_USB_DEV_DIEPDMAB8 */
    volatile ALT_USB_DEV_DIEPCTL9_t    diepctl9;            /* ALT_USB_DEV_DIEPCTL9 */
    volatile uint32_t                  _pad_0x224_0x227;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT9_t    diepint9;            /* ALT_USB_DEV_DIEPINT9 */
    volatile uint32_t                  _pad_0x22c_0x22f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ9_t   dieptsiz9;           /* ALT_USB_DEV_DIEPTSIZ9 */
    volatile ALT_USB_DEV_DIEPDMA9_t    diepdma9;            /* ALT_USB_DEV_DIEPDMA9 */
    volatile ALT_USB_DEV_DTXFSTS9_t    dtxfsts9;            /* ALT_USB_DEV_DTXFSTS9 */
    volatile ALT_USB_DEV_DIEPDMAB9_t   diepdmab9;           /* ALT_USB_DEV_DIEPDMAB9 */
    volatile ALT_USB_DEV_DIEPCTL10_t   diepctl10;           /* ALT_USB_DEV_DIEPCTL10 */
    volatile uint32_t                  _pad_0x244_0x247;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT10_t   diepint10;           /* ALT_USB_DEV_DIEPINT10 */
    volatile uint32_t                  _pad_0x24c_0x24f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ10_t  dieptsiz10;          /* ALT_USB_DEV_DIEPTSIZ10 */
    volatile ALT_USB_DEV_DIEPDMA10_t   diepdma10;           /* ALT_USB_DEV_DIEPDMA10 */
    volatile ALT_USB_DEV_DTXFSTS10_t   dtxfsts10;           /* ALT_USB_DEV_DTXFSTS10 */
    volatile ALT_USB_DEV_DIEPDMAB10_t  diepdmab10;          /* ALT_USB_DEV_DIEPDMAB10 */
    volatile ALT_USB_DEV_DIEPCTL11_t   diepctl11;           /* ALT_USB_DEV_DIEPCTL11 */
    volatile uint32_t                  _pad_0x264_0x267;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT11_t   diepint11;           /* ALT_USB_DEV_DIEPINT11 */
    volatile uint32_t                  _pad_0x26c_0x26f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ11_t  dieptsiz11;          /* ALT_USB_DEV_DIEPTSIZ11 */
    volatile ALT_USB_DEV_DIEPDMA11_t   diepdma11;           /* ALT_USB_DEV_DIEPDMA11 */
    volatile ALT_USB_DEV_DTXFSTS11_t   dtxfsts11;           /* ALT_USB_DEV_DTXFSTS11 */
    volatile ALT_USB_DEV_DIEPDMAB11_t  diepdmab11;          /* ALT_USB_DEV_DIEPDMAB11 */
    volatile ALT_USB_DEV_DIEPCTL12_t   diepctl12;           /* ALT_USB_DEV_DIEPCTL12 */
    volatile uint32_t                  _pad_0x284_0x287;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT12_t   diepint12;           /* ALT_USB_DEV_DIEPINT12 */
    volatile uint32_t                  _pad_0x28c_0x28f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ12_t  dieptsiz12;          /* ALT_USB_DEV_DIEPTSIZ12 */
    volatile ALT_USB_DEV_DIEPDMA12_t   diepdma12;           /* ALT_USB_DEV_DIEPDMA12 */
    volatile ALT_USB_DEV_DTXFSTS12_t   dtxfsts12;           /* ALT_USB_DEV_DTXFSTS12 */
    volatile ALT_USB_DEV_DIEPDMAB12_t  diepdmab12;          /* ALT_USB_DEV_DIEPDMAB12 */
    volatile ALT_USB_DEV_DIEPCTL13_t   diepctl13;           /* ALT_USB_DEV_DIEPCTL13 */
    volatile uint32_t                  _pad_0x2a4_0x2a7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT13_t   diepint13;           /* ALT_USB_DEV_DIEPINT13 */
    volatile uint32_t                  _pad_0x2ac_0x2af;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ13_t  dieptsiz13;          /* ALT_USB_DEV_DIEPTSIZ13 */
    volatile ALT_USB_DEV_DIEPDMA13_t   diepdma13;           /* ALT_USB_DEV_DIEPDMA13 */
    volatile ALT_USB_DEV_DTXFSTS13_t   dtxfsts13;           /* ALT_USB_DEV_DTXFSTS13 */
    volatile ALT_USB_DEV_DIEPDMAB13_t  diepdmab13;          /* ALT_USB_DEV_DIEPDMAB13 */
    volatile ALT_USB_DEV_DIEPCTL14_t   diepctl14;           /* ALT_USB_DEV_DIEPCTL14 */
    volatile uint32_t                  _pad_0x2c4_0x2c7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT14_t   diepint14;           /* ALT_USB_DEV_DIEPINT14 */
    volatile uint32_t                  _pad_0x2cc_0x2cf;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ14_t  dieptsiz14;          /* ALT_USB_DEV_DIEPTSIZ14 */
    volatile ALT_USB_DEV_DIEPDMA14_t   diepdma14;           /* ALT_USB_DEV_DIEPDMA14 */
    volatile ALT_USB_DEV_DTXFSTS14_t   dtxfsts14;           /* ALT_USB_DEV_DTXFSTS14 */
    volatile ALT_USB_DEV_DIEPDMAB14_t  diepdmab14;          /* ALT_USB_DEV_DIEPDMAB14 */
    volatile ALT_USB_DEV_DIEPCTL15_t   diepctl15;           /* ALT_USB_DEV_DIEPCTL15 */
    volatile uint32_t                  _pad_0x2e4_0x2e7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPINT15_t   diepint15;           /* ALT_USB_DEV_DIEPINT15 */
    volatile uint32_t                  _pad_0x2ec_0x2ef;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DIEPTSIZ15_t  dieptsiz15;          /* ALT_USB_DEV_DIEPTSIZ15 */
    volatile ALT_USB_DEV_DIEPDMA15_t   diepdma15;           /* ALT_USB_DEV_DIEPDMA15 */
    volatile ALT_USB_DEV_DTXFSTS15_t   dtxfsts15;           /* ALT_USB_DEV_DTXFSTS15 */
    volatile ALT_USB_DEV_DIEPDMAB15_t  diepdmab15;          /* ALT_USB_DEV_DIEPDMAB15 */
    volatile ALT_USB_DEV_DOEPCTL0_t    doepctl0;            /* ALT_USB_DEV_DOEPCTL0 */
    volatile uint32_t                  _pad_0x304_0x307;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT0_t    doepint0;            /* ALT_USB_DEV_DOEPINT0 */
    volatile uint32_t                  _pad_0x30c_0x30f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ0_t   doeptsiz0;           /* ALT_USB_DEV_DOEPTSIZ0 */
    volatile ALT_USB_DEV_DOEPDMA0_t    doepdma0;            /* ALT_USB_DEV_DOEPDMA0 */
    volatile uint32_t                  _pad_0x318_0x31b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB0_t   doepdmab0;           /* ALT_USB_DEV_DOEPDMAB0 */
    volatile ALT_USB_DEV_DOEPCTL1_t    doepctl1;            /* ALT_USB_DEV_DOEPCTL1 */
    volatile uint32_t                  _pad_0x324_0x327;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT1_t    doepint1;            /* ALT_USB_DEV_DOEPINT1 */
    volatile uint32_t                  _pad_0x32c_0x32f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ1_t   doeptsiz1;           /* ALT_USB_DEV_DOEPTSIZ1 */
    volatile ALT_USB_DEV_DOEPDMA1_t    doepdma1;            /* ALT_USB_DEV_DOEPDMA1 */
    volatile uint32_t                  _pad_0x338_0x33b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB1_t   doepdmab1;           /* ALT_USB_DEV_DOEPDMAB1 */
    volatile ALT_USB_DEV_DOEPCTL2_t    DOEPCTL2;            /* ALT_USB_DEV_DOEPCTL2 */
    volatile uint32_t                  _pad_0x344_0x347;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT2_t    doepint2;            /* ALT_USB_DEV_DOEPINT2 */
    volatile uint32_t                  _pad_0x34c_0x34f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ2_t   doeptsiz2;           /* ALT_USB_DEV_DOEPTSIZ2 */
    volatile ALT_USB_DEV_DOEPDMA2_t    doepdma2;            /* ALT_USB_DEV_DOEPDMA2 */
    volatile uint32_t                  _pad_0x358_0x35b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB2_t   doepdmab2;           /* ALT_USB_DEV_DOEPDMAB2 */
    volatile ALT_USB_DEV_DOEPCTL3_t    DOEPCTL3;            /* ALT_USB_DEV_DOEPCTL3 */
    volatile uint32_t                  _pad_0x364_0x367;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT3_t    doepint3;            /* ALT_USB_DEV_DOEPINT3 */
    volatile uint32_t                  _pad_0x36c_0x36f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ3_t   doeptsiz3;           /* ALT_USB_DEV_DOEPTSIZ3 */
    volatile ALT_USB_DEV_DOEPDMA3_t    doepdma3;            /* ALT_USB_DEV_DOEPDMA3 */
    volatile uint32_t                  _pad_0x378_0x37b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB3_t   doepdmab3;           /* ALT_USB_DEV_DOEPDMAB3 */
    volatile ALT_USB_DEV_DOEPCTL4_t    doepctl4;            /* ALT_USB_DEV_DOEPCTL4 */
    volatile uint32_t                  _pad_0x384_0x387;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT4_t    Doepint4;            /* ALT_USB_DEV_DOEPINT4 */
    volatile uint32_t                  _pad_0x38c_0x38f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ4_t   doeptsiz4;           /* ALT_USB_DEV_DOEPTSIZ4 */
    volatile ALT_USB_DEV_DOEPDMA4_t    doepdma4;            /* ALT_USB_DEV_DOEPDMA4 */
    volatile uint32_t                  _pad_0x398_0x39b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB4_t   doepdmab4;           /* ALT_USB_DEV_DOEPDMAB4 */
    volatile ALT_USB_DEV_DOEPCTL5_t    doepctl5;            /* ALT_USB_DEV_DOEPCTL5 */
    volatile uint32_t                  _pad_0x3a4_0x3a7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT5_t    doepint5;            /* ALT_USB_DEV_DOEPINT5 */
    volatile uint32_t                  _pad_0x3ac_0x3af;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ5_t   doeptsiz5;           /* ALT_USB_DEV_DOEPTSIZ5 */
    volatile ALT_USB_DEV_DOEPDMA5_t    doepdma5;            /* ALT_USB_DEV_DOEPDMA5 */
    volatile uint32_t                  _pad_0x3b8_0x3bb;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB5_t   doepdmab5;           /* ALT_USB_DEV_DOEPDMAB5 */
    volatile ALT_USB_DEV_DOEPCTL6_t    doepctl6;            /* ALT_USB_DEV_DOEPCTL6 */
    volatile uint32_t                  _pad_0x3c4_0x3c7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT6_t    doepint6;            /* ALT_USB_DEV_DOEPINT6 */
    volatile uint32_t                  _pad_0x3cc_0x3cf;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ6_t   doeptsiz6;           /* ALT_USB_DEV_DOEPTSIZ6 */
    volatile ALT_USB_DEV_DOEPDMA6_t    doepdma6;            /* ALT_USB_DEV_DOEPDMA6 */
    volatile uint32_t                  _pad_0x3d8_0x3db;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB6_t   doepdmab6;           /* ALT_USB_DEV_DOEPDMAB6 */
    volatile ALT_USB_DEV_DOEPCTL7_t    doepctl7;            /* ALT_USB_DEV_DOEPCTL7 */
    volatile uint32_t                  _pad_0x3e4_0x3e7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT7_t    doepint7;            /* ALT_USB_DEV_DOEPINT7 */
    volatile uint32_t                  _pad_0x3ec_0x3ef;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ7_t   doeptsiz7;           /* ALT_USB_DEV_DOEPTSIZ7 */
    volatile ALT_USB_DEV_DOEPDMA7_t    doepdma7;            /* ALT_USB_DEV_DOEPDMA7 */
    volatile uint32_t                  _pad_0x3f8_0x3fb;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB7_t   doepdmab7;           /* ALT_USB_DEV_DOEPDMAB7 */
    volatile ALT_USB_DEV_DOEPCTL8_t    doepctl8;            /* ALT_USB_DEV_DOEPCTL8 */
    volatile uint32_t                  _pad_0x404_0x407;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT8_t    doepint8;            /* ALT_USB_DEV_DOEPINT8 */
    volatile uint32_t                  _pad_0x40c_0x40f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ8_t   doeptsiz8;           /* ALT_USB_DEV_DOEPTSIZ8 */
    volatile ALT_USB_DEV_DOEPDMA8_t    doepdma8;            /* ALT_USB_DEV_DOEPDMA8 */
    volatile uint32_t                  _pad_0x418_0x41b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB8_t   doepdmab8;           /* ALT_USB_DEV_DOEPDMAB8 */
    volatile ALT_USB_DEV_DOEPCTL9_t    doepctl9;            /* ALT_USB_DEV_DOEPCTL9 */
    volatile uint32_t                  _pad_0x424_0x427;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT9_t    doepint9;            /* ALT_USB_DEV_DOEPINT9 */
    volatile uint32_t                  _pad_0x42c_0x42f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ9_t   doeptsiz9;           /* ALT_USB_DEV_DOEPTSIZ9 */
    volatile ALT_USB_DEV_DOEPDMA9_t    doepdma9;            /* ALT_USB_DEV_DOEPDMA9 */
    volatile uint32_t                  _pad_0x438_0x43b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB9_t   doepdmab9;           /* ALT_USB_DEV_DOEPDMAB9 */
    volatile ALT_USB_DEV_DOEPCTL10_t   doepctl10;           /* ALT_USB_DEV_DOEPCTL10 */
    volatile uint32_t                  _pad_0x444_0x447;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT10_t   doepint10;           /* ALT_USB_DEV_DOEPINT10 */
    volatile uint32_t                  _pad_0x44c_0x44f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ10_t  doeptsiz10;          /* ALT_USB_DEV_DOEPTSIZ10 */
    volatile ALT_USB_DEV_DOEPDMA10_t   doepdma10;           /* ALT_USB_DEV_DOEPDMA10 */
    volatile uint32_t                  _pad_0x458_0x45b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB10_t  doepdmab10;          /* ALT_USB_DEV_DOEPDMAB10 */
    volatile ALT_USB_DEV_DOEPCTL11_t   doepctl11;           /* ALT_USB_DEV_DOEPCTL11 */
    volatile uint32_t                  _pad_0x464_0x467;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT11_t   doepint11;           /* ALT_USB_DEV_DOEPINT11 */
    volatile uint32_t                  _pad_0x46c_0x46f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ11_t  doeptsiz11;          /* ALT_USB_DEV_DOEPTSIZ11 */
    volatile ALT_USB_DEV_DOEPDMA11_t   doepdma11;           /* ALT_USB_DEV_DOEPDMA11 */
    volatile uint32_t                  _pad_0x478_0x47b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB11_t  doepdmab11;          /* ALT_USB_DEV_DOEPDMAB11 */
    volatile ALT_USB_DEV_DOEPCTL12_t   doepctl12;           /* ALT_USB_DEV_DOEPCTL12 */
    volatile uint32_t                  _pad_0x484_0x487;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT12_t   doepint12;           /* ALT_USB_DEV_DOEPINT12 */
    volatile uint32_t                  _pad_0x48c_0x48f;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ12_t  doeptsiz12;          /* ALT_USB_DEV_DOEPTSIZ12 */
    volatile ALT_USB_DEV_DOEPDMA12_t   doepdma12;           /* ALT_USB_DEV_DOEPDMA12 */
    volatile uint32_t                  _pad_0x498_0x49b;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB12_t  doepdmab12;          /* ALT_USB_DEV_DOEPDMAB12 */
    volatile ALT_USB_DEV_DOEPCTL13_t   doepctl13;           /* ALT_USB_DEV_DOEPCTL13 */
    volatile uint32_t                  _pad_0x4a4_0x4a7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT13_t   doepint13;           /* ALT_USB_DEV_DOEPINT13 */
    volatile uint32_t                  _pad_0x4ac_0x4af;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ13_t  doeptsiz13;          /* ALT_USB_DEV_DOEPTSIZ13 */
    volatile ALT_USB_DEV_DOEPDMA13_t   doepdma13;           /* ALT_USB_DEV_DOEPDMA13 */
    volatile uint32_t                  _pad_0x4b8_0x4bb;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB13_t  doepdmab13;          /* ALT_USB_DEV_DOEPDMAB13 */
    volatile ALT_USB_DEV_DOEPCTL14_t   doepctl14;           /* ALT_USB_DEV_DOEPCTL14 */
    volatile uint32_t                  _pad_0x4c4_0x4c7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT14_t   doepint14;           /* ALT_USB_DEV_DOEPINT14 */
    volatile uint32_t                  _pad_0x4cc_0x4cf;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ14_t  doeptsiz14;          /* ALT_USB_DEV_DOEPTSIZ14 */
    volatile ALT_USB_DEV_DOEPDMA14_t   doepdma14;           /* ALT_USB_DEV_DOEPDMA14 */
    volatile uint32_t                  _pad_0x4d8_0x4db;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB14_t  doepdmab14;          /* ALT_USB_DEV_DOEPDMAB14 */
    volatile ALT_USB_DEV_DOEPCTL15_t   doepctl15;           /* ALT_USB_DEV_DOEPCTL15 */
    volatile uint32_t                  _pad_0x4e4_0x4e7;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPINT15_t   doepint15;           /* ALT_USB_DEV_DOEPINT15 */
    volatile uint32_t                  _pad_0x4ec_0x4ef;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPTSIZ15_t  doeptsiz15;          /* ALT_USB_DEV_DOEPTSIZ15 */
    volatile ALT_USB_DEV_DOEPDMA15_t   doepdma15;           /* ALT_USB_DEV_DOEPDMA15 */
    volatile uint32_t                  _pad_0x4f8_0x4fb;    /* *UNDEFINED* */
    volatile ALT_USB_DEV_DOEPDMAB15_t  doepdmab15;          /* ALT_USB_DEV_DOEPDMAB15 */
};

/* The typedef declaration for register group ALT_USB_DEV. */
typedef volatile struct ALT_USB_DEV_s  ALT_USB_DEV_t;
/* The struct declaration for the raw register contents of register group ALT_USB_DEV. */
struct ALT_USB_DEV_raw_s
{
    volatile uint32_t  dcfg;                /* ALT_USB_DEV_DCFG */
    volatile uint32_t  dctl;                /* ALT_USB_DEV_DCTL */
    volatile uint32_t  dsts;                /* ALT_USB_DEV_DSTS */
    volatile uint32_t  _pad_0xc_0xf;        /* *UNDEFINED* */
    volatile uint32_t  diepmsk;             /* ALT_USB_DEV_DIEPMSK */
    volatile uint32_t  doepmsk;             /* ALT_USB_DEV_DOEPMSK */
    volatile uint32_t  daint;               /* ALT_USB_DEV_DAINT */
    volatile uint32_t  daintmsk;            /* ALT_USB_DEV_DAINTMSK */
    volatile uint32_t  _pad_0x20_0x27[2];   /* *UNDEFINED* */
    volatile uint32_t  dvbusdis;            /* ALT_USB_DEV_DVBUSDIS */
    volatile uint32_t  dvbuspulse;          /* ALT_USB_DEV_DVBUSPULSE */
    volatile uint32_t  dthrctl;             /* ALT_USB_DEV_DTHRCTL */
    volatile uint32_t  diepempmsk;          /* ALT_USB_DEV_DIEPEMPMSK */
    volatile uint32_t  _pad_0x38_0xff[50];  /* *UNDEFINED* */
    volatile uint32_t  diepctl0;            /* ALT_USB_DEV_DIEPCTL0 */
    volatile uint32_t  _pad_0x104_0x107;    /* *UNDEFINED* */
    volatile uint32_t  diepint0;            /* ALT_USB_DEV_DIEPINT0 */
    volatile uint32_t  _pad_0x10c_0x10f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz0;           /* ALT_USB_DEV_DIEPTSIZ0 */
    volatile uint32_t  diepdma0;            /* ALT_USB_DEV_DIEPDMA0 */
    volatile uint32_t  dtxfsts0;            /* ALT_USB_DEV_DTXFSTS0 */
    volatile uint32_t  diepdmab0;           /* ALT_USB_DEV_DIEPDMAB0 */
    volatile uint32_t  diepctl1;            /* ALT_USB_DEV_DIEPCTL1 */
    volatile uint32_t  _pad_0x124_0x127;    /* *UNDEFINED* */
    volatile uint32_t  diepint1;            /* ALT_USB_DEV_DIEPINT1 */
    volatile uint32_t  _pad_0x12c_0x12f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz1;           /* ALT_USB_DEV_DIEPTSIZ1 */
    volatile uint32_t  diepdma1;            /* ALT_USB_DEV_DIEPDMA1 */
    volatile uint32_t  dtxfsts1;            /* ALT_USB_DEV_DTXFSTS1 */
    volatile uint32_t  diepdmab1;           /* ALT_USB_DEV_DIEPDMAB1 */
    volatile uint32_t  diepctl2;            /* ALT_USB_DEV_DIEPCTL2 */
    volatile uint32_t  _pad_0x144_0x147;    /* *UNDEFINED* */
    volatile uint32_t  diepint2;            /* ALT_USB_DEV_DIEPINT2 */
    volatile uint32_t  _pad_0x14c_0x14f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz2;           /* ALT_USB_DEV_DIEPTSIZ2 */
    volatile uint32_t  diepdma2;            /* ALT_USB_DEV_DIEPDMA2 */
    volatile uint32_t  DTXFSTS2;            /* ALT_USB_DEV_DTXFSTS2 */
    volatile uint32_t  diepdmab2;           /* ALT_USB_DEV_DIEPDMAB2 */
    volatile uint32_t  diepctl3;            /* ALT_USB_DEV_DIEPCTL3 */
    volatile uint32_t  _pad_0x164_0x167;    /* *UNDEFINED* */
    volatile uint32_t  diepint3;            /* ALT_USB_DEV_DIEPINT3 */
    volatile uint32_t  _pad_0x16c_0x16f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz3;           /* ALT_USB_DEV_DIEPTSIZ3 */
    volatile uint32_t  diepdma3;            /* ALT_USB_DEV_DIEPDMA3 */
    volatile uint32_t  dtxfsts3;            /* ALT_USB_DEV_DTXFSTS3 */
    volatile uint32_t  diepdmab3;           /* ALT_USB_DEV_DIEPDMAB3 */
    volatile uint32_t  diepctl4;            /* ALT_USB_DEV_DIEPCTL4 */
    volatile uint32_t  _pad_0x184_0x187;    /* *UNDEFINED* */
    volatile uint32_t  diepint4;            /* ALT_USB_DEV_DIEPINT4 */
    volatile uint32_t  _pad_0x18c_0x18f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz4;           /* ALT_USB_DEV_DIEPTSIZ4 */
    volatile uint32_t  diepdma4;            /* ALT_USB_DEV_DIEPDMA4 */
    volatile uint32_t  dtxfsts4;            /* ALT_USB_DEV_DTXFSTS4 */
    volatile uint32_t  diepdmab4;           /* ALT_USB_DEV_DIEPDMAB4 */
    volatile uint32_t  diepctl5;            /* ALT_USB_DEV_DIEPCTL5 */
    volatile uint32_t  _pad_0x1a4_0x1a7;    /* *UNDEFINED* */
    volatile uint32_t  diepint5;            /* ALT_USB_DEV_DIEPINT5 */
    volatile uint32_t  _pad_0x1ac_0x1af;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz5;           /* ALT_USB_DEV_DIEPTSIZ5 */
    volatile uint32_t  diepdma5;            /* ALT_USB_DEV_DIEPDMA5 */
    volatile uint32_t  dtxfsts5;            /* ALT_USB_DEV_DTXFSTS5 */
    volatile uint32_t  diepdmab5;           /* ALT_USB_DEV_DIEPDMAB5 */
    volatile uint32_t  diepctl6;            /* ALT_USB_DEV_DIEPCTL6 */
    volatile uint32_t  _pad_0x1c4_0x1c7;    /* *UNDEFINED* */
    volatile uint32_t  diepint6;            /* ALT_USB_DEV_DIEPINT6 */
    volatile uint32_t  _pad_0x1cc_0x1cf;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz6;           /* ALT_USB_DEV_DIEPTSIZ6 */
    volatile uint32_t  diepdma6;            /* ALT_USB_DEV_DIEPDMA6 */
    volatile uint32_t  dtxfsts6;            /* ALT_USB_DEV_DTXFSTS6 */
    volatile uint32_t  diepdmab6;           /* ALT_USB_DEV_DIEPDMAB6 */
    volatile uint32_t  diepctl7;            /* ALT_USB_DEV_DIEPCTL7 */
    volatile uint32_t  _pad_0x1e4_0x1e7;    /* *UNDEFINED* */
    volatile uint32_t  diepint7;            /* ALT_USB_DEV_DIEPINT7 */
    volatile uint32_t  _pad_0x1ec_0x1ef;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz7;           /* ALT_USB_DEV_DIEPTSIZ7 */
    volatile uint32_t  diepdma7;            /* ALT_USB_DEV_DIEPDMA7 */
    volatile uint32_t  dtxfsts7;            /* ALT_USB_DEV_DTXFSTS7 */
    volatile uint32_t  diepdmab7;           /* ALT_USB_DEV_DIEPDMAB7 */
    volatile uint32_t  diepctl8;            /* ALT_USB_DEV_DIEPCTL8 */
    volatile uint32_t  _pad_0x204_0x207;    /* *UNDEFINED* */
    volatile uint32_t  diepint8;            /* ALT_USB_DEV_DIEPINT8 */
    volatile uint32_t  _pad_0x20c_0x20f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz8;           /* ALT_USB_DEV_DIEPTSIZ8 */
    volatile uint32_t  diepdma8;            /* ALT_USB_DEV_DIEPDMA8 */
    volatile uint32_t  dtxfsts8;            /* ALT_USB_DEV_DTXFSTS8 */
    volatile uint32_t  diepdmab8;           /* ALT_USB_DEV_DIEPDMAB8 */
    volatile uint32_t  diepctl9;            /* ALT_USB_DEV_DIEPCTL9 */
    volatile uint32_t  _pad_0x224_0x227;    /* *UNDEFINED* */
    volatile uint32_t  diepint9;            /* ALT_USB_DEV_DIEPINT9 */
    volatile uint32_t  _pad_0x22c_0x22f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz9;           /* ALT_USB_DEV_DIEPTSIZ9 */
    volatile uint32_t  diepdma9;            /* ALT_USB_DEV_DIEPDMA9 */
    volatile uint32_t  dtxfsts9;            /* ALT_USB_DEV_DTXFSTS9 */
    volatile uint32_t  diepdmab9;           /* ALT_USB_DEV_DIEPDMAB9 */
    volatile uint32_t  diepctl10;           /* ALT_USB_DEV_DIEPCTL10 */
    volatile uint32_t  _pad_0x244_0x247;    /* *UNDEFINED* */
    volatile uint32_t  diepint10;           /* ALT_USB_DEV_DIEPINT10 */
    volatile uint32_t  _pad_0x24c_0x24f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz10;          /* ALT_USB_DEV_DIEPTSIZ10 */
    volatile uint32_t  diepdma10;           /* ALT_USB_DEV_DIEPDMA10 */
    volatile uint32_t  dtxfsts10;           /* ALT_USB_DEV_DTXFSTS10 */
    volatile uint32_t  diepdmab10;          /* ALT_USB_DEV_DIEPDMAB10 */
    volatile uint32_t  diepctl11;           /* ALT_USB_DEV_DIEPCTL11 */
    volatile uint32_t  _pad_0x264_0x267;    /* *UNDEFINED* */
    volatile uint32_t  diepint11;           /* ALT_USB_DEV_DIEPINT11 */
    volatile uint32_t  _pad_0x26c_0x26f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz11;          /* ALT_USB_DEV_DIEPTSIZ11 */
    volatile uint32_t  diepdma11;           /* ALT_USB_DEV_DIEPDMA11 */
    volatile uint32_t  dtxfsts11;           /* ALT_USB_DEV_DTXFSTS11 */
    volatile uint32_t  diepdmab11;          /* ALT_USB_DEV_DIEPDMAB11 */
    volatile uint32_t  diepctl12;           /* ALT_USB_DEV_DIEPCTL12 */
    volatile uint32_t  _pad_0x284_0x287;    /* *UNDEFINED* */
    volatile uint32_t  diepint12;           /* ALT_USB_DEV_DIEPINT12 */
    volatile uint32_t  _pad_0x28c_0x28f;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz12;          /* ALT_USB_DEV_DIEPTSIZ12 */
    volatile uint32_t  diepdma12;           /* ALT_USB_DEV_DIEPDMA12 */
    volatile uint32_t  dtxfsts12;           /* ALT_USB_DEV_DTXFSTS12 */
    volatile uint32_t  diepdmab12;          /* ALT_USB_DEV_DIEPDMAB12 */
    volatile uint32_t  diepctl13;           /* ALT_USB_DEV_DIEPCTL13 */
    volatile uint32_t  _pad_0x2a4_0x2a7;    /* *UNDEFINED* */
    volatile uint32_t  diepint13;           /* ALT_USB_DEV_DIEPINT13 */
    volatile uint32_t  _pad_0x2ac_0x2af;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz13;          /* ALT_USB_DEV_DIEPTSIZ13 */
    volatile uint32_t  diepdma13;           /* ALT_USB_DEV_DIEPDMA13 */
    volatile uint32_t  dtxfsts13;           /* ALT_USB_DEV_DTXFSTS13 */
    volatile uint32_t  diepdmab13;          /* ALT_USB_DEV_DIEPDMAB13 */
    volatile uint32_t  diepctl14;           /* ALT_USB_DEV_DIEPCTL14 */
    volatile uint32_t  _pad_0x2c4_0x2c7;    /* *UNDEFINED* */
    volatile uint32_t  diepint14;           /* ALT_USB_DEV_DIEPINT14 */
    volatile uint32_t  _pad_0x2cc_0x2cf;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz14;          /* ALT_USB_DEV_DIEPTSIZ14 */
    volatile uint32_t  diepdma14;           /* ALT_USB_DEV_DIEPDMA14 */
    volatile uint32_t  dtxfsts14;           /* ALT_USB_DEV_DTXFSTS14 */
    volatile uint32_t  diepdmab14;          /* ALT_USB_DEV_DIEPDMAB14 */
    volatile uint32_t  diepctl15;           /* ALT_USB_DEV_DIEPCTL15 */
    volatile uint32_t  _pad_0x2e4_0x2e7;    /* *UNDEFINED* */
    volatile uint32_t  diepint15;           /* ALT_USB_DEV_DIEPINT15 */
    volatile uint32_t  _pad_0x2ec_0x2ef;    /* *UNDEFINED* */
    volatile uint32_t  dieptsiz15;          /* ALT_USB_DEV_DIEPTSIZ15 */
    volatile uint32_t  diepdma15;           /* ALT_USB_DEV_DIEPDMA15 */
    volatile uint32_t  dtxfsts15;           /* ALT_USB_DEV_DTXFSTS15 */
    volatile uint32_t  diepdmab15;          /* ALT_USB_DEV_DIEPDMAB15 */
    volatile uint32_t  doepctl0;            /* ALT_USB_DEV_DOEPCTL0 */
    volatile uint32_t  _pad_0x304_0x307;    /* *UNDEFINED* */
    volatile uint32_t  doepint0;            /* ALT_USB_DEV_DOEPINT0 */
    volatile uint32_t  _pad_0x30c_0x30f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz0;           /* ALT_USB_DEV_DOEPTSIZ0 */
    volatile uint32_t  doepdma0;            /* ALT_USB_DEV_DOEPDMA0 */
    volatile uint32_t  _pad_0x318_0x31b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab0;           /* ALT_USB_DEV_DOEPDMAB0 */
    volatile uint32_t  doepctl1;            /* ALT_USB_DEV_DOEPCTL1 */
    volatile uint32_t  _pad_0x324_0x327;    /* *UNDEFINED* */
    volatile uint32_t  doepint1;            /* ALT_USB_DEV_DOEPINT1 */
    volatile uint32_t  _pad_0x32c_0x32f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz1;           /* ALT_USB_DEV_DOEPTSIZ1 */
    volatile uint32_t  doepdma1;            /* ALT_USB_DEV_DOEPDMA1 */
    volatile uint32_t  _pad_0x338_0x33b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab1;           /* ALT_USB_DEV_DOEPDMAB1 */
    volatile uint32_t  DOEPCTL2;            /* ALT_USB_DEV_DOEPCTL2 */
    volatile uint32_t  _pad_0x344_0x347;    /* *UNDEFINED* */
    volatile uint32_t  doepint2;            /* ALT_USB_DEV_DOEPINT2 */
    volatile uint32_t  _pad_0x34c_0x34f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz2;           /* ALT_USB_DEV_DOEPTSIZ2 */
    volatile uint32_t  doepdma2;            /* ALT_USB_DEV_DOEPDMA2 */
    volatile uint32_t  _pad_0x358_0x35b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab2;           /* ALT_USB_DEV_DOEPDMAB2 */
    volatile uint32_t  DOEPCTL3;            /* ALT_USB_DEV_DOEPCTL3 */
    volatile uint32_t  _pad_0x364_0x367;    /* *UNDEFINED* */
    volatile uint32_t  doepint3;            /* ALT_USB_DEV_DOEPINT3 */
    volatile uint32_t  _pad_0x36c_0x36f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz3;           /* ALT_USB_DEV_DOEPTSIZ3 */
    volatile uint32_t  doepdma3;            /* ALT_USB_DEV_DOEPDMA3 */
    volatile uint32_t  _pad_0x378_0x37b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab3;           /* ALT_USB_DEV_DOEPDMAB3 */
    volatile uint32_t  doepctl4;            /* ALT_USB_DEV_DOEPCTL4 */
    volatile uint32_t  _pad_0x384_0x387;    /* *UNDEFINED* */
    volatile uint32_t  Doepint4;            /* ALT_USB_DEV_DOEPINT4 */
    volatile uint32_t  _pad_0x38c_0x38f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz4;           /* ALT_USB_DEV_DOEPTSIZ4 */
    volatile uint32_t  doepdma4;            /* ALT_USB_DEV_DOEPDMA4 */
    volatile uint32_t  _pad_0x398_0x39b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab4;           /* ALT_USB_DEV_DOEPDMAB4 */
    volatile uint32_t  doepctl5;            /* ALT_USB_DEV_DOEPCTL5 */
    volatile uint32_t  _pad_0x3a4_0x3a7;    /* *UNDEFINED* */
    volatile uint32_t  doepint5;            /* ALT_USB_DEV_DOEPINT5 */
    volatile uint32_t  _pad_0x3ac_0x3af;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz5;           /* ALT_USB_DEV_DOEPTSIZ5 */
    volatile uint32_t  doepdma5;            /* ALT_USB_DEV_DOEPDMA5 */
    volatile uint32_t  _pad_0x3b8_0x3bb;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab5;           /* ALT_USB_DEV_DOEPDMAB5 */
    volatile uint32_t  doepctl6;            /* ALT_USB_DEV_DOEPCTL6 */
    volatile uint32_t  _pad_0x3c4_0x3c7;    /* *UNDEFINED* */
    volatile uint32_t  doepint6;            /* ALT_USB_DEV_DOEPINT6 */
    volatile uint32_t  _pad_0x3cc_0x3cf;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz6;           /* ALT_USB_DEV_DOEPTSIZ6 */
    volatile uint32_t  doepdma6;            /* ALT_USB_DEV_DOEPDMA6 */
    volatile uint32_t  _pad_0x3d8_0x3db;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab6;           /* ALT_USB_DEV_DOEPDMAB6 */
    volatile uint32_t  doepctl7;            /* ALT_USB_DEV_DOEPCTL7 */
    volatile uint32_t  _pad_0x3e4_0x3e7;    /* *UNDEFINED* */
    volatile uint32_t  doepint7;            /* ALT_USB_DEV_DOEPINT7 */
    volatile uint32_t  _pad_0x3ec_0x3ef;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz7;           /* ALT_USB_DEV_DOEPTSIZ7 */
    volatile uint32_t  doepdma7;            /* ALT_USB_DEV_DOEPDMA7 */
    volatile uint32_t  _pad_0x3f8_0x3fb;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab7;           /* ALT_USB_DEV_DOEPDMAB7 */
    volatile uint32_t  doepctl8;            /* ALT_USB_DEV_DOEPCTL8 */
    volatile uint32_t  _pad_0x404_0x407;    /* *UNDEFINED* */
    volatile uint32_t  doepint8;            /* ALT_USB_DEV_DOEPINT8 */
    volatile uint32_t  _pad_0x40c_0x40f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz8;           /* ALT_USB_DEV_DOEPTSIZ8 */
    volatile uint32_t  doepdma8;            /* ALT_USB_DEV_DOEPDMA8 */
    volatile uint32_t  _pad_0x418_0x41b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab8;           /* ALT_USB_DEV_DOEPDMAB8 */
    volatile uint32_t  doepctl9;            /* ALT_USB_DEV_DOEPCTL9 */
    volatile uint32_t  _pad_0x424_0x427;    /* *UNDEFINED* */
    volatile uint32_t  doepint9;            /* ALT_USB_DEV_DOEPINT9 */
    volatile uint32_t  _pad_0x42c_0x42f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz9;           /* ALT_USB_DEV_DOEPTSIZ9 */
    volatile uint32_t  doepdma9;            /* ALT_USB_DEV_DOEPDMA9 */
    volatile uint32_t  _pad_0x438_0x43b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab9;           /* ALT_USB_DEV_DOEPDMAB9 */
    volatile uint32_t  doepctl10;           /* ALT_USB_DEV_DOEPCTL10 */
    volatile uint32_t  _pad_0x444_0x447;    /* *UNDEFINED* */
    volatile uint32_t  doepint10;           /* ALT_USB_DEV_DOEPINT10 */
    volatile uint32_t  _pad_0x44c_0x44f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz10;          /* ALT_USB_DEV_DOEPTSIZ10 */
    volatile uint32_t  doepdma10;           /* ALT_USB_DEV_DOEPDMA10 */
    volatile uint32_t  _pad_0x458_0x45b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab10;          /* ALT_USB_DEV_DOEPDMAB10 */
    volatile uint32_t  doepctl11;           /* ALT_USB_DEV_DOEPCTL11 */
    volatile uint32_t  _pad_0x464_0x467;    /* *UNDEFINED* */
    volatile uint32_t  doepint11;           /* ALT_USB_DEV_DOEPINT11 */
    volatile uint32_t  _pad_0x46c_0x46f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz11;          /* ALT_USB_DEV_DOEPTSIZ11 */
    volatile uint32_t  doepdma11;           /* ALT_USB_DEV_DOEPDMA11 */
    volatile uint32_t  _pad_0x478_0x47b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab11;          /* ALT_USB_DEV_DOEPDMAB11 */
    volatile uint32_t  doepctl12;           /* ALT_USB_DEV_DOEPCTL12 */
    volatile uint32_t  _pad_0x484_0x487;    /* *UNDEFINED* */
    volatile uint32_t  doepint12;           /* ALT_USB_DEV_DOEPINT12 */
    volatile uint32_t  _pad_0x48c_0x48f;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz12;          /* ALT_USB_DEV_DOEPTSIZ12 */
    volatile uint32_t  doepdma12;           /* ALT_USB_DEV_DOEPDMA12 */
    volatile uint32_t  _pad_0x498_0x49b;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab12;          /* ALT_USB_DEV_DOEPDMAB12 */
    volatile uint32_t  doepctl13;           /* ALT_USB_DEV_DOEPCTL13 */
    volatile uint32_t  _pad_0x4a4_0x4a7;    /* *UNDEFINED* */
    volatile uint32_t  doepint13;           /* ALT_USB_DEV_DOEPINT13 */
    volatile uint32_t  _pad_0x4ac_0x4af;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz13;          /* ALT_USB_DEV_DOEPTSIZ13 */
    volatile uint32_t  doepdma13;           /* ALT_USB_DEV_DOEPDMA13 */
    volatile uint32_t  _pad_0x4b8_0x4bb;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab13;          /* ALT_USB_DEV_DOEPDMAB13 */
    volatile uint32_t  doepctl14;           /* ALT_USB_DEV_DOEPCTL14 */
    volatile uint32_t  _pad_0x4c4_0x4c7;    /* *UNDEFINED* */
    volatile uint32_t  doepint14;           /* ALT_USB_DEV_DOEPINT14 */
    volatile uint32_t  _pad_0x4cc_0x4cf;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz14;          /* ALT_USB_DEV_DOEPTSIZ14 */
    volatile uint32_t  doepdma14;           /* ALT_USB_DEV_DOEPDMA14 */
    volatile uint32_t  _pad_0x4d8_0x4db;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab14;          /* ALT_USB_DEV_DOEPDMAB14 */
    volatile uint32_t  doepctl15;           /* ALT_USB_DEV_DOEPCTL15 */
    volatile uint32_t  _pad_0x4e4_0x4e7;    /* *UNDEFINED* */
    volatile uint32_t  doepint15;           /* ALT_USB_DEV_DOEPINT15 */
    volatile uint32_t  _pad_0x4ec_0x4ef;    /* *UNDEFINED* */
    volatile uint32_t  doeptsiz15;          /* ALT_USB_DEV_DOEPTSIZ15 */
    volatile uint32_t  doepdma15;           /* ALT_USB_DEV_DOEPDMA15 */
    volatile uint32_t  _pad_0x4f8_0x4fb;    /* *UNDEFINED* */
    volatile uint32_t  doepdmab15;          /* ALT_USB_DEV_DOEPDMAB15 */
};

/* The typedef declaration for the raw register contents of register group ALT_USB_DEV. */
typedef volatile struct ALT_USB_DEV_raw_s  ALT_USB_DEV_raw_t;
#endif  /* __ASSEMBLY__ */


/*
 * Register Group : Power and Clock Gating Register - ALT_USB_PWRCLK
 * Power and Clock Gating Register
 * 
 * There is a single register for power and clock gating. It is available in both
 * Host and Device modes.
 * 
 */
/*
 * Register : Power and Clock Gating Control Register - pcgcctl
 * 
 * This register is available in Host and Device modes. The application can use
 * this register to control the core's power-down and clock gating features.
 * Because the CSR module is turned off during power-down, this register is
 * implemented in the AHB Slave BIU module.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description             
 * :-------|:-------|:------|:-------------------------
 *  [0]    | RW     | 0x0   | Stop Pclk               
 *  [2:1]  | ???    | 0x0   | *UNDEFINED*             
 *  [3]    | RW     | 0x0   | Reset Power-Down Modules
 *  [5:4]  | ???    | 0x0   | *UNDEFINED*             
 *  [6]    | R      | 0x0   | PHY In Sleep            
 *  [7]    | R      | 0x0   | Deep Sleep              
 *  [31:8] | ???    | 0x0   | *UNDEFINED*             
 * 
 */
/*
 * Field : Stop Pclk - stoppclk
 * 
 * The application sets this bit to stop the PHY clock (phy_clk) when the USB is
 * suspended, the session is not valid, or the device is disconnected. The
 * application clears this bit when the USB is resumed or a new session starts.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description      
 * :---------------------------------------|:------|:------------------
 *  ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD | 0x0   | Disable Stop Pclk
 *  ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END  | 0x1   | Enable Stop Pclk 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
 * 
 * Disable Stop Pclk
 */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD  0x0
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
 * 
 * Enable Stop Pclk
 */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_MSB        0
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_WIDTH      1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET_MSK    0x00000001
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_CLR_MSK    0xfffffffe
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_RESET      0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Reset Power-Down Modules - rstpdwnmodule
 * 
 * This bit is valid only in Partial Power-Down mode. Theapplication sets this bit
 * when the power is turned off. The application clears this bit after the power is
 * turned on and the PHY clock is up. The R/W of all core registers are possible
 * only when this bit is set to 1b0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description        
 * :-------------------------------------------|:------|:--------------------
 *  ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON  | 0x0   | Power is turned on 
 *  ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF | 0x1   | Power is turned off
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
 * 
 * Power is turned on
 */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON   0x0
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
 * 
 * Power is turned off
 */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF  0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_MSB        3
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_WIDTH      1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET_MSK    0x00000008
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_CLR_MSK    0xfffffff7
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_RESET      0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : PHY In Sleep - physleep
 * 
 * Indicates that the PHY is in Sleep State.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description    
 * :----------------------------------------|:------|:----------------
 *  ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT | 0x0   | Phy non-sleep  
 *  ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT   | 0x1   | Phy sleep state
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
 * 
 * Phy non-sleep
 */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT 0x0
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
 * 
 * Phy sleep state
 */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_MSB        6
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_WIDTH      1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET_MSK    0x00000040
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_CLR_MSK    0xffffffbf
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_RESET      0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Deep Sleep - l1suspended
 * 
 * Indicates that the PHY is in deep sleep when in L1 state.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description      
 * :-------------------------------------------|:------|:------------------
 *  ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT | 0x0   | Non Deep Sleep   
 *  ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT   | 0x1   | Deep Sleep active
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
 * 
 * Non Deep Sleep
 */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT  0x0
/*
 * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
 * 
 * Deep Sleep active
 */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_MSB        7
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_WIDTH      1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET_MSK    0x00000080
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_CLR_MSK    0xffffff7f
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_RESET      0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET(value) (((value) << 7) & 0x00000080)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_USB_PWRCLK_PCGCCTL.
 */
struct ALT_USB_PWRCLK_PCGCCTL_s
{
    uint32_t        stoppclk      :  1;  /* Stop Pclk */
    uint32_t                      :  2;  /* *UNDEFINED* */
    uint32_t        rstpdwnmodule :  1;  /* Reset Power-Down Modules */
    uint32_t                      :  2;  /* *UNDEFINED* */
    const uint32_t  physleep      :  1;  /* PHY In Sleep */
    const uint32_t  l1suspended   :  1;  /* Deep Sleep */
    uint32_t                      : 24;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_USB_PWRCLK_PCGCCTL. */
typedef volatile struct ALT_USB_PWRCLK_PCGCCTL_s  ALT_USB_PWRCLK_PCGCCTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_USB_PWRCLK_PCGCCTL register from the beginning of the component. */
#define ALT_USB_PWRCLK_PCGCCTL_OFST        0x0
/* The address of the ALT_USB_PWRCLK_PCGCCTL register. */
#define ALT_USB_PWRCLK_PCGCCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_PWRCLK_PCGCCTL_OFST))

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_USB_PWRCLK.
 */
struct ALT_USB_PWRCLK_s
{
    volatile ALT_USB_PWRCLK_PCGCCTL_t  pcgcctl;  /* ALT_USB_PWRCLK_PCGCCTL */
};

/* The typedef declaration for register group ALT_USB_PWRCLK. */
typedef volatile struct ALT_USB_PWRCLK_s  ALT_USB_PWRCLK_t;
/* The struct declaration for the raw register contents of register group ALT_USB_PWRCLK. */
struct ALT_USB_PWRCLK_raw_s
{
    volatile uint32_t  pcgcctl;  /* ALT_USB_PWRCLK_PCGCCTL */
};

/* The typedef declaration for the raw register contents of register group ALT_USB_PWRCLK. */
typedef volatile struct ALT_USB_PWRCLK_raw_s  ALT_USB_PWRCLK_raw_t;
#endif  /* __ASSEMBLY__ */


#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_USB.
 */
struct ALT_USB_s
{
    volatile ALT_USB_GLOB_t    globgrp;                    /* ALT_USB_GLOB */
    volatile uint32_t          _pad_0x140_0x3ff[176];      /* *UNDEFINED* */
    volatile ALT_USB_HOST_t    hostgrp;                    /* ALT_USB_HOST */
    volatile uint32_t          _pad_0x6fc_0x7ff[65];       /* *UNDEFINED* */
    volatile ALT_USB_DEV_t     devgrp;                     /* ALT_USB_DEV */
    volatile uint32_t          _pad_0xd00_0xdff[64];       /* *UNDEFINED* */
    volatile ALT_USB_PWRCLK_t  pwrclkgrp;                  /* ALT_USB_PWRCLK */
    volatile uint32_t          _pad_0xe04_0x40000[64639];  /* *UNDEFINED* */
};

/* The typedef declaration for register group ALT_USB. */
typedef volatile struct ALT_USB_s  ALT_USB_t;
/* The struct declaration for the raw register contents of register group ALT_USB. */
struct ALT_USB_raw_s
{
    volatile ALT_USB_GLOB_raw_t    globgrp;                    /* ALT_USB_GLOB */
    volatile uint32_t              _pad_0x140_0x3ff[176];      /* *UNDEFINED* */
    volatile ALT_USB_HOST_raw_t    hostgrp;                    /* ALT_USB_HOST */
    volatile uint32_t              _pad_0x6fc_0x7ff[65];       /* *UNDEFINED* */
    volatile ALT_USB_DEV_raw_t     devgrp;                     /* ALT_USB_DEV */
    volatile uint32_t              _pad_0xd00_0xdff[64];       /* *UNDEFINED* */
    volatile ALT_USB_PWRCLK_raw_t  pwrclkgrp;                  /* ALT_USB_PWRCLK */
    volatile uint32_t              _pad_0xe04_0x40000[64639];  /* *UNDEFINED* */
};

/* The typedef declaration for the raw register contents of register group ALT_USB. */
typedef volatile struct ALT_USB_raw_s  ALT_USB_raw_t;
#endif  /* __ASSEMBLY__ */


#ifdef __cplusplus
}
#endif  /* __cplusplus */
#endif  /* __ALTERA_ALT_USB_H__ */