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/*                  Atmel Microcontroller Software Support                      */
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#ifndef _SAMV71_SPI1_INSTANCE_
#define _SAMV71_SPI1_INSTANCE_

/* ========== Register definition for SPI1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_SPI1_CR                    (0x40058000U) /**< \brief (SPI1) Control Register */
  #define REG_SPI1_MR                    (0x40058004U) /**< \brief (SPI1) Mode Register */
  #define REG_SPI1_RDR                   (0x40058008U) /**< \brief (SPI1) Receive Data Register */
  #define REG_SPI1_TDR                   (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
  #define REG_SPI1_SR                    (0x40058010U) /**< \brief (SPI1) Status Register */
  #define REG_SPI1_IER                   (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
  #define REG_SPI1_IDR                   (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
  #define REG_SPI1_IMR                   (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
  #define REG_SPI1_CSR                   (0x40058030U) /**< \brief (SPI1) Chip Select Register */
  #define REG_SPI1_WPMR                  (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
  #define REG_SPI1_WPSR                  (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
#else
  #define REG_SPI1_CR   (*(__O  uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */
  #define REG_SPI1_MR   (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */
  #define REG_SPI1_RDR  (*(__I  uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */
  #define REG_SPI1_TDR  (*(__O  uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
  #define REG_SPI1_SR   (*(__I  uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */
  #define REG_SPI1_IER  (*(__O  uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
  #define REG_SPI1_IDR  (*(__O  uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
  #define REG_SPI1_IMR  (*(__I  uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
  #define REG_SPI1_CSR  (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */
  #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
  #define REG_SPI1_WPSR (*(__I  uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAMV71_SPI1_INSTANCE_ */