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#ifndef __INCmvSpiSpecH
#define __INCmvSpiSpecH

/* Constants */
#define		MV_SPI_WAIT_RDY_MAX_LOOP			100000
#define		MV_SPI_16_BIT_CHUNK_SIZE			2
#define		MV_SPI_DUMMY_WRITE_16BITS			0xFFFF
#define		MV_SPI_DUMMY_WRITE_8BITS			0xFF

/* Marvell Flash Device Controller Registers */
#define		MV_SPI_CTRLR_OFST					0x10600
#define		MV_SPI_IF_CTRL_REG					(MV_SPI_CTRLR_OFST + 0x00)
#define		MV_SPI_IF_CONFIG_REG				(MV_SPI_CTRLR_OFST + 0x04)
#define		MV_SPI_DATA_OUT_REG					(MV_SPI_CTRLR_OFST + 0x08)
#define		MV_SPI_DATA_IN_REG					(MV_SPI_CTRLR_OFST + 0x0c)
#define		MV_SPI_INT_CAUSE_REG				(MV_SPI_CTRLR_OFST + 0x10)
#define		MV_SPI_INT_CAUSE_MASK_REG			(MV_SPI_CTRLR_OFST + 0x14)

/* Serial Memory Interface Control Register Masks */
#define		MV_SPI_CS_ENABLE_OFFSET				0		/* bit 0 */
#define		MV_SPI_MEMORY_READY_OFFSET			1		/* bit 1 */
#define		MV_SPI_CS_ENABLE_MASK				(0x1  << MV_SPI_CS_ENABLE_OFFSET)
#define		MV_SPI_MEMORY_READY_MASK			(0x1  << MV_SPI_MEMORY_READY_OFFSET)

/* Serial Memory Interface Configuration Register Masks */
#define		MV_SPI_CLK_PRESCALE_OFFSET			0		/* bit 0-4 */
#define		MV_SPI_BYTE_LENGTH_OFFSET			5		/* bit 5 */
#define		MV_SPI_ADDRESS_BURST_LENGTH_OFFSET  8	    /* bit 8-9 */
#define		MV_SPI_CLK_PRESCALE_MASK			(0x1F << MV_SPI_CLK_PRESCALE_OFFSET)
#define		MV_SPI_BYTE_LENGTH_MASK				(0x1  << MV_SPI_BYTE_LENGTH_OFFSET)
#define		MV_SPI_ADDRESS_BURST_LENGTH_MASK	(0x3  << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET)

#endif /* __INCmvSpiSpecH */