/*
 * Copyright (c) 2016, Dialog Semiconductor
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without modification, 
 * are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright notice, 
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation 
 *    and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holder nor the names of its contributors 
 *    may be used to endorse or promote products derived from this software without 
 *    specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
 * INDIRECT, INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL DAMAGES (INCLUDING, 
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * @file     DA14680BA.h
 * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for DA14680BA from Dialog.
 * @version  V1.2
 * @date     9. August 2016
 * @note     Generated with SVDConv V2.87g
 *           from CMSIS SVD File 'DA14680BA.xml'
 *           Version 1.2
 */


/** @addtogroup Dialog
  * @{
  */


/** @addtogroup DA14680BA
  * @{
  */

#ifndef DA14680BA_H
#define DA14680BA_H

#ifdef __cplusplus
extern "C" {
#endif


/* -------------------------  Interrupt Number Definition  ------------------------ */

/**
  * @brief Interrupt Number Definition
  */

typedef enum {
/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
/* --------------------  DA14680BA Specific Interrupt Numbers  -------------------- */
  BLE_WAKEUP_LP_IRQn            =   0,              /*!<   0  BLE_WAKEUP_LP                                                    */
  BLE_GEN_IRQn                  =   1,              /*!<   1  BLE_GEN                                                          */
  FTDF_WAKEUP_IRQn              =   2,              /*!<   2  FTDF_WAKEUP                                                      */
  FTDF_GEN_IRQn                 =   3,              /*!<   3  FTDF_GEN                                                         */
  RFCAL_IRQn                    =   4,              /*!<   4  RFCAL                                                            */
  COEX_IRQn                     =   5,              /*!<   5  COEX                                                             */
  CRYPTO_IRQn                   =   6,              /*!<   6  CRYPTO                                                           */
  MRM_IRQn                      =   7,              /*!<   7  MRM                                                              */
  UART_IRQn                     =   8,              /*!<   8  UART                                                             */
  UART2_IRQn                    =   9,              /*!<   9  UART2                                                            */
  I2C_IRQn                      =  10,              /*!<  10  I2C                                                              */
  I2C2_IRQn                     =  11,              /*!<  11  I2C2                                                             */
  SPI_IRQn                      =  12,              /*!<  12  SPI                                                              */
  SPI2_IRQn                     =  13,              /*!<  13  SPI2                                                             */
  ADC_IRQn                      =  14,              /*!<  14  ADC                                                              */
  KEYBRD_IRQn                   =  15,              /*!<  15  KEYBRD                                                           */
  IRGEN_IRQn                    =  16,              /*!<  16  IRGEN                                                            */
  WKUP_GPIO_IRQn                =  17,              /*!<  17  WKUP_GPIO                                                        */
  SWTIM0_IRQn                   =  18,              /*!<  18  SWTIM0                                                           */
  SWTIM1_IRQn                   =  19,              /*!<  19  SWTIM1                                                           */
  QUADEC_IRQn                   =  20,              /*!<  20  QUADEC                                                           */
  USB_IRQn                      =  21,              /*!<  21  USB                                                              */
  PCM_IRQn                      =  22,              /*!<  22  PCM                                                              */
  SRC_IN_IRQn                   =  23,              /*!<  23  SRC_IN                                                           */
  SRC_OUT_IRQn                  =  24,              /*!<  24  SRC_OUT                                                          */
  VBUS_IRQn                     =  25,              /*!<  25  VBUS                                                             */
  DMA_IRQn                      =  26,              /*!<  26  DMA                                                              */
  RF_DIAG_IRQn                  =  27,              /*!<  27  RF_DIAG                                                          */
  TRNG_IRQn                     =  28,              /*!<  28  TRNG                                                             */
  DCDC_IRQn                     =  29,              /*!<  29  DCDC                                                             */
  XTAL16RDY_IRQn                =  30,              /*!<  30  XTAL16RDY                                                        */
  PLL_LOCK_IRQn                 =  31               /*!<  31  PLL_LOCK                                                         */
} IRQn_Type;


/** @addtogroup Configuration_of_CMSIS_DA14680BA
  * @{
  */


/* ================================================================================ */
/* ================      Processor and Core Peripheral Section     ================ */
/* ================================================================================ */

/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
#define __CM0_REV                 0x0100            /*!< Cortex-M0 Core Revision                                               */
#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
#include "system_DA14680.h"                       /*!< DA14680BA System                                                      */


/* ================================================================================ */
/* ================       Device Specific Peripheral Section       ================ */
/* ================================================================================ */


/** @addtogroup Device_Peripheral_Registers_DA14680BA
  * @{
  */


/* -------------------  Start of section using anonymous unions  ------------------ */
#if defined(__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined(__ICCARM__)
  #pragma language=extended
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning 586
#else
  #warning Not supported compiler type
#endif


/* ================================================================================ */
/* ================                    AES_HASH                    ================ */
/* ================================================================================ */


/**
  * @brief AES_HASH registers (AES_HASH)
  */

typedef struct {                                    /*!< (@ 0x40020000) AES_HASH Structure                                     */
  __IO uint32_t  CRYPTO_CTRL_REG;                   /*!< (@ 0x40020000) Crypto Control register                                */
  __IO uint32_t  CRYPTO_START_REG;                  /*!< (@ 0x40020004) Crypto Start calculation                               */
  __IO uint32_t  CRYPTO_FETCH_ADDR_REG;             /*!< (@ 0x40020008) Crypto DMA fetch register                              */
  __IO uint32_t  CRYPTO_LEN_REG;                    /*!< (@ 0x4002000C) Crypto Length of the input block in bytes              */
  __IO uint32_t  CRYPTO_DEST_ADDR_REG;              /*!< (@ 0x40020010) Crypto DMA destination memory                          */
  __IO uint32_t  CRYPTO_STATUS_REG;                 /*!< (@ 0x40020014) Crypto Status register                                 */
  __IO uint32_t  CRYPTO_CLRIRQ_REG;                 /*!< (@ 0x40020018) Crypto Clear interrupt request                         */
  __IO uint32_t  CRYPTO_MREG0_REG;                  /*!< (@ 0x4002001C) Crypto Mode depended register 0                        */
  __IO uint32_t  CRYPTO_MREG1_REG;                  /*!< (@ 0x40020020) Crypto Mode depended register 1                        */
  __IO uint32_t  CRYPTO_MREG2_REG;                  /*!< (@ 0x40020024) Crypto Mode depended register 2                        */
  __IO uint32_t  CRYPTO_MREG3_REG;                  /*!< (@ 0x40020028) Crypto Mode depended register 3                        */
  __I  uint32_t  RESERVED[53];
  __IO uint32_t  CRYPTO_KEYS_START;                 /*!< (@ 0x40020100) Crypto First position of the AES keys storage
                                                         memory                                                                */
} AES_HASH_Type;


/* ================================================================================ */
/* ================                     ANAMISC                    ================ */
/* ================================================================================ */


/**
  * @brief ANAMISC registers (ANAMISC)
  */

typedef struct {                                    /*!< (@ 0x50001B00) ANAMISC Structure                                      */
  __I  uint16_t  RESERVED;
  __IO uint16_t  ANA_TEST_REG;                      /*!< (@ 0x50001B02) Analog test registers                                  */
  __I  uint32_t  RESERVED1;
  __IO uint16_t  CHARGER_CTRL1_REG;                 /*!< (@ 0x50001B08) Charger control register 1                             */
  __IO uint16_t  CHARGER_CTRL2_REG;                 /*!< (@ 0x50001B0A) Charger control register 2                             */
  __IO uint16_t  CHARGER_STATUS_REG;                /*!< (@ 0x50001B0C) Charger status and trimming register                   */
  __I  uint16_t  RESERVED2[25];
  __IO uint16_t  SOC_CTRL1_REG;                     /*!< (@ 0x50001B40) Fuel Gauge Control register 1                          */
  __IO uint16_t  SOC_CTRL2_REG;                     /*!< (@ 0x50001B42) Fuel Gauge Control register 2                          */
  __IO uint16_t  SOC_CTRL3_REG;                     /*!< (@ 0x50001B44) Fuel Gauge Control register 3                          */
  __IO uint16_t  SOC_ADD2CH_REG;                    /*!< (@ 0x50001B46) Fuel Gauge manually add extra charge to SOC_CHARGE_CNTRx_RE
                                                         G                                                                     */
  __IO uint16_t  SOC_CHARGE_CNTR1_REG;              /*!< (@ 0x50001B48) Fuel Gauge Charge counter bits 15-0                    */
  __IO uint16_t  SOC_CHARGE_CNTR2_REG;              /*!< (@ 0x50001B4A) Fuel Gauge Charge counter bits 31-16                   */
  __IO uint16_t  SOC_CHARGE_CNTR3_REG;              /*!< (@ 0x50001B4C) Fuel Gauge Charge counter bits 39-32                   */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  SOC_CHARGE_AVG_REG;                /*!< (@ 0x50001B50) Fuel Gauge Average charge counter                      */
  __IO uint16_t  SOC_STATUS_REG;                    /*!< (@ 0x50001B52) Fuel Gauge Status register                             */
  __IO uint16_t  SOC_EXT_IN_REG;                    /*!< (@ 0x50001B54) Fuel Gauge input test register                         */
  __IO uint16_t  SOC_EXT_OUT_REG;                   /*!< (@ 0x50001B56) Fuel Gauge output test register                        */
  __I  uint32_t  RESERVED4[2];
  __IO uint16_t  CLK_REF_SEL_REG;                   /*!< (@ 0x50001B60) Select clock for oscillator calibration                */
  __IO uint16_t  CLK_REF_CNT_REG;                   /*!< (@ 0x50001B62) Count value for oscillator calibration                 */
  __IO uint16_t  CLK_REF_VAL_L_REG;                 /*!< (@ 0x50001B64) DIVN reference cycles, lower 16 bits                   */
  __IO uint16_t  CLK_REF_VAL_H_REG;                 /*!< (@ 0x50001B66) DIVN reference cycles, upper 16 bits                   */
} ANAMISC_Type;


/* ================================================================================ */
/* ================                       APU                      ================ */
/* ================================================================================ */


/**
  * @brief APU registers (APU)
  */

typedef struct {                                    /*!< (@ 0x50004000) APU Structure                                          */
  __IO uint32_t  SRC1_CTRL_REG;                     /*!< (@ 0x50004000) SRC1 control register                                  */
  __IO uint32_t  SRC1_IN_FS_REG;                    /*!< (@ 0x50004004) SRC1 Sample input rate                                 */
  __IO uint32_t  SRC1_OUT_FS_REG;                   /*!< (@ 0x50004008) SRC1 Sample output rate                                */
  __IO uint32_t  SRC1_IN1_REG;                      /*!< (@ 0x5000400C) SRC1 data in 1                                         */
  __IO uint32_t  SRC1_IN2_REG;                      /*!< (@ 0x50004010) SRC1 data in 2                                         */
  __IO uint32_t  SRC1_OUT1_REG;                     /*!< (@ 0x50004014) SRC1 data out 1                                        */
  __IO uint32_t  SRC1_OUT2_REG;                     /*!< (@ 0x50004018) SRC1 data out 2                                        */
  __IO uint32_t  APU_MUX_REG;                       /*!< (@ 0x5000401C) APU mux register                                       */
  __IO uint32_t  COEF10_SET1_REG;                   /*!< (@ 0x50004020) SRC coefficient 1,0 set 1                              */
  __IO uint32_t  COEF32_SET1_REG;                   /*!< (@ 0x50004024) SRC coefficient 3,2 set 1                              */
  __IO uint32_t  COEF54_SET1_REG;                   /*!< (@ 0x50004028) SRC coefficient 5,4 set 1                              */
  __IO uint32_t  COEF76_SET1_REG;                   /*!< (@ 0x5000402C) SRC coefficient 7,6 set 1                              */
  __IO uint32_t  COEF98_SET1_REG;                   /*!< (@ 0x50004030) SRC coefficient 9,8 set 1                              */
  __IO uint32_t  COEF0A_SET1_REG;                   /*!< (@ 0x50004034) SRC coefficient 10 set 1                               */
  __I  uint32_t  RESERVED[50];
  __IO uint32_t  PCM1_CTRL_REG;                     /*!< (@ 0x50004100) PCM1 Control register                                  */
  __IO uint32_t  PCM1_IN1_REG;                      /*!< (@ 0x50004104) PCM1 data in 1                                         */
  __IO uint32_t  PCM1_IN2_REG;                      /*!< (@ 0x50004108) PCM1 data in 2                                         */
  __IO uint32_t  PCM1_OUT1_REG;                     /*!< (@ 0x5000410C) PCM1 data out 1                                        */
  __IO uint32_t  PCM1_OUT2_REG;                     /*!< (@ 0x50004110) PCM1 data out 2                                        */
} APU_Type;


/* ================================================================================ */
/* ================                       BLE                      ================ */
/* ================================================================================ */


/**
  * @brief BLE registers (BLE)
  */

typedef struct {                                    /*!< (@ 0x40000000) BLE Structure                                          */
  __IO uint32_t  BLE_RWBLECNTL_REG;                 /*!< (@ 0x40000000) BLE Control register                                   */
  __IO uint32_t  BLE_VERSION_REG;                   /*!< (@ 0x40000004) Version register                                       */
  __IO uint32_t  BLE_RWBLECONF_REG;                 /*!< (@ 0x40000008) Configuration register                                 */
  __IO uint32_t  BLE_INTCNTL_REG;                   /*!< (@ 0x4000000C) Interrupt controller register                          */
  __IO uint32_t  BLE_INTSTAT_REG;                   /*!< (@ 0x40000010) Interrupt status register                              */
  __IO uint32_t  BLE_INTRAWSTAT_REG;                /*!< (@ 0x40000014) Interrupt raw status register                          */
  __IO uint32_t  BLE_INTACK_REG;                    /*!< (@ 0x40000018) Interrupt acknowledge register                         */
  __IO uint32_t  BLE_BASETIMECNT_REG;               /*!< (@ 0x4000001C) Base time reference counter                            */
  __IO uint32_t  BLE_FINETIMECNT_REG;               /*!< (@ 0x40000020) Fine time reference counter                            */
  __IO uint32_t  BLE_BDADDRL_REG;                   /*!< (@ 0x40000024) BLE device address LSB register                        */
  __IO uint32_t  BLE_BDADDRU_REG;                   /*!< (@ 0x40000028) BLE device address MSB register                        */
  __IO uint32_t  BLE_CURRENTRXDESCPTR_REG;          /*!< (@ 0x4000002C) Rx Descriptor Pointer for the Receive Buffer
                                                         Chained List                                                          */
  __IO uint32_t  BLE_DEEPSLCNTL_REG;                /*!< (@ 0x40000030) Deep-Sleep control register                            */
  __IO uint32_t  BLE_DEEPSLWKUP_REG;                /*!< (@ 0x40000034) Time (measured in Low Power clock cycles) in
                                                         Deep Sleep Mode before waking-up the device                           */
  __IO uint32_t  BLE_DEEPSLSTAT_REG;                /*!< (@ 0x40000038) Duration of the last deep sleep phase register         */
  __IO uint32_t  BLE_ENBPRESET_REG;                 /*!< (@ 0x4000003C) Time in low power oscillator cycles register           */
  __IO uint32_t  BLE_FINECNTCORR_REG;               /*!< (@ 0x40000040) Phase correction value register                        */
  __IO uint32_t  BLE_BASETIMECNTCORR_REG;           /*!< (@ 0x40000044) Base Time Counter                                      */
  __I  uint32_t  RESERVED[2];
  __IO uint32_t  BLE_DIAGCNTL_REG;                  /*!< (@ 0x40000050) Diagnostics Register                                   */
  __IO uint32_t  BLE_DIAGSTAT_REG;                  /*!< (@ 0x40000054) Debug use only                                         */
  __IO uint32_t  BLE_DEBUGADDMAX_REG;               /*!< (@ 0x40000058) Upper limit for the memory zone                        */
  __IO uint32_t  BLE_DEBUGADDMIN_REG;               /*!< (@ 0x4000005C) Lower limit for the memory zone                        */
  __IO uint32_t  BLE_ERRORTYPESTAT_REG;             /*!< (@ 0x40000060) Error Type Status registers                            */
  __IO uint32_t  BLE_SWPROFILING_REG;               /*!< (@ 0x40000064) Software Profiling register                            */
  __I  uint32_t  RESERVED1[2];
  __IO uint32_t  BLE_RADIOCNTL0_REG;                /*!< (@ 0x40000070) Radio interface control register                       */
  __IO uint32_t  BLE_RADIOCNTL1_REG;                /*!< (@ 0x40000074) Radio interface control register                       */
  __IO uint32_t  BLE_RADIOCNTL2_REG;                /*!< (@ 0x40000078) Radio interface control register                       */
  __IO uint32_t  BLE_RADIOCNTL3_REG;                /*!< (@ 0x4000007C) Radio interface control register                       */
  __IO uint32_t  BLE_RADIOPWRUPDN_REG;              /*!< (@ 0x40000080) RX/TX power up/down phase register                     */
  __I  uint32_t  RESERVED2[3];
  __IO uint32_t  BLE_ADVCHMAP_REG;                  /*!< (@ 0x40000090) Advertising Channel Map                                */
  __I  uint32_t  RESERVED3[3];
  __IO uint32_t  BLE_ADVTIM_REG;                    /*!< (@ 0x400000A0) Advertising Packet Interval                            */
  __IO uint32_t  BLE_ACTSCANSTAT_REG;               /*!< (@ 0x400000A4) Active scan register                                   */
  __I  uint32_t  RESERVED4[2];
  __IO uint32_t  BLE_WLPUBADDPTR_REG;               /*!< (@ 0x400000B0) Start address of public devices list                   */
  __IO uint32_t  BLE_WLPRIVADDPTR_REG;              /*!< (@ 0x400000B4) Start address of private devices list                  */
  __IO uint32_t  BLE_WLNBDEV_REG;                   /*!< (@ 0x400000B8) Devices in white list                                  */
  __I  uint32_t  RESERVED5;
  __IO uint32_t  BLE_AESCNTL_REG;                   /*!< (@ 0x400000C0) Start AES register                                     */
  __IO uint32_t  BLE_AESKEY31_0_REG;                /*!< (@ 0x400000C4) AES encryption key                                     */
  __IO uint32_t  BLE_AESKEY63_32_REG;               /*!< (@ 0x400000C8) AES encryption key                                     */
  __IO uint32_t  BLE_AESKEY95_64_REG;               /*!< (@ 0x400000CC) AES encryption key                                     */
  __IO uint32_t  BLE_AESKEY127_96_REG;              /*!< (@ 0x400000D0) AES encryption key                                     */
  __IO uint32_t  BLE_AESPTR_REG;                    /*!< (@ 0x400000D4) Pointer to the block to encrypt/decrypt                */
  __IO uint32_t  BLE_TXMICVAL_REG;                  /*!< (@ 0x400000D8) AES / CCM plain MIC value                              */
  __IO uint32_t  BLE_RXMICVAL_REG;                  /*!< (@ 0x400000DC) AES / CCM plain MIC value                              */
  __IO uint32_t  BLE_RFTESTCNTL_REG;                /*!< (@ 0x400000E0) RF Testing Register                                    */
  __IO uint32_t  BLE_RFTESTTXSTAT_REG;              /*!< (@ 0x400000E4) RF Testing Register                                    */
  __IO uint32_t  BLE_RFTESTRXSTAT_REG;              /*!< (@ 0x400000E8) RF Testing Register                                    */
  __I  uint32_t  RESERVED6;
  __IO uint32_t  BLE_TIMGENCNTL_REG;                /*!< (@ 0x400000F0) Timing Generator Register                              */
  __IO uint32_t  BLE_GROSSTIMTGT_REG;               /*!< (@ 0x400000F4) Gross Timer Target value                               */
  __IO uint32_t  BLE_FINETIMTGT_REG;                /*!< (@ 0x400000F8) Fine Timer Target value                                */
  __IO uint32_t  BLE_SAMPLECLK_REG;                 /*!< (@ 0x400000FC) Samples the Base Time Counter                          */
  __IO uint32_t  BLE_COEXIFCNTL0_REG;               /*!< (@ 0x40000100) Coexistence interface Control 0 Register               */
  __IO uint32_t  BLE_COEXIFCNTL1_REG;               /*!< (@ 0x40000104) Coexistence interface Control 1 Register               */
  __IO uint32_t  BLE_BLEMPRIO0_REG;                 /*!< (@ 0x40000108) Coexistence interface Priority 0 Register              */
  __IO uint32_t  BLE_BLEMPRIO1_REG;                 /*!< (@ 0x4000010C) Coexistence interface Priority 1 Register              */
  __I  uint32_t  RESERVED7[60];
  __IO uint32_t  BLE_CNTL2_REG;                     /*!< (@ 0x40000200) BLE Control Register 2                                 */
  __I  uint32_t  RESERVED8;
  __IO uint32_t  BLE_EM_BASE_REG;                   /*!< (@ 0x40000208) Exchange Memory Base Register                          */
  __IO uint32_t  BLE_DIAGCNTL2_REG;                 /*!< (@ 0x4000020C) Debug use only                                         */
  __IO uint32_t  BLE_DIAGCNTL3_REG;                 /*!< (@ 0x40000210) Debug use only                                         */
} BLE_Type;


/* ================================================================================ */
/* ================                      CACHE                     ================ */
/* ================================================================================ */


/**
  * @brief CACHE registers (CACHE)
  */

typedef struct {                                    /*!< (@ 0x400C3000) CACHE Structure                                        */
  __IO uint32_t  CACHE_CTRL1_REG;                   /*!< (@ 0x400C3000) Cache control register 1                               */
  __IO uint32_t  CACHE_LNSIZECFG_REG;               /*!< (@ 0x400C3004) Cache line size configuration register                 */
  __IO uint32_t  CACHE_ASSOCCFG_REG;                /*!< (@ 0x400C3008) Cache associativity configuration register             */
  __I  uint32_t  RESERVED[5];
  __IO uint32_t  CACHE_CTRL2_REG;                   /*!< (@ 0x400C3020) Cache control register 2                               */
  __IO uint32_t  CACHE_CTRL3_REG;                   /*!< (@ 0x400C3024) Cache control register 3 (for the Cache Controller
                                                         configuration reset values)                                           */
  __IO uint32_t  CACHE_MRM_HITS_REG;                /*!< (@ 0x400C3028) Cache MRM (Miss Rate Monitor) HITS register            */
  __IO uint32_t  CACHE_MRM_MISSES_REG;              /*!< (@ 0x400C302C) Cache MRM (Miss Rate Monitor) MISSES register          */
  __IO uint32_t  CACHE_MRM_CTRL_REG;                /*!< (@ 0x400C3030) Cache MRM (Miss Rate Monitor) CONTROL register         */
  __IO uint32_t  CACHE_MRM_TINT_REG;                /*!< (@ 0x400C3034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register   */
  __IO uint32_t  CACHE_MRM_THRES_REG;               /*!< (@ 0x400C3038) Cache MRM (Miss Rate Monitor) THRESHOLD register       */
  __I  uint32_t  RESERVED1[5];
  __IO uint32_t  SWD_RESET_REG;                     /*!< (@ 0x400C3050) SWD HW reset control register                          */
} CACHE_Type;


/* ================================================================================ */
/* ================                  CHIP_VERSION                  ================ */
/* ================================================================================ */


/**
  * @brief CHIP_VERSION registers (CHIP_VERSION)
  */

typedef struct {                                    /*!< (@ 0x50003200) CHIP_VERSION Structure                                 */
  __IO uint8_t   CHIP_ID1_REG;                      /*!< (@ 0x50003200) Chip identification register 1.                        */
  __IO uint8_t   CHIP_ID2_REG;                      /*!< (@ 0x50003201) Chip identification register 2.                        */
  __IO uint8_t   CHIP_ID3_REG;                      /*!< (@ 0x50003202) Chip identification register 3.                        */
  __IO uint8_t   CHIP_SWC_REG;                      /*!< (@ 0x50003203) Software compatibility register.                       */
  __IO uint8_t   CHIP_REVISION_REG;                 /*!< (@ 0x50003204) Chip revision register.                                */
  __IO uint8_t   CHIP_CONFIG1_REG;                  /*!< (@ 0x50003205) Chip configuration register 1.                         */
  __IO uint8_t   CHIP_CONFIG2_REG;                  /*!< (@ 0x50003206) Chip configuration register 2.                         */
  __IO uint8_t   CHIP_CONFIG3_REG;                  /*!< (@ 0x50003207) Chip configuration register 3.                         */
  __I  uint16_t  RESERVED;
  __IO uint8_t   CHIP_TEST1_REG;                    /*!< (@ 0x5000320A) Chip test register 1.                                  */
  __IO uint8_t   CHIP_TEST2_REG;                    /*!< (@ 0x5000320B) Chip test register 2.                                  */
  __IO uint8_t   CHIP_TEST3_REG;                    /*!< (@ 0x5000320C) Chip test register 3.                                  */
} CHIP_VERSION_Type;


/* ================================================================================ */
/* ================                      COEX                      ================ */
/* ================================================================================ */


/**
  * @brief COEX registers (COEX)
  */

typedef struct {                                    /*!< (@ 0x50002F00) COEX Structure                                         */
  __IO uint16_t  COEX_CTRL_REG;                     /*!< (@ 0x50002F00) COEX Control Register                                  */
  __IO uint16_t  COEX_STAT_REG;                     /*!< (@ 0x50002F02) COEX Status Register                                   */
  __IO uint16_t  COEX_STAT2_REG;                    /*!< (@ 0x50002F04) COEX Status 2 Register                                 */
  __IO uint16_t  COEX_INT_MASK_REG;                 /*!< (@ 0x50002F06) COEX Interrupt Mask Register                           */
  __IO uint16_t  COEX_INT_STAT_REG;                 /*!< (@ 0x50002F08) COEX Interrupt Status Register                         */
  __IO uint16_t  COEX_BLE_PTI_REG;                  /*!< (@ 0x50002F0A) COEX BLE PTI Control Register                          */
  __IO uint16_t  COEX_FTDF_PTI_REG;                 /*!< (@ 0x50002F0C) COEX FTDF PTI Control Register                         */
  __I  uint16_t  RESERVED[2];
  __IO uint16_t  COEX_PRI1_REG;                     /*!< (@ 0x50002F12) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI2_REG;                     /*!< (@ 0x50002F14) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI3_REG;                     /*!< (@ 0x50002F16) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI4_REG;                     /*!< (@ 0x50002F18) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI5_REG;                     /*!< (@ 0x50002F1A) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI6_REG;                     /*!< (@ 0x50002F1C) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI7_REG;                     /*!< (@ 0x50002F1E) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI8_REG;                     /*!< (@ 0x50002F20) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI9_REG;                     /*!< (@ 0x50002F22) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI10_REG;                    /*!< (@ 0x50002F24) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI11_REG;                    /*!< (@ 0x50002F26) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI12_REG;                    /*!< (@ 0x50002F28) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI13_REG;                    /*!< (@ 0x50002F2A) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI14_REG;                    /*!< (@ 0x50002F2C) COEX Priority Register                                 */
  __IO uint16_t  COEX_PRI15_REG;                    /*!< (@ 0x50002F2E) COEX Priority Register                                 */
} COEX_Type;


/* ================================================================================ */
/* ================                     CRG_PER                    ================ */
/* ================================================================================ */


/**
  * @brief CRG_PER registers (CRG_PER)
  */

typedef struct {                                    /*!< (@ 0x50001C00) CRG_PER Structure                                      */
  __I  uint32_t  RESERVED;
  __IO uint16_t  CLK_PER_REG;                       /*!< (@ 0x50001C04) Peripheral divider register                            */
  __I  uint16_t  RESERVED1[29];
  __IO uint16_t  PCM_DIV_REG;                       /*!< (@ 0x50001C40) PCM divider and enables                                */
  __IO uint16_t  PCM_FDIV_REG;                      /*!< (@ 0x50001C42) PCM fractional division register                       */
  __IO uint16_t  PDM_DIV_REG;                       /*!< (@ 0x50001C44) PDM divider and enables                                */
  __IO uint16_t  SRC_DIV_REG;                       /*!< (@ 0x50001C46) SRC divider and enables                                */
  __IO uint16_t  EH_REG;                            /*!< (@ 0x50001C48) EH_REG                                                 */
  __IO uint16_t  USBPAD_REG;                        /*!< (@ 0x50001C4A) USB pads control register                              */
} CRG_PER_Type;


/* ================================================================================ */
/* ================                     CRG_TOP                    ================ */
/* ================================================================================ */


/**
  * @brief CRG_TOP registers (CRG_TOP)
  */

typedef struct {                                    /*!< (@ 0x50000000) CRG_TOP Structure                                      */
  __IO uint16_t  CLK_AMBA_REG;                      /*!< (@ 0x50000000) HCLK, PCLK, divider and clock gates                    */
  __IO uint16_t  CLK_FREQ_TRIM_REG;                 /*!< (@ 0x50000002) Xtal frequency trimming register.                      */
  __I  uint32_t  RESERVED;
  __IO uint16_t  CLK_RADIO_REG;                     /*!< (@ 0x50000008) Radio PLL control register                             */
  __IO uint16_t  CLK_CTRL_REG;                      /*!< (@ 0x5000000A) Clock control register                                 */
  __IO uint16_t  CLK_TMR_REG;                       /*!< (@ 0x5000000C) Clock control for the timers                           */
  __I  uint16_t  RESERVED1;
  __IO uint16_t  PMU_CTRL_REG;                      /*!< (@ 0x50000010) Power Management Unit control register                 */
  __IO uint16_t  SYS_CTRL_REG;                      /*!< (@ 0x50000012) System Control register                                */
  __IO uint16_t  SYS_STAT_REG;                      /*!< (@ 0x50000014) System status register                                 */
  __IO uint16_t  TRIM_CTRL_REG;                     /*!< (@ 0x50000016) Control trimming of the XTAL16M                        */
  __I  uint32_t  RESERVED2[2];
  __IO uint16_t  CLK_32K_REG;                       /*!< (@ 0x50000020) 32 kHz oscillator register                             */
  __IO uint16_t  CLK_16M_REG;                       /*!< (@ 0x50000022) 16 MHz RC and xtal oscillator register                 */
  __IO uint16_t  CLK_RCX20K_REG;                    /*!< (@ 0x50000024) 20KHz RXC-oscillator control register                  */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  BANDGAP_REG;                       /*!< (@ 0x50000028) bandgap trimming                                       */
  __IO uint16_t  ANA_STATUS_REG;                    /*!< (@ 0x5000002A) status bit of analog (power management) circuits       */
  __IO uint16_t  STARTUP_STATUS_REG;                /*!< (@ 0x5000002C) Startup timeout bits                                   */
  __I  uint16_t  RESERVED4;
  __IO uint16_t  VBUS_IRQ_MASK_REG;                 /*!< (@ 0x50000030) IRQ masking                                            */
  __IO uint16_t  VBUS_IRQ_CLEAR_REG;                /*!< (@ 0x50000032) Clear pending IRQ register                             */
  __IO uint16_t  BOD_CTRL_REG;                      /*!< (@ 0x50000034) Brown Out Detection control register                   */
  __IO uint16_t  BOD_CTRL2_REG;                     /*!< (@ 0x50000036) Brown Out Detection control register                   */
  __IO uint16_t  BOD_STATUS_REG;                    /*!< (@ 0x50000038) Brown Out Detection status register                    */
  __IO uint16_t  LDO_CTRL1_REG;                     /*!< (@ 0x5000003A) LDO control register                                   */
  __IO uint16_t  LDO_CTRL2_REG;                     /*!< (@ 0x5000003C) LDO control register                                   */
  __IO uint16_t  SLEEP_TIMER_REG;                   /*!< (@ 0x5000003E) Timer for regulated sleep                              */
  __IO uint16_t  POWER_CTRL_REG;                    /*!< (@ 0x50000040) Power control register                                 */
  __IO uint16_t  POR_VBAT_CTRL_REG;                 /*!< (@ 0x50000042) Controls the POR on VBAT                               */
  __I  uint32_t  RESERVED5[3];
  __IO uint16_t  XTALRDY_CTRL_REG;                  /*!< (@ 0x50000050) Control register for XTALRDY IRQ                       */
  __IO uint16_t  XTALRDY_STAT_REG;                  /*!< (@ 0x50000052) Difference between XTAL_OK and XTALRDY_IRQ in
                                                         LP clock cycles                                                       */
  __IO uint16_t  LDO_CTRL3_REG;                     /*!< (@ 0x50000054) Retention LDO control register                         */
  __I  uint16_t  RESERVED6;
  __IO uint16_t  XTAL16M_START_REG;                 /*!< (@ 0x50000058) Xtal frequency trimming register during startup        */
  __IO uint16_t  XTAL16M_RAMP_REG;                  /*!< (@ 0x5000005A) Xtal frequency trimming register during ramping        */
  __IO uint16_t  XTAL16M_TRSTAT_REG;                /*!< (@ 0x5000005C) Read back value of current XTAL trimming               */
  __IO uint16_t  RESET_STAT_REG;                    /*!< (@ 0x5000005E) Reset status register                                  */
  __IO uint16_t  FORCE_SLEEP_REG;                   /*!< (@ 0x50000060) Force FTDF/BLE to sleep                                */
  __IO uint16_t  LDOS_DISABLE_REG;                  /*!< (@ 0x50000062) Force off all LDOs                                     */
  __IO uint16_t  AON_SPARE_REG;                     /*!< (@ 0x50000064) Spare register                                         */
  __IO uint16_t  SECURE_BOOT_REG;                   /*!< (@ 0x50000066) Controls secure booting                                */
  __IO uint16_t  PMU_RESET_RAIL_REG;                /*!< (@ 0x50000068) Controls rail resetting when RST is pulsed             */
  __IO uint16_t  DISCHARGE_RAIL_REG;                /*!< (@ 0x5000006A) Immediate rail resetting. There is no LDO/DCDC
                                                         gating                                                                */
} CRG_TOP_Type;


/* ================================================================================ */
/* ================                      DCDC                      ================ */
/* ================================================================================ */


/**
  * @brief DCDC registers (DCDC)
  */

typedef struct {                                    /*!< (@ 0x50000080) DCDC Structure                                         */
  __I  uint16_t  RESERVED;
  __IO uint16_t  DCDC_CTRL_0_REG;                   /*!< (@ 0x50000082) DCDC First Control Register                            */
  __IO uint16_t  DCDC_CTRL_1_REG;                   /*!< (@ 0x50000084) DCDC Second Control Register                           */
  __IO uint16_t  DCDC_CTRL_2_REG;                   /*!< (@ 0x50000086) DCDC Third Control Register                            */
  __IO uint16_t  DCDC_V14_0_REG;                    /*!< (@ 0x50000088) DCDC V14 First Control Register                        */
  __IO uint16_t  DCDC_V14_1_REG;                    /*!< (@ 0x5000008A) DCDC V14 Second Control Register                       */
  __IO uint16_t  DCDC_V18_0_REG;                    /*!< (@ 0x5000008C) DCDC V18 First Control Register                        */
  __IO uint16_t  DCDC_V18_1_REG;                    /*!< (@ 0x5000008E) DCDC V18 Second Control Register                       */
  __IO uint16_t  DCDC_VDD_0_REG;                    /*!< (@ 0x50000090) DCDC VDD First Control Register                        */
  __IO uint16_t  DCDC_VDD_1_REG;                    /*!< (@ 0x50000092) DCDC VDD Second Control Register                       */
  __IO uint16_t  DCDC_V18P_0_REG;                   /*!< (@ 0x50000094) DCDC VPA First Control Register                        */
  __IO uint16_t  DCDC_V18P_1_REG;                   /*!< (@ 0x50000096) DCDC VPA Second Control Register                       */
  __IO uint16_t  DCDC_RET_0_REG;                    /*!< (@ 0x50000098) DCDC First Retention Mode Register                     */
  __IO uint16_t  DCDC_RET_1_REG;                    /*!< (@ 0x5000009A) DCDC Second Retention Mode Register                    */
  __IO uint16_t  DCDC_TRIM_REG;                     /*!< (@ 0x5000009C) DCDC Comparator Trim Register                          */
  __IO uint16_t  DCDC_TEST_0_REG;                   /*!< (@ 0x5000009E) DCDC Test Register                                     */
  __IO uint16_t  DCDC_TEST_1_REG;                   /*!< (@ 0x500000A0) DCDC Test Register                                     */
  __IO uint16_t  DCDC_STATUS_0_REG;                 /*!< (@ 0x500000A2) DCDC First Status Register                             */
  __IO uint16_t  DCDC_STATUS_1_REG;                 /*!< (@ 0x500000A4) DCDC Second Status Register                            */
  __IO uint16_t  DCDC_STATUS_2_REG;                 /*!< (@ 0x500000A6) DCDC Third Status Register                             */
  __IO uint16_t  DCDC_STATUS_3_REG;                 /*!< (@ 0x500000A8) DCDC Fourth Status Register                            */
  __IO uint16_t  DCDC_STATUS_4_REG;                 /*!< (@ 0x500000AA) DCDC Fifth Status Register                             */
  __IO uint16_t  DCDC_TRIM_0_REG;                   /*!< (@ 0x500000AC) DCDC V14 Comparator Trim Register                      */
  __IO uint16_t  DCDC_TRIM_1_REG;                   /*!< (@ 0x500000AE) DCDC V18 Comparator Trim Register                      */
  __IO uint16_t  DCDC_TRIM_2_REG;                   /*!< (@ 0x500000B0) DCDC VDD Comparator Trim Register                      */
  __IO uint16_t  DCDC_TRIM_3_REG;                   /*!< (@ 0x500000B2) DCDC VPA Comparator Trim Register                      */
  __IO uint16_t  DCDC_IRQ_STATUS_REG;               /*!< (@ 0x500000B4) DCDC Interrupt Status Register                         */
  __IO uint16_t  DCDC_IRQ_CLEAR_REG;                /*!< (@ 0x500000B6) DCDC Interrupt Clear Register                          */
  __IO uint16_t  DCDC_IRQ_MASK_REG;                 /*!< (@ 0x500000B8) DCDC Interrupt Clear Register                          */
} DCDC_Type;


/* ================================================================================ */
/* ================                       DEM                      ================ */
/* ================================================================================ */


/**
  * @brief DEM registers (DEM)
  */

typedef struct {                                    /*!< (@ 0x50002E00) DEM Structure                                          */
  __IO uint16_t  RF_DEM_CTRL_REG;                   /*!< (@ 0x50002E00) RF_DEM_CTRL_REG                                        */
  __IO uint16_t  RF_AGC_LUT_01_REG;                 /*!< (@ 0x50002E02) RF_AGC_LUT_01_REG                                      */
  __IO uint16_t  RF_AGC_LUT_23_REG;                 /*!< (@ 0x50002E04) RF_AGC_LUT_23_REG                                      */
  __IO uint16_t  RF_AGC_LUT_45_REG;                 /*!< (@ 0x50002E06) RF_AGC_LUT_45_REG                                      */
  __IO uint16_t  RF_AGC_LUT_67_REG;                 /*!< (@ 0x50002E08) RF_AGC_LUT_67_REG                                      */
  __IO uint16_t  RF_AGC_LUT_89_REG;                 /*!< (@ 0x50002E0A) RF_AGC_LUT_89_REG                                      */
  __IO uint16_t  RF_AGC_CTRL1_REG;                  /*!< (@ 0x50002E0C) RF_AGC_CTRL1_REG                                       */
  __IO uint16_t  RF_AGC_CTRL2_REG;                  /*!< (@ 0x50002E0E) RF_AGC_CTRL2_REG                                       */
  __IO uint16_t  RF_AFC_CTRL_REG;                   /*!< (@ 0x50002E10) RF_AFC_CTRL_REG                                        */
  __IO uint16_t  RF_DC_OFFSET_CTRL1_REG;            /*!< (@ 0x50002E12) RF_DC_OFFSET_CTRL1_REG                                 */
  __IO uint16_t  RF_DC_OFFSET_CTRL2_REG;            /*!< (@ 0x50002E14) RF_DC_OFFSET_CTRL2_REG                                 */
  __IO uint16_t  RF_DC_OFFSET_CTRL3_REG;            /*!< (@ 0x50002E16) RF_DC_OFFSET_CTRL3_REG                                 */
  __IO uint16_t  RF_DC_OFFSET_CTRL4_REG;            /*!< (@ 0x50002E18) RF_DC_OFFSET_CTRL4_REG                                 */
  __I  uint16_t  RESERVED;
  __IO uint16_t  RF_AGC_RESULT_REG;                 /*!< (@ 0x50002E1C) RF_AGC_RESULT_REG                                      */
  __IO uint16_t  RF_RSSI_RESULT_REG;                /*!< (@ 0x50002E1E) RF_RSSI_RESULT_REG                                     */
  __IO uint16_t  RF_DC_OFFSET_RESULT_REG;           /*!< (@ 0x50002E20) Must be Retained                                       */
  __IO uint16_t  RF_RSSI_COMP_CTRL_REG;             /*!< (@ 0x50002E22) RF_RSSI_COMP_CTRL_REG                                  */
  __I  uint32_t  RESERVED1[3];
  __IO uint16_t  RF_FTDF_CTRL1_REG;                 /*!< (@ 0x50002E30) RF_FTDF_CTRL1_REG                                      */
  __IO uint16_t  RF_FTDF_CTRL2_REG;                 /*!< (@ 0x50002E32) RF_FTDF_CTRL2_REG                                      */
  __IO uint16_t  RF_FTDF_CTRL3_REG;                 /*!< (@ 0x50002E34) RF_FTDF_CTRL3_REG                                      */
  __IO uint16_t  RF_FTDF_CTRL4_REG;                 /*!< (@ 0x50002E36) RF_FTDF_CTRL4_REG                                      */
  __IO uint16_t  RF_FTDF_LOOP_GAIN_PD_REG;          /*!< (@ 0x50002E38) RF_FTDF_LOOP_GAIN_PD_REG                               */
  __IO uint16_t  RF_FTDF_LOOP_GAIN_DS_REG;          /*!< (@ 0x50002E3A) RF_FTDF_LOOP_GAIN_DS_REG                               */
  __IO uint16_t  RF_FTDF_CTRL5_REG;                 /*!< (@ 0x50002E3C) RF_FTDF_CTRL5_REG                                      */
  __IO uint16_t  RF_FTDF_COBI_LOW_REG;              /*!< (@ 0x50002E3E) RF_FTDF_COBI_LOW_REG                                   */
  __IO uint16_t  RF_FTDF_COBI_HIGH_REG;             /*!< (@ 0x50002E40) RF_FTDF_COBI_HIGH_REG                                  */
  __IO uint16_t  RF_DEM_TESTMODE_REG;               /*!< (@ 0x50002E42) RF_DEM_TESTMODE_REG                                    */
  __IO uint16_t  RF_DEM_IQCORRECT_REG;              /*!< (@ 0x50002E44) RF_DEM_IQCORRECT_REG                                   */
  __IO uint16_t  RF_PAD_CNT_CTRL_REG;               /*!< (@ 0x50002E46) RF_PAD_CNT_CTRL_REG                                    */
  __IO uint16_t  RF_PAD_CNT_RESULT_REG;             /*!< (@ 0x50002E48) RF_PAD_CNT_RESULT_REG                                  */
  __I  uint16_t  RESERVED2[3];
  __IO uint16_t  RF_FSSS_I_RESULT_REG;              /*!< (@ 0x50002E50) RF_FSSS_I_RESULT_REG                                   */
  __IO uint16_t  RF_FSSS_Q_RESULT_REG;              /*!< (@ 0x50002E52) RF_FSSS_Q_RESULT_REG                                   */
  __IO uint16_t  RF_FSSS_MAG_RESULT_REG;            /*!< (@ 0x50002E54) RF_FSSS_MAG_RESULT_REG                                 */
  __IO uint16_t  RF_CCA_RSSITH_REG;                 /*!< (@ 0x50002E56) RF_CCA_RSSITH_REG                                      */
  __IO uint16_t  RF_FTDF_SIGDET_CTRL_REG;           /*!< (@ 0x50002E58) RF_FTDF_SIGDET_CTRL_REG                                */
} DEM_Type;


/* ================================================================================ */
/* ================                       DMA                      ================ */
/* ================================================================================ */


/**
  * @brief DMA registers (DMA)
  */

typedef struct {                                    /*!< (@ 0x50003500) DMA Structure                                          */
  __IO uint16_t  DMA0_A_STARTL_REG;                 /*!< (@ 0x50003500) Start address Low A of DMA channel 0                   */
  __IO uint16_t  DMA0_A_STARTH_REG;                 /*!< (@ 0x50003502) Start address High A of DMA channel 0                  */
  __IO uint16_t  DMA0_B_STARTL_REG;                 /*!< (@ 0x50003504) Start address Low B of DMA channel 0                   */
  __IO uint16_t  DMA0_B_STARTH_REG;                 /*!< (@ 0x50003506) Start address High B of DMA channel 0                  */
  __IO uint16_t  DMA0_INT_REG;                      /*!< (@ 0x50003508) DMA receive interrupt register channel 0               */
  __IO uint16_t  DMA0_LEN_REG;                      /*!< (@ 0x5000350A) DMA receive length register channel 0                  */
  __IO uint16_t  DMA0_CTRL_REG;                     /*!< (@ 0x5000350C) Control register for the DMA channel 0                 */
  __IO uint16_t  DMA0_IDX_REG;                      /*!< (@ 0x5000350E) Index value of DMA channel 0                           */
  __IO uint16_t  DMA1_A_STARTL_REG;                 /*!< (@ 0x50003510) Start address Low A of DMA channel 1                   */
  __IO uint16_t  DMA1_A_STARTH_REG;                 /*!< (@ 0x50003512) Start address High A of DMA channel 1                  */
  __IO uint16_t  DMA1_B_STARTL_REG;                 /*!< (@ 0x50003514) Start address Low B of DMA channel 1                   */
  __IO uint16_t  DMA1_B_STARTH_REG;                 /*!< (@ 0x50003516) Start address High B of DMA channel 1                  */
  __IO uint16_t  DMA1_INT_REG;                      /*!< (@ 0x50003518) DMA receive interrupt register channel 1               */
  __IO uint16_t  DMA1_LEN_REG;                      /*!< (@ 0x5000351A) DMA receive length register channel 1                  */
  __IO uint16_t  DMA1_CTRL_REG;                     /*!< (@ 0x5000351C) Control register for the DMA channel 1                 */
  __IO uint16_t  DMA1_IDX_REG;                      /*!< (@ 0x5000351E) Index value of DMA channel 1                           */
  __IO uint16_t  DMA2_A_STARTL_REG;                 /*!< (@ 0x50003520) Start address Low A of DMA channel 2                   */
  __IO uint16_t  DMA2_A_STARTH_REG;                 /*!< (@ 0x50003522) Start address High A of DMA channel 2                  */
  __IO uint16_t  DMA2_B_STARTL_REG;                 /*!< (@ 0x50003524) Start address Low B of DMA channel 2                   */
  __IO uint16_t  DMA2_B_STARTH_REG;                 /*!< (@ 0x50003526) Start address High B of DMA channel 2                  */
  __IO uint16_t  DMA2_INT_REG;                      /*!< (@ 0x50003528) DMA receive interrupt register channel 2               */
  __IO uint16_t  DMA2_LEN_REG;                      /*!< (@ 0x5000352A) DMA receive length register channel 2                  */
  __IO uint16_t  DMA2_CTRL_REG;                     /*!< (@ 0x5000352C) Control register for the DMA channel 2                 */
  __IO uint16_t  DMA2_IDX_REG;                      /*!< (@ 0x5000352E) Index value of DMA channel 2                           */
  __IO uint16_t  DMA3_A_STARTL_REG;                 /*!< (@ 0x50003530) Start address Low A of DMA channel 3                   */
  __IO uint16_t  DMA3_A_STARTH_REG;                 /*!< (@ 0x50003532) Start address High A of DMA channel 3                  */
  __IO uint16_t  DMA3_B_STARTL_REG;                 /*!< (@ 0x50003534) Start address Low B of DMA channel 3                   */
  __IO uint16_t  DMA3_B_STARTH_REG;                 /*!< (@ 0x50003536) Start address High B of DMA channel 3                  */
  __IO uint16_t  DMA3_INT_REG;                      /*!< (@ 0x50003538) DMA receive interrupt register channel 3               */
  __IO uint16_t  DMA3_LEN_REG;                      /*!< (@ 0x5000353A) DMA receive length register channel 3                  */
  __IO uint16_t  DMA3_CTRL_REG;                     /*!< (@ 0x5000353C) Control register for the DMA channel 3                 */
  __IO uint16_t  DMA3_IDX_REG;                      /*!< (@ 0x5000353E) Index value of DMA channel 3                           */
  __IO uint16_t  DMA4_A_STARTL_REG;                 /*!< (@ 0x50003540) Start address Low A of DMA channel 4                   */
  __IO uint16_t  DMA4_A_STARTH_REG;                 /*!< (@ 0x50003542) Start address High A of DMA channel 4                  */
  __IO uint16_t  DMA4_B_STARTL_REG;                 /*!< (@ 0x50003544) Start address Low B of DMA channel 4                   */
  __IO uint16_t  DMA4_B_STARTH_REG;                 /*!< (@ 0x50003546) Start address High B of DMA channel 4                  */
  __IO uint16_t  DMA4_INT_REG;                      /*!< (@ 0x50003548) DMA receive interrupt register channel 4               */
  __IO uint16_t  DMA4_LEN_REG;                      /*!< (@ 0x5000354A) DMA receive length register channel 4                  */
  __IO uint16_t  DMA4_CTRL_REG;                     /*!< (@ 0x5000354C) Control register for the DMA channel 4                 */
  __IO uint16_t  DMA4_IDX_REG;                      /*!< (@ 0x5000354E) Index value of DMA channel 4                           */
  __IO uint16_t  DMA5_A_STARTL_REG;                 /*!< (@ 0x50003550) Start address Low A of DMA channel 5                   */
  __IO uint16_t  DMA5_A_STARTH_REG;                 /*!< (@ 0x50003552) Start address High A of DMA channel 5                  */
  __IO uint16_t  DMA5_B_STARTL_REG;                 /*!< (@ 0x50003554) Start address Low B of DMA channel 5                   */
  __IO uint16_t  DMA5_B_STARTH_REG;                 /*!< (@ 0x50003556) Start address High B of DMA channel 5                  */
  __IO uint16_t  DMA5_INT_REG;                      /*!< (@ 0x50003558) DMA receive interrupt register channel 5               */
  __IO uint16_t  DMA5_LEN_REG;                      /*!< (@ 0x5000355A) DMA receive length register channel 5                  */
  __IO uint16_t  DMA5_CTRL_REG;                     /*!< (@ 0x5000355C) Control register for the DMA channel 5                 */
  __IO uint16_t  DMA5_IDX_REG;                      /*!< (@ 0x5000355E) Index value of DMA channel 5                           */
  __IO uint16_t  DMA6_A_STARTL_REG;                 /*!< (@ 0x50003560) Start address Low A of DMA channel 6                   */
  __IO uint16_t  DMA6_A_STARTH_REG;                 /*!< (@ 0x50003562) Start address High A of DMA channel 6                  */
  __IO uint16_t  DMA6_B_STARTL_REG;                 /*!< (@ 0x50003564) Start address Low B of DMA channel 6                   */
  __IO uint16_t  DMA6_B_STARTH_REG;                 /*!< (@ 0x50003566) Start address High B of DMA channel 6                  */
  __IO uint16_t  DMA6_INT_REG;                      /*!< (@ 0x50003568) DMA receive interrupt register channel 6               */
  __IO uint16_t  DMA6_LEN_REG;                      /*!< (@ 0x5000356A) DMA receive length register channel 6                  */
  __IO uint16_t  DMA6_CTRL_REG;                     /*!< (@ 0x5000356C) Control register for the DMA channel 6                 */
  __IO uint16_t  DMA6_IDX_REG;                      /*!< (@ 0x5000356E) Index value of DMA channel 6                           */
  __IO uint16_t  DMA7_A_STARTL_REG;                 /*!< (@ 0x50003570) Start address Low A of DMA channel 7                   */
  __IO uint16_t  DMA7_A_STARTH_REG;                 /*!< (@ 0x50003572) Start address High A of DMA channel 7                  */
  __IO uint16_t  DMA7_B_STARTL_REG;                 /*!< (@ 0x50003574) Start address Low B of DMA channel 7                   */
  __IO uint16_t  DMA7_B_STARTH_REG;                 /*!< (@ 0x50003576) Start address High B of DMA channel 7                  */
  __IO uint16_t  DMA7_INT_REG;                      /*!< (@ 0x50003578) DMA receive interrupt register channel 7               */
  __IO uint16_t  DMA7_LEN_REG;                      /*!< (@ 0x5000357A) DMA receive length register channel 7                  */
  __IO uint16_t  DMA7_CTRL_REG;                     /*!< (@ 0x5000357C) Control register for the DMA channel 7                 */
  __IO uint16_t  DMA7_IDX_REG;                      /*!< (@ 0x5000357E) Index value of DMA channel 7                           */
  __IO uint16_t  DMA_REQ_MUX_REG;                   /*!< (@ 0x50003580) DMA channel assignments                                */
  __IO uint16_t  DMA_INT_STATUS_REG;                /*!< (@ 0x50003582) DMA interrupt status register                          */
  __IO uint16_t  DMA_CLEAR_INT_REG;                 /*!< (@ 0x50003584) DMA clear interrupt register                           */
} DMA_Type;


/* ================================================================================ */
/* ================                       ECC                      ================ */
/* ================================================================================ */


/**
  * @brief ECC registers (ECC)
  */

typedef struct {                                    /*!< (@ 0x50006000) ECC Structure                                          */
  __IO uint32_t  ECC_CONFIG_REG;                    /*!< (@ 0x50006000) Configuration register                                 */
  __IO uint32_t  ECC_COMMAND_REG;                   /*!< (@ 0x50006004) Command register                                       */
  __IO uint32_t  ECC_CONTROL_REG;                   /*!< (@ 0x50006008) Control register                                       */
  __IO uint32_t  ECC_STATUS_REG;                    /*!< (@ 0x5000600C) Status register                                        */
  __IO uint32_t  ECC_VERSION_REG;                   /*!< (@ 0x50006010) Version register                                       */
} ECC_Type;


/* ================================================================================ */
/* ================                      FTDF                      ================ */
/* ================================================================================ */


/**
  * @brief FTDF registers (FTDF)
  */

typedef struct {                                    /*!< (@ 0x40080000) FTDF Structure                                         */
  __IO uint32_t  FTDF_TX_FIFO_0_0_REG;              /*!< (@ 0x40080000) Address transmit fifo 0                                */
  __I  uint32_t  RESERVED[31];
  __IO uint32_t  FTDF_TX_FIFO_1_0_REG;              /*!< (@ 0x40080080) Address transmit fifo 1                                */
  __I  uint32_t  RESERVED1[31];
  __IO uint32_t  FTDF_TX_FIFO_2_0_REG;              /*!< (@ 0x40080100) Address transmit fifo 2                                */
  __I  uint32_t  RESERVED2[31];
  __IO uint32_t  FTDF_TX_FIFO_3_0_REG;              /*!< (@ 0x40080180) Address transmit fifo 3                                */
  __I  uint32_t  RESERVED3[31];
  __IO uint32_t  FTDF_TX_META_DATA_0_0_REG;         /*!< (@ 0x40080200) Transmit metadata register 0                           */
  __IO uint32_t  FTDF_TX_META_DATA_1_0_REG;         /*!< (@ 0x40080204) Transmit metadata register 0                           */
  __I  uint32_t  RESERVED4[2];
  __IO uint32_t  FTDF_TX_META_DATA_0_1_REG;         /*!< (@ 0x40080210) Transmit metadata register 1                           */
  __IO uint32_t  FTDF_TX_META_DATA_1_1_REG;         /*!< (@ 0x40080214) Transmit metadata register 1                           */
  __I  uint32_t  RESERVED5[2];
  __IO uint32_t  FTDF_TX_META_DATA_0_2_REG;         /*!< (@ 0x40080220) Transmit metadata register 2                           */
  __IO uint32_t  FTDF_TX_META_DATA_1_2_REG;         /*!< (@ 0x40080224) Transmit metadata register 2                           */
  __I  uint32_t  RESERVED6[2];
  __IO uint32_t  FTDF_TX_META_DATA_0_3_REG;         /*!< (@ 0x40080230) Transmit metadata register 3                           */
  __IO uint32_t  FTDF_TX_META_DATA_1_3_REG;         /*!< (@ 0x40080234) Transmit metadata register 3                           */
  __I  uint32_t  RESERVED7[2];
  __IO uint32_t  FTDF_TX_RETURN_STATUS_0_0_REG;     /*!< (@ 0x40080240) Transmit status register 0                             */
  __IO uint32_t  FTDF_TX_RETURN_STATUS_1_0_REG;     /*!< (@ 0x40080244) Transmit status register 0                             */
  __I  uint32_t  RESERVED8[2];
  __IO uint32_t  FTDF_TX_RETURN_STATUS_0_1_REG;     /*!< (@ 0x40080250) Transmit status register 1                             */
  __IO uint32_t  FTDF_TX_RETURN_STATUS_1_1_REG;     /*!< (@ 0x40080254) Transmit status register 1                             */
  __I  uint32_t  RESERVED9[2];
  __IO uint32_t  FTDF_TX_RETURN_STATUS_0_2_REG;     /*!< (@ 0x40080260) Transmit status register 2                             */
  __IO uint32_t  FTDF_TX_RETURN_STATUS_1_2_REG;     /*!< (@ 0x40080264) Transmit status register 2                             */
  __I  uint32_t  RESERVED10[2];
  __IO uint32_t  FTDF_TX_RETURN_STATUS_0_3_REG;     /*!< (@ 0x40080270) Transmit status register 3                             */
  __IO uint32_t  FTDF_TX_RETURN_STATUS_1_3_REG;     /*!< (@ 0x40080274) Transmit status register 3                             */
  __I  uint32_t  RESERVED11[2];
  __IO uint32_t  FTDF_RX_META_0_0_REG;              /*!< (@ 0x40080280) Receive metadata register 0                            */
  __IO uint32_t  FTDF_RX_META_1_0_REG;              /*!< (@ 0x40080284) Receive metadata register 0                            */
  __I  uint32_t  RESERVED12[2];
  __IO uint32_t  FTDF_RX_META_0_1_REG;              /*!< (@ 0x40080290) Receive metadata register 1                            */
  __IO uint32_t  FTDF_RX_META_1_1_REG;              /*!< (@ 0x40080294) Receive metadata register 1                            */
  __I  uint32_t  RESERVED13[2];
  __IO uint32_t  FTDF_RX_META_0_2_REG;              /*!< (@ 0x400802A0) Receive metadata register 2                            */
  __IO uint32_t  FTDF_RX_META_1_2_REG;              /*!< (@ 0x400802A4) Receive metadata register 2                            */
  __I  uint32_t  RESERVED14[2];
  __IO uint32_t  FTDF_RX_META_0_3_REG;              /*!< (@ 0x400802B0) Receive metadata register 3                            */
  __IO uint32_t  FTDF_RX_META_1_3_REG;              /*!< (@ 0x400802B4) Receive metadata register 3                            */
  __I  uint32_t  RESERVED15[2];
  __IO uint32_t  FTDF_RX_META_0_4_REG;              /*!< (@ 0x400802C0) Receive metadata register 4                            */
  __IO uint32_t  FTDF_RX_META_1_4_REG;              /*!< (@ 0x400802C4) Receive metadata register 4                            */
  __I  uint32_t  RESERVED16[2];
  __IO uint32_t  FTDF_RX_META_0_5_REG;              /*!< (@ 0x400802D0) Receive metadata register 5                            */
  __IO uint32_t  FTDF_RX_META_1_5_REG;              /*!< (@ 0x400802D4) Receive metadata register 5                            */
  __I  uint32_t  RESERVED17[2];
  __IO uint32_t  FTDF_RX_META_0_6_REG;              /*!< (@ 0x400802E0) Receive metadata register 6                            */
  __IO uint32_t  FTDF_RX_META_1_6_REG;              /*!< (@ 0x400802E4) Receive metadata register 6                            */
  __I  uint32_t  RESERVED18[2];
  __IO uint32_t  FTDF_RX_META_0_7_REG;              /*!< (@ 0x400802F0) Receive metadata register 7                            */
  __IO uint32_t  FTDF_RX_META_1_7_REG;              /*!< (@ 0x400802F4) Receive metadata register 7                            */
  __I  uint32_t  RESERVED19[8002];
  __IO uint32_t  FTDF_RX_FIFO_0_0_REG;              /*!< (@ 0x40088000) Address receive fifo 0                                 */
  __I  uint32_t  RESERVED20[31];
  __IO uint32_t  FTDF_RX_FIFO_1_0_REG;              /*!< (@ 0x40088080) Address transmit fifo 1                                */
  __I  uint32_t  RESERVED21[31];
  __IO uint32_t  FTDF_RX_FIFO_2_0_REG;              /*!< (@ 0x40088100) Address transmit fifo 2                                */
  __I  uint32_t  RESERVED22[31];
  __IO uint32_t  FTDF_RX_FIFO_3_0_REG;              /*!< (@ 0x40088180) Address transmit fifo 3                                */
  __I  uint32_t  RESERVED23[31];
  __IO uint32_t  FTDF_RX_FIFO_4_0_REG;              /*!< (@ 0x40088200) Address transmit fifo 4                                */
  __I  uint32_t  RESERVED24[31];
  __IO uint32_t  FTDF_RX_FIFO_5_0_REG;              /*!< (@ 0x40088280) Address transmit fifo 5                                */
  __I  uint32_t  RESERVED25[31];
  __IO uint32_t  FTDF_RX_FIFO_6_0_REG;              /*!< (@ 0x40088300) Address transmit fifo 6                                */
  __I  uint32_t  RESERVED26[31];
  __IO uint32_t  FTDF_RX_FIFO_7_0_REG;              /*!< (@ 0x40088380) Address transmit fifo 7                                */
  __I  uint32_t  RESERVED27[7967];
  __IO uint32_t  FTDF_REL_NAME_0_REG;               /*!< (@ 0x40090000) Name of the release                                    */
  __IO uint32_t  FTDF_REL_NAME_1_REG;               /*!< (@ 0x40090004) Name of the release                                    */
  __IO uint32_t  FTDF_REL_NAME_2_REG;               /*!< (@ 0x40090008) Name of the release                                    */
  __IO uint32_t  FTDF_REL_NAME_3_REG;               /*!< (@ 0x4009000C) Name of the release                                    */
  __IO uint32_t  FTDF_BUILDTIME_0_REG;              /*!< (@ 0x40090010) Build time                                             */
  __IO uint32_t  FTDF_BUILDTIME_1_REG;              /*!< (@ 0x40090014) Build time                                             */
  __IO uint32_t  FTDF_BUILDTIME_2_REG;              /*!< (@ 0x40090018) Build time                                             */
  __IO uint32_t  FTDF_BUILDTIME_3_REG;              /*!< (@ 0x4009001C) Build time                                             */
  __IO uint32_t  FTDF_GLOB_CONTROL_0_REG;           /*!< (@ 0x40090020) Global control register                                */
  __IO uint32_t  FTDF_GLOB_CONTROL_1_REG;           /*!< (@ 0x40090024) Global control register                                */
  __IO uint32_t  FTDF_GLOB_CONTROL_2_REG;           /*!< (@ 0x40090028) Global control register                                */
  __IO uint32_t  FTDF_GLOB_CONTROL_3_REG;           /*!< (@ 0x4009002C) Global control register                                */
  __IO uint32_t  FTDF_LMAC_CONTROL_0_REG;           /*!< (@ 0x40090030) Lmac control register                                  */
  __IO uint32_t  FTDF_TXPIPEPROPDELAY_REG;          /*!< (@ 0x40090034) Prop delay transmit register                           */
  __IO uint32_t  FTDF_MACACKWAITDURATION_REG;       /*!< (@ 0x40090038) Maximum time to wait for a ACK                         */
  __IO uint32_t  FTDF_MACENHACKWAITDURATION_REG;    /*!< (@ 0x4009003C) Maximum time to wait for an enhanced ACK frame         */
  __IO uint32_t  FTDF_LMAC_CONTROL_1_REG;           /*!< (@ 0x40090040) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_2_REG;           /*!< (@ 0x40090044) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_3_REG;           /*!< (@ 0x40090048) Lmac control register                                  */
  __I  uint32_t  RESERVED28;
  __IO uint32_t  FTDF_LMAC_CONTROL_OS_REG;          /*!< (@ 0x40090050) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_STATUS_REG;      /*!< (@ 0x40090054) Lmac status register                                   */
  __IO uint32_t  FTDF_EVENTCURRVAL_REG;             /*!< (@ 0x40090058) Value of event generator                               */
  __IO uint32_t  FTDF_TIMESTAMPCURRVAL_REG;         /*!< (@ 0x4009005C) Value of timestamp generator                           */
  __IO uint32_t  FTDF_LMAC_CONTROL_4_REG;           /*!< (@ 0x40090060) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_5_REG;           /*!< (@ 0x40090064) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_6_REG;           /*!< (@ 0x40090068) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_11_REG;          /*!< (@ 0x4009006C) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_DELTA_REG;       /*!< (@ 0x40090070) Lmac delta control register                            */
  __IO uint32_t  FTDF_TIMESTAMPCURRPHASEVAL_REG;    /*!< (@ 0x40090074) Value of timestamp generator phase within a symbol     */
  __IO uint32_t  FTDF_MACTSTXACKDELAYVAL_REG;       /*!< (@ 0x40090078) Time left until next ACK is sent (us)                  */
  __I  uint32_t  RESERVED29;
  __IO uint32_t  FTDF_LMAC_CONTROL_MASK_REG;        /*!< (@ 0x40090080) Lmac mask control register                             */
  __I  uint32_t  RESERVED30[3];
  __IO uint32_t  FTDF_LMAC_EVENT_REG;               /*!< (@ 0x40090090) Lmac event regsiter                                    */
  __IO uint32_t  FTDF_LMAC_MASK_REG;                /*!< (@ 0x40090094) Lmac mask register                                     */
  __I  uint32_t  RESERVED31[2];
  __IO uint32_t  FTDF_LMAC_MANUAL_1_REG;            /*!< (@ 0x400900A0) Lmax manual PHY register                               */
  __IO uint32_t  FTDF_LMAC_MANUAL_OS_REG;           /*!< (@ 0x400900A4) One shot register triggers transmission in manual
                                                         mode                                                                  */
  __IO uint32_t  FTDF_LMAC_MANUAL_STATUS_REG;       /*!< (@ 0x400900A8) Lmac status register in manual mode                    */
  __I  uint32_t  RESERVED32[21];
  __IO uint32_t  FTDF_LMAC_CONTROL_7_REG;           /*!< (@ 0x40090100) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_8_REG;           /*!< (@ 0x40090104) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_9_REG;           /*!< (@ 0x40090108) Lmac control register                                  */
  __IO uint32_t  FTDF_LMAC_CONTROL_10_REG;          /*!< (@ 0x4009010C) Lmac control register                                  */
  __IO uint32_t  FTDF_SECURITY_0_REG;               /*!< (@ 0x40090110) Security register                                      */
  __IO uint32_t  FTDF_SECURITY_1_REG;               /*!< (@ 0x40090114) Security register                                      */
  __IO uint32_t  FTDF_SECKEY_0_REG;                 /*!< (@ 0x40090118) Seckey register                                        */
  __IO uint32_t  FTDF_SECKEY_1_REG;                 /*!< (@ 0x4009011C) Seckey register                                        */
  __IO uint32_t  FTDF_SECKEY_2_REG;                 /*!< (@ 0x40090120) SecKey register                                        */
  __IO uint32_t  FTDF_SECKEY_3_REG;                 /*!< (@ 0x40090124) Seckey register                                        */
  __IO uint32_t  FTDF_SECNONCE_0_REG;               /*!< (@ 0x40090128) Nonce register used for encryption/decryption          */
  __IO uint32_t  FTDF_SECNONCE_1_REG;               /*!< (@ 0x4009012C) Nonce register used for encryption/decryption          */
  __IO uint32_t  FTDF_SECNONCE_2_REG;               /*!< (@ 0x40090130) Nonce register used for encryption/decryption          */
  __IO uint32_t  FTDF_SECNONCE_3_REG;               /*!< (@ 0x40090134) Nonce register used for encryption/decryption          */
  __IO uint32_t  FTDF_SECURITY_OS_REG;              /*!< (@ 0x40090138) One shot register to start encryption/decryption       */
  __I  uint32_t  RESERVED33;
  __IO uint32_t  FTDF_SECURITY_STATUS_REG;          /*!< (@ 0x40090140) Security status register                               */
  __I  uint32_t  RESERVED34[3];
  __IO uint32_t  FTDF_SECURITY_EVENT_REG;           /*!< (@ 0x40090150) security event register                                */
  __IO uint32_t  FTDF_SECURITY_EVENTMASK_REG;       /*!< (@ 0x40090154) security event mask register                           */
  __I  uint32_t  RESERVED35[2];
  __IO uint32_t  FTDF_TSCH_CONTROL_0_REG;           /*!< (@ 0x40090160) Lmac tsch control register                             */
  __IO uint32_t  FTDF_TSCH_CONTROL_1_REG;           /*!< (@ 0x40090164) Lmac tsch control register                             */
  __IO uint32_t  FTDF_TSCH_CONTROL_2_REG;           /*!< (@ 0x40090168) Lmac tsch control register                             */
  __I  uint32_t  RESERVED36[5];
  __IO uint32_t  FTDF_PHY_PARAMETERS_0_REG;         /*!< (@ 0x40090180) Lmac PHY parameter register                            */
  __IO uint32_t  FTDF_PHY_PARAMETERS_1_REG;         /*!< (@ 0x40090184) Lmac PHY parameter register                            */
  __IO uint32_t  FTDF_PHY_PARAMETERS_2_REG;         /*!< (@ 0x40090188) Lmac PHY parameter register                            */
  __IO uint32_t  FTDF_PHY_PARAMETERS_3_REG;         /*!< (@ 0x4009018C) Lmac PHY parameter register                            */
  __I  uint32_t  RESERVED37[28];
  __IO uint32_t  FTDF_RX_CONTROL_0_REG;             /*!< (@ 0x40090200) Receive control register                               */
  __IO uint32_t  FTDF_RX_EVENT_REG;                 /*!< (@ 0x40090204) Receive event register                                 */
  __IO uint32_t  FTDF_RX_MASK_REG;                  /*!< (@ 0x40090208) Receive event mask register                            */
  __IO uint32_t  FTDF_RX_STATUS_REG;                /*!< (@ 0x4009020C) Receive status register                                */
  __IO uint32_t  FTDF_SYMBOLTIMESNAPSHOTVAL_REG;    /*!< (@ 0x40090210) Value timestamp generator                              */
  __I  uint32_t  RESERVED38[3];
  __IO uint32_t  FTDF_RX_STATUS_DELTA_REG;          /*!< (@ 0x40090220) Receive status delta register                          */
  __IO uint32_t  FTDF_RX_STATUS_MASK_REG;           /*!< (@ 0x40090224) Receive status delta mask register                     */
  __I  uint32_t  RESERVED39[6];
  __IO uint32_t  FTDF_TX_CONTROL_0_REG;             /*!< (@ 0x40090240) Transmit control register                              */
  __I  uint32_t  RESERVED40[3];
  __IO uint32_t  FTDF_FTDF_CE_REG;                  /*!< (@ 0x40090250) Selection register events                              */
  __IO uint32_t  FTDF_FTDF_CM_REG;                  /*!< (@ 0x40090254) Mask selection register events                         */
  __I  uint32_t  RESERVED41[43];
  __IO uint32_t  FTDF_SYNCTIMESTAMPTHR_REG;         /*!< (@ 0x40090304) Threshold timestamp generator                          */
  __IO uint32_t  FTDF_SYNCTIMESTAMPVAL_REG;         /*!< (@ 0x40090308) Value timestamp generator                              */
  __IO uint32_t  FTDF_TIMER_CONTROL_1_REG;          /*!< (@ 0x4009030C) Timer control register                                 */
  __IO uint32_t  FTDF_MACTXSTDACKFRMCNT_REG;        /*!< (@ 0x40090310) Transmitted acknowledgment frames                      */
  __IO uint32_t  FTDF_MACRXSTDACKFRMOKCNT_REG;      /*!< (@ 0x40090314) Received acknowledgment frames                         */
  __IO uint32_t  FTDF_MACRXADDRFAILFRMCNT_REG;      /*!< (@ 0x40090318) Discarded frames register                              */
  __IO uint32_t  FTDF_MACRXUNSUPFRMCNT_REG;         /*!< (@ 0x4009031C) Unsupported frames register                            */
  __IO uint32_t  FTDF_SYNCTIMESTAMPPHASEVAL_REG;    /*!< (@ 0x40090320) Timestamp phase value regsiter                         */
  __I  uint32_t  RESERVED42[7];
  __IO uint32_t  FTDF_MACFCSERRORCOUNT_REG;         /*!< (@ 0x40090340) Lmac FCS error register                                */
  __I  uint32_t  RESERVED43[7];
  __IO uint32_t  FTDF_LMACRESET_REG;                /*!< (@ 0x40090360) Lmax reset register                                    */
  __IO uint32_t  FTDF_WAKEUP_CONTROL_OS_REG;        /*!< (@ 0x40090364) FTDF_WAKEUP_CONTROL_OS_REG                             */
  __I  uint32_t  RESERVED44[6];
  __IO uint32_t  FTDF_SYMBOLTIMETHR_REG;            /*!< (@ 0x40090380) Symboltime threshold register 1                        */
  __IO uint32_t  FTDF_SYMBOLTIME2THR_REG;           /*!< (@ 0x40090384) Symboltime threshold register 2                        */
  __I  uint32_t  RESERVED45[2];
  __IO uint32_t  FTDF_DEBUGCONTROL_REG;             /*!< (@ 0x40090390) Debug control register                                 */
  __IO uint32_t  FTDF_TXBYTE_E_REG;                 /*!< (@ 0x40090394) Transmit first byte register                           */
  __IO uint32_t  FTDF_TXBYTE_M_REG;                 /*!< (@ 0x40090398) Transmit first byte mask register                      */
  __I  uint32_t  RESERVED46[25];
  __IO uint32_t  FTDF_TX_FLAG_S_0_REG;              /*!< (@ 0x40090400) Transmit packet ready for transmission register
                                                         0                                                                     */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_E_0_REG;        /*!< (@ 0x40090404) Clear flag register 0                                  */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_M_0_REG;        /*!< (@ 0x40090408) Mask flag register 0                                   */
  __I  uint32_t  RESERVED47;
  __IO uint32_t  FTDF_TX_PRIORITY_0_REG;            /*!< (@ 0x40090410) Transmit priority register 0                           */
  __I  uint32_t  RESERVED48[3];
  __IO uint32_t  FTDF_TX_FLAG_S_1_REG;              /*!< (@ 0x40090420) Transmit packet ready for transmission register
                                                         1                                                                     */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_E_1_REG;        /*!< (@ 0x40090424) Clear flag register 1                                  */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_M_1_REG;        /*!< (@ 0x40090428) Mask flag register 1                                   */
  __I  uint32_t  RESERVED49;
  __IO uint32_t  FTDF_TX_PRIORITY_1_REG;            /*!< (@ 0x40090430) Transmit priority register 1                           */
  __I  uint32_t  RESERVED50[3];
  __IO uint32_t  FTDF_TX_FLAG_S_2_REG;              /*!< (@ 0x40090440) Transmit packet ready for transmission register
                                                         2                                                                     */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_E_2_REG;        /*!< (@ 0x40090444) Clear flag register 2                                  */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_M_2_REG;        /*!< (@ 0x40090448) Clear flag register 2                                  */
  __I  uint32_t  RESERVED51;
  __IO uint32_t  FTDF_TX_PRIORITY_2_REG;            /*!< (@ 0x40090450) Transmit priority register 2                           */
  __I  uint32_t  RESERVED52[3];
  __IO uint32_t  FTDF_TX_FLAG_S_3_REG;              /*!< (@ 0x40090460) Transmit packet ready for transmission register
                                                         3                                                                     */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_E_3_REG;        /*!< (@ 0x40090464) Clear flag register 3                                  */
  __IO uint32_t  FTDF_TX_FLAG_CLEAR_M_3_REG;        /*!< (@ 0x40090468) Clear flag register 3                                  */
  __I  uint32_t  RESERVED53;
  __IO uint32_t  FTDF_TX_PRIORITY_3_REG;            /*!< (@ 0x40090470) Transmit priority register 3                           */
  __I  uint32_t  RESERVED54[3];
  __IO uint32_t  FTDF_TX_SET_OS_REG;                /*!< (@ 0x40090480) One shot register to set flag                          */
  __IO uint32_t  FTDF_TX_CLEAR_OS_REG;              /*!< (@ 0x40090484) One shot register to clear flag                        */
  __I  uint32_t  RESERVED55[734];
  __IO uint32_t  FTDF_WAKEUP_CONTROL_REG;           /*!< (@ 0x40091000) Wakeup timer vcontrol register                         */
  __I  uint32_t  RESERVED56[1023];
  __IO uint32_t  FTDF_LONG_ADDR_0_0_REG;            /*!< (@ 0x40092000) FTDF_LONG_ADDR_0_0_REG                                 */
  __IO uint32_t  FTDF_LONG_ADDR_1_0_REG;            /*!< (@ 0x40092004) FTDF_LONG_ADDR_1_0_REG                                 */
  __IO uint32_t  FTDF_SIZE_AND_VAL_0_REG;           /*!< (@ 0x40092008) FTDF_SIZE_AND_VAL_0_REG                                */
} FTDF_Type;


/* ================================================================================ */
/* ================                    GP_TIMERS                   ================ */
/* ================================================================================ */


/**
  * @brief GP_TIMERS registers (GP_TIMERS)
  */

typedef struct {                                    /*!< (@ 0x50003400) GP_TIMERS Structure                                    */
  __IO uint16_t  TIMER0_CTRL_REG;                   /*!< (@ 0x50003400) Timer0 control register                                */
  __IO uint16_t  TIMER0_ON_REG;                     /*!< (@ 0x50003402) Timer0 on control register                             */
  __IO uint16_t  TIMER0_RELOAD_M_REG;               /*!< (@ 0x50003404) 16 bits reload value for Timer0                        */
  __IO uint16_t  TIMER0_RELOAD_N_REG;               /*!< (@ 0x50003406) 16 bits reload value for Timer0                        */
  __IO uint16_t  PWM2_START_CYCLE;                  /*!< (@ 0x50003408) Defines start Cycle for PWM2                           */
  __IO uint16_t  PWM3_START_CYCLE;                  /*!< (@ 0x5000340A) Defines start Cycle for PWM3                           */
  __IO uint16_t  PWM4_START_CYCLE;                  /*!< (@ 0x5000340C) Defines start Cycle for PWM4                           */
  __IO uint16_t  PWM2_END_CYCLE;                    /*!< (@ 0x5000340E) Defines end Cycle for PWM2                             */
  __IO uint16_t  PWM3_END_CYCLE;                    /*!< (@ 0x50003410) Defines end Cycle for PWM3                             */
  __IO uint16_t  PWM4_END_CYCLE;                    /*!< (@ 0x50003412) Defines end Cycle for PWM4                             */
  __IO uint16_t  TRIPLE_PWM_FREQUENCY;              /*!< (@ 0x50003414) Defines the PMW2,3,4 frequency                         */
  __IO uint16_t  TRIPLE_PWM_CTRL_REG;               /*!< (@ 0x50003416) PWM 2 3 4 Control register                             */
  __IO uint16_t  BREATH_CFG_REG;                    /*!< (@ 0x50003418) Breath configuration register                          */
  __IO uint16_t  BREATH_DUTY_MAX_REG;               /*!< (@ 0x5000341A) Breath max duty cycle register                         */
  __IO uint16_t  BREATH_DUTY_MIN_REG;               /*!< (@ 0x5000341C) Breath min duty cycle register                         */
  __IO uint16_t  BREATH_CTRL_REG;                   /*!< (@ 0x5000341E) Breath control register                                */
} GP_TIMERS_Type;


/* ================================================================================ */
/* ================                      GPADC                     ================ */
/* ================================================================================ */


/**
  * @brief GPADC registers (GPADC)
  */

typedef struct {                                    /*!< (@ 0x50001900) GPADC Structure                                        */
  __IO uint16_t  GP_ADC_CTRL_REG;                   /*!< (@ 0x50001900) General Purpose ADC Control Register                   */
  __IO uint16_t  GP_ADC_CTRL2_REG;                  /*!< (@ 0x50001902) General Purpose ADC Second Control Register            */
  __IO uint16_t  GP_ADC_CTRL3_REG;                  /*!< (@ 0x50001904) General Purpose ADC Third Control Register             */
  __IO uint16_t  GP_ADC_OFFP_REG;                   /*!< (@ 0x50001906) General Purpose ADC Positive Offset Register           */
  __IO uint16_t  GP_ADC_OFFN_REG;                   /*!< (@ 0x50001908) General Purpose ADC Negative Offset Register           */
  __IO uint16_t  GP_ADC_CLEAR_INT_REG;              /*!< (@ 0x5000190A) General Purpose ADC Clear Interrupt Register           */
  __IO uint16_t  GP_ADC_RESULT_REG;                 /*!< (@ 0x5000190C) General Purpose ADC Result Register                    */
} GPADC_Type;


/* ================================================================================ */
/* ================                      GPIO                      ================ */
/* ================================================================================ */


/**
  * @brief GPIO registers (GPIO)
  */

typedef struct {                                    /*!< (@ 0x50003000) GPIO Structure                                         */
  __IO uint16_t  P0_DATA_REG;                       /*!< (@ 0x50003000) P0 Data input / output Register                        */
  __IO uint16_t  P1_DATA_REG;                       /*!< (@ 0x50003002) P1 Data input / output Register                        */
  __IO uint16_t  P2_DATA_REG;                       /*!< (@ 0x50003004) P2 Data input / output Register                        */
  __IO uint16_t  P3_DATA_REG;                       /*!< (@ 0x50003006) P3 Data input / output Register                        */
  __IO uint16_t  P4_DATA_REG;                       /*!< (@ 0x50003008) P4 Data input / output Register                        */
  __IO uint16_t  P0_SET_DATA_REG;                   /*!< (@ 0x5000300A) P0 Set port pins Register                              */
  __IO uint16_t  P1_SET_DATA_REG;                   /*!< (@ 0x5000300C) P1 Set port pins Register                              */
  __IO uint16_t  P2_SET_DATA_REG;                   /*!< (@ 0x5000300E) P2 Set port pins Register                              */
  __IO uint16_t  P3_SET_DATA_REG;                   /*!< (@ 0x50003010) P3 Set port pins Register                              */
  __IO uint16_t  P4_SET_DATA_REG;                   /*!< (@ 0x50003012) P4 Set port pins Register                              */
  __IO uint16_t  P0_RESET_DATA_REG;                 /*!< (@ 0x50003014) P0 Reset port pins Register                            */
  __IO uint16_t  P1_RESET_DATA_REG;                 /*!< (@ 0x50003016) P1 Reset port pins Register                            */
  __IO uint16_t  P2_RESET_DATA_REG;                 /*!< (@ 0x50003018) P2 Reset port pins Register                            */
  __IO uint16_t  P3_RESET_DATA_REG;                 /*!< (@ 0x5000301A) P3 Reset port pins Register                            */
  __IO uint16_t  P4_RESET_DATA_REG;                 /*!< (@ 0x5000301C) P4 Reset port pins Register                            */
  __IO uint16_t  P00_MODE_REG;                      /*!< (@ 0x5000301E) P00 Mode Register                                      */
  __IO uint16_t  P01_MODE_REG;                      /*!< (@ 0x50003020) P01 Mode Register                                      */
  __IO uint16_t  P02_MODE_REG;                      /*!< (@ 0x50003022) P02 Mode Register                                      */
  __IO uint16_t  P03_MODE_REG;                      /*!< (@ 0x50003024) P03 Mode Register                                      */
  __IO uint16_t  P04_MODE_REG;                      /*!< (@ 0x50003026) P04 Mode Register                                      */
  __IO uint16_t  P05_MODE_REG;                      /*!< (@ 0x50003028) P05 Mode Register                                      */
  __IO uint16_t  P06_MODE_REG;                      /*!< (@ 0x5000302A) P06 Mode Register                                      */
  __IO uint16_t  P07_MODE_REG;                      /*!< (@ 0x5000302C) P07 Mode Register                                      */
  __IO uint16_t  P10_MODE_REG;                      /*!< (@ 0x5000302E) P10 Mode Register                                      */
  __IO uint16_t  P11_MODE_REG;                      /*!< (@ 0x50003030) P11 Mode Register                                      */
  __IO uint16_t  P12_MODE_REG;                      /*!< (@ 0x50003032) P12 Mode Register                                      */
  __IO uint16_t  P13_MODE_REG;                      /*!< (@ 0x50003034) P13 Mode Register                                      */
  __IO uint16_t  P14_MODE_REG;                      /*!< (@ 0x50003036) P14 Mode Register                                      */
  __IO uint16_t  P15_MODE_REG;                      /*!< (@ 0x50003038) P15 Mode Register                                      */
  __IO uint16_t  P16_MODE_REG;                      /*!< (@ 0x5000303A) P24 Mode Register                                      */
  __IO uint16_t  P17_MODE_REG;                      /*!< (@ 0x5000303C) P25 Mode Register                                      */
  __IO uint16_t  P20_MODE_REG;                      /*!< (@ 0x5000303E) P20 Mode Register                                      */
  __IO uint16_t  P21_MODE_REG;                      /*!< (@ 0x50003040) P21 Mode Register                                      */
  __IO uint16_t  P22_MODE_REG;                      /*!< (@ 0x50003042) P22 Mode Register                                      */
  __IO uint16_t  P23_MODE_REG;                      /*!< (@ 0x50003044) P23 Mode Register                                      */
  __IO uint16_t  P24_MODE_REG;                      /*!< (@ 0x50003046) P24 Mode Register                                      */
  __I  uint16_t  RESERVED[3];
  __IO uint16_t  P30_MODE_REG;                      /*!< (@ 0x5000304E) P30 Mode Register                                      */
  __IO uint16_t  P31_MODE_REG;                      /*!< (@ 0x50003050) P31 Mode Register                                      */
  __IO uint16_t  P32_MODE_REG;                      /*!< (@ 0x50003052) P32 Mode Register                                      */
  __IO uint16_t  P33_MODE_REG;                      /*!< (@ 0x50003054) P33 Mode Register                                      */
  __IO uint16_t  P34_MODE_REG;                      /*!< (@ 0x50003056) P34 Mode Register                                      */
  __IO uint16_t  P35_MODE_REG;                      /*!< (@ 0x50003058) P35 Mode Register                                      */
  __IO uint16_t  P36_MODE_REG;                      /*!< (@ 0x5000305A) P36 Mode Register                                      */
  __IO uint16_t  P37_MODE_REG;                      /*!< (@ 0x5000305C) P37 Mode Register                                      */
  __IO uint16_t  P40_MODE_REG;                      /*!< (@ 0x5000305E) P40 Mode Register                                      */
  __IO uint16_t  P41_MODE_REG;                      /*!< (@ 0x50003060) P41 Mode Register                                      */
  __IO uint16_t  P42_MODE_REG;                      /*!< (@ 0x50003062) P42 Mode Register                                      */
  __IO uint16_t  P43_MODE_REG;                      /*!< (@ 0x50003064) P43 Mode Register                                      */
  __IO uint16_t  P44_MODE_REG;                      /*!< (@ 0x50003066) P44 Mode Register                                      */
  __IO uint16_t  P45_MODE_REG;                      /*!< (@ 0x50003068) P45 Mode Register                                      */
  __IO uint16_t  P46_MODE_REG;                      /*!< (@ 0x5000306A) P46 Mode Register                                      */
  __IO uint16_t  P47_MODE_REG;                      /*!< (@ 0x5000306C) P47 Mode Register                                      */
  __I  uint16_t  RESERVED1[41];
  __IO uint16_t  P0_PADPWR_CTRL_REG;                /*!< (@ 0x500030C0) P0 Output Power Control Register                       */
  __IO uint16_t  P1_PADPWR_CTRL_REG;                /*!< (@ 0x500030C2) P1 Output Power Control Register                       */
  __IO uint16_t  P2_PADPWR_CTRL_REG;                /*!< (@ 0x500030C4) P2 Output Power Control Register                       */
  __IO uint16_t  P3_PADPWR_CTRL_REG;                /*!< (@ 0x500030C6) P3 Output Power Control Register                       */
  __IO uint16_t  P4_PADPWR_CTRL_REG;                /*!< (@ 0x500030C8) P4 Output Power Control Register                       */
  __I  uint16_t  RESERVED2[3];
  __IO uint16_t  GPIO_CLK_SEL;                      /*!< (@ 0x500030D0) Select which clock to map on port in PPA               */
  __I  uint16_t  RESERVED3[7];
  __IO uint16_t  BIST_CTRL_REG;                     /*!< (@ 0x500030E0) BIST_CTRL_REG                                          */
  __IO uint16_t  RAMBIST_STATUS1_REG;               /*!< (@ 0x500030E2) RAMBIST_STATUS1_REG                                    */
  __IO uint16_t  RAMBIST_STATUS2_REG;               /*!< (@ 0x500030E4) RAMBIST_STATUS2_REG                                    */
  __IO uint16_t  RAMBIST_STATUS3_REG;               /*!< (@ 0x500030E6) RAMBIST_STATUS3_REG                                    */
  __IO uint16_t  ROMBIST_RESULTL_REG;               /*!< (@ 0x500030E8) ROMBIST_RESULTL_REG                                    */
  __IO uint16_t  ROMBIST_RESULTH_REG;               /*!< (@ 0x500030EA) ROMBIST_RESULTH_REG                                    */
  __I  uint32_t  RESERVED4;
  __IO uint16_t  TEST_CTRL_REG;                     /*!< (@ 0x500030F0) TEST_CTRL_REG                                          */
  __IO uint16_t  TEST_CTRL2_REG;                    /*!< (@ 0x500030F2) TEST_CTRL2_REG                                         */
  __IO uint16_t  TEST_CTRL3_REG;                    /*!< (@ 0x500030F4) TEST_CTRL3_REG                                         */
  __IO uint16_t  TEST_CTRL4_REG;                    /*!< (@ 0x500030F6) TEST_CTRL4_REG                                         */
  __IO uint16_t  TEST_CTRL5_REG;                    /*!< (@ 0x500030F8) TEST_CTRL5_REG                                         */
} GPIO_Type;


/* ================================================================================ */
/* ================                      GPREG                     ================ */
/* ================================================================================ */


/**
  * @brief GPREG registers (GPREG)
  */

typedef struct {                                    /*!< (@ 0x50003300) GPREG Structure                                        */
  __IO uint16_t  SET_FREEZE_REG;                    /*!< (@ 0x50003300) Controls freezing of various timers/counters
                                                         (incl. DMA and USB).                                                  */
  __IO uint16_t  RESET_FREEZE_REG;                  /*!< (@ 0x50003302) Controls unfreezing of various timers/counters
                                                         (incl. DMA and USB).                                                  */
  __IO uint16_t  DEBUG_REG;                         /*!< (@ 0x50003304) Various debug information register.                    */
  __IO uint16_t  GP_STATUS_REG;                     /*!< (@ 0x50003306) General purpose system status register.                */
  __IO uint16_t  GP_CONTROL_REG;                    /*!< (@ 0x50003308) General purpose system control register.               */
  __IO uint16_t  ECC_BASE_ADDR_REG;                 /*!< (@ 0x5000330A) Base address of the ECC Crypto memory register.        */
  __IO uint16_t  LED_CONTROL_REG;                   /*!< (@ 0x5000330C) Controls muxing and enabling of the LEDs.              */
  __IO uint16_t  BLE_FINECNT_SAMP_REG;              /*!< (@ 0x5000330E) BLE FINECNT sampled value while in deep sleep
                                                         state.                                                                */
  __IO uint16_t  PLL_SYS_CTRL1_REG;                 /*!< (@ 0x50003310) System PLL control register 1.                         */
  __IO uint16_t  PLL_SYS_CTRL2_REG;                 /*!< (@ 0x50003312) System PLL control register 2.                         */
  __IO uint16_t  PLL_SYS_CTRL3_REG;                 /*!< (@ 0x50003314) System PLL control register 3.                         */
  __IO uint16_t  PLL_SYS_STATUS_REG;                /*!< (@ 0x50003316) System PLL status register.                            */
  __IO uint16_t  PLL_SYS_TEST_REG;                  /*!< (@ 0x50003318) System PLL test register.                              */
} GPREG_Type;


/* ================================================================================ */
/* ================                       I2C                      ================ */
/* ================================================================================ */


/**
  * @brief I2C registers (I2C)
  */

typedef struct {                                    /*!< (@ 0x50001400) I2C Structure                                          */
  __IO uint16_t  I2C_CON_REG;                       /*!< (@ 0x50001400) I2C Control Register                                   */
  __I  uint16_t  RESERVED;
  __IO uint16_t  I2C_TAR_REG;                       /*!< (@ 0x50001404) I2C Target Address Register                            */
  __I  uint16_t  RESERVED1;
  __IO uint16_t  I2C_SAR_REG;                       /*!< (@ 0x50001408) I2C Slave Address Register                             */
  __I  uint16_t  RESERVED2[3];
  __IO uint16_t  I2C_DATA_CMD_REG;                  /*!< (@ 0x50001410) I2C Rx/Tx Data Buffer and Command Register             */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  I2C_SS_SCL_HCNT_REG;               /*!< (@ 0x50001414) Standard Speed I2C Clock SCL High Count Register       */
  __I  uint16_t  RESERVED4;
  __IO uint16_t  I2C_SS_SCL_LCNT_REG;               /*!< (@ 0x50001418) Standard Speed I2C Clock SCL Low Count Register        */
  __I  uint16_t  RESERVED5;
  __IO uint16_t  I2C_FS_SCL_HCNT_REG;               /*!< (@ 0x5000141C) Fast Speed I2C Clock SCL High Count Register           */
  __I  uint16_t  RESERVED6;
  __IO uint16_t  I2C_FS_SCL_LCNT_REG;               /*!< (@ 0x50001420) Fast Speed I2C Clock SCL Low Count Register            */
  __I  uint16_t  RESERVED7[5];
  __IO uint16_t  I2C_INTR_STAT_REG;                 /*!< (@ 0x5000142C) I2C Interrupt Status Register                          */
  __I  uint16_t  RESERVED8;
  __IO uint16_t  I2C_INTR_MASK_REG;                 /*!< (@ 0x50001430) I2C Interrupt Mask Register                            */
  __I  uint16_t  RESERVED9;
  __IO uint16_t  I2C_RAW_INTR_STAT_REG;             /*!< (@ 0x50001434) I2C Raw Interrupt Status Register                      */
  __I  uint16_t  RESERVED10;
  __IO uint16_t  I2C_RX_TL_REG;                     /*!< (@ 0x50001438) I2C Receive FIFO Threshold Register                    */
  __I  uint16_t  RESERVED11;
  __IO uint16_t  I2C_TX_TL_REG;                     /*!< (@ 0x5000143C) I2C Transmit FIFO Threshold Register                   */
  __I  uint16_t  RESERVED12;
  __IO uint16_t  I2C_CLR_INTR_REG;                  /*!< (@ 0x50001440) Clear Combined and Individual Interrupt Register       */
  __I  uint16_t  RESERVED13;
  __IO uint16_t  I2C_CLR_RX_UNDER_REG;              /*!< (@ 0x50001444) Clear RX_UNDER Interrupt Register                      */
  __I  uint16_t  RESERVED14;
  __IO uint16_t  I2C_CLR_RX_OVER_REG;               /*!< (@ 0x50001448) Clear RX_OVER Interrupt Register                       */
  __I  uint16_t  RESERVED15;
  __IO uint16_t  I2C_CLR_TX_OVER_REG;               /*!< (@ 0x5000144C) Clear TX_OVER Interrupt Register                       */
  __I  uint16_t  RESERVED16;
  __IO uint16_t  I2C_CLR_RD_REQ_REG;                /*!< (@ 0x50001450) Clear RD_REQ Interrupt Register                        */
  __I  uint16_t  RESERVED17;
  __IO uint16_t  I2C_CLR_TX_ABRT_REG;               /*!< (@ 0x50001454) Clear TX_ABRT Interrupt Register                       */
  __I  uint16_t  RESERVED18;
  __IO uint16_t  I2C_CLR_RX_DONE_REG;               /*!< (@ 0x50001458) Clear RX_DONE Interrupt Register                       */
  __I  uint16_t  RESERVED19;
  __IO uint16_t  I2C_CLR_ACTIVITY_REG;              /*!< (@ 0x5000145C) Clear ACTIVITY Interrupt Register                      */
  __I  uint16_t  RESERVED20;
  __IO uint16_t  I2C_CLR_STOP_DET_REG;              /*!< (@ 0x50001460) Clear STOP_DET Interrupt Register                      */
  __I  uint16_t  RESERVED21;
  __IO uint16_t  I2C_CLR_START_DET_REG;             /*!< (@ 0x50001464) Clear START_DET Interrupt Register                     */
  __I  uint16_t  RESERVED22;
  __IO uint16_t  I2C_CLR_GEN_CALL_REG;              /*!< (@ 0x50001468) Clear GEN_CALL Interrupt Register                      */
  __I  uint16_t  RESERVED23;
  __IO uint16_t  I2C_ENABLE_REG;                    /*!< (@ 0x5000146C) I2C Enable Register                                    */
  __I  uint16_t  RESERVED24;
  __IO uint16_t  I2C_STATUS_REG;                    /*!< (@ 0x50001470) I2C Status Register                                    */
  __I  uint16_t  RESERVED25;
  __IO uint16_t  I2C_TXFLR_REG;                     /*!< (@ 0x50001474) I2C Transmit FIFO Level Register                       */
  __I  uint16_t  RESERVED26;
  __IO uint16_t  I2C_RXFLR_REG;                     /*!< (@ 0x50001478) I2C Receive FIFO Level Register                        */
  __I  uint16_t  RESERVED27;
  __IO uint16_t  I2C_SDA_HOLD_REG;                  /*!< (@ 0x5000147C) I2C SDA Hold Time Length Register                      */
  __I  uint16_t  RESERVED28;
  __IO uint16_t  I2C_TX_ABRT_SOURCE_REG;            /*!< (@ 0x50001480) I2C Transmit Abort Source Register                     */
  __I  uint16_t  RESERVED29[3];
  __IO uint16_t  I2C_DMA_CR_REG;                    /*!< (@ 0x50001488) DMA Control Register                                   */
  __I  uint16_t  RESERVED30;
  __IO uint16_t  I2C_DMA_TDLR_REG;                  /*!< (@ 0x5000148C) DMA Transmit Data Level Register                       */
  __I  uint16_t  RESERVED31;
  __IO uint16_t  I2C_DMA_RDLR_REG;                  /*!< (@ 0x50001490) I2C Receive Data Level Register                        */
  __I  uint16_t  RESERVED32;
  __IO uint16_t  I2C_SDA_SETUP_REG;                 /*!< (@ 0x50001494) I2C SDA Setup Register                                 */
  __I  uint16_t  RESERVED33;
  __IO uint16_t  I2C_ACK_GENERAL_CALL_REG;          /*!< (@ 0x50001498) I2C ACK General Call Register                          */
  __I  uint16_t  RESERVED34;
  __IO uint16_t  I2C_ENABLE_STATUS_REG;             /*!< (@ 0x5000149C) I2C Enable Status Register                             */
  __I  uint16_t  RESERVED35;
  __IO uint16_t  I2C_IC_FS_SPKLEN_REG;              /*!< (@ 0x500014A0) I2C SS and FS spike suppression limit Size             */
  __I  uint16_t  RESERVED36[41];
  __IO uint16_t  I2C_COMP_PARAM1_REG;               /*!< (@ 0x500014F4) Component Parameter Register                           */
  __IO uint16_t  I2C_COMP_PARAM2_REG;               /*!< (@ 0x500014F6) Component Parameter Register 2                         */
  __IO uint16_t  I2C_COMP_VERSION_REG;              /*!< (@ 0x500014F8) I2C Component Version Register                         */
  __IO uint16_t  I2C_COMP2_VERSION;                 /*!< (@ 0x500014FA) I2C Component2 Version Register                        */
  __IO uint16_t  I2C_COMP_TYPE_REG;                 /*!< (@ 0x500014FC) I2C Component Type Register                            */
  __IO uint16_t  I2C_COMP_TYPE2_REG;                /*!< (@ 0x500014FE) I2C Component2 Type Register                           */
} I2C_Type;


/* ================================================================================ */
/* ================                      I2C2                      ================ */
/* ================================================================================ */


/**
  * @brief I2C2 registers (I2C2)
  */

typedef struct {                                    /*!< (@ 0x50001500) I2C2 Structure                                         */
  __IO uint16_t  I2C2_CON_REG;                      /*!< (@ 0x50001500) I2C Control Register                                   */
  __I  uint16_t  RESERVED;
  __IO uint16_t  I2C2_TAR_REG;                      /*!< (@ 0x50001504) I2C Target Address Register                            */
  __I  uint16_t  RESERVED1;
  __IO uint16_t  I2C2_SAR_REG;                      /*!< (@ 0x50001508) I2C Slave Address Register                             */
  __I  uint16_t  RESERVED2[3];
  __IO uint16_t  I2C2_DATA_CMD_REG;                 /*!< (@ 0x50001510) I2C Rx/Tx Data Buffer and Command Register             */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  I2C2_SS_SCL_HCNT_REG;              /*!< (@ 0x50001514) Standard Speed I2C Clock SCL High Count Register       */
  __I  uint16_t  RESERVED4;
  __IO uint16_t  I2C2_SS_SCL_LCNT_REG;              /*!< (@ 0x50001518) Standard Speed I2C Clock SCL Low Count Register        */
  __I  uint16_t  RESERVED5;
  __IO uint16_t  I2C2_FS_SCL_HCNT_REG;              /*!< (@ 0x5000151C) Fast Speed I2C Clock SCL High Count Register           */
  __I  uint16_t  RESERVED6;
  __IO uint16_t  I2C2_FS_SCL_LCNT_REG;              /*!< (@ 0x50001520) Fast Speed I2C Clock SCL Low Count Register            */
  __I  uint16_t  RESERVED7[5];
  __IO uint16_t  I2C2_INTR_STAT_REG;                /*!< (@ 0x5000152C) I2C Interrupt Status Register                          */
  __I  uint16_t  RESERVED8;
  __IO uint16_t  I2C2_INTR_MASK_REG;                /*!< (@ 0x50001530) I2C Interrupt Mask Register                            */
  __I  uint16_t  RESERVED9;
  __IO uint16_t  I2C2_RAW_INTR_STAT_REG;            /*!< (@ 0x50001534) I2C Raw Interrupt Status Register                      */
  __I  uint16_t  RESERVED10;
  __IO uint16_t  I2C2_RX_TL_REG;                    /*!< (@ 0x50001538) I2C Receive FIFO Threshold Register                    */
  __I  uint16_t  RESERVED11;
  __IO uint16_t  I2C2_TX_TL_REG;                    /*!< (@ 0x5000153C) I2C Transmit FIFO Threshold Register                   */
  __I  uint16_t  RESERVED12;
  __IO uint16_t  I2C2_CLR_INTR_REG;                 /*!< (@ 0x50001540) Clear Combined and Individual Interrupt Register       */
  __I  uint16_t  RESERVED13;
  __IO uint16_t  I2C2_CLR_RX_UNDER_REG;             /*!< (@ 0x50001544) Clear RX_UNDER Interrupt Register                      */
  __I  uint16_t  RESERVED14;
  __IO uint16_t  I2C2_CLR_RX_OVER_REG;              /*!< (@ 0x50001548) Clear RX_OVER Interrupt Register                       */
  __I  uint16_t  RESERVED15;
  __IO uint16_t  I2C2_CLR_TX_OVER_REG;              /*!< (@ 0x5000154C) Clear TX_OVER Interrupt Register                       */
  __I  uint16_t  RESERVED16;
  __IO uint16_t  I2C2_CLR_RD_REQ_REG;               /*!< (@ 0x50001550) Clear RD_REQ Interrupt Register                        */
  __I  uint16_t  RESERVED17;
  __IO uint16_t  I2C2_CLR_TX_ABRT_REG;              /*!< (@ 0x50001554) Clear TX_ABRT Interrupt Register                       */
  __I  uint16_t  RESERVED18;
  __IO uint16_t  I2C2_CLR_RX_DONE_REG;              /*!< (@ 0x50001558) Clear RX_DONE Interrupt Register                       */
  __I  uint16_t  RESERVED19;
  __IO uint16_t  I2C2_CLR_ACTIVITY_REG;             /*!< (@ 0x5000155C) Clear ACTIVITY Interrupt Register                      */
  __I  uint16_t  RESERVED20;
  __IO uint16_t  I2C2_CLR_STOP_DET_REG;             /*!< (@ 0x50001560) Clear STOP_DET Interrupt Register                      */
  __I  uint16_t  RESERVED21;
  __IO uint16_t  I2C2_CLR_START_DET_REG;            /*!< (@ 0x50001564) Clear START_DET Interrupt Register                     */
  __I  uint16_t  RESERVED22;
  __IO uint16_t  I2C2_CLR_GEN_CALL_REG;             /*!< (@ 0x50001568) Clear GEN_CALL Interrupt Register                      */
  __I  uint16_t  RESERVED23;
  __IO uint16_t  I2C2_ENABLE_REG;                   /*!< (@ 0x5000156C) I2C Enable Register                                    */
  __I  uint16_t  RESERVED24;
  __IO uint16_t  I2C2_STATUS_REG;                   /*!< (@ 0x50001570) I2C Status Register                                    */
  __I  uint16_t  RESERVED25;
  __IO uint16_t  I2C2_TXFLR_REG;                    /*!< (@ 0x50001574) I2C Transmit FIFO Level Register                       */
  __I  uint16_t  RESERVED26;
  __IO uint16_t  I2C2_RXFLR_REG;                    /*!< (@ 0x50001578) I2C Receive FIFO Level Register                        */
  __I  uint16_t  RESERVED27;
  __IO uint16_t  I2C2_SDA_HOLD_REG;                 /*!< (@ 0x5000157C) I2C SDA Hold Time Length Register                      */
  __I  uint16_t  RESERVED28;
  __IO uint16_t  I2C2_TX_ABRT_SOURCE_REG;           /*!< (@ 0x50001580) I2C Transmit Abort Source Register                     */
  __I  uint16_t  RESERVED29[3];
  __IO uint16_t  I2C2_DMA_CR_REG;                   /*!< (@ 0x50001588) DMA Control Register                                   */
  __I  uint16_t  RESERVED30;
  __IO uint16_t  I2C2_DMA_TDLR_REG;                 /*!< (@ 0x5000158C) DMA Transmit Data Level Register                       */
  __I  uint16_t  RESERVED31;
  __IO uint16_t  I2C2_DMA_RDLR_REG;                 /*!< (@ 0x50001590) I2C Receive Data Level Register                        */
  __I  uint16_t  RESERVED32;
  __IO uint16_t  I2C2_SDA_SETUP_REG;                /*!< (@ 0x50001594) I2C SDA Setup Register                                 */
  __I  uint16_t  RESERVED33;
  __IO uint16_t  I2C2_ACK_GENERAL_CALL_REG;         /*!< (@ 0x50001598) I2C ACK General Call Register                          */
  __I  uint16_t  RESERVED34;
  __IO uint16_t  I2C2_ENABLE_STATUS_REG;            /*!< (@ 0x5000159C) I2C Enable Status Register                             */
  __I  uint16_t  RESERVED35;
  __IO uint16_t  I2C2_IC_FS_SPKLEN_REG;             /*!< (@ 0x500015A0) I2C SS and FS spike suppression limit Size             */
  __I  uint16_t  RESERVED36[41];
  __IO uint16_t  I2C2_COMP_PARAM1_REG;              /*!< (@ 0x500015F4) Component Parameter Register                           */
  __IO uint16_t  I2C2_COMP_PARAM2_REG;              /*!< (@ 0x500015F6) Component Parameter Register 2                         */
  __IO uint16_t  I2C2_COMP_VERSION_REG;             /*!< (@ 0x500015F8) I2C Component Version Register                         */
  __IO uint16_t  I2C2_COMP2_VERSION;                /*!< (@ 0x500015FA) I2C Component2 Version Register                        */
  __IO uint16_t  I2C2_COMP_TYPE_REG;                /*!< (@ 0x500015FC) I2C Component Type Register                            */
  __IO uint16_t  I2C2_COMP_TYPE2_REG;               /*!< (@ 0x500015FE) I2C Component2 Type Register                           */
} I2C2_Type;


/* ================================================================================ */
/* ================                       IR                       ================ */
/* ================================================================================ */


/**
  * @brief IR registers (IR)
  */

typedef struct {                                    /*!< (@ 0x50001700) IR Structure                                           */
  __IO uint16_t  IR_FREQ_CARRIER_ON_REG;            /*!< (@ 0x50001700) Defines the carrier signal high duration               */
  __IO uint16_t  IR_FREQ_CARRIER_OFF_REG;           /*!< (@ 0x50001702) Defnes the carrier signal low duration                 */
  __IO uint16_t  IR_LOGIC_ONE_TIME_REG;             /*!< (@ 0x50001704) Defines the logic one waveform                         */
  __IO uint16_t  IR_LOGIC_ZERO_TIME_REG;            /*!< (@ 0x50001706) Defines the logic zero wavefrom                        */
  __IO uint16_t  IR_CTRL_REG;                       /*!< (@ 0x50001708) IR control register                                    */
  __IO uint16_t  IR_STATUS_REG;                     /*!< (@ 0x5000170A) IR status register                                     */
  __IO uint16_t  IR_REPEAT_TIME_REG;                /*!< (@ 0x5000170C) Defines the repeat time                                */
  __IO uint16_t  IR_MAIN_FIFO_REG;                  /*!< (@ 0x5000170E) Main fifo write register                               */
  __IO uint16_t  IR_REPEAT_FIFO_REG;                /*!< (@ 0x50001710) Repeat fifo write register                             */
  __IO uint16_t  IR_IRQ_STATUS_REG;                 /*!< (@ 0x50001712) IR interrupt status register                           */
} IR_Type;


/* ================================================================================ */
/* ================                     KBSCAN                     ================ */
/* ================================================================================ */


/**
  * @brief KBSCAN registers (KBSCAN)
  */

typedef struct {                                    /*!< (@ 0x50001600) KBSCAN Structure                                       */
  __IO uint16_t  KBSCN_CTRL_REG;                    /*!< (@ 0x50001600) Keyboard scanner control register                      */
  __IO uint16_t  KBSCN_CTRL2_REG;                   /*!< (@ 0x50001602) Keyboard scanner control 2 register                    */
  __IO uint16_t  KBSCN_MATRIX_SIZE_REG;             /*!< (@ 0x50001604) Defines the number of rows and columns of the
                                                         matrix                                                                */
  __IO uint16_t  KBSCN_DEBOUNCE_REG;                /*!< (@ 0x50001606) Defines the debounce time for key press and release    */
  __IO uint16_t  KBSCN_STATUS_REG;                  /*!< (@ 0x50001608) keyboard scanner Interrupt status register             */
  __IO uint16_t  KBSCN_MESSAGE_KEY_REG;             /*!< (@ 0x5000160A) Returns a key message from the message queue           */
  __IO uint16_t  KBSCN_P00_MODE_REG;                /*!< (@ 0x5000160C) Defines the keyboard mode for P00                      */
  __IO uint16_t  KBSCN_P01_MODE_REG;                /*!< (@ 0x5000160E) Defines the keyboard mode for P01                      */
  __IO uint16_t  KBSCN_P02_MODE_REG;                /*!< (@ 0x50001610) Defines the keyboard mode for P02                      */
  __IO uint16_t  KBSCN_P03_MODE_REG;                /*!< (@ 0x50001612) Defines the keyboard mode for P03                      */
  __IO uint16_t  KBSCN_P04_MODE_REG;                /*!< (@ 0x50001614) Defines the keyboard mode for P04                      */
  __IO uint16_t  KBSCN_P05_MODE_REG;                /*!< (@ 0x50001616) Defines the keyboard mode for P05                      */
  __IO uint16_t  KBSCN_P06_MODE_REG;                /*!< (@ 0x50001618) Defines the keyboard mode for P06                      */
  __IO uint16_t  KBSCN_P07_MODE_REG;                /*!< (@ 0x5000161A) Defines the keyboard mode for P07                      */
  __IO uint16_t  KBSCN_P10_MODE_REG;                /*!< (@ 0x5000161C) Defines the keyboard mode for P10                      */
  __IO uint16_t  KBSCN_P11_MODE_REG;                /*!< (@ 0x5000161E) Defines the keyboard mode for P11                      */
  __IO uint16_t  KBSCN_P12_MODE_REG;                /*!< (@ 0x50001620) Defines the keyboard mode for P12                      */
  __IO uint16_t  KBSCN_P13_MODE_REG;                /*!< (@ 0x50001622) Defines the keyboard mode for P13                      */
  __IO uint16_t  KBSCN_P14_MODE_REG;                /*!< (@ 0x50001624) Defines the keyboard mode for P14                      */
  __IO uint16_t  KBSCN_P15_MODE_REG;                /*!< (@ 0x50001626) Defines the keyboard mode for P15                      */
  __IO uint16_t  KBSCN_P16_MODE_REG;                /*!< (@ 0x50001628) Defines the keyboard mode for P16                      */
  __IO uint16_t  KBSCN_P17_MODE_REG;                /*!< (@ 0x5000162A) Defines the keyboard mode for P17                      */
  __IO uint16_t  KBSCN_P20_MODE_REG;                /*!< (@ 0x5000162C) Defines the keyboard mode for P20                      */
  __IO uint16_t  KBSCN_P21_MODE_REG;                /*!< (@ 0x5000162E) Defines the keyboard mode for P21                      */
  __IO uint16_t  KBSCN_P22_MODE_REG;                /*!< (@ 0x50001630) Defines the keyboard mode for P22                      */
  __IO uint16_t  KBSCN_P23_MODE_REG;                /*!< (@ 0x50001632) Defines the keyboard mode for P23                      */
  __IO uint16_t  KBSCN_P24_MODE_REG;                /*!< (@ 0x50001634) Defines the keyboard mode for P24                      */
  __I  uint16_t  RESERVED[3];
  __IO uint16_t  KBSCN_P30_MODE_REG;                /*!< (@ 0x5000163C) Defines the keyboard mode for P30                      */
  __IO uint16_t  KBSCN_P31_MODE_REG;                /*!< (@ 0x5000163E) Defines the keyboard mode for P31                      */
  __IO uint16_t  KBSCN_P32_MODE_REG;                /*!< (@ 0x50001640) Defines the keyboard mode for P32                      */
  __IO uint16_t  KBSCN_P33_MODE_REG;                /*!< (@ 0x50001642) Defines the keyboard mode for P33                      */
  __IO uint16_t  KBSCN_P34_MODE_REG;                /*!< (@ 0x50001644) Defines the keyboard mode for P34                      */
  __IO uint16_t  KBSCN_P35_MODE_REG;                /*!< (@ 0x50001646) Defines the keyboard mode for P35                      */
  __IO uint16_t  KBSCN_P36_MODE_REG;                /*!< (@ 0x50001648) Defines the keyboard mode for P36                      */
  __IO uint16_t  KBSCN_P37_MODE_REG;                /*!< (@ 0x5000164A) Defines the keyboard mode for P37                      */
  __IO uint16_t  KBSCN_P40_MODE_REG;                /*!< (@ 0x5000164C) Defines the keyboard mode for P40                      */
  __IO uint16_t  KBSCN_P41_MODE_REG;                /*!< (@ 0x5000164E) Defines the keyboard mode for P41                      */
  __IO uint16_t  KBSCN_P42_MODE_REG;                /*!< (@ 0x50001650) Defines the keyboard mode for P42                      */
  __IO uint16_t  KBSCN_P43_MODE_REG;                /*!< (@ 0x50001652) Defines the keyboard mode for P43                      */
  __IO uint16_t  KBSCN_P44_MODE_REG;                /*!< (@ 0x50001654) Defines the keyboard mode for P44                      */
  __IO uint16_t  KBSCN_P45_MODE_REG;                /*!< (@ 0x50001656) Defines the keyboard mode for P45                      */
  __IO uint16_t  KBSCN_P46_MODE_REG;                /*!< (@ 0x50001658) Defines the keyboard mode for P46                      */
  __IO uint16_t  KBSCN_P47_MODE_REG;                /*!< (@ 0x5000165A) Defines the keyboard mode for P47                      */
} KBSCAN_Type;


/* ================================================================================ */
/* ================                      OTPC                      ================ */
/* ================================================================================ */


/**
  * @brief OTPC registers (OTPC)
  */

typedef struct {                                    /*!< (@ 0x07F40000) OTPC Structure                                         */
  __IO uint32_t  OTPC_MODE_REG;                     /*!< (@ 0x07F40000) Mode register                                          */
  __IO uint32_t  OTPC_PCTRL_REG;                    /*!< (@ 0x07F40004) Bit-programming control register                       */
  __IO uint32_t  OTPC_STAT_REG;                     /*!< (@ 0x07F40008) Status register                                        */
  __IO uint32_t  OTPC_AHBADR_REG;                   /*!< (@ 0x07F4000C) AHB master start address                               */
  __IO uint32_t  OTPC_CELADR_REG;                   /*!< (@ 0x07F40010) Macrocell start address                                */
  __IO uint32_t  OTPC_NWORDS_REG;                   /*!< (@ 0x07F40014) Number of words                                        */
  __IO uint32_t  OTPC_FFPRT_REG;                    /*!< (@ 0x07F40018) Ports access to fifo logic                             */
  __IO uint32_t  OTPC_FFRD_REG;                     /*!< (@ 0x07F4001C) The data which have taken with the latest read
                                                         from the OTPC_FFPRT_REG                                               */
  __IO uint32_t  OTPC_PWORDL_REG;                   /*!< (@ 0x07F40020) The 32 lower bits of the 64-bit word that will
                                                         be programmed, when the MPROG mode is used.                           */
  __IO uint32_t  OTPC_PWORDH_REG;                   /*!< (@ 0x07F40024) The 32 higher bits of the 64-bit word that will
                                                         be programmed, when the MPROG mode is used.                           */
  __IO uint32_t  OTPC_TIM1_REG;                     /*!< (@ 0x07F40028) Various timing parameters of the OTP cell.             */
  __IO uint32_t  OTPC_TIM2_REG;                     /*!< (@ 0x07F4002C) Various timing parameters of the OTP cell.             */
  __IO uint32_t  OTPC_TEST_REG;                     /*!< (@ 0x07F40030) OTPC_TEST_REG                                          */
} OTPC_Type;


/* ================================================================================ */
/* ================                      PATCH                     ================ */
/* ================================================================================ */


/**
  * @brief PATCH registers (PATCH)
  */

typedef struct {                                    /*!< (@ 0x40050000) PATCH Structure                                        */
  __IO uint32_t  PATCH_VALID_REG;                   /*!< (@ 0x40050000) Validity Control Register                              */
  __IO uint32_t  PATCH_VALID_SET_REG;               /*!< (@ 0x40050004) Validity Set Control Register                          */
  __IO uint32_t  PATCH_VALID_RESET_REG;             /*!< (@ 0x40050008) Validity Reset Control Register                        */
  __I  uint32_t  RESERVED[5];
  __IO uint32_t  PATCH_ADDR0_REG;                   /*!< (@ 0x40050020) Patch Address field                                    */
  __I  uint32_t  RESERVED1;
  __IO uint32_t  PATCH_ADDR1_REG;                   /*!< (@ 0x40050028) Patch Address field                                    */
  __I  uint32_t  RESERVED2;
  __IO uint32_t  PATCH_ADDR2_REG;                   /*!< (@ 0x40050030) Patch Address field                                    */
  __I  uint32_t  RESERVED3;
  __IO uint32_t  PATCH_ADDR3_REG;                   /*!< (@ 0x40050038) Patch Address field                                    */
  __I  uint32_t  RESERVED4;
  __IO uint32_t  PATCH_ADDR4_REG;                   /*!< (@ 0x40050040) Patch Address field                                    */
  __I  uint32_t  RESERVED5;
  __IO uint32_t  PATCH_ADDR5_REG;                   /*!< (@ 0x40050048) Patch Address field                                    */
  __I  uint32_t  RESERVED6;
  __IO uint32_t  PATCH_ADDR6_REG;                   /*!< (@ 0x40050050) Patch Address field                                    */
  __I  uint32_t  RESERVED7;
  __IO uint32_t  PATCH_ADDR7_REG;                   /*!< (@ 0x40050058) Patch Address field                                    */
  __I  uint32_t  RESERVED8;
  __IO uint32_t  PATCH_ADDR8_REG;                   /*!< (@ 0x40050060) Patch Address field                                    */
  __I  uint32_t  RESERVED9;
  __IO uint32_t  PATCH_ADDR9_REG;                   /*!< (@ 0x40050068) Patch Address field                                    */
  __I  uint32_t  RESERVED10;
  __IO uint32_t  PATCH_ADDR10_REG;                  /*!< (@ 0x40050070) Patch Address field                                    */
  __I  uint32_t  RESERVED11;
  __IO uint32_t  PATCH_ADDR11_REG;                  /*!< (@ 0x40050078) Patch Address field                                    */
  __I  uint32_t  RESERVED12;
  __IO uint32_t  PATCH_ADDR12_REG;                  /*!< (@ 0x40050080) Patch Address field                                    */
  __I  uint32_t  RESERVED13;
  __IO uint32_t  PATCH_ADDR13_REG;                  /*!< (@ 0x40050088) Patch Address field                                    */
  __I  uint32_t  RESERVED14;
  __IO uint32_t  PATCH_ADDR14_REG;                  /*!< (@ 0x40050090) Patch Address field                                    */
  __I  uint32_t  RESERVED15;
  __IO uint32_t  PATCH_ADDR15_REG;                  /*!< (@ 0x40050098) Patch Address field                                    */
  __I  uint32_t  RESERVED16;
  __IO uint32_t  PATCH_ADDR16_REG;                  /*!< (@ 0x400500A0) Patch Address field                                    */
  __I  uint32_t  RESERVED17;
  __IO uint32_t  PATCH_ADDR17_REG;                  /*!< (@ 0x400500A8) Patch Address field                                    */
  __I  uint32_t  RESERVED18;
  __IO uint32_t  PATCH_ADDR18_REG;                  /*!< (@ 0x400500B0) Patch Address field                                    */
  __I  uint32_t  RESERVED19;
  __IO uint32_t  PATCH_ADDR19_REG;                  /*!< (@ 0x400500B8) Patch Address field                                    */
  __I  uint32_t  RESERVED20;
  __IO uint32_t  PATCH_ADDR20_REG;                  /*!< (@ 0x400500C0) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA20_REG;                  /*!< (@ 0x400500C4) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR21_REG;                  /*!< (@ 0x400500C8) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA21_REG;                  /*!< (@ 0x400500CC) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR22_REG;                  /*!< (@ 0x400500D0) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA22_REG;                  /*!< (@ 0x400500D4) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR23_REG;                  /*!< (@ 0x400500D8) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA23_REG;                  /*!< (@ 0x400500DC) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR24_REG;                  /*!< (@ 0x400500E0) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA24_REG;                  /*!< (@ 0x400500E4) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR25_REG;                  /*!< (@ 0x400500E8) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA25_REG;                  /*!< (@ 0x400500EC) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR26_REG;                  /*!< (@ 0x400500F0) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA26_REG;                  /*!< (@ 0x400500F4) Patch Data field                                       */
  __IO uint32_t  PATCH_ADDR27_REG;                  /*!< (@ 0x400500F8) Patch Address field                                    */
  __IO uint32_t  PATCH_DATA27_REG;                  /*!< (@ 0x400500FC) Patch Data field                                       */
} PATCH_Type;


/* ================================================================================ */
/* ================                     PLLDIG                     ================ */
/* ================================================================================ */


/**
  * @brief PLLDIG registers (PLLDIG)
  */

typedef struct {                                    /*!< (@ 0x50002D00) PLLDIG Structure                                       */
  __IO uint16_t  RF_SYNTH_CTRL1_BLE_REG;            /*!< (@ 0x50002D00) RF_SYNTH_CTRL1_BLE_REG                                 */
  __IO uint16_t  RF_SYNTH_CTRL1_FTDF_REG;           /*!< (@ 0x50002D02) RF_SYNTH_CTRL1_FTDF_REG                                */
  __IO uint16_t  RF_SYNTH_CTRL2_BLE_REG;            /*!< (@ 0x50002D04) RF_SYNTH_CTRL2_BLE_REG                                 */
  __IO uint16_t  RF_SYNTH_CTRL2_FTDF_REG;           /*!< (@ 0x50002D06) RF_SYNTH_CTRL2_FTDF_REG                                */
  __IO uint16_t  RF_SYNTH_CTRL3_REG;                /*!< (@ 0x50002D08) RF_SYNTH_CTRL3_REG                                     */
  __IO uint16_t  RF_VCOCAL_CTRL_REG;                /*!< (@ 0x50002D0A) RF_VCOCAL_CTRL_REG                                     */
  __IO uint16_t  RF_MGAIN_CTRL_BLE_REG;             /*!< (@ 0x50002D0C) RF_MGAIN_CTRL_BLE_REG                                  */
  __IO uint16_t  RF_MGAIN_CTRL_FTDF_REG;            /*!< (@ 0x50002D0E) RF_MGAIN_CTRL_FTDF_REG                                 */
  __IO uint16_t  RF_MGAIN_CTRL2_REG;                /*!< (@ 0x50002D10) RF_MGAIN_CTRL2_REG                                     */
  __IO uint16_t  RF_VCO_CALCAP_BIT14_REG;           /*!< (@ 0x50002D12) RF_VCO_CALCAP_BIT14_REG                                */
  __IO uint16_t  RF_VCO_CALCAP_BIT15_REG;           /*!< (@ 0x50002D14) RF_VCO_CALCAP_BIT15_REG                                */
  __IO uint16_t  RF_BMCW_REG;                       /*!< (@ 0x50002D16) RF_BMCW_REG                                            */
  __IO uint16_t  RF_KMOD_ALPHA_BLE_REG;             /*!< (@ 0x50002D18) RF_KMOD_ALPHA_BLE_REG                                  */
  __IO uint16_t  RF_KMOD_ALPHA_FTDF_REG;            /*!< (@ 0x50002D1A) RF_KMOD_ALPHA_FTDF_REG                                 */
  __I  uint16_t  RESERVED;
  __IO uint16_t  RF_SYNTH_RESULT_BLE_REG;           /*!< (@ 0x50002D1E) Must be Retained                                       */
  __IO uint16_t  RF_SYNTH_RESULT_FTDF_REG;          /*!< (@ 0x50002D20) Must be Retained                                       */
  __IO uint16_t  RF_SYNTH_RESULT2_BLE_REG;          /*!< (@ 0x50002D22) Must be Retained                                       */
  __IO uint16_t  RF_SYNTH_RESULT2_FTDF_REG;         /*!< (@ 0x50002D24) Must be Retained                                       */
  __IO uint16_t  RF_SYNTH_RESULT3_FTDF_REG;         /*!< (@ 0x50002D26) RF_SYNTH_RESULT3_FTDF_REG                              */
  __IO uint16_t  RF_CALCAP1_REG;                    /*!< (@ 0x50002D28) RF_CALCAP1_REG                                         */
  __IO uint16_t  RF_CALCAP2_REG;                    /*!< (@ 0x50002D2A) RF_CALCAP2_REG                                         */
  __IO uint16_t  RF_NMD_OFFSET_REG;                 /*!< (@ 0x50002D2C) Offset values for phase alignment after VCO calibration. */
  __I  uint16_t  RESERVED1;
  __IO uint16_t  RF_FTDF_PHYATTR_REG;               /*!< (@ 0x50002D30) RF_FTDF_PHYATTR_REG                                    */
  __IO uint16_t  RF_CALTRIM_STEP1_REG;              /*!< (@ 0x50002D32) RF_CALTRIM_STEP1_REG                                   */
  __IO uint16_t  RF_CALTRIM_STEP2_REG;              /*!< (@ 0x50002D34) RF_CALTRIM_STEP2_REG                                   */
  __IO uint16_t  RF_CALTRIM_STEP3_REG;              /*!< (@ 0x50002D36) RF_CALTRIM_STEP3_REG                                   */
  __IO uint16_t  RF_CALTRIM_STEP4_REG;              /*!< (@ 0x50002D38) RF_CALTRIM_STEP4_REG                                   */
  __IO uint16_t  RF_MGAIN_CTRL3_REG;                /*!< (@ 0x50002D3A) RF_MGAIN_CTRL3_REG                                     */
  __IO uint16_t  RF_VCO_FREQ_EST_REG;               /*!< (@ 0x50002D3C) RF_VCO_FREQ_EST_REG                                    */
  __I  uint16_t  RESERVED2;
  __IO uint16_t  RF_SYNTH_SPARE_REG;                /*!< (@ 0x50002D40) MSK modulator control register                         */
  __IO uint16_t  RF_MSKMOD_CTRL1_REG;               /*!< (@ 0x50002D42) MSK modulator control register                         */
  __IO uint16_t  RF_MSKMOD_CHIPL_REG;               /*!< (@ 0x50002D44) MSK modulator CHIP control lower 16 bit                */
  __IO uint16_t  RF_MSKMOD_CHIPH_REG;               /*!< (@ 0x50002D46) MSK modulator CHIP control upper 16 bit                */
  __IO uint16_t  RF_TXDAC_TEST_REG;                 /*!< (@ 0x50002D48) Register to provide value to TXDAC                     */
  __I  uint16_t  RESERVED3[3];
  __IO uint16_t  RF_MGAIN_COMP_VAL0_REG;            /*!< (@ 0x50002D50) RF_MGAIN_COMP_VAL0_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL1_REG;            /*!< (@ 0x50002D52) RF_MGAIN_COMP_VAL1_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL2_REG;            /*!< (@ 0x50002D54) RF_MGAIN_COMP_VAL2_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL3_REG;            /*!< (@ 0x50002D56) RF_MGAIN_COMP_VAL3_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL4_REG;            /*!< (@ 0x50002D58) RF_MGAIN_COMP_VAL4_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL5_REG;            /*!< (@ 0x50002D5A) RF_MGAIN_COMP_VAL5_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL6_REG;            /*!< (@ 0x50002D5C) RF_MGAIN_COMP_VAL6_REG                                 */
  __IO uint16_t  RF_MGAIN_COMP_VAL7_REG;            /*!< (@ 0x50002D5E) RF_MGAIN_COMP_VAL7_REG                                 */
  __IO uint16_t  RF_PULSE_TBL_0_REG;                /*!< (@ 0x50002D60) RF_PULSE_TBL_0_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_1_REG;                /*!< (@ 0x50002D62) RF_PULSE_TBL_1_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_2_REG;                /*!< (@ 0x50002D64) RF_PULSE_TBL_2_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_3_REG;                /*!< (@ 0x50002D66) RF_PULSE_TBL_3_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_4_REG;                /*!< (@ 0x50002D68) RF_PULSE_TBL_4_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_5_REG;                /*!< (@ 0x50002D6A) RF_PULSE_TBL_5_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_6_REG;                /*!< (@ 0x50002D6C) RF_PULSE_TBL_6_REG                                     */
  __IO uint16_t  RF_PULSE_TBL_7_REG;                /*!< (@ 0x50002D6E) RF_PULSE_TBL_7_REG                                     */
  __IO uint16_t  RF_PULSE_CTRL_REG;                 /*!< (@ 0x50002D70) RF_PULSE_CTRL_REG                                      */
} PLLDIG_Type;


/* ================================================================================ */
/* ================                      QSPIC                     ================ */
/* ================================================================================ */


/**
  * @brief QSPIC registers (QSPIC)
  */

typedef struct {                                    /*!< (@ 0x0C000000) QSPIC Structure                                        */
  __IO uint32_t  QSPIC_CTRLBUS_REG;                 /*!< (@ 0x0C000000) SPI Bus control register for the Manual mode           */
  __IO uint32_t  QSPIC_CTRLMODE_REG;                /*!< (@ 0x0C000004) Mode Control register                                  */
  __IO uint32_t  QSPIC_RECVDATA_REG;                /*!< (@ 0x0C000008) Received data for the Manual mode                      */
  __IO uint32_t  QSPIC_BURSTCMDA_REG;               /*!< (@ 0x0C00000C) The way of reading in Auto mode (command register
                                                         A)                                                                    */
  __IO uint32_t  QSPIC_BURSTCMDB_REG;               /*!< (@ 0x0C000010) The way of reading in Auto mode (command register
                                                         B)                                                                    */
  __IO uint32_t  QSPIC_STATUS_REG;                  /*!< (@ 0x0C000014) The status register of the QSPI controller             */
  __IO uint32_t  QSPIC_WRITEDATA_REG;               /*!< (@ 0x0C000018) Write data to SPI Bus for the Manual mode              */
  __IO uint32_t  QSPIC_READDATA_REG;                /*!< (@ 0x0C00001C) Read data from SPI Bus for the Manual mode             */
  __IO uint32_t  QSPIC_DUMMYDATA_REG;               /*!< (@ 0x0C000020) Send dummy clocks to SPI Bus for the Manual mode       */
  __IO uint32_t  QSPIC_ERASECTRL_REG;               /*!< (@ 0x0C000024) QSPI Erase control register                            */
  __IO uint32_t  QSPIC_ERASECMDA_REG;               /*!< (@ 0x0C000028) The way of erasing in Auto mode (command register
                                                         A)                                                                    */
  __IO uint32_t  QSPIC_ERASECMDB_REG;               /*!< (@ 0x0C00002C) The way of erasing in Auto mode (command register
                                                         B)                                                                    */
  __IO uint32_t  QSPIC_BURSTBRK_REG;                /*!< (@ 0x0C000030) Read break sequence in Auto mode                       */
  __IO uint32_t  QSPIC_STATUSCMD_REG;               /*!< (@ 0x0C000034) The way of reading the status of external device
                                                         in Auto mode                                                          */
  __IO uint32_t  QSPIC_CHCKERASE_REG;               /*!< (@ 0x0C000038) Check erase progress in Auto mode                      */
  __IO uint32_t  QSPIC_GP_REG;                      /*!< (@ 0x0C00003C) QSPI General Purpose control register                  */
  __IO uint32_t  QSPIC_UCODE_START;                 /*!< (@ 0x0C000040) QSPIC uCode memory                                     */
} QSPIC_Type;


/* ================================================================================ */
/* ================                      QUAD                      ================ */
/* ================================================================================ */


/**
  * @brief QUAD registers (QUAD)
  */

typedef struct {                                    /*!< (@ 0x50001A00) QUAD Structure                                         */
  __IO uint16_t  QDEC_CTRL_REG;                     /*!< (@ 0x50001A00) Quad decoder control register                          */
  __IO uint16_t  QDEC_XCNT_REG;                     /*!< (@ 0x50001A02) Counter value of the X Axis                            */
  __IO uint16_t  QDEC_YCNT_REG;                     /*!< (@ 0x50001A04) Counter value of the Y Axis                            */
  __IO uint16_t  QDEC_ZCNT_REG;                     /*!< (@ 0x50001A06) Counter value of the Z Axis                            */
  __IO uint16_t  QDEC_CLOCKDIV_REG;                 /*!< (@ 0x50001A08) Quad decoder clock divider register                    */
} QUAD_Type;


/* ================================================================================ */
/* ================                      RFCU                      ================ */
/* ================================================================================ */


/**
  * @brief RFCU registers (RFCU)
  */

typedef struct {                                    /*!< (@ 0x50002000) RFCU Structure                                         */
  __I  uint32_t  RESERVED[4];
  __IO uint16_t  RF_OVERRULE_REG;                   /*!< (@ 0x50002010) RF_OVERRULE_REG                                        */
  __IO uint16_t  RF_DIAGIRQ01_REG;                  /*!< (@ 0x50002012) BLE/RF Diagnostic IRQ Control Register                 */
  __IO uint16_t  RF_DIAGIRQ23_REG;                  /*!< (@ 0x50002014) BLE/RF Diagnostic IRQ Control Register                 */
  __IO uint16_t  RF_DIAGIRQ_STAT_REG;               /*!< (@ 0x50002016) BLE/RF Diagnostic IRQ Status Register                  */
  __IO uint16_t  RF_AGC_EXT1_LUT_REG;               /*!< (@ 0x50002018) RF_AGC_EXT1_LUT_REG                                    */
  __I  uint16_t  RESERVED1[3];
  __IO uint16_t  RF_CALSTATE_REG;                   /*!< (@ 0x50002020) RF_CALSTATE_REG                                        */
  __I  uint16_t  RESERVED2[15];
  __IO uint16_t  RF_SCAN_FEEDBACK_REG;              /*!< (@ 0x50002040) RF_SCAN_FEEDBACK_REG                                   */
  __IO uint16_t  RF_REF_OSC_BLE_REG;                /*!< (@ 0x50002042) RF_REF_OSC_BLE_REG                                     */
  __IO uint16_t  RF_REF_OSC_FTDF_REG;               /*!< (@ 0x50002044) RF_REF_OSC_FTDF_REG                                    */
  __I  uint16_t  RESERVED3[5];
  __IO uint16_t  RF_CAL_CTRL_REG;                   /*!< (@ 0x50002050) RF_CAL_CTRL_REG                                        */
  __I  uint16_t  RESERVED4;
  __IO uint16_t  RF_IRQ_CTRL_REG;                   /*!< (@ 0x50002054) RF_IRQ_CTRL_REG                                        */
  __I  uint16_t  RESERVED5;
  __IO uint16_t  RF_ADCI_DC_OFFSET_REG;             /*!< (@ 0x50002058) Must be Retained                                       */
  __IO uint16_t  RF_ADCQ_DC_OFFSET_REG;             /*!< (@ 0x5000205A) Must be Retained                                       */
  __I  uint32_t  RESERVED6[9];
  __IO uint16_t  RF_SPARE1_BLE_REG;                 /*!< (@ 0x50002080) RF_SPARE1_BLE_REG                                      */
  __IO uint16_t  RF_SPARE1_FTDF_REG;                /*!< (@ 0x50002082) RF_SPARE1_FTDF_REG                                     */
  __IO uint16_t  RF_BIAS_CTRL1_BLE_REG;             /*!< (@ 0x50002084) RF_BIAS_CTRL1_BLE_REG                                  */
  __IO uint16_t  RF_BIAS_CTRL1_FTDF_REG;            /*!< (@ 0x50002086) RF_BIAS_CTRL1_FTDF_REG                                 */
  __IO uint16_t  RF_IFF_CTRL1_REG;                  /*!< (@ 0x50002088) RF_IFF_CTRL1_REG                                       */
  __IO uint16_t  RF_ADC_CTRL1_REG;                  /*!< (@ 0x5000208A) RF_ADC_CTRL1_REG                                       */
  __IO uint16_t  RF_ADC_CTRL2_REG;                  /*!< (@ 0x5000208C) RF_ADC_CTRL2_REG                                       */
  __IO uint16_t  RF_ADC_CTRL3_REG;                  /*!< (@ 0x5000208E) RF_ADC_CTRL3_REG                                       */
  __IO uint16_t  RF_PA_CTRL_REG;                    /*!< (@ 0x50002090) Removed obsolete values of bits 10:7, pa_pw back
                                                         to 4                                                                  */
  __IO uint16_t  RF_MGC_CTRL_REG;                   /*!< (@ 0x50002092) RF_MGC_CTRL_REG                                        */
  __IO uint16_t  RF_VCOVAR_CTRL_REG;                /*!< (@ 0x50002094) RF_VCOVAR_CTRL_REG                                     */
  __IO uint16_t  RF_PFD_CTRL_REG;                   /*!< (@ 0x50002096) RF_PFD_CTRL_REG                                        */
  __IO uint16_t  RF_CP_CTRL_BLE_REG;                /*!< (@ 0x50002098) RF_CP_CTRL_BLE_REG                                     */
  __IO uint16_t  RF_CP_CTRL_FTDF_REG;               /*!< (@ 0x5000209A) RF_CP_CTRL_FTDF_REG                                    */
  __IO uint16_t  RF_LF_RES_CTRL_BLE_REG;            /*!< (@ 0x5000209C) LF resistor setting in BLE mode                        */
  __IO uint16_t  RF_LF_RES_CTRL_FTDF_REG;           /*!< (@ 0x5000209E) LF resistor setting in FTDF mode                       */
  __IO uint16_t  RF_MIXER_CTRL1_BLE_REG;            /*!< (@ 0x500020A0) RF_MIXER_CTRL1_BLE_REG                                 */
  __IO uint16_t  RF_MIXER_CTRL1_FTDF_REG;           /*!< (@ 0x500020A2) RF_MIXER_CTRL1_FTDF_REG                                */
  __IO uint16_t  RF_MIXER_CTRL2_REG;                /*!< (@ 0x500020A4) RF_MIXER_CTRL2_REG                                     */
  __IO uint16_t  RF_LF_CTRL_REG;                    /*!< (@ 0x500020A6) RF_LF_CTRL_REG                                         */
  __IO uint16_t  RF_TDC_CTRL_REG;                   /*!< (@ 0x500020A8) TDC settings                                           */
  __IO uint16_t  RF_IO_CTRL1_REG;                   /*!< (@ 0x500020AA) RF_IO_CTRL1_REG                                        */
  __IO uint16_t  RF_LNA_CTRL1_REG;                  /*!< (@ 0x500020AC) RF_LNA_CTRL1_REG                                       */
  __IO uint16_t  RF_LNA_CTRL2_REG;                  /*!< (@ 0x500020AE) RF_LNA_CTRL2_REG                                       */
  __IO uint16_t  RF_LNA_CTRL3_REG;                  /*!< (@ 0x500020B0) RF_LNA_CTRL3_REG                                       */
  __IO uint16_t  RF_VCO_AMP_CTRL1_REG;              /*!< (@ 0x500020B2) RF_VCO_AMP_CTRL1_REG                                   */
  __IO uint16_t  RF_VCO_AMP_CTRL2_REG;              /*!< (@ 0x500020B4) RF_VCO_AMP_CTRL2_REG                                   */
  __I  uint16_t  RESERVED7[5];
  __IO uint16_t  RF_TX_PWR_BLE_REG;                 /*!< (@ 0x500020C0) TX Power setting                                       */
  __IO uint16_t  RF_TX_PWR_LUT_1_REG;               /*!< (@ 0x500020C2) TX Power setting 1                                     */
  __IO uint16_t  RF_TX_PWR_LUT_2_REG;               /*!< (@ 0x500020C4) TX Power setting 2                                     */
  __IO uint16_t  RF_TX_PWR_LUT_3_REG;               /*!< (@ 0x500020C6) TX Power setting 3                                     */
  __IO uint16_t  RF_TX_PWR_LUT_4_REG;               /*!< (@ 0x500020C8) TX Power setting 4                                     */
  __IO uint16_t  RF_TX_PWR_LUT_5_REG;               /*!< (@ 0x500020CA) TX Power setting 5                                     */
  __IO uint16_t  RF_TX_PWR_LUT_6_REG;               /*!< (@ 0x500020CC) TX Power setting 6                                     */
  __IO uint16_t  RF_TX_PWR_LUT_7_REG;               /*!< (@ 0x500020CE) TX Power setting 7                                     */
  __IO uint16_t  RF_TX_PWR_FTDF_REG;                /*!< (@ 0x500020D0) TX Power setting                                       */
  __IO uint16_t  RF_TX_PWR_LUT_RD_REG;              /*!< (@ 0x500020D2) TX Power read back                                     */
  __IO uint16_t  RF_DIV_IQ_RX_REG;                  /*!< (@ 0x500020D4) Bias trimming of IQ divider                            */
  __IO uint16_t  RF_DIV_IQ_TX_REG;                  /*!< (@ 0x500020D6) Bias trimming of IQ divider                            */
  __IO uint16_t  RF_LO_IQ_TRIM_REG;                 /*!< (@ 0x500020D8) Trim settings for IQ LO path                           */
  __IO uint16_t  RF_TXDAC_CTRL_REG;                 /*!< (@ 0x500020DA) Control settings for the TXDAC                         */
  __IO uint16_t  RF_TXDAC_CAL_CAP_STAT_REG;         /*!< (@ 0x500020DC) Current CAL CAP value for TXDAC                        */
  __I  uint16_t  RESERVED8;
  __IO uint16_t  RF_IFF_RESULT_REG;                 /*!< (@ 0x500020E0) Not retained                                           */
  __IO uint16_t  RF_IFF_CC_BLE_SET1_REG;            /*!< (@ 0x500020E2) Must be retained                                       */
  __IO uint16_t  RF_IFF_CC_BLE_SET2_REG;            /*!< (@ 0x500020E4) Must be retained                                       */
  __IO uint16_t  RF_IFF_CC_FTDF_SET1_REG;           /*!< (@ 0x500020E6) Must be retained                                       */
  __IO uint16_t  RF_IFF_CC_FTDF_SET2_REG;           /*!< (@ 0x500020E8) Must be retained                                       */
  __IO uint16_t  RF_IFF_CAL_CAP_STAT_REG;           /*!< (@ 0x500020EA) Current CAL_CAP value applied to IF                    */
  __IO uint16_t  RF_MIX_CAL_CAP_STAT_REG;           /*!< (@ 0x500020EC) Current CAL_CAP value applied to IF                    */
  __IO uint16_t  RF_LF_CAL_CAP_STAT_REG;            /*!< (@ 0x500020EE) Current CAL_CAP value applied to IF                    */
} RFCU_Type;


/* ================================================================================ */
/* ================                   RFCU_POWER                   ================ */
/* ================================================================================ */


/**
  * @brief RFCU_POWER registers (RFCU_POWER)
  */

typedef struct {                                    /*!< (@ 0x50002200) RFCU_POWER Structure                                   */
  __IO uint16_t  RF_ENABLE_CONFIG0_REG;             /*!< (@ 0x50002200) RF_ENABLE_CONFIG0_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG1_REG;             /*!< (@ 0x50002202) RF_ENABLE_CONFIG1_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG2_REG;             /*!< (@ 0x50002204) RF_ENABLE_CONFIG2_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG3_REG;             /*!< (@ 0x50002206) RF_ENABLE_CONFIG3_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG4_REG;             /*!< (@ 0x50002208) RF_ENABLE_CONFIG4_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG5_REG;             /*!< (@ 0x5000220A) RF_ENABLE_CONFIG5_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG6_REG;             /*!< (@ 0x5000220C) RF_ENABLE_CONFIG6_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG7_REG;             /*!< (@ 0x5000220E) RF_ENABLE_CONFIG7_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG8_REG;             /*!< (@ 0x50002210) RF_ENABLE_CONFIG8_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG9_REG;             /*!< (@ 0x50002212) RF_ENABLE_CONFIG9_REG                                  */
  __IO uint16_t  RF_ENABLE_CONFIG10_REG;            /*!< (@ 0x50002214) RF_ENABLE_CONFIG10_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG11_REG;            /*!< (@ 0x50002216) RF_ENABLE_CONFIG11_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG12_REG;            /*!< (@ 0x50002218) RF_ENABLE_CONFIG12_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG13_REG;            /*!< (@ 0x5000221A) RF_ENABLE_CONFIG13_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG14_REG;            /*!< (@ 0x5000221C) RF_ENABLE_CONFIG14_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG15_REG;            /*!< (@ 0x5000221E) RF_ENABLE_CONFIG15_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG16_REG;            /*!< (@ 0x50002220) RF_ENABLE_CONFIG16_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG17_REG;            /*!< (@ 0x50002222) RF_ENABLE_CONFIG17_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG18_REG;            /*!< (@ 0x50002224) RF_ENABLE_CONFIG18_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG19_REG;            /*!< (@ 0x50002226) RF_ENABLE_CONFIG19_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG20_REG;            /*!< (@ 0x50002228) RF_ENABLE_CONFIG20_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG21_REG;            /*!< (@ 0x5000222A) RF_ENABLE_CONFIG21_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG22_REG;            /*!< (@ 0x5000222C) RF_ENABLE_CONFIG22_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG23_BLE_REG;        /*!< (@ 0x5000222E) RF_ENABLE_CONFIG23_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG24_BLE_REG;        /*!< (@ 0x50002230) RF_ENABLE_CONFIG24_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG25_REG;            /*!< (@ 0x50002232) RF_ENABLE_CONFIG25_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG26_REG;            /*!< (@ 0x50002234) RF_ENABLE_CONFIG26_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG27_REG;            /*!< (@ 0x50002236) RF_ENABLE_CONFIG27_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG28_REG;            /*!< (@ 0x50002238) RF_ENABLE_CONFIG28_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG29_REG;            /*!< (@ 0x5000223A) RF_ENABLE_CONFIG29_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG30_REG;            /*!< (@ 0x5000223C) RF_ENABLE_CONFIG30_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG31_BLE_REG;        /*!< (@ 0x5000223E) RF_ENABLE_CONFIG31_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG32_REG;            /*!< (@ 0x50002240) RF_ENABLE_CONFIG32_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG33_REG;            /*!< (@ 0x50002242) RF_ENABLE_CONFIG33_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG34_REG;            /*!< (@ 0x50002244) RF_ENABLE_CONFIG34_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG35_BLE_REG;        /*!< (@ 0x50002246) RF_ENABLE_CONFIG35_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG36_REG;            /*!< (@ 0x50002248) RF_ENABLE_CONFIG36_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG37_BLE_REG;        /*!< (@ 0x5000224A) RF_ENABLE_CONFIG37_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG38_BLE_REG;        /*!< (@ 0x5000224C) RF_ENABLE_CONFIG38_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG39_REG;            /*!< (@ 0x5000224E) RF_ENABLE_CONFIG39_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG40_REG;            /*!< (@ 0x50002250) RF_ENABLE_CONFIG40_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG41_REG;            /*!< (@ 0x50002252) RF_ENABLE_CONFIG41_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG42_REG;            /*!< (@ 0x50002254) RF_ENABLE_CONFIG42_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG43_REG;            /*!< (@ 0x50002256) RF_ENABLE_CONFIG43_REG                                 */
  __IO uint16_t  RF_ENABLE_CONFIG44_BLE_REG;        /*!< (@ 0x50002258) RF_ENABLE_CONFIG44_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG45_BLE_REG;        /*!< (@ 0x5000225A) RF_ENABLE_CONFIG45_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG46_BLE_REG;        /*!< (@ 0x5000225C) RF_ENABLE_CONFIG46_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG47_BLE_REG;        /*!< (@ 0x5000225E) RF_ENABLE_CONFIG47_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG48_BLE_REG;        /*!< (@ 0x50002260) RF_ENABLE_CONFIG48_BLE_REG                             */
  __IO uint16_t  RF_ENABLE_CONFIG49_BLE_REG;        /*!< (@ 0x50002262) RF_ENABLE_CONFIG49_BLE_REG                             */
  __I  uint16_t  RESERVED[37];
  __IO uint16_t  RF_ENABLE_CONFIG23_FTDF_REG;       /*!< (@ 0x500022AE) RF_ENABLE_CONFIG23_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG24_FTDF_REG;       /*!< (@ 0x500022B0) RF_ENABLE_CONFIG24_FTDF_REG                            */
  __I  uint16_t  RESERVED1[6];
  __IO uint16_t  RF_ENABLE_CONFIG31_FTDF_REG;       /*!< (@ 0x500022BE) RF_ENABLE_CONFIG31_FTDF_REG                            */
  __I  uint16_t  RESERVED2[3];
  __IO uint16_t  RF_ENABLE_CONFIG35_FTDF_REG;       /*!< (@ 0x500022C6) RF_ENABLE_CONFIG35_FTDF_REG                            */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  RF_ENABLE_CONFIG37_FTDF_REG;       /*!< (@ 0x500022CA) RF_ENABLE_CONFIG37_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG38_FTDF_REG;       /*!< (@ 0x500022CC) RF_ENABLE_CONFIG38_FTDF_REG                            */
  __I  uint16_t  RESERVED4[5];
  __IO uint16_t  RF_ENABLE_CONFIG44_FTDF_REG;       /*!< (@ 0x500022D8) RF_ENABLE_CONFIG44_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG45_FTDF_REG;       /*!< (@ 0x500022DA) RF_ENABLE_CONFIG45_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG46_FTDF_REG;       /*!< (@ 0x500022DC) RF_ENABLE_CONFIG46_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG47_FTDF_REG;       /*!< (@ 0x500022DE) RF_ENABLE_CONFIG47_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG48_FTDF_REG;       /*!< (@ 0x500022E0) RF_ENABLE_CONFIG48_FTDF_REG                            */
  __IO uint16_t  RF_ENABLE_CONFIG49_FTDF_REG;       /*!< (@ 0x500022E2) RF_ENABLE_CONFIG49_FTDF_REG                            */
  __I  uint16_t  RESERVED5[15];
  __IO uint16_t  RF_CNTRL_TIMER_1_REG;              /*!< (@ 0x50002302) RF_CNTRL_TIMER_1_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_2_REG;              /*!< (@ 0x50002304) RF_CNTRL_TIMER_2_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_3_REG;              /*!< (@ 0x50002306) RF_CNTRL_TIMER_3_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_4_REG;              /*!< (@ 0x50002308) RF_CNTRL_TIMER_4_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_5_REG;              /*!< (@ 0x5000230A) RF_CNTRL_TIMER_5_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_6_REG;              /*!< (@ 0x5000230C) RF_CNTRL_TIMER_6_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_7_REG;              /*!< (@ 0x5000230E) RF_CNTRL_TIMER_7_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_8_REG;              /*!< (@ 0x50002310) RF_CNTRL_TIMER_8_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_9_REG;              /*!< (@ 0x50002312) RF_CNTRL_TIMER_9_REG                                   */
  __IO uint16_t  RF_CNTRL_TIMER_10_REG;             /*!< (@ 0x50002314) RF_CNTRL_TIMER_10_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_11_REG;             /*!< (@ 0x50002316) RF_CNTRL_TIMER_11_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_12_REG;             /*!< (@ 0x50002318) RF_CNTRL_TIMER_12_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_13_REG;             /*!< (@ 0x5000231A) RF_CNTRL_TIMER_13_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_14_REG;             /*!< (@ 0x5000231C) RF_CNTRL_TIMER_14_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_15_REG;             /*!< (@ 0x5000231E) RF_CNTRL_TIMER_15_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_16_REG;             /*!< (@ 0x50002320) RF_CNTRL_TIMER_16_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_17_REG;             /*!< (@ 0x50002322) RF_CNTRL_TIMER_17_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_18_REG;             /*!< (@ 0x50002324) RF_CNTRL_TIMER_18_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_19_REG;             /*!< (@ 0x50002326) RF_CNTRL_TIMER_19_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_20_REG;             /*!< (@ 0x50002328) RF_CNTRL_TIMER_20_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_21_REG;             /*!< (@ 0x5000232A) RF_CNTRL_TIMER_21_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_22_REG;             /*!< (@ 0x5000232C) RF_CNTRL_TIMER_22_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_23_REG;             /*!< (@ 0x5000232E) RF_CNTRL_TIMER_23_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_24_REG;             /*!< (@ 0x50002330) RF_CNTRL_TIMER_24_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_25_REG;             /*!< (@ 0x50002332) RF_CNTRL_TIMER_25_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_26_REG;             /*!< (@ 0x50002334) RF_CNTRL_TIMER_26_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_27_REG;             /*!< (@ 0x50002336) RF_CNTRL_TIMER_27_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_28_REG;             /*!< (@ 0x50002338) RF_CNTRL_TIMER_28_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_29_REG;             /*!< (@ 0x5000233A) RF_CNTRL_TIMER_29_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_30_REG;             /*!< (@ 0x5000233C) RF_CNTRL_TIMER_30_REG                                  */
  __IO uint16_t  RF_CNTRL_TIMER_31_REG;             /*!< (@ 0x5000233E) RF_CNTRL_TIMER_31_REG                                  */
  __I  uint32_t  RESERVED6[16];
  __IO uint16_t  RF_ALWAYS_EN1_REG;                 /*!< (@ 0x50002380) RF_ALWAYS_EN1_REG                                      */
  __IO uint16_t  RF_ALWAYS_EN2_REG;                 /*!< (@ 0x50002382) RF_ALWAYS_EN2_REG                                      */
  __IO uint16_t  RF_ALWAYS_EN3_REG;                 /*!< (@ 0x50002384) RF_ALWAYS_EN3_REG                                      */
  __IO uint16_t  RF_ALWAYS_EN4_REG;                 /*!< (@ 0x50002386) RF_ALWAYS_EN4_REG                                      */
  __IO uint16_t  RF_PORT_EN_BLE_REG;                /*!< (@ 0x50002388) RF_PORT_EN_BLE_REG                                     */
  __IO uint16_t  RF_PORT_EN_FTDF_REG;               /*!< (@ 0x5000238A) RF_PORT_EN_FTDF_REG                                    */
  __IO uint16_t  RF_PORT_POL_REG;                   /*!< (@ 0x5000238C) RF_PORT_POL_REG                                        */
} RFCU_POWER_Type;


/* ================================================================================ */
/* ================                      RFPT                      ================ */
/* ================================================================================ */


/**
  * @brief RFPT registers (RFPT)
  */

typedef struct {                                    /*!< (@ 0x50003600) RFPT Structure                                         */
  __IO uint16_t  RFPT_CTRL_REG;                     /*!< (@ 0x50003600) Control register                                       */
  __IO uint16_t  RFPT_ADDRL_REG;                    /*!< (@ 0x50003602) AHB master start address (Low part)                    */
  __IO uint16_t  RFPT_ADDRH_REG;                    /*!< (@ 0x50003604) AHB master start address (High part)                   */
  __IO uint16_t  RFPT_LEN_REG;                      /*!< (@ 0x50003606) Data length register                                   */
  __IO uint16_t  RFPT_STAT_REG;                     /*!< (@ 0x50003608) Status register                                        */
  __IO uint16_t  RFPT_CRV_ADDRL_REG;                /*!< (@ 0x5000360A) AHB master current address (Low part)                  */
  __IO uint16_t  RFPT_CRV_ADDRH_REG;                /*!< (@ 0x5000360C) AHB master current address (High part)                 */
  __IO uint16_t  RFPT_CRV_LEN_REG;                  /*!< (@ 0x5000360E) The remaining data to be transferred                   */
} RFPT_Type;


/* ================================================================================ */
/* ================                       SPI                      ================ */
/* ================================================================================ */


/**
  * @brief SPI registers (SPI)
  */

typedef struct {                                    /*!< (@ 0x50001200) SPI Structure                                          */
  __IO uint16_t  SPI_CTRL_REG;                      /*!< (@ 0x50001200) SPI control register 0                                 */
  __IO uint16_t  SPI_RX_TX_REG0;                    /*!< (@ 0x50001202) SPI RX/TX register0                                    */
  __IO uint16_t  SPI_RX_TX_REG1;                    /*!< (@ 0x50001204) SPI RX/TX register1                                    */
  __IO uint16_t  SPI_CLEAR_INT_REG;                 /*!< (@ 0x50001206) SPI clear interrupt register                           */
  __IO uint16_t  SPI_CTRL_REG1;                     /*!< (@ 0x50001208) SPI control register 1                                 */
} SPI_Type;


/* ================================================================================ */
/* ================                      SPI2                      ================ */
/* ================================================================================ */


/**
  * @brief SPI2 registers (SPI2)
  */

typedef struct {                                    /*!< (@ 0x50001300) SPI2 Structure                                         */
  __IO uint16_t  SPI2_CTRL_REG;                     /*!< (@ 0x50001300) SPI control register 0                                 */
  __IO uint16_t  SPI2_RX_TX_REG0;                   /*!< (@ 0x50001302) SPI RX/TX register0                                    */
  __IO uint16_t  SPI2_RX_TX_REG1;                   /*!< (@ 0x50001304) SPI RX/TX register1                                    */
  __IO uint16_t  SPI2_CLEAR_INT_REG;                /*!< (@ 0x50001306) SPI clear interrupt register                           */
  __IO uint16_t  SPI2_CTRL_REG1;                    /*!< (@ 0x50001308) SPI control register 1                                 */
} SPI2_Type;


/* ================================================================================ */
/* ================                     TIMER1                     ================ */
/* ================================================================================ */


/**
  * @brief TIMER1 registers (TIMER1)
  */

typedef struct {                                    /*!< (@ 0x50000200) TIMER1 Structure                                       */
  __IO uint16_t  CAPTIM_CTRL_REG;                   /*!< (@ 0x50000200) Capture Timer control register                         */
  __IO uint16_t  CAPTIM_TIMER_VAL_REG;              /*!< (@ 0x50000202) Capture Timer counter value                            */
  __IO uint16_t  CAPTIM_STATUS_REG;                 /*!< (@ 0x50000204) Capture Timer status register                          */
  __IO uint16_t  CAPTIM_GPIO1_CONF_REG;             /*!< (@ 0x50000206) Capture Timer gpio1 selection                          */
  __IO uint16_t  CAPTIM_GPIO2_CONF_REG;             /*!< (@ 0x50000208) Capture Timer gpio2 selection                          */
  __IO uint16_t  CAPTIM_RELOAD_REG;                 /*!< (@ 0x5000020A) Capture Timer reload value and Delay in shot
                                                         mode                                                                  */
  __IO uint16_t  CAPTIM_SHOTWIDTH_REG;              /*!< (@ 0x5000020C) Capture Timer Shot duration in shot mode               */
  __IO uint16_t  CAPTIM_PRESCALER_REG;              /*!< (@ 0x5000020E) Capture Timer prescaler value                          */
  __IO uint16_t  CAPTIM_CAPTURE_GPIO1_REG;          /*!< (@ 0x50000210) Capture Timer value for event on GPIO1                 */
  __IO uint16_t  CAPTIM_CAPTURE_GPIO2_REG;          /*!< (@ 0x50000212) Capture Timer value for event on GPIO2                 */
  __IO uint16_t  CAPTIM_PRESCALER_VAL_REG;          /*!< (@ 0x50000214) Capture Timer interrupt status register                */
  __IO uint16_t  CAPTIM_PWM_FREQ_REG;               /*!< (@ 0x50000216) Capture Timer pwm frequency register                   */
  __IO uint16_t  CAPTIM_PWM_DC_REG;                 /*!< (@ 0x50000218) Capture Timer pwm dc register                          */
  __IO uint16_t  CAPTIM_TIMER_HVAL_REG;             /*!< (@ 0x5000021A) Capture Timer counter high value                       */
  __IO uint16_t  CAPTIM_RELOAD_HIGH_REG;            /*!< (@ 0x5000021C) Capture Timer reload high value and Delay in
                                                         shot mode                                                             */
  __IO uint16_t  CAPTIM_CAPTURE_HIGH_GPIO1_REG;     /*!< (@ 0x5000021E) Capture Timer high value for event on GPIO01           */
  __IO uint16_t  CAPTIM_CAPTURE_HIGH_GPIO2_REG;     /*!< (@ 0x50000220) Capture Timer high value for event on GPIO02           */
  __IO uint16_t  CAPTIM_SHOTWIDTH_HIGH_REG;         /*!< (@ 0x50000222) Capture Timer Shot high duration in shot mode          */
} TIMER1_Type;


/* ================================================================================ */
/* ================                      TRNG                      ================ */
/* ================================================================================ */


/**
  * @brief TRNG registers (TRNG)
  */

typedef struct {                                    /*!< (@ 0x50005000) TRNG Structure                                         */
  __IO uint32_t  TRNG_CTRL_REG;                     /*!< (@ 0x50005000) TRNG control register                                  */
  __IO uint32_t  TRNG_FIFOLVL_REG;                  /*!< (@ 0x50005004) TRNG FIFO level register                               */
  __IO uint32_t  TRNG_VER_REG;                      /*!< (@ 0x50005008) TRNG Version register                                  */
} TRNG_Type;


/* ================================================================================ */
/* ================                      UART                      ================ */
/* ================================================================================ */


/**
  * @brief UART registers (UART)
  */

typedef struct {                                    /*!< (@ 0x50001000) UART Structure                                         */
  __IO uint16_t  UART_RBR_THR_DLL_REG;              /*!< (@ 0x50001000) Receive Buffer Register                                */
  __I  uint16_t  RESERVED;
  __IO uint16_t  UART_IER_DLH_REG;                  /*!< (@ 0x50001004) Interrupt Enable Register                              */
  __I  uint16_t  RESERVED1;
  __IO uint16_t  UART_IIR_FCR_REG;                  /*!< (@ 0x50001008) Interrupt Identification Register                      */
  __I  uint16_t  RESERVED2;
  __IO uint16_t  UART_LCR_REG;                      /*!< (@ 0x5000100C) Line Control Register                                  */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  UART_MCR_REG;                      /*!< (@ 0x50001010) Modem Control Register                                 */
  __I  uint16_t  RESERVED4;
  __IO uint16_t  UART_LSR_REG;                      /*!< (@ 0x50001014) Line Status Register                                   */
  __I  uint16_t  RESERVED5[3];
  __IO uint16_t  UART_SCR_REG;                      /*!< (@ 0x5000101C) Scratchpad Register                                    */
  __I  uint16_t  RESERVED6[47];
  __IO uint16_t  UART_USR_REG;                      /*!< (@ 0x5000107C) UART Status register.                                  */
  __I  uint16_t  RESERVED7[5];
  __IO uint16_t  UART_SRR_REG;                      /*!< (@ 0x50001088) Software Reset Register.                               */
  __I  uint16_t  RESERVED8[3];
  __IO uint16_t  UART_SBCR_REG;                     /*!< (@ 0x50001090) Shadow Break Control Register                          */
  __I  uint16_t  RESERVED9[11];
  __IO uint16_t  UART_DMASA_REG;                    /*!< (@ 0x500010A8) DMA Software Acknowledge                               */
  __I  uint16_t  RESERVED10[11];
  __IO uint16_t  UART_DLF_REG;                      /*!< (@ 0x500010C0) Divisor Latch Fraction Register                        */
  __I  uint16_t  RESERVED11[25];
  __IO uint16_t  UART_CPR_REG;                      /*!< (@ 0x500010F4) Component Parameter Register                           */
  __I  uint16_t  RESERVED12;
  __IO uint16_t  UART_UCV_REG;                      /*!< (@ 0x500010F8) Component Version                                      */
  __I  uint16_t  RESERVED13;
  __IO uint16_t  UART_CTR_REG;                      /*!< (@ 0x500010FC) Component Type Register                                */
} UART_Type;


/* ================================================================================ */
/* ================                      UART2                     ================ */
/* ================================================================================ */


/**
  * @brief UART2 registers (UART2)
  */

typedef struct {                                    /*!< (@ 0x50001100) UART2 Structure                                        */
  __IO uint16_t  UART2_RBR_THR_DLL_REG;             /*!< (@ 0x50001100) Receive Buffer Register                                */
  __I  uint16_t  RESERVED;
  __IO uint16_t  UART2_IER_DLH_REG;                 /*!< (@ 0x50001104) Interrupt Enable Register                              */
  __I  uint16_t  RESERVED1;
  __IO uint16_t  UART2_IIR_FCR_REG;                 /*!< (@ 0x50001108) Interrupt Identification Register/FIFO Control
                                                         Register                                                              */
  __I  uint16_t  RESERVED2;
  __IO uint16_t  UART2_LCR_REG;                     /*!< (@ 0x5000110C) Line Control Register                                  */
  __I  uint16_t  RESERVED3;
  __IO uint16_t  UART2_MCR_REG;                     /*!< (@ 0x50001110) Modem Control Register                                 */
  __I  uint16_t  RESERVED4;
  __IO uint16_t  UART2_LSR_REG;                     /*!< (@ 0x50001114) Line Status Register                                   */
  __I  uint16_t  RESERVED5;
  __IO uint16_t  UART2_MSR_REG;                     /*!< (@ 0x50001118) Modem Status Register                                  */
  __I  uint16_t  RESERVED6;
  __IO uint16_t  UART2_SCR_REG;                     /*!< (@ 0x5000111C) Scratchpad Register                                    */
  __I  uint16_t  RESERVED7[9];
  __IO uint16_t  UART2_SRBR_STHR0_REG;              /*!< (@ 0x50001130) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED8;
  __IO uint16_t  UART2_SRBR_STHR1_REG;              /*!< (@ 0x50001134) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED9;
  __IO uint16_t  UART2_SRBR_STHR2_REG;              /*!< (@ 0x50001138) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED10;
  __IO uint16_t  UART2_SRBR_STHR3_REG;              /*!< (@ 0x5000113C) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED11;
  __IO uint16_t  UART2_SRBR_STHR4_REG;              /*!< (@ 0x50001140) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED12;
  __IO uint16_t  UART2_SRBR_STHR5_REG;              /*!< (@ 0x50001144) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED13;
  __IO uint16_t  UART2_SRBR_STHR6_REG;              /*!< (@ 0x50001148) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED14;
  __IO uint16_t  UART2_SRBR_STHR7_REG;              /*!< (@ 0x5000114C) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED15;
  __IO uint16_t  UART2_SRBR_STHR8_REG;              /*!< (@ 0x50001150) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED16;
  __IO uint16_t  UART2_SRBR_STHR9_REG;              /*!< (@ 0x50001154) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED17;
  __IO uint16_t  UART2_SRBR_STHR10_REG;             /*!< (@ 0x50001158) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED18;
  __IO uint16_t  UART2_SRBR_STHR11_REG;             /*!< (@ 0x5000115C) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED19;
  __IO uint16_t  UART2_SRBR_STHR12_REG;             /*!< (@ 0x50001160) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED20;
  __IO uint16_t  UART2_SRBR_STHR13_REG;             /*!< (@ 0x50001164) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED21;
  __IO uint16_t  UART2_SRBR_STHR14_REG;             /*!< (@ 0x50001168) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED22;
  __IO uint16_t  UART2_SRBR_STHR15_REG;             /*!< (@ 0x5000116C) Shadow Receive/Transmit Buffer Register                */
  __I  uint16_t  RESERVED23;
  __IO uint16_t  UART2_FAR_REG;                     /*!< (@ 0x50001170) FIFO Access Register                                   */
  __I  uint16_t  RESERVED24[5];
  __IO uint16_t  UART2_USR_REG;                     /*!< (@ 0x5000117C) UART Status register.                                  */
  __I  uint16_t  RESERVED25;
  __IO uint16_t  UART2_TFL_REG;                     /*!< (@ 0x50001180) Transmit FIFO Level                                    */
  __I  uint16_t  RESERVED26;
  __IO uint16_t  UART2_RFL_REG;                     /*!< (@ 0x50001184) Receive FIFO Level.                                    */
  __I  uint16_t  RESERVED27;
  __IO uint16_t  UART2_SRR_REG;                     /*!< (@ 0x50001188) Software Reset Register.                               */
  __I  uint16_t  RESERVED28;
  __IO uint16_t  UART2_SRTS_REG;                    /*!< (@ 0x5000118C) Shadow Request to Send                                 */
  __I  uint16_t  RESERVED29;
  __IO uint16_t  UART2_SBCR_REG;                    /*!< (@ 0x50001190) Shadow Break Control Register                          */
  __I  uint16_t  RESERVED30;
  __IO uint16_t  UART2_SDMAM_REG;                   /*!< (@ 0x50001194) Shadow DMA Mode                                        */
  __I  uint16_t  RESERVED31;
  __IO uint16_t  UART2_SFE_REG;                     /*!< (@ 0x50001198) Shadow FIFO Enable                                     */
  __I  uint16_t  RESERVED32;
  __IO uint16_t  UART2_SRT_REG;                     /*!< (@ 0x5000119C) Shadow RCVR Trigger                                    */
  __I  uint16_t  RESERVED33;
  __IO uint16_t  UART2_STET_REG;                    /*!< (@ 0x500011A0) Shadow TX Empty Trigger                                */
  __I  uint16_t  RESERVED34;
  __IO uint16_t  UART2_HTX_REG;                     /*!< (@ 0x500011A4) Halt TX                                                */
  __I  uint16_t  RESERVED35;
  __IO uint16_t  UART2_DMASA_REG;                   /*!< (@ 0x500011A8) DMA Software Acknowledge                               */
  __I  uint16_t  RESERVED36[11];
  __IO uint16_t  UART2_DLF_REG;                     /*!< (@ 0x500011C0) Divisor Latch Fraction Register                        */
  __I  uint16_t  RESERVED37[25];
  __IO uint16_t  UART2_CPR_REG;                     /*!< (@ 0x500011F4) Component Parameter Register                           */
  __I  uint16_t  RESERVED38;
  __IO uint16_t  UART2_UCV_REG;                     /*!< (@ 0x500011F8) Component Version                                      */
  __I  uint16_t  RESERVED39;
  __IO uint16_t  UART2_CTR_REG;                     /*!< (@ 0x500011FC) Component Type Register                                */
} UART2_Type;


/* ================================================================================ */
/* ================                       USB                      ================ */
/* ================================================================================ */


/**
  * @brief USB registers (USB)
  */

typedef struct {                                    /*!< (@ 0x50001800) USB Structure                                          */
  __IO uint16_t  USB_MCTRL_REG;                     /*!< (@ 0x50001800) Main Control Register)                                 */
  __IO uint16_t  USB_XCVDIAG_REG;                   /*!< (@ 0x50001802) Transceiver diagnostic Register (for test purpose
                                                         only)                                                                 */
  __IO uint16_t  USB_TCR_REG;                       /*!< (@ 0x50001804) Transceiver configuration Register                     */
  __IO uint16_t  USB_UTR_REG;                       /*!< (@ 0x50001806) USB test Register (for test purpose only)              */
  __IO uint16_t  USB_FAR_REG;                       /*!< (@ 0x50001808) Function Address Register                              */
  __IO uint16_t  USB_NFSR_REG;                      /*!< (@ 0x5000180A) Node Functional State Register                         */
  __IO uint16_t  USB_MAEV_REG;                      /*!< (@ 0x5000180C) Main Event Register                                    */
  __IO uint16_t  USB_MAMSK_REG;                     /*!< (@ 0x5000180E) Main Mask Register                                     */
  __IO uint16_t  USB_ALTEV_REG;                     /*!< (@ 0x50001810) Alternate Event Register                               */
  __IO uint16_t  USB_ALTMSK_REG;                    /*!< (@ 0x50001812) Alternate Mask Register                                */
  __IO uint16_t  USB_TXEV_REG;                      /*!< (@ 0x50001814) Transmit Event Register                                */
  __IO uint16_t  USB_TXMSK_REG;                     /*!< (@ 0x50001816) Transmit Mask Register                                 */
  __IO uint16_t  USB_RXEV_REG;                      /*!< (@ 0x50001818) Receive Event Register                                 */
  __IO uint16_t  USB_RXMSK_REG;                     /*!< (@ 0x5000181A) Receive Mask Register                                  */
  __IO uint16_t  USB_NAKEV_REG;                     /*!< (@ 0x5000181C) NAK Event Register                                     */
  __IO uint16_t  USB_NAKMSK_REG;                    /*!< (@ 0x5000181E) NAK Mask Register                                      */
  __IO uint16_t  USB_FWEV_REG;                      /*!< (@ 0x50001820) FIFO Warning Event Register                            */
  __IO uint16_t  USB_FWMSK_REG;                     /*!< (@ 0x50001822) FIFO Warning Mask Register                             */
  __IO uint16_t  USB_FNH_REG;                       /*!< (@ 0x50001824) Frame Number High Byte Register                        */
  __IO uint16_t  USB_FNL_REG;                       /*!< (@ 0x50001826) Frame Number Low Byte Register                         */
  __I  uint16_t  RESERVED[11];
  __IO uint16_t  USB_UX20CDR_REG;                   /*!< (@ 0x5000183E) Transceiver 2.0 Configuration and Diagnostics
                                                         Register(for test purpose only)                                       */
  __IO uint16_t  USB_EPC0_REG;                      /*!< (@ 0x50001840) Endpoint Control 0 Register                            */
  __IO uint16_t  USB_TXD0_REG;                      /*!< (@ 0x50001842) Transmit Data 0 Register                               */
  __IO uint16_t  USB_TXS0_REG;                      /*!< (@ 0x50001844) Transmit Status 0 Register                             */
  __IO uint16_t  USB_TXC0_REG;                      /*!< (@ 0x50001846) Transmit command 0 Register                            */
  __IO uint16_t  USB_EP0_NAK_REG;                   /*!< (@ 0x50001848) EP0 INNAK and OUTNAK Register                          */
  __IO uint16_t  USB_RXD0_REG;                      /*!< (@ 0x5000184A) Receive Data 0 Register                                */
  __IO uint16_t  USB_RXS0_REG;                      /*!< (@ 0x5000184C) Receive Status 0 Register                              */
  __IO uint16_t  USB_RXC0_REG;                      /*!< (@ 0x5000184E) Receive Command 0 Register                             */
  __IO uint16_t  USB_EPC1_REG;                      /*!< (@ 0x50001850) Endpoint Control Register 1                            */
  __IO uint16_t  USB_TXD1_REG;                      /*!< (@ 0x50001852) Transmit Data Register 1                               */
  __IO uint16_t  USB_TXS1_REG;                      /*!< (@ 0x50001854) Transmit Status Register 1                             */
  __IO uint16_t  USB_TXC1_REG;                      /*!< (@ 0x50001856) Transmit Command Register 1                            */
  __IO uint16_t  USB_EPC2_REG;                      /*!< (@ 0x50001858) Endpoint Control Register 2                            */
  __IO uint16_t  USB_RXD1_REG;                      /*!< (@ 0x5000185A) Receive Data Register,1                                */
  __IO uint16_t  USB_RXS1_REG;                      /*!< (@ 0x5000185C) Receive Status Register 1                              */
  __IO uint16_t  USB_RXC1_REG;                      /*!< (@ 0x5000185E) Receive Command Register 1                             */
  __IO uint16_t  USB_EPC3_REG;                      /*!< (@ 0x50001860) Endpoint Control Register 3                            */
  __IO uint16_t  USB_TXD2_REG;                      /*!< (@ 0x50001862) Transmit Data Register 2                               */
  __IO uint16_t  USB_TXS2_REG;                      /*!< (@ 0x50001864) Transmit Status Register 2                             */
  __IO uint16_t  USB_TXC2_REG;                      /*!< (@ 0x50001866) Transmit Command Register 2                            */
  __IO uint16_t  USB_EPC4_REG;                      /*!< (@ 0x50001868) Endpoint Control Register 4                            */
  __IO uint16_t  USB_RXD2_REG;                      /*!< (@ 0x5000186A) Receive Data Register 2                                */
  __IO uint16_t  USB_RXS2_REG;                      /*!< (@ 0x5000186C) Receive Status Register 2                              */
  __IO uint16_t  USB_RXC2_REG;                      /*!< (@ 0x5000186E) Receive Command Register 2                             */
  __IO uint16_t  USB_EPC5_REG;                      /*!< (@ 0x50001870) Endpoint Control Register 5                            */
  __IO uint16_t  USB_TXD3_REG;                      /*!< (@ 0x50001872) Transmit Data Register 3                               */
  __IO uint16_t  USB_TXS3_REG;                      /*!< (@ 0x50001874) Transmit Status Register 3                             */
  __IO uint16_t  USB_TXC3_REG;                      /*!< (@ 0x50001876) Transmit Command Register 3                            */
  __IO uint16_t  USB_EPC6_REG;                      /*!< (@ 0x50001878) Endpoint Control Register 6                            */
  __IO uint16_t  USB_RXD3_REG;                      /*!< (@ 0x5000187A) Receive Data Register 3                                */
  __IO uint16_t  USB_RXS3_REG;                      /*!< (@ 0x5000187C) Receive Status Register 3                              */
  __IO uint16_t  USB_RXC3_REG;                      /*!< (@ 0x5000187E) Receive Command Register 3                             */
  __I  uint32_t  RESERVED1[20];
  __IO uint16_t  USB_DMA_CTRL_REG;                  /*!< (@ 0x500018D0) USB DMA control register                               */
  __I  uint16_t  RESERVED2;
  __IO uint16_t  USB_CHARGER_CTRL_REG;              /*!< (@ 0x500018D4) USB Charger Control Register                           */
  __IO uint16_t  USB_CHARGER_STAT_REG;              /*!< (@ 0x500018D6) USB Charger Status Register                            */
} USB_Type;


/* ================================================================================ */
/* ================                     WAKEUP                     ================ */
/* ================================================================================ */


/**
  * @brief WAKEUP registers (WAKEUP)
  */

typedef struct {                                    /*!< (@ 0x50000100) WAKEUP Structure                                       */
  __IO uint16_t  WKUP_CTRL_REG;                     /*!< (@ 0x50000100) Control register for the wakeup counter                */
  __I  uint16_t  RESERVED;
  __IO uint16_t  WKUP_RESET_IRQ_REG;                /*!< (@ 0x50000104) Reset wakeup interrupt                                 */
  __I  uint16_t  RESERVED1[2];
  __IO uint16_t  WKUP_SELECT_P0_REG;                /*!< (@ 0x5000010A) select which inputs from P0 port can trigger
                                                         wkup counter                                                          */
  __IO uint16_t  WKUP_SELECT_P1_REG;                /*!< (@ 0x5000010C) select which inputs from P1 port can trigger
                                                         wkup counter                                                          */
  __IO uint16_t  WKUP_SELECT_P2_REG;                /*!< (@ 0x5000010E) select which inputs from P2 port can trigger
                                                         wkup counter                                                          */
  __IO uint16_t  WKUP_SELECT_P3_REG;                /*!< (@ 0x50000110) select which inputs from P3 port can trigger
                                                         wkup counter                                                          */
  __IO uint16_t  WKUP_SELECT_P4_REG;                /*!< (@ 0x50000112) select which inputs from P3 port can trigger
                                                         wkup counter                                                          */
  __IO uint16_t  WKUP_POL_P0_REG;                   /*!< (@ 0x50000114) select the sesitivity polarity for each P0 input       */
  __IO uint16_t  WKUP_POL_P1_REG;                   /*!< (@ 0x50000116) select the sesitivity polarity for each P1 input       */
  __IO uint16_t  WKUP_POL_P2_REG;                   /*!< (@ 0x50000118) select the sesitivity polarity for each P2 input       */
  __IO uint16_t  WKUP_POL_P3_REG;                   /*!< (@ 0x5000011A) select the sesitivity polarity for each P3 input       */
  __IO uint16_t  WKUP_POL_P4_REG;                   /*!< (@ 0x5000011C) select the sesitivity polarity for each P3 input       */
  __IO uint16_t  WKUP_STATUS_0_REG;                 /*!< (@ 0x5000011E) Event status register for P0 and P1                    */
  __IO uint16_t  WKUP_STATUS_1_REG;                 /*!< (@ 0x50000120) Event status register for P2                           */
  __IO uint16_t  WKUP_STATUS_2_REG;                 /*!< (@ 0x50000122) Event status register for P3 and P4                    */
  __IO uint16_t  WKUP_CLEAR_0_REG;                  /*!< (@ 0x50000124) Clear event register for P0 and P1                     */
  __IO uint16_t  WKUP_CLEAR_1_REG;                  /*!< (@ 0x50000126) Clear event register for P2                            */
  __IO uint16_t  WKUP_CLEAR_2_REG;                  /*!< (@ 0x50000128) Clear event register for P3 and P4                     */
  __IO uint16_t  WKUP_SEL_GPIO_P0_REG;              /*!< (@ 0x5000012A) select which inputs from P0 port can trigger
                                                         interrupt                                                             */
  __IO uint16_t  WKUP_SEL_GPIO_P1_REG;              /*!< (@ 0x5000012C) select which inputs from P1 port can trigger
                                                         interrupt                                                             */
  __IO uint16_t  WKUP_SEL_GPIO_P2_REG;              /*!< (@ 0x5000012E) select which inputs from P2 port can trigger
                                                         interrupt                                                             */
  __IO uint16_t  WKUP_SEL_GPIO_P3_REG;              /*!< (@ 0x50000130) select which inputs from P3 port can trigger
                                                         interrupt                                                             */
  __IO uint16_t  WKUP_SEL_GPIO_P4_REG;              /*!< (@ 0x50000132) select which inputs from P3 port can trigger
                                                         interrupt                                                             */
} WAKEUP_Type;


/* ================================================================================ */
/* ================                      WDOG                      ================ */
/* ================================================================================ */


/**
  * @brief WDOG registers (WDOG)
  */

typedef struct {                                    /*!< (@ 0x50003100) WDOG Structure                                         */
  __IO uint16_t  WATCHDOG_REG;                      /*!< (@ 0x50003100) Watchdog timer register.                               */
  __IO uint16_t  WATCHDOG_CTRL_REG;                 /*!< (@ 0x50003102) Watchdog control register.                             */
} WDOG_Type;


/* --------------------  End of section using anonymous unions  ------------------- */
#if defined(__CC_ARM)
  #pragma pop
#elif defined(__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning restore
#else
  #warning Not supported compiler type
#endif


/* ================================================================================ */
/* ================          struct 'NVIC' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------------  NVIC_ISER  --------------------------------- */
#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Pos      (0UL)                     /*!< NVIC ISER: BLE_WAKEUP_LP_IRQn (Bit 0)                       */
#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Msk      (0x1UL)                   /*!< NVIC ISER: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)         */
#define NVIC_ISER_BLE_GEN_IRQn_Pos            (1UL)                     /*!< NVIC ISER: BLE_GEN_IRQn (Bit 1)                             */
#define NVIC_ISER_BLE_GEN_IRQn_Msk            (0x2UL)                   /*!< NVIC ISER: BLE_GEN_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ISER_FTDF_WAKEUP_IRQn_Pos        (2UL)                     /*!< NVIC ISER: FTDF_WAKEUP_IRQn (Bit 2)                         */
#define NVIC_ISER_FTDF_WAKEUP_IRQn_Msk        (0x4UL)                   /*!< NVIC ISER: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)           */
#define NVIC_ISER_FTDF_GEN_IRQn_Pos           (3UL)                     /*!< NVIC ISER: FTDF_GEN_IRQn (Bit 3)                            */
#define NVIC_ISER_FTDF_GEN_IRQn_Msk           (0x8UL)                   /*!< NVIC ISER: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)              */
#define NVIC_ISER_RFCAL_IRQn_Pos              (4UL)                     /*!< NVIC ISER: RFCAL_IRQn (Bit 4)                               */
#define NVIC_ISER_RFCAL_IRQn_Msk              (0x10UL)                  /*!< NVIC ISER: RFCAL_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ISER_COEX_IRQn_Pos               (5UL)                     /*!< NVIC ISER: COEX_IRQn (Bit 5)                                */
#define NVIC_ISER_COEX_IRQn_Msk               (0x20UL)                  /*!< NVIC ISER: COEX_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_CRYPTO_IRQn_Pos             (6UL)                     /*!< NVIC ISER: CRYPTO_IRQn (Bit 6)                              */
#define NVIC_ISER_CRYPTO_IRQn_Msk             (0x40UL)                  /*!< NVIC ISER: CRYPTO_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISER_MRM_IRQn_Pos                (7UL)                     /*!< NVIC ISER: MRM_IRQn (Bit 7)                                 */
#define NVIC_ISER_MRM_IRQn_Msk                (0x80UL)                  /*!< NVIC ISER: MRM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_UART_IRQn_Pos               (8UL)                     /*!< NVIC ISER: UART_IRQn (Bit 8)                                */
#define NVIC_ISER_UART_IRQn_Msk               (0x100UL)                 /*!< NVIC ISER: UART_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_UART2_IRQn_Pos              (9UL)                     /*!< NVIC ISER: UART2_IRQn (Bit 9)                               */
#define NVIC_ISER_UART2_IRQn_Msk              (0x200UL)                 /*!< NVIC ISER: UART2_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ISER_I2C_IRQn_Pos                (10UL)                    /*!< NVIC ISER: I2C_IRQn (Bit 10)                                */
#define NVIC_ISER_I2C_IRQn_Msk                (0x400UL)                 /*!< NVIC ISER: I2C_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_I2C2_IRQn_Pos               (11UL)                    /*!< NVIC ISER: I2C2_IRQn (Bit 11)                               */
#define NVIC_ISER_I2C2_IRQn_Msk               (0x800UL)                 /*!< NVIC ISER: I2C2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_SPI_IRQn_Pos                (12UL)                    /*!< NVIC ISER: SPI_IRQn (Bit 12)                                */
#define NVIC_ISER_SPI_IRQn_Msk                (0x1000UL)                /*!< NVIC ISER: SPI_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_SPI2_IRQn_Pos               (13UL)                    /*!< NVIC ISER: SPI2_IRQn (Bit 13)                               */
#define NVIC_ISER_SPI2_IRQn_Msk               (0x2000UL)                /*!< NVIC ISER: SPI2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_ADC_IRQn_Pos                (14UL)                    /*!< NVIC ISER: ADC_IRQn (Bit 14)                                */
#define NVIC_ISER_ADC_IRQn_Msk                (0x4000UL)                /*!< NVIC ISER: ADC_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_KEYBRD_IRQn_Pos             (15UL)                    /*!< NVIC ISER: KEYBRD_IRQn (Bit 15)                             */
#define NVIC_ISER_KEYBRD_IRQn_Msk             (0x8000UL)                /*!< NVIC ISER: KEYBRD_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISER_IRGEN_IRQn_Pos              (16UL)                    /*!< NVIC ISER: IRGEN_IRQn (Bit 16)                              */
#define NVIC_ISER_IRGEN_IRQn_Msk              (0x10000UL)               /*!< NVIC ISER: IRGEN_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ISER_WKUP_GPIO_IRQn_Pos          (17UL)                    /*!< NVIC ISER: WKUP_GPIO_IRQn (Bit 17)                          */
#define NVIC_ISER_WKUP_GPIO_IRQn_Msk          (0x20000UL)               /*!< NVIC ISER: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ISER_SWTIM0_IRQn_Pos             (18UL)                    /*!< NVIC ISER: SWTIM0_IRQn (Bit 18)                             */
#define NVIC_ISER_SWTIM0_IRQn_Msk             (0x40000UL)               /*!< NVIC ISER: SWTIM0_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISER_SWTIM1_IRQn_Pos             (19UL)                    /*!< NVIC ISER: SWTIM1_IRQn (Bit 19)                             */
#define NVIC_ISER_SWTIM1_IRQn_Msk             (0x80000UL)               /*!< NVIC ISER: SWTIM1_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISER_QUADEC_IRQn_Pos             (20UL)                    /*!< NVIC ISER: QUADEC_IRQn (Bit 20)                             */
#define NVIC_ISER_QUADEC_IRQn_Msk             (0x100000UL)              /*!< NVIC ISER: QUADEC_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISER_USB_IRQn_Pos                (21UL)                    /*!< NVIC ISER: USB_IRQn (Bit 21)                                */
#define NVIC_ISER_USB_IRQn_Msk                (0x200000UL)              /*!< NVIC ISER: USB_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_PCM_IRQn_Pos                (22UL)                    /*!< NVIC ISER: PCM_IRQn (Bit 22)                                */
#define NVIC_ISER_PCM_IRQn_Msk                (0x400000UL)              /*!< NVIC ISER: PCM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_SRC_IN_IRQn_Pos             (23UL)                    /*!< NVIC ISER: SRC_IN_IRQn (Bit 23)                             */
#define NVIC_ISER_SRC_IN_IRQn_Msk             (0x800000UL)              /*!< NVIC ISER: SRC_IN_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISER_SRC_OUT_IRQn_Pos            (24UL)                    /*!< NVIC ISER: SRC_OUT_IRQn (Bit 24)                            */
#define NVIC_ISER_SRC_OUT_IRQn_Msk            (0x1000000UL)             /*!< NVIC ISER: SRC_OUT_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ISER_VBUS_IRQn_Pos               (25UL)                    /*!< NVIC ISER: VBUS_IRQn (Bit 25)                               */
#define NVIC_ISER_VBUS_IRQn_Msk               (0x2000000UL)             /*!< NVIC ISER: VBUS_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_DMA_IRQn_Pos                (26UL)                    /*!< NVIC ISER: DMA_IRQn (Bit 26)                                */
#define NVIC_ISER_DMA_IRQn_Msk                (0x4000000UL)             /*!< NVIC ISER: DMA_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISER_RF_DIAG_IRQn_Pos            (27UL)                    /*!< NVIC ISER: RF_DIAG_IRQn (Bit 27)                            */
#define NVIC_ISER_RF_DIAG_IRQn_Msk            (0x8000000UL)             /*!< NVIC ISER: RF_DIAG_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ISER_TRNG_IRQn_Pos               (28UL)                    /*!< NVIC ISER: TRNG_IRQn (Bit 28)                               */
#define NVIC_ISER_TRNG_IRQn_Msk               (0x10000000UL)            /*!< NVIC ISER: TRNG_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_DCDC_IRQn_Pos               (29UL)                    /*!< NVIC ISER: DCDC_IRQn (Bit 29)                               */
#define NVIC_ISER_DCDC_IRQn_Msk               (0x20000000UL)            /*!< NVIC ISER: DCDC_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISER_XTAL16RDY_IRQn_Pos          (30UL)                    /*!< NVIC ISER: XTAL16RDY_IRQn (Bit 30)                          */
#define NVIC_ISER_XTAL16RDY_IRQn_Msk          (0x40000000UL)            /*!< NVIC ISER: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ISER_Rsvd__irq__n_Pos            (31UL)                    /*!< NVIC ISER: Rsvd__irq__n (Bit 31)                            */
#define NVIC_ISER_Rsvd__irq__n_Msk            (0x80000000UL)            /*!< NVIC ISER: Rsvd__irq__n (Bitfield-Mask: 0x01)               */

/* ----------------------------------  NVIC_ICER  --------------------------------- */
#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Pos      (0UL)                     /*!< NVIC ICER: BLE_WAKEUP_LP_IRQn (Bit 0)                       */
#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Msk      (0x1UL)                   /*!< NVIC ICER: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)         */
#define NVIC_ICER_BLE_GEN_IRQn_Pos            (1UL)                     /*!< NVIC ICER: BLE_GEN_IRQn (Bit 1)                             */
#define NVIC_ICER_BLE_GEN_IRQn_Msk            (0x2UL)                   /*!< NVIC ICER: BLE_GEN_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ICER_FTDF_WAKEUP_IRQn_Pos        (2UL)                     /*!< NVIC ICER: FTDF_WAKEUP_IRQn (Bit 2)                         */
#define NVIC_ICER_FTDF_WAKEUP_IRQn_Msk        (0x4UL)                   /*!< NVIC ICER: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)           */
#define NVIC_ICER_FTDF_GEN_IRQn_Pos           (3UL)                     /*!< NVIC ICER: FTDF_GEN_IRQn (Bit 3)                            */
#define NVIC_ICER_FTDF_GEN_IRQn_Msk           (0x8UL)                   /*!< NVIC ICER: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)              */
#define NVIC_ICER_RFCAL_IRQn_Pos              (4UL)                     /*!< NVIC ICER: RFCAL_IRQn (Bit 4)                               */
#define NVIC_ICER_RFCAL_IRQn_Msk              (0x10UL)                  /*!< NVIC ICER: RFCAL_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ICER_COEX_IRQn_Pos               (5UL)                     /*!< NVIC ICER: COEX_IRQn (Bit 5)                                */
#define NVIC_ICER_COEX_IRQn_Msk               (0x20UL)                  /*!< NVIC ICER: COEX_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_CRYPTO_IRQn_Pos             (6UL)                     /*!< NVIC ICER: CRYPTO_IRQn (Bit 6)                              */
#define NVIC_ICER_CRYPTO_IRQn_Msk             (0x40UL)                  /*!< NVIC ICER: CRYPTO_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICER_MRM_IRQn_Pos                (7UL)                     /*!< NVIC ICER: MRM_IRQn (Bit 7)                                 */
#define NVIC_ICER_MRM_IRQn_Msk                (0x80UL)                  /*!< NVIC ICER: MRM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_UART_IRQn_Pos               (8UL)                     /*!< NVIC ICER: UART_IRQn (Bit 8)                                */
#define NVIC_ICER_UART_IRQn_Msk               (0x100UL)                 /*!< NVIC ICER: UART_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_UART2_IRQn_Pos              (9UL)                     /*!< NVIC ICER: UART2_IRQn (Bit 9)                               */
#define NVIC_ICER_UART2_IRQn_Msk              (0x200UL)                 /*!< NVIC ICER: UART2_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ICER_I2C_IRQn_Pos                (10UL)                    /*!< NVIC ICER: I2C_IRQn (Bit 10)                                */
#define NVIC_ICER_I2C_IRQn_Msk                (0x400UL)                 /*!< NVIC ICER: I2C_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_I2C2_IRQn_Pos               (11UL)                    /*!< NVIC ICER: I2C2_IRQn (Bit 11)                               */
#define NVIC_ICER_I2C2_IRQn_Msk               (0x800UL)                 /*!< NVIC ICER: I2C2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_SPI_IRQn_Pos                (12UL)                    /*!< NVIC ICER: SPI_IRQn (Bit 12)                                */
#define NVIC_ICER_SPI_IRQn_Msk                (0x1000UL)                /*!< NVIC ICER: SPI_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_SPI2_IRQn_Pos               (13UL)                    /*!< NVIC ICER: SPI2_IRQn (Bit 13)                               */
#define NVIC_ICER_SPI2_IRQn_Msk               (0x2000UL)                /*!< NVIC ICER: SPI2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_ADC_IRQn_Pos                (14UL)                    /*!< NVIC ICER: ADC_IRQn (Bit 14)                                */
#define NVIC_ICER_ADC_IRQn_Msk                (0x4000UL)                /*!< NVIC ICER: ADC_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_KEYBRD_IRQn_Pos             (15UL)                    /*!< NVIC ICER: KEYBRD_IRQn (Bit 15)                             */
#define NVIC_ICER_KEYBRD_IRQn_Msk             (0x8000UL)                /*!< NVIC ICER: KEYBRD_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICER_IRGEN_IRQn_Pos              (16UL)                    /*!< NVIC ICER: IRGEN_IRQn (Bit 16)                              */
#define NVIC_ICER_IRGEN_IRQn_Msk              (0x10000UL)               /*!< NVIC ICER: IRGEN_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ICER_WKUP_GPIO_IRQn_Pos          (17UL)                    /*!< NVIC ICER: WKUP_GPIO_IRQn (Bit 17)                          */
#define NVIC_ICER_WKUP_GPIO_IRQn_Msk          (0x20000UL)               /*!< NVIC ICER: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ICER_SWTIM0_IRQn_Pos             (18UL)                    /*!< NVIC ICER: SWTIM0_IRQn (Bit 18)                             */
#define NVIC_ICER_SWTIM0_IRQn_Msk             (0x40000UL)               /*!< NVIC ICER: SWTIM0_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICER_SWTIM1_IRQn_Pos             (19UL)                    /*!< NVIC ICER: SWTIM1_IRQn (Bit 19)                             */
#define NVIC_ICER_SWTIM1_IRQn_Msk             (0x80000UL)               /*!< NVIC ICER: SWTIM1_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICER_QUADEC_IRQn_Pos             (20UL)                    /*!< NVIC ICER: QUADEC_IRQn (Bit 20)                             */
#define NVIC_ICER_QUADEC_IRQn_Msk             (0x100000UL)              /*!< NVIC ICER: QUADEC_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICER_USB_IRQn_Pos                (21UL)                    /*!< NVIC ICER: USB_IRQn (Bit 21)                                */
#define NVIC_ICER_USB_IRQn_Msk                (0x200000UL)              /*!< NVIC ICER: USB_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_PCM_IRQn_Pos                (22UL)                    /*!< NVIC ICER: PCM_IRQn (Bit 22)                                */
#define NVIC_ICER_PCM_IRQn_Msk                (0x400000UL)              /*!< NVIC ICER: PCM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_SRC_IN_IRQn_Pos             (23UL)                    /*!< NVIC ICER: SRC_IN_IRQn (Bit 23)                             */
#define NVIC_ICER_SRC_IN_IRQn_Msk             (0x800000UL)              /*!< NVIC ICER: SRC_IN_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICER_SRC_OUT_IRQn_Pos            (24UL)                    /*!< NVIC ICER: SRC_OUT_IRQn (Bit 24)                            */
#define NVIC_ICER_SRC_OUT_IRQn_Msk            (0x1000000UL)             /*!< NVIC ICER: SRC_OUT_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ICER_VBUS_IRQn_Pos               (25UL)                    /*!< NVIC ICER: VBUS_IRQn (Bit 25)                               */
#define NVIC_ICER_VBUS_IRQn_Msk               (0x2000000UL)             /*!< NVIC ICER: VBUS_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_DMA_IRQn_Pos                (26UL)                    /*!< NVIC ICER: DMA_IRQn (Bit 26)                                */
#define NVIC_ICER_DMA_IRQn_Msk                (0x4000000UL)             /*!< NVIC ICER: DMA_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICER_RF_DIAG_IRQn_Pos            (27UL)                    /*!< NVIC ICER: RF_DIAG_IRQn (Bit 27)                            */
#define NVIC_ICER_RF_DIAG_IRQn_Msk            (0x8000000UL)             /*!< NVIC ICER: RF_DIAG_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ICER_TRNG_IRQn_Pos               (28UL)                    /*!< NVIC ICER: TRNG_IRQn (Bit 28)                               */
#define NVIC_ICER_TRNG_IRQn_Msk               (0x10000000UL)            /*!< NVIC ICER: TRNG_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_DCDC_IRQn_Pos               (29UL)                    /*!< NVIC ICER: DCDC_IRQn (Bit 29)                               */
#define NVIC_ICER_DCDC_IRQn_Msk               (0x20000000UL)            /*!< NVIC ICER: DCDC_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICER_XTAL16RDY_IRQn_Pos          (30UL)                    /*!< NVIC ICER: XTAL16RDY_IRQn (Bit 30)                          */
#define NVIC_ICER_XTAL16RDY_IRQn_Msk          (0x40000000UL)            /*!< NVIC ICER: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ICER_Rsvd__irq__n_Pos            (31UL)                    /*!< NVIC ICER: Rsvd__irq__n (Bit 31)                            */
#define NVIC_ICER_Rsvd__irq__n_Msk            (0x80000000UL)            /*!< NVIC ICER: Rsvd__irq__n (Bitfield-Mask: 0x01)               */

/* ----------------------------------  NVIC_ISPR  --------------------------------- */
#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Pos      (0UL)                     /*!< NVIC ISPR: BLE_WAKEUP_LP_IRQn (Bit 0)                       */
#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Msk      (0x1UL)                   /*!< NVIC ISPR: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)         */
#define NVIC_ISPR_BLE_GEN_IRQn_Pos            (1UL)                     /*!< NVIC ISPR: BLE_GEN_IRQn (Bit 1)                             */
#define NVIC_ISPR_BLE_GEN_IRQn_Msk            (0x2UL)                   /*!< NVIC ISPR: BLE_GEN_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Pos        (2UL)                     /*!< NVIC ISPR: FTDF_WAKEUP_IRQn (Bit 2)                         */
#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Msk        (0x4UL)                   /*!< NVIC ISPR: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)           */
#define NVIC_ISPR_FTDF_GEN_IRQn_Pos           (3UL)                     /*!< NVIC ISPR: FTDF_GEN_IRQn (Bit 3)                            */
#define NVIC_ISPR_FTDF_GEN_IRQn_Msk           (0x8UL)                   /*!< NVIC ISPR: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)              */
#define NVIC_ISPR_RFCAL_IRQn_Pos              (4UL)                     /*!< NVIC ISPR: RFCAL_IRQn (Bit 4)                               */
#define NVIC_ISPR_RFCAL_IRQn_Msk              (0x10UL)                  /*!< NVIC ISPR: RFCAL_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ISPR_COEX_IRQn_Pos               (5UL)                     /*!< NVIC ISPR: COEX_IRQn (Bit 5)                                */
#define NVIC_ISPR_COEX_IRQn_Msk               (0x20UL)                  /*!< NVIC ISPR: COEX_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_CRYPTO_IRQn_Pos             (6UL)                     /*!< NVIC ISPR: CRYPTO_IRQn (Bit 6)                              */
#define NVIC_ISPR_CRYPTO_IRQn_Msk             (0x40UL)                  /*!< NVIC ISPR: CRYPTO_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISPR_MRM_IRQn_Pos                (7UL)                     /*!< NVIC ISPR: MRM_IRQn (Bit 7)                                 */
#define NVIC_ISPR_MRM_IRQn_Msk                (0x80UL)                  /*!< NVIC ISPR: MRM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_UART_IRQn_Pos               (8UL)                     /*!< NVIC ISPR: UART_IRQn (Bit 8)                                */
#define NVIC_ISPR_UART_IRQn_Msk               (0x100UL)                 /*!< NVIC ISPR: UART_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_UART2_IRQn_Pos              (9UL)                     /*!< NVIC ISPR: UART2_IRQn (Bit 9)                               */
#define NVIC_ISPR_UART2_IRQn_Msk              (0x200UL)                 /*!< NVIC ISPR: UART2_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ISPR_I2C_IRQn_Pos                (10UL)                    /*!< NVIC ISPR: I2C_IRQn (Bit 10)                                */
#define NVIC_ISPR_I2C_IRQn_Msk                (0x400UL)                 /*!< NVIC ISPR: I2C_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_I2C2_IRQn_Pos               (11UL)                    /*!< NVIC ISPR: I2C2_IRQn (Bit 11)                               */
#define NVIC_ISPR_I2C2_IRQn_Msk               (0x800UL)                 /*!< NVIC ISPR: I2C2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_SPI_IRQn_Pos                (12UL)                    /*!< NVIC ISPR: SPI_IRQn (Bit 12)                                */
#define NVIC_ISPR_SPI_IRQn_Msk                (0x1000UL)                /*!< NVIC ISPR: SPI_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_SPI2_IRQn_Pos               (13UL)                    /*!< NVIC ISPR: SPI2_IRQn (Bit 13)                               */
#define NVIC_ISPR_SPI2_IRQn_Msk               (0x2000UL)                /*!< NVIC ISPR: SPI2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_ADC_IRQn_Pos                (14UL)                    /*!< NVIC ISPR: ADC_IRQn (Bit 14)                                */
#define NVIC_ISPR_ADC_IRQn_Msk                (0x4000UL)                /*!< NVIC ISPR: ADC_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_KEYBRD_IRQn_Pos             (15UL)                    /*!< NVIC ISPR: KEYBRD_IRQn (Bit 15)                             */
#define NVIC_ISPR_KEYBRD_IRQn_Msk             (0x8000UL)                /*!< NVIC ISPR: KEYBRD_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISPR_IRGEN_IRQn_Pos              (16UL)                    /*!< NVIC ISPR: IRGEN_IRQn (Bit 16)                              */
#define NVIC_ISPR_IRGEN_IRQn_Msk              (0x10000UL)               /*!< NVIC ISPR: IRGEN_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ISPR_WKUP_GPIO_IRQn_Pos          (17UL)                    /*!< NVIC ISPR: WKUP_GPIO_IRQn (Bit 17)                          */
#define NVIC_ISPR_WKUP_GPIO_IRQn_Msk          (0x20000UL)               /*!< NVIC ISPR: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ISPR_SWTIM0_IRQn_Pos             (18UL)                    /*!< NVIC ISPR: SWTIM0_IRQn (Bit 18)                             */
#define NVIC_ISPR_SWTIM0_IRQn_Msk             (0x40000UL)               /*!< NVIC ISPR: SWTIM0_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISPR_SWTIM1_IRQn_Pos             (19UL)                    /*!< NVIC ISPR: SWTIM1_IRQn (Bit 19)                             */
#define NVIC_ISPR_SWTIM1_IRQn_Msk             (0x80000UL)               /*!< NVIC ISPR: SWTIM1_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISPR_QUADEC_IRQn_Pos             (20UL)                    /*!< NVIC ISPR: QUADEC_IRQn (Bit 20)                             */
#define NVIC_ISPR_QUADEC_IRQn_Msk             (0x100000UL)              /*!< NVIC ISPR: QUADEC_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISPR_USB_IRQn_Pos                (21UL)                    /*!< NVIC ISPR: USB_IRQn (Bit 21)                                */
#define NVIC_ISPR_USB_IRQn_Msk                (0x200000UL)              /*!< NVIC ISPR: USB_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_PCM_IRQn_Pos                (22UL)                    /*!< NVIC ISPR: PCM_IRQn (Bit 22)                                */
#define NVIC_ISPR_PCM_IRQn_Msk                (0x400000UL)              /*!< NVIC ISPR: PCM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_SRC_IN_IRQn_Pos             (23UL)                    /*!< NVIC ISPR: SRC_IN_IRQn (Bit 23)                             */
#define NVIC_ISPR_SRC_IN_IRQn_Msk             (0x800000UL)              /*!< NVIC ISPR: SRC_IN_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ISPR_SRC_OUT_IRQn_Pos            (24UL)                    /*!< NVIC ISPR: SRC_OUT_IRQn (Bit 24)                            */
#define NVIC_ISPR_SRC_OUT_IRQn_Msk            (0x1000000UL)             /*!< NVIC ISPR: SRC_OUT_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ISPR_VBUS_IRQn_Pos               (25UL)                    /*!< NVIC ISPR: VBUS_IRQn (Bit 25)                               */
#define NVIC_ISPR_VBUS_IRQn_Msk               (0x2000000UL)             /*!< NVIC ISPR: VBUS_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_DMA_IRQn_Pos                (26UL)                    /*!< NVIC ISPR: DMA_IRQn (Bit 26)                                */
#define NVIC_ISPR_DMA_IRQn_Msk                (0x4000000UL)             /*!< NVIC ISPR: DMA_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ISPR_RF_DIAG_IRQn_Pos            (27UL)                    /*!< NVIC ISPR: RF_DIAG_IRQn (Bit 27)                            */
#define NVIC_ISPR_RF_DIAG_IRQn_Msk            (0x8000000UL)             /*!< NVIC ISPR: RF_DIAG_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ISPR_TRNG_IRQn_Pos               (28UL)                    /*!< NVIC ISPR: TRNG_IRQn (Bit 28)                               */
#define NVIC_ISPR_TRNG_IRQn_Msk               (0x10000000UL)            /*!< NVIC ISPR: TRNG_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_DCDC_IRQn_Pos               (29UL)                    /*!< NVIC ISPR: DCDC_IRQn (Bit 29)                               */
#define NVIC_ISPR_DCDC_IRQn_Msk               (0x20000000UL)            /*!< NVIC ISPR: DCDC_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ISPR_XTAL16RDY_IRQn_Pos          (30UL)                    /*!< NVIC ISPR: XTAL16RDY_IRQn (Bit 30)                          */
#define NVIC_ISPR_XTAL16RDY_IRQn_Msk          (0x40000000UL)            /*!< NVIC ISPR: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ISPR_Rsvd__irq__n_Pos            (31UL)                    /*!< NVIC ISPR: Rsvd__irq__n (Bit 31)                            */
#define NVIC_ISPR_Rsvd__irq__n_Msk            (0x80000000UL)            /*!< NVIC ISPR: Rsvd__irq__n (Bitfield-Mask: 0x01)               */

/* ----------------------------------  NVIC_ICPR  --------------------------------- */
#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Pos      (0UL)                     /*!< NVIC ICPR: BLE_WAKEUP_LP_IRQn (Bit 0)                       */
#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Msk      (0x1UL)                   /*!< NVIC ICPR: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)         */
#define NVIC_ICPR_BLE_GEN_IRQn_Pos            (1UL)                     /*!< NVIC ICPR: BLE_GEN_IRQn (Bit 1)                             */
#define NVIC_ICPR_BLE_GEN_IRQn_Msk            (0x2UL)                   /*!< NVIC ICPR: BLE_GEN_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Pos        (2UL)                     /*!< NVIC ICPR: FTDF_WAKEUP_IRQn (Bit 2)                         */
#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Msk        (0x4UL)                   /*!< NVIC ICPR: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)           */
#define NVIC_ICPR_FTDF_GEN_IRQn_Pos           (3UL)                     /*!< NVIC ICPR: FTDF_GEN_IRQn (Bit 3)                            */
#define NVIC_ICPR_FTDF_GEN_IRQn_Msk           (0x8UL)                   /*!< NVIC ICPR: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)              */
#define NVIC_ICPR_RFCAL_IRQn_Pos              (4UL)                     /*!< NVIC ICPR: RFCAL_IRQn (Bit 4)                               */
#define NVIC_ICPR_RFCAL_IRQn_Msk              (0x10UL)                  /*!< NVIC ICPR: RFCAL_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ICPR_COEX_IRQn_Pos               (5UL)                     /*!< NVIC ICPR: COEX_IRQn (Bit 5)                                */
#define NVIC_ICPR_COEX_IRQn_Msk               (0x20UL)                  /*!< NVIC ICPR: COEX_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_CRYPTO_IRQn_Pos             (6UL)                     /*!< NVIC ICPR: CRYPTO_IRQn (Bit 6)                              */
#define NVIC_ICPR_CRYPTO_IRQn_Msk             (0x40UL)                  /*!< NVIC ICPR: CRYPTO_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICPR_MRM_IRQn_Pos                (7UL)                     /*!< NVIC ICPR: MRM_IRQn (Bit 7)                                 */
#define NVIC_ICPR_MRM_IRQn_Msk                (0x80UL)                  /*!< NVIC ICPR: MRM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_UART_IRQn_Pos               (8UL)                     /*!< NVIC ICPR: UART_IRQn (Bit 8)                                */
#define NVIC_ICPR_UART_IRQn_Msk               (0x100UL)                 /*!< NVIC ICPR: UART_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_UART2_IRQn_Pos              (9UL)                     /*!< NVIC ICPR: UART2_IRQn (Bit 9)                               */
#define NVIC_ICPR_UART2_IRQn_Msk              (0x200UL)                 /*!< NVIC ICPR: UART2_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ICPR_I2C_IRQn_Pos                (10UL)                    /*!< NVIC ICPR: I2C_IRQn (Bit 10)                                */
#define NVIC_ICPR_I2C_IRQn_Msk                (0x400UL)                 /*!< NVIC ICPR: I2C_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_I2C2_IRQn_Pos               (11UL)                    /*!< NVIC ICPR: I2C2_IRQn (Bit 11)                               */
#define NVIC_ICPR_I2C2_IRQn_Msk               (0x800UL)                 /*!< NVIC ICPR: I2C2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_SPI_IRQn_Pos                (12UL)                    /*!< NVIC ICPR: SPI_IRQn (Bit 12)                                */
#define NVIC_ICPR_SPI_IRQn_Msk                (0x1000UL)                /*!< NVIC ICPR: SPI_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_SPI2_IRQn_Pos               (13UL)                    /*!< NVIC ICPR: SPI2_IRQn (Bit 13)                               */
#define NVIC_ICPR_SPI2_IRQn_Msk               (0x2000UL)                /*!< NVIC ICPR: SPI2_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_ADC_IRQn_Pos                (14UL)                    /*!< NVIC ICPR: ADC_IRQn (Bit 14)                                */
#define NVIC_ICPR_ADC_IRQn_Msk                (0x4000UL)                /*!< NVIC ICPR: ADC_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_KEYBRD_IRQn_Pos             (15UL)                    /*!< NVIC ICPR: KEYBRD_IRQn (Bit 15)                             */
#define NVIC_ICPR_KEYBRD_IRQn_Msk             (0x8000UL)                /*!< NVIC ICPR: KEYBRD_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICPR_IRGEN_IRQn_Pos              (16UL)                    /*!< NVIC ICPR: IRGEN_IRQn (Bit 16)                              */
#define NVIC_ICPR_IRGEN_IRQn_Msk              (0x10000UL)               /*!< NVIC ICPR: IRGEN_IRQn (Bitfield-Mask: 0x01)                 */
#define NVIC_ICPR_WKUP_GPIO_IRQn_Pos          (17UL)                    /*!< NVIC ICPR: WKUP_GPIO_IRQn (Bit 17)                          */
#define NVIC_ICPR_WKUP_GPIO_IRQn_Msk          (0x20000UL)               /*!< NVIC ICPR: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ICPR_SWTIM0_IRQn_Pos             (18UL)                    /*!< NVIC ICPR: SWTIM0_IRQn (Bit 18)                             */
#define NVIC_ICPR_SWTIM0_IRQn_Msk             (0x40000UL)               /*!< NVIC ICPR: SWTIM0_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICPR_SWTIM1_IRQn_Pos             (19UL)                    /*!< NVIC ICPR: SWTIM1_IRQn (Bit 19)                             */
#define NVIC_ICPR_SWTIM1_IRQn_Msk             (0x80000UL)               /*!< NVIC ICPR: SWTIM1_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICPR_QUADEC_IRQn_Pos             (20UL)                    /*!< NVIC ICPR: QUADEC_IRQn (Bit 20)                             */
#define NVIC_ICPR_QUADEC_IRQn_Msk             (0x100000UL)              /*!< NVIC ICPR: QUADEC_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICPR_USB_IRQn_Pos                (21UL)                    /*!< NVIC ICPR: USB_IRQn (Bit 21)                                */
#define NVIC_ICPR_USB_IRQn_Msk                (0x200000UL)              /*!< NVIC ICPR: USB_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_PCM_IRQn_Pos                (22UL)                    /*!< NVIC ICPR: PCM_IRQn (Bit 22)                                */
#define NVIC_ICPR_PCM_IRQn_Msk                (0x400000UL)              /*!< NVIC ICPR: PCM_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_SRC_IN_IRQn_Pos             (23UL)                    /*!< NVIC ICPR: SRC_IN_IRQn (Bit 23)                             */
#define NVIC_ICPR_SRC_IN_IRQn_Msk             (0x800000UL)              /*!< NVIC ICPR: SRC_IN_IRQn (Bitfield-Mask: 0x01)                */
#define NVIC_ICPR_SRC_OUT_IRQn_Pos            (24UL)                    /*!< NVIC ICPR: SRC_OUT_IRQn (Bit 24)                            */
#define NVIC_ICPR_SRC_OUT_IRQn_Msk            (0x1000000UL)             /*!< NVIC ICPR: SRC_OUT_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ICPR_VBUS_IRQn_Pos               (25UL)                    /*!< NVIC ICPR: VBUS_IRQn (Bit 25)                               */
#define NVIC_ICPR_VBUS_IRQn_Msk               (0x2000000UL)             /*!< NVIC ICPR: VBUS_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_DMA_IRQn_Pos                (26UL)                    /*!< NVIC ICPR: DMA_IRQn (Bit 26)                                */
#define NVIC_ICPR_DMA_IRQn_Msk                (0x4000000UL)             /*!< NVIC ICPR: DMA_IRQn (Bitfield-Mask: 0x01)                   */
#define NVIC_ICPR_RF_DIAG_IRQn_Pos            (27UL)                    /*!< NVIC ICPR: RF_DIAG_IRQn (Bit 27)                            */
#define NVIC_ICPR_RF_DIAG_IRQn_Msk            (0x8000000UL)             /*!< NVIC ICPR: RF_DIAG_IRQn (Bitfield-Mask: 0x01)               */
#define NVIC_ICPR_TRNG_IRQn_Pos               (28UL)                    /*!< NVIC ICPR: TRNG_IRQn (Bit 28)                               */
#define NVIC_ICPR_TRNG_IRQn_Msk               (0x10000000UL)            /*!< NVIC ICPR: TRNG_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_DCDC_IRQn_Pos               (29UL)                    /*!< NVIC ICPR: DCDC_IRQn (Bit 29)                               */
#define NVIC_ICPR_DCDC_IRQn_Msk               (0x20000000UL)            /*!< NVIC ICPR: DCDC_IRQn (Bitfield-Mask: 0x01)                  */
#define NVIC_ICPR_XTAL16RDY_IRQn_Pos          (30UL)                    /*!< NVIC ICPR: XTAL16RDY_IRQn (Bit 30)                          */
#define NVIC_ICPR_XTAL16RDY_IRQn_Msk          (0x40000000UL)            /*!< NVIC ICPR: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)             */
#define NVIC_ICPR_Rsvd__irq__n_Pos            (31UL)                    /*!< NVIC ICPR: Rsvd__irq__n (Bit 31)                            */
#define NVIC_ICPR_Rsvd__irq__n_Msk            (0x80000000UL)            /*!< NVIC ICPR: Rsvd__irq__n (Bitfield-Mask: 0x01)               */

/* ----------------------------------  NVIC_IPR0  --------------------------------- */
#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Pos (0UL)                     /*!< NVIC IPR0: BLE_WAKEUP_LP_IRQn_prio (Bit 0)                  */
#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Msk (0xffUL)                  /*!< NVIC IPR0: BLE_WAKEUP_LP_IRQn_prio (Bitfield-Mask: 0xff)    */
#define NVIC_IPR0_BLE_GEN_IRQn_prio_Pos       (8UL)                     /*!< NVIC IPR0: BLE_GEN_IRQn_prio (Bit 8)                        */
#define NVIC_IPR0_BLE_GEN_IRQn_prio_Msk       (0xff00UL)                /*!< NVIC IPR0: BLE_GEN_IRQn_prio (Bitfield-Mask: 0xff)          */
#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Pos   (16UL)                    /*!< NVIC IPR0: FTDF_WAKEUP_IRQn_prio (Bit 16)                   */
#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Msk   (0xff0000UL)              /*!< NVIC IPR0: FTDF_WAKEUP_IRQn_prio (Bitfield-Mask: 0xff)      */
#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Pos      (24UL)                    /*!< NVIC IPR0: FTDF_GEN_IRQn_prio (Bit 24)                      */
#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Msk      (0xff000000UL)            /*!< NVIC IPR0: FTDF_GEN_IRQn_prio (Bitfield-Mask: 0xff)         */

/* ----------------------------------  NVIC_IPR1  --------------------------------- */
#define NVIC_IPR1_RFCAL_IRQn_prio_Pos         (0UL)                     /*!< NVIC IPR1: RFCAL_IRQn_prio (Bit 0)                          */
#define NVIC_IPR1_RFCAL_IRQn_prio_Msk         (0xffUL)                  /*!< NVIC IPR1: RFCAL_IRQn_prio (Bitfield-Mask: 0xff)            */
#define NVIC_IPR1_COEX_IRQn_prio_Pos          (8UL)                     /*!< NVIC IPR1: COEX_IRQn_prio (Bit 8)                           */
#define NVIC_IPR1_COEX_IRQn_prio_Msk          (0xff00UL)                /*!< NVIC IPR1: COEX_IRQn_prio (Bitfield-Mask: 0xff)             */
#define NVIC_IPR1_CRYPTO_IRQn_prio_Pos        (16UL)                    /*!< NVIC IPR1: CRYPTO_IRQn_prio (Bit 16)                        */
#define NVIC_IPR1_CRYPTO_IRQn_prio_Msk        (0xff0000UL)              /*!< NVIC IPR1: CRYPTO_IRQn_prio (Bitfield-Mask: 0xff)           */
#define NVIC_IPR1_MRM_IRQn_prio_Pos           (24UL)                    /*!< NVIC IPR1: MRM_IRQn_prio (Bit 24)                           */
#define NVIC_IPR1_MRM_IRQn_prio_Msk           (0xff000000UL)            /*!< NVIC IPR1: MRM_IRQn_prio (Bitfield-Mask: 0xff)              */

/* ----------------------------------  NVIC_IPR2  --------------------------------- */
#define NVIC_IPR2_UART_IRQn_prio_Pos          (0UL)                     /*!< NVIC IPR2: UART_IRQn_prio (Bit 0)                           */
#define NVIC_IPR2_UART_IRQn_prio_Msk          (0xffUL)                  /*!< NVIC IPR2: UART_IRQn_prio (Bitfield-Mask: 0xff)             */
#define NVIC_IPR2_UART2_IRQn_prio_Pos         (8UL)                     /*!< NVIC IPR2: UART2_IRQn_prio (Bit 8)                          */
#define NVIC_IPR2_UART2_IRQn_prio_Msk         (0xff00UL)                /*!< NVIC IPR2: UART2_IRQn_prio (Bitfield-Mask: 0xff)            */
#define NVIC_IPR2_I2C_IRQn_prio_Pos           (16UL)                    /*!< NVIC IPR2: I2C_IRQn_prio (Bit 16)                           */
#define NVIC_IPR2_I2C_IRQn_prio_Msk           (0xff0000UL)              /*!< NVIC IPR2: I2C_IRQn_prio (Bitfield-Mask: 0xff)              */
#define NVIC_IPR2_I2C2_IRQn_prio_Pos          (24UL)                    /*!< NVIC IPR2: I2C2_IRQn_prio (Bit 24)                          */
#define NVIC_IPR2_I2C2_IRQn_prio_Msk          (0xff000000UL)            /*!< NVIC IPR2: I2C2_IRQn_prio (Bitfield-Mask: 0xff)             */

/* ----------------------------------  NVIC_IPR3  --------------------------------- */
#define NVIC_IPR3_SPI_IRQn_prio_Pos           (0UL)                     /*!< NVIC IPR3: SPI_IRQn_prio (Bit 0)                            */
#define NVIC_IPR3_SPI_IRQn_prio_Msk           (0xffUL)                  /*!< NVIC IPR3: SPI_IRQn_prio (Bitfield-Mask: 0xff)              */
#define NVIC_IPR3_SPI2_IRQn_prio_Pos          (8UL)                     /*!< NVIC IPR3: SPI2_IRQn_prio (Bit 8)                           */
#define NVIC_IPR3_SPI2_IRQn_prio_Msk          (0xff00UL)                /*!< NVIC IPR3: SPI2_IRQn_prio (Bitfield-Mask: 0xff)             */
#define NVIC_IPR3_ADC_IRQn_prio_Pos           (16UL)                    /*!< NVIC IPR3: ADC_IRQn_prio (Bit 16)                           */
#define NVIC_IPR3_ADC_IRQn_prio_Msk           (0xff0000UL)              /*!< NVIC IPR3: ADC_IRQn_prio (Bitfield-Mask: 0xff)              */
#define NVIC_IPR3_KEYBRD_IRQn_prio_Pos        (24UL)                    /*!< NVIC IPR3: KEYBRD_IRQn_prio (Bit 24)                        */
#define NVIC_IPR3_KEYBRD_IRQn_prio_Msk        (0xff000000UL)            /*!< NVIC IPR3: KEYBRD_IRQn_prio (Bitfield-Mask: 0xff)           */

/* ----------------------------------  NVIC_IPR4  --------------------------------- */
#define NVIC_IPR4_IRGEN_IRQn_prio_Pos         (0UL)                     /*!< NVIC IPR4: IRGEN_IRQn_prio (Bit 0)                          */
#define NVIC_IPR4_IRGEN_IRQn_prio_Msk         (0xffUL)                  /*!< NVIC IPR4: IRGEN_IRQn_prio (Bitfield-Mask: 0xff)            */
#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Pos     (8UL)                     /*!< NVIC IPR4: WKUP_GPIO_IRQn_prio (Bit 8)                      */
#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Msk     (0xff00UL)                /*!< NVIC IPR4: WKUP_GPIO_IRQn_prio (Bitfield-Mask: 0xff)        */
#define NVIC_IPR4_SWTIM0_IRQn_prio_Pos        (16UL)                    /*!< NVIC IPR4: SWTIM0_IRQn_prio (Bit 16)                        */
#define NVIC_IPR4_SWTIM0_IRQn_prio_Msk        (0xff0000UL)              /*!< NVIC IPR4: SWTIM0_IRQn_prio (Bitfield-Mask: 0xff)           */
#define NVIC_IPR4_SWTIM1_IRQn_prio_Pos        (24UL)                    /*!< NVIC IPR4: SWTIM1_IRQn_prio (Bit 24)                        */
#define NVIC_IPR4_SWTIM1_IRQn_prio_Msk        (0xff000000UL)            /*!< NVIC IPR4: SWTIM1_IRQn_prio (Bitfield-Mask: 0xff)           */

/* ----------------------------------  NVIC_IPR5  --------------------------------- */
#define NVIC_IPR5_QUADEC_IRQn_prio_Pos        (0UL)                     /*!< NVIC IPR5: QUADEC_IRQn_prio (Bit 0)                         */
#define NVIC_IPR5_QUADEC_IRQn_prio_Msk        (0xffUL)                  /*!< NVIC IPR5: QUADEC_IRQn_prio (Bitfield-Mask: 0xff)           */
#define NVIC_IPR5_USB_IRQn_prio_Pos           (8UL)                     /*!< NVIC IPR5: USB_IRQn_prio (Bit 8)                            */
#define NVIC_IPR5_USB_IRQn_prio_Msk           (0xff00UL)                /*!< NVIC IPR5: USB_IRQn_prio (Bitfield-Mask: 0xff)              */
#define NVIC_IPR5_PCM_IRQn_prio_Pos           (16UL)                    /*!< NVIC IPR5: PCM_IRQn_prio (Bit 16)                           */
#define NVIC_IPR5_PCM_IRQn_prio_Msk           (0xff0000UL)              /*!< NVIC IPR5: PCM_IRQn_prio (Bitfield-Mask: 0xff)              */
#define NVIC_IPR5_SRC_IN_IRQn_prio_Pos        (24UL)                    /*!< NVIC IPR5: SRC_IN_IRQn_prio (Bit 24)                        */
#define NVIC_IPR5_SRC_IN_IRQn_prio_Msk        (0xff000000UL)            /*!< NVIC IPR5: SRC_IN_IRQn_prio (Bitfield-Mask: 0xff)           */

/* ----------------------------------  NVIC_IPR6  --------------------------------- */
#define NVIC_IPR6_SRC_OUT_IRQn_prio_Pos       (0UL)                     /*!< NVIC IPR6: SRC_OUT_IRQn_prio (Bit 0)                        */
#define NVIC_IPR6_SRC_OUT_IRQn_prio_Msk       (0xffUL)                  /*!< NVIC IPR6: SRC_OUT_IRQn_prio (Bitfield-Mask: 0xff)          */
#define NVIC_IPR6_VBUS_IRQn_prio_Pos          (8UL)                     /*!< NVIC IPR6: VBUS_IRQn_prio (Bit 8)                           */
#define NVIC_IPR6_VBUS_IRQn_prio_Msk          (0xff00UL)                /*!< NVIC IPR6: VBUS_IRQn_prio (Bitfield-Mask: 0xff)             */
#define NVIC_IPR6_DMA_IRQn_prio_Pos           (16UL)                    /*!< NVIC IPR6: DMA_IRQn_prio (Bit 16)                           */
#define NVIC_IPR6_DMA_IRQn_prio_Msk           (0xff0000UL)              /*!< NVIC IPR6: DMA_IRQn_prio (Bitfield-Mask: 0xff)              */
#define NVIC_IPR6_RF_DIAG_IRQn_prio_Pos       (24UL)                    /*!< NVIC IPR6: RF_DIAG_IRQn_prio (Bit 24)                       */
#define NVIC_IPR6_RF_DIAG_IRQn_prio_Msk       (0xff000000UL)            /*!< NVIC IPR6: RF_DIAG_IRQn_prio (Bitfield-Mask: 0xff)          */

/* ----------------------------------  NVIC_IPR7  --------------------------------- */
#define NVIC_IPR7_TRNG_IRQn_prio_Pos          (0UL)                     /*!< NVIC IPR7: TRNG_IRQn_prio (Bit 0)                           */
#define NVIC_IPR7_TRNG_IRQn_prio_Msk          (0xffUL)                  /*!< NVIC IPR7: TRNG_IRQn_prio (Bitfield-Mask: 0xff)             */
#define NVIC_IPR7_DCDC_IRQn_prio_Pos          (8UL)                     /*!< NVIC IPR7: DCDC_IRQn_prio (Bit 8)                           */
#define NVIC_IPR7_DCDC_IRQn_prio_Msk          (0xff00UL)                /*!< NVIC IPR7: DCDC_IRQn_prio (Bitfield-Mask: 0xff)             */
#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Pos     (16UL)                    /*!< NVIC IPR7: XTAL16RDY_IRQn_prio (Bit 16)                     */
#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Msk     (0xff0000UL)              /*!< NVIC IPR7: XTAL16RDY_IRQn_prio (Bitfield-Mask: 0xff)        */
#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Pos (24UL)                   /*!< NVIC IPR7: RESERVED31_IRQn_DONT_USE (Bit 24)                */
#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Msk (0xff000000UL)           /*!< NVIC IPR7: RESERVED31_IRQn_DONT_USE (Bitfield-Mask: 0xff)   */


/* ================================================================================ */
/* ================        struct 'AES_HASH' Position & Mask       ================ */
/* ================================================================================ */


/* --------------------------  AES_HASH_CRYPTO_CTRL_REG  -------------------------- */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL)                   /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG (Bit 0)                */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL)                 /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG (Bitfield-Mask: 0x03)  */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL)                /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG_MD (Bit 2)             */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL)              /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG_MD (Bitfield-Mask: 0x03) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL)                /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_OUT_MD (Bit 4)             */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL)             /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_OUT_MD (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL)            /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEY_SZ (Bit 5)         */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL)         /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL)                /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ENCDEC (Bit 7)             */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL)             /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ENCDEC (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL)                /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_IRQ_EN (Bit 8)             */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL)            /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_IRQ_EN (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL)              /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_SEL (Bit 9)           */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL)          /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_SEL (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL)         /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_OUT_LEN (Bit 10)      */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0xfc00UL)     /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x3f) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (16UL)              /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_MORE_IN (Bit 16)           */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x10000UL)         /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_MORE_IN (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (17UL)             /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEXP (Bit 17)          */
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x20000UL)        /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEXP (Bitfield-Mask: 0x01) */

/* --------------------------  AES_HASH_CRYPTO_START_REG  ------------------------- */
#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL)                /*!< AES_HASH CRYPTO_START_REG: CRYPTO_START (Bit 0)             */
#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL)              /*!< AES_HASH CRYPTO_START_REG: CRYPTO_START (Bitfield-Mask: 0x01) */

/* -----------------------  AES_HASH_CRYPTO_FETCH_ADDR_REG  ----------------------- */
#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL)      /*!< AES_HASH CRYPTO_FETCH_ADDR_REG: CRYPTO_FETCH_ADDR (Bit 0)   */
#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_FETCH_ADDR_REG: CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  AES_HASH_CRYPTO_LEN_REG  -------------------------- */
#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL)                    /*!< AES_HASH CRYPTO_LEN_REG: CRYPTO_LEN (Bit 0)                 */
#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL)             /*!< AES_HASH CRYPTO_LEN_REG: CRYPTO_LEN (Bitfield-Mask: 0xffffff) */

/* ------------------------  AES_HASH_CRYPTO_DEST_ADDR_REG  ----------------------- */
#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL)        /*!< AES_HASH CRYPTO_DEST_ADDR_REG: CRYPTO_DEST_ADDR (Bit 0)     */
#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_DEST_ADDR_REG: CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff) */

/* -------------------------  AES_HASH_CRYPTO_STATUS_REG  ------------------------- */
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL)            /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_INACTIVE (Bit 0)         */
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL)          /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_INACTIVE (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL)         /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_WAIT_FOR_IN (Bit 1)      */
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL)       /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01) */
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL)              /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_IRQ_ST (Bit 2)           */
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL)            /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_IRQ_ST (Bitfield-Mask: 0x01) */

/* -------------------------  AES_HASH_CRYPTO_CLRIRQ_REG  ------------------------- */
#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL)              /*!< AES_HASH CRYPTO_CLRIRQ_REG: CRYPTO_CLRIRQ (Bit 0)           */
#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL)            /*!< AES_HASH CRYPTO_CLRIRQ_REG: CRYPTO_CLRIRQ (Bitfield-Mask: 0x01) */

/* --------------------------  AES_HASH_CRYPTO_MREG0_REG  ------------------------- */
#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL)                /*!< AES_HASH CRYPTO_MREG0_REG: CRYPTO_MREG0 (Bit 0)             */
#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL)       /*!< AES_HASH CRYPTO_MREG0_REG: CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  AES_HASH_CRYPTO_MREG1_REG  ------------------------- */
#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL)                /*!< AES_HASH CRYPTO_MREG1_REG: CRYPTO_MREG1 (Bit 0)             */
#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL)       /*!< AES_HASH CRYPTO_MREG1_REG: CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  AES_HASH_CRYPTO_MREG2_REG  ------------------------- */
#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL)                /*!< AES_HASH CRYPTO_MREG2_REG: CRYPTO_MREG2 (Bit 0)             */
#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL)       /*!< AES_HASH CRYPTO_MREG2_REG: CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  AES_HASH_CRYPTO_MREG3_REG  ------------------------- */
#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL)                /*!< AES_HASH CRYPTO_MREG3_REG: CRYPTO_MREG3 (Bit 0)             */
#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL)       /*!< AES_HASH CRYPTO_MREG3_REG: CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff) */

/* -------------------------  AES_HASH_CRYPTO_KEYS_START  ------------------------- */
#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL)               /*!< AES_HASH CRYPTO_KEYS_START: CRYPTO_KEY_X (Bit 0)            */
#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL)      /*!< AES_HASH CRYPTO_KEYS_START: CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff) */


/* ================================================================================ */
/* ================        struct 'ANAMISC' Position & Mask        ================ */
/* ================================================================================ */


/* ----------------------------  ANAMISC_ANA_TEST_REG  ---------------------------- */
#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Pos (0UL)                   /*!< ANAMISC ANA_TEST_REG: TEST_STRUCTURE (Bit 0)                */
#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Msk (0xfUL)                 /*!< ANAMISC ANA_TEST_REG: TEST_STRUCTURE (Bitfield-Mask: 0x0f)  */
#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Pos (4UL)                 /*!< ANAMISC ANA_TEST_REG: ACORE_TESTBUS_EN (Bit 4)              */
#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Msk (0x10UL)              /*!< ANAMISC ANA_TEST_REG: ACORE_TESTBUS_EN (Bitfield-Mask: 0x01) */

/* --------------------------  ANAMISC_CHARGER_CTRL1_REG  ------------------------- */
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Pos (0UL)                /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_LEVEL (Bit 0)             */
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Msk (0x1fUL)             /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_LEVEL (Bitfield-Mask: 0x1f) */
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Pos (5UL)                   /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_ON (Bit 5)                */
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Msk (0x20UL)                /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_ON (Bitfield-Mask: 0x01)  */
#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Pos (6UL)                 /*!< ANAMISC CHARGER_CTRL1_REG: NTC_DISABLE (Bit 6)              */
#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Msk (0x40UL)              /*!< ANAMISC CHARGER_CTRL1_REG: NTC_DISABLE (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Pos (7UL)             /*!< ANAMISC CHARGER_CTRL1_REG: NTC_LOW_DISABLE (Bit 7)          */
#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Msk (0x80UL)          /*!< ANAMISC CHARGER_CTRL1_REG: NTC_LOW_DISABLE (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Pos (8UL)                  /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_CUR (Bit 8)               */
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Msk (0xf00UL)              /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_CUR (Bitfield-Mask: 0x0f) */
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Pos (12UL)               /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_SET (Bit 12)            */
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Msk (0x3000UL)           /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_SET (Bitfield-Mask: 0x03) */
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Pos (14UL)           /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_DISABLE (Bit 14)        */
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Msk (0x4000UL)       /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_DISABLE (Bitfield-Mask: 0x01) */

/* --------------------------  ANAMISC_CHARGER_CTRL2_REG  ------------------------- */
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Pos (0UL)           /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_GAIN_TRIM (Bit 0)        */
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Msk (0xfUL)         /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_GAIN_TRIM (Bitfield-Mask: 0x0f) */
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Pos (4UL)          /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_VFLOAT_ADJ (Bit 4)       */
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Msk (0xf0UL)       /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_VFLOAT_ADJ (Bitfield-Mask: 0x0f) */
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Pos (8UL)         /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_OFFSET_TRIM (Bit 8)      */
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Msk (0x1f00UL)    /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_OFFSET_TRIM (Bitfield-Mask: 0x1f) */
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Pos (13UL)               /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_TEST (Bit 13)            */
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Msk (0xe000UL)           /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_TEST (Bitfield-Mask: 0x07) */

/* -------------------------  ANAMISC_CHARGER_STATUS_REG  ------------------------- */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos (0UL)            /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CC_MODE (Bit 0)         */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk (0x1UL)          /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CC_MODE (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos (1UL)            /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CV_MODE (Bit 1)         */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk (0x2UL)          /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CV_MODE (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Pos (2UL)              /*!< ANAMISC CHARGER_STATUS_REG: END_OF_CHARGE (Bit 2)           */
#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Msk (0x4UL)            /*!< ANAMISC CHARGER_STATUS_REG: END_OF_CHARGE (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Pos (3UL)        /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_LOW (Bit 3)     */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Msk (0x8UL)      /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_LOW (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Pos (4UL)         /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_OK (Bit 4)      */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Msk (0x10UL)      /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_OK (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Pos (5UL)       /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_HIGH (Bit 5)    */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Msk (0x20UL)    /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_HIGH (Bitfield-Mask: 0x01) */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Pos (6UL)         /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_TMODE_PROT (Bit 6)      */
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Msk (0x40UL)      /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_TMODE_PROT (Bitfield-Mask: 0x01) */

/* ----------------------------  ANAMISC_SOC_CTRL1_REG  --------------------------- */
#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Pos  (0UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_ENABLE (Bit 0)                   */
#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Msk  (0x1UL)                   /*!< ANAMISC SOC_CTRL1_REG: SOC_ENABLE (Bitfield-Mask: 0x01)     */
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Pos (1UL)                /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_CHARGE (Bit 1)             */
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Msk (0x2UL)              /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_CHARGE (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Pos (2UL)                   /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_AVG (Bit 2)                */
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Msk (0x4UL)                 /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_AVG (Bitfield-Mask: 0x01)  */
#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Pos    (3UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_MUTE (Bit 3)                     */
#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Msk    (0x8UL)                   /*!< ANAMISC SOC_CTRL1_REG: SOC_MUTE (Bitfield-Mask: 0x01)       */
#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Pos    (4UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_GPIO (Bit 4)                     */
#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Msk    (0x10UL)                  /*!< ANAMISC SOC_CTRL1_REG: SOC_GPIO (Bitfield-Mask: 0x01)       */
#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Pos    (5UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_SIGN (Bit 5)                     */
#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Msk    (0x20UL)                  /*!< ANAMISC SOC_CTRL1_REG: SOC_SIGN (Bitfield-Mask: 0x01)       */
#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Pos    (6UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_IDAC (Bit 6)                     */
#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Msk    (0xc0UL)                  /*!< ANAMISC SOC_CTRL1_REG: SOC_IDAC (Bitfield-Mask: 0x03)       */
#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Pos     (8UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_LPF (Bit 8)                      */
#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Msk     (0x100UL)                 /*!< ANAMISC SOC_CTRL1_REG: SOC_LPF (Bitfield-Mask: 0x01)        */
#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Pos     (9UL)                     /*!< ANAMISC SOC_CTRL1_REG: SOC_CLK (Bit 9)                      */
#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Msk     (0xe00UL)                 /*!< ANAMISC SOC_CTRL1_REG: SOC_CLK (Bitfield-Mask: 0x07)        */
#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Pos    (12UL)                    /*!< ANAMISC SOC_CTRL1_REG: SOC_BIAS (Bit 12)                    */
#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Msk    (0x3000UL)                /*!< ANAMISC SOC_CTRL1_REG: SOC_BIAS (Bitfield-Mask: 0x03)       */
#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Pos    (14UL)                    /*!< ANAMISC SOC_CTRL1_REG: SOC_CINT (Bit 14)                    */
#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Msk    (0xc000UL)                /*!< ANAMISC SOC_CTRL1_REG: SOC_CINT (Bitfield-Mask: 0x03)       */

/* ----------------------------  ANAMISC_SOC_CTRL2_REG  --------------------------- */
#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Pos     (0UL)                     /*!< ANAMISC SOC_CTRL2_REG: SOC_RVI (Bit 0)                      */
#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Msk     (0x3UL)                   /*!< ANAMISC SOC_CTRL2_REG: SOC_RVI (Bitfield-Mask: 0x03)        */
#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Pos  (2UL)                     /*!< ANAMISC SOC_CTRL2_REG: SOC_SCYCLE (Bit 2)                   */
#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Msk  (0x1cUL)                  /*!< ANAMISC SOC_CTRL2_REG: SOC_SCYCLE (Bitfield-Mask: 0x07)     */
#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Pos  (5UL)                     /*!< ANAMISC SOC_CTRL2_REG: SOC_DCYCLE (Bit 5)                   */
#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Msk  (0x20UL)                  /*!< ANAMISC SOC_CTRL2_REG: SOC_DCYCLE (Bitfield-Mask: 0x01)     */
#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Pos     (6UL)                     /*!< ANAMISC SOC_CTRL2_REG: SOC_ICM (Bit 6)                      */
#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Msk     (0xc0UL)                  /*!< ANAMISC SOC_CTRL2_REG: SOC_ICM (Bitfield-Mask: 0x03)        */
#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Pos    (8UL)                     /*!< ANAMISC SOC_CTRL2_REG: SOC_CHOP (Bit 8)                     */
#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Msk    (0x700UL)                 /*!< ANAMISC SOC_CTRL2_REG: SOC_CHOP (Bitfield-Mask: 0x07)       */
#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Pos (11UL)              /*!< ANAMISC SOC_CTRL2_REG: SOC_CMIREG_ENABLE (Bit 11)           */
#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Msk (0x800UL)           /*!< ANAMISC SOC_CTRL2_REG: SOC_CMIREG_ENABLE (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Pos     (12UL)                    /*!< ANAMISC SOC_CTRL2_REG: SOC_MAW (Bit 12)                     */
#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Msk     (0x7000UL)                /*!< ANAMISC SOC_CTRL2_REG: SOC_MAW (Bitfield-Mask: 0x07)        */
#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Pos  (15UL)                    /*!< ANAMISC SOC_CTRL2_REG: SOC_DYNAVG (Bit 15)                  */
#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Msk  (0x8000UL)                /*!< ANAMISC SOC_CTRL2_REG: SOC_DYNAVG (Bitfield-Mask: 0x01)     */

/* ----------------------------  ANAMISC_SOC_CTRL3_REG  --------------------------- */
#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Pos    (0UL)                     /*!< ANAMISC SOC_CTRL3_REG: SOC_VSAT (Bit 0)                     */
#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Msk    (0x3UL)                   /*!< ANAMISC SOC_CTRL3_REG: SOC_VSAT (Bitfield-Mask: 0x03)       */
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Pos (2UL)                     /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNTARG (Bit 2)                  */
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Msk (0x4UL)                   /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNTARG (Bitfield-Mask: 0x01)    */
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Pos  (3UL)                     /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNHYS (Bit 3)                   */
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Msk  (0x8UL)                   /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNHYS (Bitfield-Mask: 0x01)     */
#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Pos    (4UL)                     /*!< ANAMISC SOC_CTRL3_REG: SOC_VCMI (Bit 4)                     */
#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Msk    (0x30UL)                  /*!< ANAMISC SOC_CTRL3_REG: SOC_VCMI (Bitfield-Mask: 0x03)       */

/* ---------------------------  ANAMISC_SOC_ADD2CH_REG  --------------------------- */
#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Pos (0UL)                     /*!< ANAMISC SOC_ADD2CH_REG: SOC_ADD2CH (Bit 0)                  */
#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Msk (0xffffUL)                /*!< ANAMISC SOC_ADD2CH_REG: SOC_ADD2CH (Bitfield-Mask: 0xffff)  */

/* ------------------------  ANAMISC_SOC_CHARGE_CNTR1_REG  ------------------------ */
#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Pos (0UL)              /*!< ANAMISC SOC_CHARGE_CNTR1_REG: CHARGE_CNT1 (Bit 0)           */
#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Msk (0xffffUL)         /*!< ANAMISC SOC_CHARGE_CNTR1_REG: CHARGE_CNT1 (Bitfield-Mask: 0xffff) */

/* ------------------------  ANAMISC_SOC_CHARGE_CNTR2_REG  ------------------------ */
#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Pos (0UL)              /*!< ANAMISC SOC_CHARGE_CNTR2_REG: CHARGE_CNT2 (Bit 0)           */
#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Msk (0xffffUL)         /*!< ANAMISC SOC_CHARGE_CNTR2_REG: CHARGE_CNT2 (Bitfield-Mask: 0xffff) */

/* ------------------------  ANAMISC_SOC_CHARGE_CNTR3_REG  ------------------------ */
#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Pos (0UL)              /*!< ANAMISC SOC_CHARGE_CNTR3_REG: CHARGE_CNT3 (Bit 0)           */
#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Msk (0xffUL)           /*!< ANAMISC SOC_CHARGE_CNTR3_REG: CHARGE_CNT3 (Bitfield-Mask: 0xff) */

/* -------------------------  ANAMISC_SOC_CHARGE_AVG_REG  ------------------------- */
#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Pos (0UL)                 /*!< ANAMISC SOC_CHARGE_AVG_REG: CHARGE_AVG (Bit 0)              */
#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Msk (0xffffUL)            /*!< ANAMISC SOC_CHARGE_AVG_REG: CHARGE_AVG (Bitfield-Mask: 0xffff) */

/* ---------------------------  ANAMISC_SOC_STATUS_REG  --------------------------- */
#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Pos (0UL)               /*!< ANAMISC SOC_STATUS_REG: SOC_INT_OVERLOAD (Bit 0)            */
#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Msk (0x1UL)             /*!< ANAMISC SOC_STATUS_REG: SOC_INT_OVERLOAD (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Pos (1UL)                 /*!< ANAMISC SOC_STATUS_REG: SOC_INT_LOCKED (Bit 1)              */
#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Msk (0x2UL)               /*!< ANAMISC SOC_STATUS_REG: SOC_INT_LOCKED (Bitfield-Mask: 0x01) */

/* ---------------------------  ANAMISC_SOC_EXT_IN_REG  --------------------------- */
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Pos (0UL)                   /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_VAL (Bit 0)                */
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Msk (0x1ffUL)               /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_VAL (Bitfield-Mask: 0x1ff) */
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Pos (9UL)                  /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_SIGN (Bit 9)               */
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Msk (0x200UL)              /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_SIGN (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Pos (10UL)                  /*!< ANAMISC SOC_EXT_IN_REG: SOC_RDAC_DIS (Bit 10)               */
#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Msk (0x400UL)               /*!< ANAMISC SOC_EXT_IN_REG: SOC_RDAC_DIS (Bitfield-Mask: 0x01)  */
#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Pos (11UL)                 /*!< ANAMISC SOC_EXT_IN_REG: SOC_NR_SCYCLE (Bit 11)              */
#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Msk (0x3800UL)             /*!< ANAMISC SOC_EXT_IN_REG: SOC_NR_SCYCLE (Bitfield-Mask: 0x07) */
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Pos (14UL)             /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_SCYCLE_EN (Bit 14)          */
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Msk (0x4000UL)         /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_SCYCLE_EN (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Pos (15UL)               /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_IDAC_EN (Bit 15)            */
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Msk (0x8000UL)           /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_IDAC_EN (Bitfield-Mask: 0x01) */

/* ---------------------------  ANAMISC_SOC_EXT_OUT_REG  -------------------------- */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Pos (0UL)                  /*!< ANAMISC SOC_EXT_OUT_REG: SOC_HIGH_LIM (Bit 0)               */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Msk (0x1UL)                /*!< ANAMISC SOC_EXT_OUT_REG: SOC_HIGH_LIM (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Pos (1UL)               /*!< ANAMISC SOC_EXT_OUT_REG: SOC_LOWLIM_COMP (Bit 1)            */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Msk (0x2UL)             /*!< ANAMISC SOC_EXT_OUT_REG: SOC_LOWLIM_COMP (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Pos (2UL)                  /*!< ANAMISC SOC_EXT_OUT_REG: SOC_POS_COMP (Bit 2)               */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Msk (0x4UL)                /*!< ANAMISC SOC_EXT_OUT_REG: SOC_POS_COMP (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Pos (3UL)               /*!< ANAMISC SOC_EXT_OUT_REG: SOC_RISING_COMP (Bit 3)            */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Msk (0x8UL)             /*!< ANAMISC SOC_EXT_OUT_REG: SOC_RISING_COMP (Bitfield-Mask: 0x01) */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Pos (4UL)                     /*!< ANAMISC SOC_EXT_OUT_REG: SOC_STATE (Bit 4)                  */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Msk (0xf0UL)                  /*!< ANAMISC SOC_EXT_OUT_REG: SOC_STATE (Bitfield-Mask: 0x0f)    */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Pos (8UL)                /*!< ANAMISC SOC_EXT_OUT_REG: SOC_CTRL_EVENT (Bit 8)             */
#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Msk (0x100UL)            /*!< ANAMISC SOC_EXT_OUT_REG: SOC_CTRL_EVENT (Bitfield-Mask: 0x01) */

/* ---------------------------  ANAMISC_CLK_REF_SEL_REG  -------------------------- */
#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL)                   /*!< ANAMISC CLK_REF_SEL_REG: REF_CLK_SEL (Bit 0)                */
#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x3UL)                 /*!< ANAMISC CLK_REF_SEL_REG: REF_CLK_SEL (Bitfield-Mask: 0x03)  */
#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Pos (2UL)                 /*!< ANAMISC CLK_REF_SEL_REG: REF_CAL_START (Bit 2)              */
#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x4UL)               /*!< ANAMISC CLK_REF_SEL_REG: REF_CAL_START (Bitfield-Mask: 0x01) */

/* ---------------------------  ANAMISC_CLK_REF_CNT_REG  -------------------------- */
#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL)                   /*!< ANAMISC CLK_REF_CNT_REG: REF_CNT_VAL (Bit 0)                */
#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL)              /*!< ANAMISC CLK_REF_CNT_REG: REF_CNT_VAL (Bitfield-Mask: 0xffff) */

/* --------------------------  ANAMISC_CLK_REF_VAL_L_REG  ------------------------- */
#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Pos (0UL)                /*!< ANAMISC CLK_REF_VAL_L_REG: XTAL_CNT_VAL (Bit 0)             */
#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Msk (0xffffUL)           /*!< ANAMISC CLK_REF_VAL_L_REG: XTAL_CNT_VAL (Bitfield-Mask: 0xffff) */

/* --------------------------  ANAMISC_CLK_REF_VAL_H_REG  ------------------------- */
#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Pos (0UL)                /*!< ANAMISC CLK_REF_VAL_H_REG: XTAL_CNT_VAL (Bit 0)             */
#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Msk (0xffffUL)           /*!< ANAMISC CLK_REF_VAL_H_REG: XTAL_CNT_VAL (Bitfield-Mask: 0xffff) */


/* ================================================================================ */
/* ================          struct 'APU' Position & Mask          ================ */
/* ================================================================================ */


/* ------------------------------  APU_SRC1_CTRL_REG  ----------------------------- */
#define APU_SRC1_CTRL_REG_SRC_EN_Pos          (0UL)                     /*!< APU SRC1_CTRL_REG: SRC_EN (Bit 0)                           */
#define APU_SRC1_CTRL_REG_SRC_EN_Msk          (0x1UL)                   /*!< APU SRC1_CTRL_REG: SRC_EN (Bitfield-Mask: 0x01)             */
#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos    (1UL)                     /*!< APU SRC1_CTRL_REG: SRC_IN_AMODE (Bit 1)                     */
#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk    (0x2UL)                   /*!< APU SRC1_CTRL_REG: SRC_IN_AMODE (Bitfield-Mask: 0x01)       */
#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)                   /*!< APU SRC1_CTRL_REG: SRC_IN_CAL_BYPASS (Bit 2)                */
#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)                 /*!< APU SRC1_CTRL_REG: SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01)  */
#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos       (4UL)                     /*!< APU SRC1_CTRL_REG: SRC_IN_DS (Bit 4)                        */
#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk       (0x30UL)                  /*!< APU SRC1_CTRL_REG: SRC_IN_DS (Bitfield-Mask: 0x03)          */
#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos       (6UL)                     /*!< APU SRC1_CTRL_REG: SRC_IN_OK (Bit 6)                        */
#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk       (0x40UL)                  /*!< APU SRC1_CTRL_REG: SRC_IN_OK (Bitfield-Mask: 0x01)          */
#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)                  /*!< APU SRC1_CTRL_REG: SRC_DITHER_DISABLE (Bit 7)               */
#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)               /*!< APU SRC1_CTRL_REG: SRC_DITHER_DISABLE (Bitfield-Mask: 0x01) */
#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos   (13UL)                    /*!< APU SRC1_CTRL_REG: SRC_OUT_AMODE (Bit 13)                   */
#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk   (0x2000UL)                /*!< APU SRC1_CTRL_REG: SRC_OUT_AMODE (Bitfield-Mask: 0x01)      */
#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)                 /*!< APU SRC1_CTRL_REG: SRC_OUT_CAL_BYPASS (Bit 14)              */
#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)             /*!< APU SRC1_CTRL_REG: SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01) */
#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos      (16UL)                    /*!< APU SRC1_CTRL_REG: SRC_OUT_US (Bit 16)                      */
#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk      (0x30000UL)               /*!< APU SRC1_CTRL_REG: SRC_OUT_US (Bitfield-Mask: 0x03)         */
#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos      (18UL)                    /*!< APU SRC1_CTRL_REG: SRC_OUT_OK (Bit 18)                      */
#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk      (0x40000UL)               /*!< APU SRC1_CTRL_REG: SRC_OUT_OK (Bitfield-Mask: 0x01)         */
#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos      (19UL)                    /*!< APU SRC1_CTRL_REG: SRC_RESYNC (Bit 19)                      */
#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk      (0x80000UL)               /*!< APU SRC1_CTRL_REG: SRC_RESYNC (Bitfield-Mask: 0x01)         */
#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos   (20UL)                    /*!< APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bit 20)                   */
#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk   (0x100000UL)              /*!< APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bitfield-Mask: 0x01)      */
#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos   (21UL)                    /*!< APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bit 21)                   */
#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk   (0x200000UL)              /*!< APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bitfield-Mask: 0x01)      */
#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos  (22UL)                    /*!< APU SRC1_CTRL_REG: SRC_OUT_OVFLOW (Bit 22)                  */
#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk  (0x400000UL)              /*!< APU SRC1_CTRL_REG: SRC_OUT_OVFLOW (Bitfield-Mask: 0x01)     */
#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos  (23UL)                    /*!< APU SRC1_CTRL_REG: SRC_OUT_UNFLOW (Bit 23)                  */
#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk  (0x800000UL)              /*!< APU SRC1_CTRL_REG: SRC_OUT_UNFLOW (Bitfield-Mask: 0x01)     */
#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos  (24UL)                    /*!< APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bit 24)                  */
#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk  (0x1000000UL)             /*!< APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bitfield-Mask: 0x01)     */
#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)                    /*!< APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bit 25)                 */
#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)             /*!< APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01)    */
#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos  (26UL)                    /*!< APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bit 26)                  */
#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk  (0xc000000UL)             /*!< APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bitfield-Mask: 0x03)     */
#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos    (28UL)                    /*!< APU SRC1_CTRL_REG: SRC_PDM_MODE (Bit 28)                    */
#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk    (0x30000000UL)            /*!< APU SRC1_CTRL_REG: SRC_PDM_MODE (Bitfield-Mask: 0x03)       */
#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos  (30UL)                    /*!< APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bit 30)                  */
#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk  (0xc0000000UL)            /*!< APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bitfield-Mask: 0x03)     */

/* -----------------------------  APU_SRC1_IN_FS_REG  ----------------------------- */
#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos      (0UL)                     /*!< APU SRC1_IN_FS_REG: SRC_IN_FS (Bit 0)                       */
#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk      (0xffffffUL)              /*!< APU SRC1_IN_FS_REG: SRC_IN_FS (Bitfield-Mask: 0xffffff)     */

/* -----------------------------  APU_SRC1_OUT_FS_REG  ---------------------------- */
#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos    (0UL)                     /*!< APU SRC1_OUT_FS_REG: SRC_OUT_FS (Bit 0)                     */
#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk    (0xffffffUL)              /*!< APU SRC1_OUT_FS_REG: SRC_OUT_FS (Bitfield-Mask: 0xffffff)   */

/* ------------------------------  APU_SRC1_IN1_REG  ------------------------------ */
#define APU_SRC1_IN1_REG_SRC_IN_Pos           (8UL)                     /*!< APU SRC1_IN1_REG: SRC_IN (Bit 8)                            */
#define APU_SRC1_IN1_REG_SRC_IN_Msk           (0xffffff00UL)            /*!< APU SRC1_IN1_REG: SRC_IN (Bitfield-Mask: 0xffffff)          */

/* ------------------------------  APU_SRC1_IN2_REG  ------------------------------ */
#define APU_SRC1_IN2_REG_SRC_IN_Pos           (8UL)                     /*!< APU SRC1_IN2_REG: SRC_IN (Bit 8)                            */
#define APU_SRC1_IN2_REG_SRC_IN_Msk           (0xffffff00UL)            /*!< APU SRC1_IN2_REG: SRC_IN (Bitfield-Mask: 0xffffff)          */

/* ------------------------------  APU_SRC1_OUT1_REG  ----------------------------- */
#define APU_SRC1_OUT1_REG_SRC_OUT_Pos         (8UL)                     /*!< APU SRC1_OUT1_REG: SRC_OUT (Bit 8)                          */
#define APU_SRC1_OUT1_REG_SRC_OUT_Msk         (0xffffff00UL)            /*!< APU SRC1_OUT1_REG: SRC_OUT (Bitfield-Mask: 0xffffff)        */

/* ------------------------------  APU_SRC1_OUT2_REG  ----------------------------- */
#define APU_SRC1_OUT2_REG_SRC_OUT_Pos         (8UL)                     /*!< APU SRC1_OUT2_REG: SRC_OUT (Bit 8)                          */
#define APU_SRC1_OUT2_REG_SRC_OUT_Msk         (0xffffff00UL)            /*!< APU SRC1_OUT2_REG: SRC_OUT (Bitfield-Mask: 0xffffff)        */

/* -------------------------------  APU_APU_MUX_REG  ------------------------------ */
#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos       (0UL)                     /*!< APU APU_MUX_REG: SRC1_MUX_IN (Bit 0)                        */
#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk       (0x7UL)                   /*!< APU APU_MUX_REG: SRC1_MUX_IN (Bitfield-Mask: 0x07)          */
#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos       (3UL)                     /*!< APU APU_MUX_REG: PCM1_MUX_IN (Bit 3)                        */
#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk       (0x38UL)                  /*!< APU APU_MUX_REG: PCM1_MUX_IN (Bitfield-Mask: 0x07)          */
#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos       (6UL)                     /*!< APU APU_MUX_REG: PDM1_MUX_IN (Bit 6)                        */
#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk       (0x40UL)                  /*!< APU APU_MUX_REG: PDM1_MUX_IN (Bitfield-Mask: 0x01)          */

/* -----------------------------  APU_COEF10_SET1_REG  ---------------------------- */
#define APU_COEF10_SET1_REG_SRC_COEF0_Pos     (0UL)                     /*!< APU COEF10_SET1_REG: SRC_COEF0 (Bit 0)                      */
#define APU_COEF10_SET1_REG_SRC_COEF0_Msk     (0xffffUL)                /*!< APU COEF10_SET1_REG: SRC_COEF0 (Bitfield-Mask: 0xffff)      */
#define APU_COEF10_SET1_REG_SRC_COEF1_Pos     (16UL)                    /*!< APU COEF10_SET1_REG: SRC_COEF1 (Bit 16)                     */
#define APU_COEF10_SET1_REG_SRC_COEF1_Msk     (0xffff0000UL)            /*!< APU COEF10_SET1_REG: SRC_COEF1 (Bitfield-Mask: 0xffff)      */

/* -----------------------------  APU_COEF32_SET1_REG  ---------------------------- */
#define APU_COEF32_SET1_REG_SRC_COEF2_Pos     (0UL)                     /*!< APU COEF32_SET1_REG: SRC_COEF2 (Bit 0)                      */
#define APU_COEF32_SET1_REG_SRC_COEF2_Msk     (0xffffUL)                /*!< APU COEF32_SET1_REG: SRC_COEF2 (Bitfield-Mask: 0xffff)      */
#define APU_COEF32_SET1_REG_SRC_COEF3_Pos     (16UL)                    /*!< APU COEF32_SET1_REG: SRC_COEF3 (Bit 16)                     */
#define APU_COEF32_SET1_REG_SRC_COEF3_Msk     (0xffff0000UL)            /*!< APU COEF32_SET1_REG: SRC_COEF3 (Bitfield-Mask: 0xffff)      */

/* -----------------------------  APU_COEF54_SET1_REG  ---------------------------- */
#define APU_COEF54_SET1_REG_SRC_COEF4_Pos     (0UL)                     /*!< APU COEF54_SET1_REG: SRC_COEF4 (Bit 0)                      */
#define APU_COEF54_SET1_REG_SRC_COEF4_Msk     (0xffffUL)                /*!< APU COEF54_SET1_REG: SRC_COEF4 (Bitfield-Mask: 0xffff)      */
#define APU_COEF54_SET1_REG_SRC_COEF5_Pos     (16UL)                    /*!< APU COEF54_SET1_REG: SRC_COEF5 (Bit 16)                     */
#define APU_COEF54_SET1_REG_SRC_COEF5_Msk     (0xffff0000UL)            /*!< APU COEF54_SET1_REG: SRC_COEF5 (Bitfield-Mask: 0xffff)      */

/* -----------------------------  APU_COEF76_SET1_REG  ---------------------------- */
#define APU_COEF76_SET1_REG_SRC_COEF6_Pos     (0UL)                     /*!< APU COEF76_SET1_REG: SRC_COEF6 (Bit 0)                      */
#define APU_COEF76_SET1_REG_SRC_COEF6_Msk     (0xffffUL)                /*!< APU COEF76_SET1_REG: SRC_COEF6 (Bitfield-Mask: 0xffff)      */
#define APU_COEF76_SET1_REG_SRC_COEF7_Pos     (16UL)                    /*!< APU COEF76_SET1_REG: SRC_COEF7 (Bit 16)                     */
#define APU_COEF76_SET1_REG_SRC_COEF7_Msk     (0xffff0000UL)            /*!< APU COEF76_SET1_REG: SRC_COEF7 (Bitfield-Mask: 0xffff)      */

/* -----------------------------  APU_COEF98_SET1_REG  ---------------------------- */
#define APU_COEF98_SET1_REG_SRC_COEF8_Pos     (0UL)                     /*!< APU COEF98_SET1_REG: SRC_COEF8 (Bit 0)                      */
#define APU_COEF98_SET1_REG_SRC_COEF8_Msk     (0xffffUL)                /*!< APU COEF98_SET1_REG: SRC_COEF8 (Bitfield-Mask: 0xffff)      */
#define APU_COEF98_SET1_REG_SRC_COEF9_Pos     (16UL)                    /*!< APU COEF98_SET1_REG: SRC_COEF9 (Bit 16)                     */
#define APU_COEF98_SET1_REG_SRC_COEF9_Msk     (0xffff0000UL)            /*!< APU COEF98_SET1_REG: SRC_COEF9 (Bitfield-Mask: 0xffff)      */

/* -----------------------------  APU_COEF0A_SET1_REG  ---------------------------- */
#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos    (0UL)                     /*!< APU COEF0A_SET1_REG: SRC_COEF10 (Bit 0)                     */
#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk    (0xffffUL)                /*!< APU COEF0A_SET1_REG: SRC_COEF10 (Bitfield-Mask: 0xffff)     */

/* ------------------------------  APU_PCM1_CTRL_REG  ----------------------------- */
#define APU_PCM1_CTRL_REG_PCM_EN_Pos          (0UL)                     /*!< APU PCM1_CTRL_REG: PCM_EN (Bit 0)                           */
#define APU_PCM1_CTRL_REG_PCM_EN_Msk          (0x1UL)                   /*!< APU PCM1_CTRL_REG: PCM_EN (Bitfield-Mask: 0x01)             */
#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos      (1UL)                     /*!< APU PCM1_CTRL_REG: PCM_MASTER (Bit 1)                       */
#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk      (0x2UL)                   /*!< APU PCM1_CTRL_REG: PCM_MASTER (Bitfield-Mask: 0x01)         */
#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos      (2UL)                     /*!< APU PCM1_CTRL_REG: PCM_FSCLEN (Bit 2)                       */
#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk      (0x3cUL)                  /*!< APU PCM1_CTRL_REG: PCM_FSCLEN (Bitfield-Mask: 0x0f)         */
#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos      (6UL)                     /*!< APU PCM1_CTRL_REG: PCM_FSCDEL (Bit 6)                       */
#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk      (0x40UL)                  /*!< APU PCM1_CTRL_REG: PCM_FSCDEL (Bitfield-Mask: 0x01)         */
#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos        (7UL)                     /*!< APU PCM1_CTRL_REG: PCM_PPOD (Bit 7)                         */
#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk        (0x80UL)                  /*!< APU PCM1_CTRL_REG: PCM_PPOD (Bitfield-Mask: 0x01)           */
#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos      (8UL)                     /*!< APU PCM1_CTRL_REG: PCM_CLKINV (Bit 8)                       */
#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk      (0x100UL)                 /*!< APU PCM1_CTRL_REG: PCM_CLKINV (Bitfield-Mask: 0x01)         */
#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos      (9UL)                     /*!< APU PCM1_CTRL_REG: PCM_FSCINV (Bit 9)                       */
#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk      (0x200UL)                 /*!< APU PCM1_CTRL_REG: PCM_FSCINV (Bitfield-Mask: 0x01)         */
#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos     (10UL)                    /*!< APU PCM1_CTRL_REG: PCM_CLK_BIT (Bit 10)                     */
#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk     (0x400UL)                 /*!< APU PCM1_CTRL_REG: PCM_CLK_BIT (Bitfield-Mask: 0x01)        */
#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos      (11UL)                    /*!< APU PCM1_CTRL_REG: PCM_CH_DEL (Bit 11)                      */
#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk      (0xf800UL)                /*!< APU PCM1_CTRL_REG: PCM_CH_DEL (Bitfield-Mask: 0x1f)         */
#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos    (16UL)                    /*!< APU PCM1_CTRL_REG: PCM_FSC_EDGE (Bit 16)                    */
#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk    (0x10000UL)               /*!< APU PCM1_CTRL_REG: PCM_FSC_EDGE (Bitfield-Mask: 0x01)       */
#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos     (20UL)                    /*!< APU PCM1_CTRL_REG: PCM_FSC_DIV (Bit 20)                     */
#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk     (0xfff00000UL)            /*!< APU PCM1_CTRL_REG: PCM_FSC_DIV (Bitfield-Mask: 0xfff)       */

/* ------------------------------  APU_PCM1_IN1_REG  ------------------------------ */
#define APU_PCM1_IN1_REG_PCM_IN_Pos           (0UL)                     /*!< APU PCM1_IN1_REG: PCM_IN (Bit 0)                            */
#define APU_PCM1_IN1_REG_PCM_IN_Msk           (0xffffffffUL)            /*!< APU PCM1_IN1_REG: PCM_IN (Bitfield-Mask: 0xffffffff)        */

/* ------------------------------  APU_PCM1_IN2_REG  ------------------------------ */
#define APU_PCM1_IN2_REG_PCM_IN_Pos           (0UL)                     /*!< APU PCM1_IN2_REG: PCM_IN (Bit 0)                            */
#define APU_PCM1_IN2_REG_PCM_IN_Msk           (0xffffffffUL)            /*!< APU PCM1_IN2_REG: PCM_IN (Bitfield-Mask: 0xffffffff)        */

/* ------------------------------  APU_PCM1_OUT1_REG  ----------------------------- */
#define APU_PCM1_OUT1_REG_PCM_OUT_Pos         (0UL)                     /*!< APU PCM1_OUT1_REG: PCM_OUT (Bit 0)                          */
#define APU_PCM1_OUT1_REG_PCM_OUT_Msk         (0xffffffffUL)            /*!< APU PCM1_OUT1_REG: PCM_OUT (Bitfield-Mask: 0xffffffff)      */

/* ------------------------------  APU_PCM1_OUT2_REG  ----------------------------- */
#define APU_PCM1_OUT2_REG_PCM_OUT_Pos         (0UL)                     /*!< APU PCM1_OUT2_REG: PCM_OUT (Bit 0)                          */
#define APU_PCM1_OUT2_REG_PCM_OUT_Msk         (0xffffffffUL)            /*!< APU PCM1_OUT2_REG: PCM_OUT (Bitfield-Mask: 0xffffffff)      */


/* ================================================================================ */
/* ================          struct 'BLE' Position & Mask          ================ */
/* ================================================================================ */


/* ----------------------------  BLE_BLE_RWBLECNTL_REG  --------------------------- */
#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Pos     (0UL)                     /*!< BLE BLE_RWBLECNTL_REG: SYNCERR (Bit 0)                      */
#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Msk     (0x7UL)                   /*!< BLE BLE_RWBLECNTL_REG: SYNCERR (Bitfield-Mask: 0x07)        */
#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Pos  (4UL)                     /*!< BLE BLE_RWBLECNTL_REG: RXWINSZDEF (Bit 4)                   */
#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Msk  (0xf0UL)                  /*!< BLE BLE_RWBLECNTL_REG: RXWINSZDEF (Bitfield-Mask: 0x0f)     */
#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Pos    (8UL)                     /*!< BLE BLE_RWBLECNTL_REG: RWBLE_EN (Bit 8)                     */
#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Msk    (0x100UL)                 /*!< BLE BLE_RWBLECNTL_REG: RWBLE_EN (Bitfield-Mask: 0x01)       */
#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Pos (9UL)                   /*!< BLE BLE_RWBLECNTL_REG: ADVERTFILT_EN (Bit 9)                */
#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Msk (0x200UL)               /*!< BLE BLE_RWBLECNTL_REG: ADVERTFILT_EN (Bitfield-Mask: 0x01)  */
#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Pos   (12UL)                    /*!< BLE BLE_RWBLECNTL_REG: CORR_MODE (Bit 12)                   */
#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Msk   (0x3000UL)                /*!< BLE BLE_RWBLECNTL_REG: CORR_MODE (Bitfield-Mask: 0x03)      */
#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Pos (16UL)                  /*!< BLE BLE_RWBLECNTL_REG: HOP_REMAP_DSB (Bit 16)               */
#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Msk (0x10000UL)             /*!< BLE BLE_RWBLECNTL_REG: HOP_REMAP_DSB (Bitfield-Mask: 0x01)  */
#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Pos     (17UL)                    /*!< BLE BLE_RWBLECNTL_REG: CRC_DSB (Bit 17)                     */
#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Msk     (0x20000UL)               /*!< BLE BLE_RWBLECNTL_REG: CRC_DSB (Bitfield-Mask: 0x01)        */
#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Pos    (18UL)                    /*!< BLE BLE_RWBLECNTL_REG: WHIT_DSB (Bit 18)                    */
#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Msk    (0x40000UL)               /*!< BLE BLE_RWBLECNTL_REG: WHIT_DSB (Bitfield-Mask: 0x01)       */
#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Pos   (19UL)                    /*!< BLE BLE_RWBLECNTL_REG: CRYPT_DSB (Bit 19)                   */
#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Msk   (0x80000UL)               /*!< BLE BLE_RWBLECNTL_REG: CRYPT_DSB (Bitfield-Mask: 0x01)      */
#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Pos    (20UL)                    /*!< BLE BLE_RWBLECNTL_REG: NESN_DSB (Bit 20)                    */
#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Msk    (0x100000UL)              /*!< BLE BLE_RWBLECNTL_REG: NESN_DSB (Bitfield-Mask: 0x01)       */
#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Pos      (21UL)                    /*!< BLE BLE_RWBLECNTL_REG: SN_DSB (Bit 21)                      */
#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Msk      (0x200000UL)              /*!< BLE BLE_RWBLECNTL_REG: SN_DSB (Bitfield-Mask: 0x01)         */
#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Pos      (22UL)                    /*!< BLE BLE_RWBLECNTL_REG: MD_DSB (Bit 22)                      */
#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Msk      (0x400000UL)              /*!< BLE BLE_RWBLECNTL_REG: MD_DSB (Bitfield-Mask: 0x01)         */
#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Pos  (24UL)                    /*!< BLE BLE_RWBLECNTL_REG: SCAN_ABORT (Bit 24)                  */
#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Msk  (0x1000000UL)             /*!< BLE BLE_RWBLECNTL_REG: SCAN_ABORT (Bitfield-Mask: 0x01)     */
#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Pos (25UL)                   /*!< BLE BLE_RWBLECNTL_REG: ADVERT_ABORT (Bit 25)                */
#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Msk (0x2000000UL)            /*!< BLE BLE_RWBLECNTL_REG: ADVERT_ABORT (Bitfield-Mask: 0x01)   */
#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Pos (26UL)                   /*!< BLE BLE_RWBLECNTL_REG: RFTEST_ABORT (Bit 26)                */
#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Msk (0x4000000UL)            /*!< BLE BLE_RWBLECNTL_REG: RFTEST_ABORT (Bitfield-Mask: 0x01)   */
#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Pos   (28UL)                    /*!< BLE BLE_RWBLECNTL_REG: SWINT_REQ (Bit 28)                   */
#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Msk   (0x10000000UL)            /*!< BLE BLE_RWBLECNTL_REG: SWINT_REQ (Bitfield-Mask: 0x01)      */
#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Pos (29UL)                   /*!< BLE BLE_RWBLECNTL_REG: REG_SOFT_RST (Bit 29)                */
#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Msk (0x20000000UL)           /*!< BLE BLE_RWBLECNTL_REG: REG_SOFT_RST (Bitfield-Mask: 0x01)   */
#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Pos (30UL)              /*!< BLE BLE_RWBLECNTL_REG: MASTER_TGSOFT_RST (Bit 30)           */
#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Msk (0x40000000UL)      /*!< BLE BLE_RWBLECNTL_REG: MASTER_TGSOFT_RST (Bitfield-Mask: 0x01) */
#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Pos (31UL)                /*!< BLE BLE_RWBLECNTL_REG: MASTER_SOFT_RST (Bit 31)             */
#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Msk (0x80000000UL)        /*!< BLE BLE_RWBLECNTL_REG: MASTER_SOFT_RST (Bitfield-Mask: 0x01) */

/* -----------------------------  BLE_BLE_VERSION_REG  ---------------------------- */
#define BLE_BLE_VERSION_REG_BUILD_Pos         (0UL)                     /*!< BLE BLE_VERSION_REG: BUILD (Bit 0)                          */
#define BLE_BLE_VERSION_REG_BUILD_Msk         (0xffUL)                  /*!< BLE BLE_VERSION_REG: BUILD (Bitfield-Mask: 0xff)            */
#define BLE_BLE_VERSION_REG_UPG_Pos           (8UL)                     /*!< BLE BLE_VERSION_REG: UPG (Bit 8)                            */
#define BLE_BLE_VERSION_REG_UPG_Msk           (0xff00UL)                /*!< BLE BLE_VERSION_REG: UPG (Bitfield-Mask: 0xff)              */
#define BLE_BLE_VERSION_REG_REL_Pos           (16UL)                    /*!< BLE BLE_VERSION_REG: REL (Bit 16)                           */
#define BLE_BLE_VERSION_REG_REL_Msk           (0xff0000UL)              /*!< BLE BLE_VERSION_REG: REL (Bitfield-Mask: 0xff)              */
#define BLE_BLE_VERSION_REG_TYP_Pos           (24UL)                    /*!< BLE BLE_VERSION_REG: TYP (Bit 24)                           */
#define BLE_BLE_VERSION_REG_TYP_Msk           (0xff000000UL)            /*!< BLE BLE_VERSION_REG: TYP (Bitfield-Mask: 0xff)              */

/* ----------------------------  BLE_BLE_RWBLECONF_REG  --------------------------- */
#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Pos    (0UL)                     /*!< BLE BLE_RWBLECONF_REG: BUSWIDTH (Bit 0)                     */
#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Msk    (0x1UL)                   /*!< BLE BLE_RWBLECONF_REG: BUSWIDTH (Bitfield-Mask: 0x01)       */
#define BLE_BLE_RWBLECONF_REG_USECRYPT_Pos    (1UL)                     /*!< BLE BLE_RWBLECONF_REG: USECRYPT (Bit 1)                     */
#define BLE_BLE_RWBLECONF_REG_USECRYPT_Msk    (0x2UL)                   /*!< BLE BLE_RWBLECONF_REG: USECRYPT (Bitfield-Mask: 0x01)       */
#define BLE_BLE_RWBLECONF_REG_USEDBG_Pos      (2UL)                     /*!< BLE BLE_RWBLECONF_REG: USEDBG (Bit 2)                       */
#define BLE_BLE_RWBLECONF_REG_USEDBG_Msk      (0x4UL)                   /*!< BLE BLE_RWBLECONF_REG: USEDBG (Bitfield-Mask: 0x01)         */
#define BLE_BLE_RWBLECONF_REG_COEX_Pos        (3UL)                     /*!< BLE BLE_RWBLECONF_REG: COEX (Bit 3)                         */
#define BLE_BLE_RWBLECONF_REG_COEX_Msk        (0x8UL)                   /*!< BLE BLE_RWBLECONF_REG: COEX (Bitfield-Mask: 0x01)           */
#define BLE_BLE_RWBLECONF_REG_INTMODE_Pos     (4UL)                     /*!< BLE BLE_RWBLECONF_REG: INTMODE (Bit 4)                      */
#define BLE_BLE_RWBLECONF_REG_INTMODE_Msk     (0x10UL)                  /*!< BLE BLE_RWBLECONF_REG: INTMODE (Bitfield-Mask: 0x01)        */
#define BLE_BLE_RWBLECONF_REG_DMMODE_Pos      (5UL)                     /*!< BLE BLE_RWBLECONF_REG: DMMODE (Bit 5)                       */
#define BLE_BLE_RWBLECONF_REG_DMMODE_Msk      (0x20UL)                  /*!< BLE BLE_RWBLECONF_REG: DMMODE (Bitfield-Mask: 0x01)         */
#define BLE_BLE_RWBLECONF_REG_DECIPHER_Pos    (6UL)                     /*!< BLE BLE_RWBLECONF_REG: DECIPHER (Bit 6)                     */
#define BLE_BLE_RWBLECONF_REG_DECIPHER_Msk    (0x40UL)                  /*!< BLE BLE_RWBLECONF_REG: DECIPHER (Bitfield-Mask: 0x01)       */
#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Pos     (8UL)                     /*!< BLE BLE_RWBLECONF_REG: CLK_SEL (Bit 8)                      */
#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Msk     (0x3f00UL)                /*!< BLE BLE_RWBLECONF_REG: CLK_SEL (Bitfield-Mask: 0x3f)        */
#define BLE_BLE_RWBLECONF_REG_RFIF_Pos        (16UL)                    /*!< BLE BLE_RWBLECONF_REG: RFIF (Bit 16)                        */
#define BLE_BLE_RWBLECONF_REG_RFIF_Msk        (0x7f0000UL)              /*!< BLE BLE_RWBLECONF_REG: RFIF (Bitfield-Mask: 0x7f)           */
#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Pos   (24UL)                    /*!< BLE BLE_RWBLECONF_REG: ADD_WIDTH (Bit 24)                   */
#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Msk   (0x3f000000UL)            /*!< BLE BLE_RWBLECONF_REG: ADD_WIDTH (Bitfield-Mask: 0x3f)      */

/* -----------------------------  BLE_BLE_INTCNTL_REG  ---------------------------- */
#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Pos   (0UL)                     /*!< BLE BLE_INTCNTL_REG: CSCNTINTMSK (Bit 0)                    */
#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Msk   (0x1UL)                   /*!< BLE BLE_INTCNTL_REG: CSCNTINTMSK (Bitfield-Mask: 0x01)      */
#define BLE_BLE_INTCNTL_REG_RXINTMSK_Pos      (1UL)                     /*!< BLE BLE_INTCNTL_REG: RXINTMSK (Bit 1)                       */
#define BLE_BLE_INTCNTL_REG_RXINTMSK_Msk      (0x2UL)                   /*!< BLE BLE_INTCNTL_REG: RXINTMSK (Bitfield-Mask: 0x01)         */
#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Pos     (2UL)                     /*!< BLE BLE_INTCNTL_REG: SLPINTMSK (Bit 2)                      */
#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Msk     (0x4UL)                   /*!< BLE BLE_INTCNTL_REG: SLPINTMSK (Bitfield-Mask: 0x01)        */
#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Pos   (3UL)                     /*!< BLE BLE_INTCNTL_REG: EVENTINTMSK (Bit 3)                    */
#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Msk   (0x8UL)                   /*!< BLE BLE_INTCNTL_REG: EVENTINTMSK (Bitfield-Mask: 0x01)      */
#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Pos   (4UL)                     /*!< BLE BLE_INTCNTL_REG: CRYPTINTMSK (Bit 4)                    */
#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Msk   (0x10UL)                  /*!< BLE BLE_INTCNTL_REG: CRYPTINTMSK (Bitfield-Mask: 0x01)      */
#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Pos   (5UL)                     /*!< BLE BLE_INTCNTL_REG: ERRORINTMSK (Bit 5)                    */
#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Msk   (0x20UL)                  /*!< BLE BLE_INTCNTL_REG: ERRORINTMSK (Bitfield-Mask: 0x01)      */
#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Pos (6UL)                  /*!< BLE BLE_INTCNTL_REG: GROSSTGTIMINTMSK (Bit 6)               */
#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Msk (0x40UL)               /*!< BLE BLE_INTCNTL_REG: GROSSTGTIMINTMSK (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Pos (7UL)                   /*!< BLE BLE_INTCNTL_REG: FINETGTIMINTMSK (Bit 7)                */
#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Msk (0x80UL)                /*!< BLE BLE_INTCNTL_REG: FINETGTIMINTMSK (Bitfield-Mask: 0x01)  */
#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Pos (8UL)                   /*!< BLE BLE_INTCNTL_REG: EVENTAPFAINTMSK (Bit 8)                */
#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Msk (0x100UL)               /*!< BLE BLE_INTCNTL_REG: EVENTAPFAINTMSK (Bitfield-Mask: 0x01)  */
#define BLE_BLE_INTCNTL_REG_SWINTMSK_Pos      (9UL)                     /*!< BLE BLE_INTCNTL_REG: SWINTMSK (Bit 9)                       */
#define BLE_BLE_INTCNTL_REG_SWINTMSK_Msk      (0x200UL)                 /*!< BLE BLE_INTCNTL_REG: SWINTMSK (Bitfield-Mask: 0x01)         */
#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Pos   (15UL)                    /*!< BLE BLE_INTCNTL_REG: CSCNTDEVMSK (Bit 15)                   */
#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Msk   (0x8000UL)                /*!< BLE BLE_INTCNTL_REG: CSCNTDEVMSK (Bitfield-Mask: 0x01)      */

/* -----------------------------  BLE_BLE_INTSTAT_REG  ---------------------------- */
#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Pos  (0UL)                     /*!< BLE BLE_INTSTAT_REG: CSCNTINTSTAT (Bit 0)                   */
#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Msk  (0x1UL)                   /*!< BLE BLE_INTSTAT_REG: CSCNTINTSTAT (Bitfield-Mask: 0x01)     */
#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Pos     (1UL)                     /*!< BLE BLE_INTSTAT_REG: RXINTSTAT (Bit 1)                      */
#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Msk     (0x2UL)                   /*!< BLE BLE_INTSTAT_REG: RXINTSTAT (Bitfield-Mask: 0x01)        */
#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Pos    (2UL)                     /*!< BLE BLE_INTSTAT_REG: SLPINTSTAT (Bit 2)                     */
#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Msk    (0x4UL)                   /*!< BLE BLE_INTSTAT_REG: SLPINTSTAT (Bitfield-Mask: 0x01)       */
#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Pos  (3UL)                     /*!< BLE BLE_INTSTAT_REG: EVENTINTSTAT (Bit 3)                   */
#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Msk  (0x8UL)                   /*!< BLE BLE_INTSTAT_REG: EVENTINTSTAT (Bitfield-Mask: 0x01)     */
#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Pos  (4UL)                     /*!< BLE BLE_INTSTAT_REG: CRYPTINTSTAT (Bit 4)                   */
#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Msk  (0x10UL)                  /*!< BLE BLE_INTSTAT_REG: CRYPTINTSTAT (Bitfield-Mask: 0x01)     */
#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Pos  (5UL)                     /*!< BLE BLE_INTSTAT_REG: ERRORINTSTAT (Bit 5)                   */
#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Msk  (0x20UL)                  /*!< BLE BLE_INTSTAT_REG: ERRORINTSTAT (Bitfield-Mask: 0x01)     */
#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Pos (6UL)                 /*!< BLE BLE_INTSTAT_REG: GROSSTGTIMINTSTAT (Bit 6)              */
#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Msk (0x40UL)              /*!< BLE BLE_INTSTAT_REG: GROSSTGTIMINTSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Pos (7UL)                  /*!< BLE BLE_INTSTAT_REG: FINETGTIMINTSTAT (Bit 7)               */
#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Msk (0x80UL)               /*!< BLE BLE_INTSTAT_REG: FINETGTIMINTSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Pos (8UL)                  /*!< BLE BLE_INTSTAT_REG: EVENTAPFAINTSTAT (Bit 8)               */
#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Msk (0x100UL)              /*!< BLE BLE_INTSTAT_REG: EVENTAPFAINTSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Pos     (9UL)                     /*!< BLE BLE_INTSTAT_REG: SWINTSTAT (Bit 9)                      */
#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Msk     (0x200UL)                 /*!< BLE BLE_INTSTAT_REG: SWINTSTAT (Bitfield-Mask: 0x01)        */

/* ---------------------------  BLE_BLE_INTRAWSTAT_REG  --------------------------- */
#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Pos (0UL)                /*!< BLE BLE_INTRAWSTAT_REG: CSCNTINTRAWSTAT (Bit 0)             */
#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Msk (0x1UL)              /*!< BLE BLE_INTRAWSTAT_REG: CSCNTINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Pos (1UL)                   /*!< BLE BLE_INTRAWSTAT_REG: RXINTRAWSTAT (Bit 1)                */
#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Msk (0x2UL)                 /*!< BLE BLE_INTRAWSTAT_REG: RXINTRAWSTAT (Bitfield-Mask: 0x01)  */
#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Pos (2UL)                  /*!< BLE BLE_INTRAWSTAT_REG: SLPINTRAWSTAT (Bit 2)               */
#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Msk (0x4UL)                /*!< BLE BLE_INTRAWSTAT_REG: SLPINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Pos (3UL)                /*!< BLE BLE_INTRAWSTAT_REG: EVENTINTRAWSTAT (Bit 3)             */
#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Msk (0x8UL)              /*!< BLE BLE_INTRAWSTAT_REG: EVENTINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Pos (4UL)                /*!< BLE BLE_INTRAWSTAT_REG: CRYPTINTRAWSTAT (Bit 4)             */
#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Msk (0x10UL)             /*!< BLE BLE_INTRAWSTAT_REG: CRYPTINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Pos (5UL)                /*!< BLE BLE_INTRAWSTAT_REG: ERRORINTRAWSTAT (Bit 5)             */
#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Msk (0x20UL)             /*!< BLE BLE_INTRAWSTAT_REG: ERRORINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Pos (6UL)           /*!< BLE BLE_INTRAWSTAT_REG: GROSSTGTIMINTRAWSTAT (Bit 6)        */
#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Msk (0x40UL)        /*!< BLE BLE_INTRAWSTAT_REG: GROSSTGTIMINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Pos (7UL)            /*!< BLE BLE_INTRAWSTAT_REG: FINETGTIMINTRAWSTAT (Bit 7)         */
#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Msk (0x80UL)         /*!< BLE BLE_INTRAWSTAT_REG: FINETGTIMINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Pos (8UL)            /*!< BLE BLE_INTRAWSTAT_REG: EVENTAPFAINTRAWSTAT (Bit 8)         */
#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Msk (0x100UL)        /*!< BLE BLE_INTRAWSTAT_REG: EVENTAPFAINTRAWSTAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Pos (9UL)                   /*!< BLE BLE_INTRAWSTAT_REG: SWINTRAWSTAT (Bit 9)                */
#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Msk (0x200UL)               /*!< BLE BLE_INTRAWSTAT_REG: SWINTRAWSTAT (Bitfield-Mask: 0x01)  */

/* -----------------------------  BLE_BLE_INTACK_REG  ----------------------------- */
#define BLE_BLE_INTACK_REG_CSCNTINTACK_Pos    (0UL)                     /*!< BLE BLE_INTACK_REG: CSCNTINTACK (Bit 0)                     */
#define BLE_BLE_INTACK_REG_CSCNTINTACK_Msk    (0x1UL)                   /*!< BLE BLE_INTACK_REG: CSCNTINTACK (Bitfield-Mask: 0x01)       */
#define BLE_BLE_INTACK_REG_RXINTACK_Pos       (1UL)                     /*!< BLE BLE_INTACK_REG: RXINTACK (Bit 1)                        */
#define BLE_BLE_INTACK_REG_RXINTACK_Msk       (0x2UL)                   /*!< BLE BLE_INTACK_REG: RXINTACK (Bitfield-Mask: 0x01)          */
#define BLE_BLE_INTACK_REG_SLPINTACK_Pos      (2UL)                     /*!< BLE BLE_INTACK_REG: SLPINTACK (Bit 2)                       */
#define BLE_BLE_INTACK_REG_SLPINTACK_Msk      (0x4UL)                   /*!< BLE BLE_INTACK_REG: SLPINTACK (Bitfield-Mask: 0x01)         */
#define BLE_BLE_INTACK_REG_EVENTINTACK_Pos    (3UL)                     /*!< BLE BLE_INTACK_REG: EVENTINTACK (Bit 3)                     */
#define BLE_BLE_INTACK_REG_EVENTINTACK_Msk    (0x8UL)                   /*!< BLE BLE_INTACK_REG: EVENTINTACK (Bitfield-Mask: 0x01)       */
#define BLE_BLE_INTACK_REG_CRYPTINTACK_Pos    (4UL)                     /*!< BLE BLE_INTACK_REG: CRYPTINTACK (Bit 4)                     */
#define BLE_BLE_INTACK_REG_CRYPTINTACK_Msk    (0x10UL)                  /*!< BLE BLE_INTACK_REG: CRYPTINTACK (Bitfield-Mask: 0x01)       */
#define BLE_BLE_INTACK_REG_ERRORINTACK_Pos    (5UL)                     /*!< BLE BLE_INTACK_REG: ERRORINTACK (Bit 5)                     */
#define BLE_BLE_INTACK_REG_ERRORINTACK_Msk    (0x20UL)                  /*!< BLE BLE_INTACK_REG: ERRORINTACK (Bitfield-Mask: 0x01)       */
#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Pos (6UL)                   /*!< BLE BLE_INTACK_REG: GROSSTGTIMINTACK (Bit 6)                */
#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Msk (0x40UL)                /*!< BLE BLE_INTACK_REG: GROSSTGTIMINTACK (Bitfield-Mask: 0x01)  */
#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Pos (7UL)                    /*!< BLE BLE_INTACK_REG: FINETGTIMINTACK (Bit 7)                 */
#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Msk (0x80UL)                 /*!< BLE BLE_INTACK_REG: FINETGTIMINTACK (Bitfield-Mask: 0x01)   */
#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Pos (8UL)                    /*!< BLE BLE_INTACK_REG: EVENTAPFAINTACK (Bit 8)                 */
#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Msk (0x100UL)                /*!< BLE BLE_INTACK_REG: EVENTAPFAINTACK (Bitfield-Mask: 0x01)   */
#define BLE_BLE_INTACK_REG_SWINTACK_Pos       (9UL)                     /*!< BLE BLE_INTACK_REG: SWINTACK (Bit 9)                        */
#define BLE_BLE_INTACK_REG_SWINTACK_Msk       (0x200UL)                 /*!< BLE BLE_INTACK_REG: SWINTACK (Bitfield-Mask: 0x01)          */

/* ---------------------------  BLE_BLE_BASETIMECNT_REG  -------------------------- */
#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Pos (0UL)                   /*!< BLE BLE_BASETIMECNT_REG: BASETIMECNT (Bit 0)                */
#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Msk (0x7ffffffUL)           /*!< BLE BLE_BASETIMECNT_REG: BASETIMECNT (Bitfield-Mask: 0x7ffffff) */

/* ---------------------------  BLE_BLE_FINETIMECNT_REG  -------------------------- */
#define BLE_BLE_FINETIMECNT_REG_FINECNT_Pos   (0UL)                     /*!< BLE BLE_FINETIMECNT_REG: FINECNT (Bit 0)                    */
#define BLE_BLE_FINETIMECNT_REG_FINECNT_Msk   (0x3ffUL)                 /*!< BLE BLE_FINETIMECNT_REG: FINECNT (Bitfield-Mask: 0x3ff)     */

/* -----------------------------  BLE_BLE_BDADDRL_REG  ---------------------------- */
#define BLE_BLE_BDADDRL_REG_BDADDRL_Pos       (0UL)                     /*!< BLE BLE_BDADDRL_REG: BDADDRL (Bit 0)                        */
#define BLE_BLE_BDADDRL_REG_BDADDRL_Msk       (0xffffffffUL)            /*!< BLE BLE_BDADDRL_REG: BDADDRL (Bitfield-Mask: 0xffffffff)    */

/* -----------------------------  BLE_BLE_BDADDRU_REG  ---------------------------- */
#define BLE_BLE_BDADDRU_REG_BDADDRU_Pos       (0UL)                     /*!< BLE BLE_BDADDRU_REG: BDADDRU (Bit 0)                        */
#define BLE_BLE_BDADDRU_REG_BDADDRU_Msk       (0xffffUL)                /*!< BLE BLE_BDADDRU_REG: BDADDRU (Bitfield-Mask: 0xffff)        */
#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Pos     (16UL)                    /*!< BLE BLE_BDADDRU_REG: PRIV_NPUB (Bit 16)                     */
#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Msk     (0x10000UL)               /*!< BLE BLE_BDADDRU_REG: PRIV_NPUB (Bitfield-Mask: 0x01)        */

/* ------------------------  BLE_BLE_CURRENTRXDESCPTR_REG  ------------------------ */
#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Pos (0UL)         /*!< BLE BLE_CURRENTRXDESCPTR_REG: CURRENTRXDESCPTR (Bit 0)      */
#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Msk (0x7fffUL)    /*!< BLE BLE_CURRENTRXDESCPTR_REG: CURRENTRXDESCPTR (Bitfield-Mask: 0x7fff) */
#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Pos (16UL)                   /*!< BLE BLE_CURRENTRXDESCPTR_REG: ETPTR (Bit 16)                */
#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Msk (0xffff0000UL)           /*!< BLE BLE_CURRENTRXDESCPTR_REG: ETPTR (Bitfield-Mask: 0xffff) */

/* ---------------------------  BLE_BLE_DEEPSLCNTL_REG  --------------------------- */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Pos (0UL)              /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_IRQ_EN (Bit 0)           */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Msk (0x3UL)            /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_IRQ_EN (Bitfield-Mask: 0x03) */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Pos (2UL)                  /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_ON (Bit 2)               */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Msk (0x4UL)                /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_ON (Bitfield-Mask: 0x01) */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Pos (3UL)             /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_CORR_EN (Bit 3)          */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Msk (0x8UL)           /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_CORR_EN (Bitfield-Mask: 0x01) */
#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Pos (4UL)                /*!< BLE BLE_DEEPSLCNTL_REG: SOFT_WAKEUP_REQ (Bit 4)             */
#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Msk (0x10UL)             /*!< BLE BLE_DEEPSLCNTL_REG: SOFT_WAKEUP_REQ (Bitfield-Mask: 0x01) */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Pos (15UL)               /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_STAT (Bit 15)            */
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Msk (0x8000UL)           /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_STAT (Bitfield-Mask: 0x01) */
#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Pos (31UL)                    /*!< BLE BLE_DEEPSLCNTL_REG: EXTWKUPDSB (Bit 31)                 */
#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Msk (0x80000000UL)            /*!< BLE BLE_DEEPSLCNTL_REG: EXTWKUPDSB (Bitfield-Mask: 0x01)    */

/* ---------------------------  BLE_BLE_DEEPSLWKUP_REG  --------------------------- */
#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Pos (0UL)                     /*!< BLE BLE_DEEPSLWKUP_REG: DEEPSLTIME (Bit 0)                  */
#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Msk (0xffffffffUL)            /*!< BLE BLE_DEEPSLWKUP_REG: DEEPSLTIME (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  BLE_BLE_DEEPSLSTAT_REG  --------------------------- */
#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Pos  (0UL)                     /*!< BLE BLE_DEEPSLSTAT_REG: DEEPSLDUR (Bit 0)                   */
#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Msk  (0xffffffffUL)            /*!< BLE BLE_DEEPSLSTAT_REG: DEEPSLDUR (Bitfield-Mask: 0xffffffff) */

/* ----------------------------  BLE_BLE_ENBPRESET_REG  --------------------------- */
#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Pos (0UL)                     /*!< BLE BLE_ENBPRESET_REG: TWIRQ_RESET (Bit 0)                  */
#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Msk (0x3ffUL)                 /*!< BLE BLE_ENBPRESET_REG: TWIRQ_RESET (Bitfield-Mask: 0x3ff)   */
#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Pos   (10UL)                    /*!< BLE BLE_ENBPRESET_REG: TWIRQ_SET (Bit 10)                   */
#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Msk   (0x1ffc00UL)              /*!< BLE BLE_ENBPRESET_REG: TWIRQ_SET (Bitfield-Mask: 0x7ff)     */
#define BLE_BLE_ENBPRESET_REG_TWEXT_Pos       (21UL)                    /*!< BLE BLE_ENBPRESET_REG: TWEXT (Bit 21)                       */
#define BLE_BLE_ENBPRESET_REG_TWEXT_Msk       (0xffe00000UL)            /*!< BLE BLE_ENBPRESET_REG: TWEXT (Bitfield-Mask: 0x7ff)         */

/* ---------------------------  BLE_BLE_FINECNTCORR_REG  -------------------------- */
#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Pos (0UL)                   /*!< BLE BLE_FINECNTCORR_REG: FINECNTCORR (Bit 0)                */
#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Msk (0x3ffUL)               /*!< BLE BLE_FINECNTCORR_REG: FINECNTCORR (Bitfield-Mask: 0x3ff) */

/* -------------------------  BLE_BLE_BASETIMECNTCORR_REG  ------------------------ */
#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Pos (0UL)           /*!< BLE BLE_BASETIMECNTCORR_REG: BASETIMECNTCORR (Bit 0)        */
#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Msk (0x7ffffffUL)   /*!< BLE BLE_BASETIMECNTCORR_REG: BASETIMECNTCORR (Bitfield-Mask: 0x7ffffff) */

/* ----------------------------  BLE_BLE_DIAGCNTL_REG  ---------------------------- */
#define BLE_BLE_DIAGCNTL_REG_DIAG0_Pos        (0UL)                     /*!< BLE BLE_DIAGCNTL_REG: DIAG0 (Bit 0)                         */
#define BLE_BLE_DIAGCNTL_REG_DIAG0_Msk        (0x3fUL)                  /*!< BLE BLE_DIAGCNTL_REG: DIAG0 (Bitfield-Mask: 0x3f)           */
#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Pos     (7UL)                     /*!< BLE BLE_DIAGCNTL_REG: DIAG0_EN (Bit 7)                      */
#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Msk     (0x80UL)                  /*!< BLE BLE_DIAGCNTL_REG: DIAG0_EN (Bitfield-Mask: 0x01)        */
#define BLE_BLE_DIAGCNTL_REG_DIAG1_Pos        (8UL)                     /*!< BLE BLE_DIAGCNTL_REG: DIAG1 (Bit 8)                         */
#define BLE_BLE_DIAGCNTL_REG_DIAG1_Msk        (0x3f00UL)                /*!< BLE BLE_DIAGCNTL_REG: DIAG1 (Bitfield-Mask: 0x3f)           */
#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Pos     (15UL)                    /*!< BLE BLE_DIAGCNTL_REG: DIAG1_EN (Bit 15)                     */
#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Msk     (0x8000UL)                /*!< BLE BLE_DIAGCNTL_REG: DIAG1_EN (Bitfield-Mask: 0x01)        */
#define BLE_BLE_DIAGCNTL_REG_DIAG2_Pos        (16UL)                    /*!< BLE BLE_DIAGCNTL_REG: DIAG2 (Bit 16)                        */
#define BLE_BLE_DIAGCNTL_REG_DIAG2_Msk        (0x3f0000UL)              /*!< BLE BLE_DIAGCNTL_REG: DIAG2 (Bitfield-Mask: 0x3f)           */
#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Pos     (23UL)                    /*!< BLE BLE_DIAGCNTL_REG: DIAG2_EN (Bit 23)                     */
#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Msk     (0x800000UL)              /*!< BLE BLE_DIAGCNTL_REG: DIAG2_EN (Bitfield-Mask: 0x01)        */
#define BLE_BLE_DIAGCNTL_REG_DIAG3_Pos        (24UL)                    /*!< BLE BLE_DIAGCNTL_REG: DIAG3 (Bit 24)                        */
#define BLE_BLE_DIAGCNTL_REG_DIAG3_Msk        (0x3f000000UL)            /*!< BLE BLE_DIAGCNTL_REG: DIAG3 (Bitfield-Mask: 0x3f)           */
#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Pos     (31UL)                    /*!< BLE BLE_DIAGCNTL_REG: DIAG3_EN (Bit 31)                     */
#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Msk     (0x80000000UL)            /*!< BLE BLE_DIAGCNTL_REG: DIAG3_EN (Bitfield-Mask: 0x01)        */

/* ----------------------------  BLE_BLE_DIAGSTAT_REG  ---------------------------- */
#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Pos    (0UL)                     /*!< BLE BLE_DIAGSTAT_REG: DIAG0STAT (Bit 0)                     */
#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Msk    (0xffUL)                  /*!< BLE BLE_DIAGSTAT_REG: DIAG0STAT (Bitfield-Mask: 0xff)       */
#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Pos    (8UL)                     /*!< BLE BLE_DIAGSTAT_REG: DIAG1STAT (Bit 8)                     */
#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Msk    (0xff00UL)                /*!< BLE BLE_DIAGSTAT_REG: DIAG1STAT (Bitfield-Mask: 0xff)       */
#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Pos    (16UL)                    /*!< BLE BLE_DIAGSTAT_REG: DIAG2STAT (Bit 16)                    */
#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Msk    (0xff0000UL)              /*!< BLE BLE_DIAGSTAT_REG: DIAG2STAT (Bitfield-Mask: 0xff)       */
#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Pos    (24UL)                    /*!< BLE BLE_DIAGSTAT_REG: DIAG3STAT (Bit 24)                    */
#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Msk    (0xff000000UL)            /*!< BLE BLE_DIAGSTAT_REG: DIAG3STAT (Bitfield-Mask: 0xff)       */

/* ---------------------------  BLE_BLE_DEBUGADDMAX_REG  -------------------------- */
#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Pos (0UL)                     /*!< BLE BLE_DEBUGADDMAX_REG: EM_ADDMAX (Bit 0)                  */
#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Msk (0xffffUL)                /*!< BLE BLE_DEBUGADDMAX_REG: EM_ADDMAX (Bitfield-Mask: 0xffff)  */
#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Pos (16UL)                   /*!< BLE BLE_DEBUGADDMAX_REG: REG_ADDMAX (Bit 16)                */
#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Msk (0xffff0000UL)           /*!< BLE BLE_DEBUGADDMAX_REG: REG_ADDMAX (Bitfield-Mask: 0xffff) */

/* ---------------------------  BLE_BLE_DEBUGADDMIN_REG  -------------------------- */
#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Pos (0UL)                     /*!< BLE BLE_DEBUGADDMIN_REG: EM_ADDMIN (Bit 0)                  */
#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Msk (0xffffUL)                /*!< BLE BLE_DEBUGADDMIN_REG: EM_ADDMIN (Bitfield-Mask: 0xffff)  */
#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Pos (16UL)                   /*!< BLE BLE_DEBUGADDMIN_REG: REG_ADDMIN (Bit 16)                */
#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Msk (0xffff0000UL)           /*!< BLE BLE_DEBUGADDMIN_REG: REG_ADDMIN (Bitfield-Mask: 0xffff) */

/* --------------------------  BLE_BLE_ERRORTYPESTAT_REG  ------------------------- */
#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Pos (0UL)               /*!< BLE BLE_ERRORTYPESTAT_REG: TXCRYPT_ERROR (Bit 0)            */
#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Msk (0x1UL)             /*!< BLE BLE_ERRORTYPESTAT_REG: TXCRYPT_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Pos (1UL)               /*!< BLE BLE_ERRORTYPESTAT_REG: RXCRYPT_ERROR (Bit 1)            */
#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Msk (0x2UL)             /*!< BLE BLE_ERRORTYPESTAT_REG: RXCRYPT_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Pos (2UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: PKTCNTL_EMACC_ERROR (Bit 2)      */
#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Msk (0x4UL)       /*!< BLE BLE_ERRORTYPESTAT_REG: PKTCNTL_EMACC_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Pos (3UL)           /*!< BLE BLE_ERRORTYPESTAT_REG: RADIO_EMACC_ERROR (Bit 3)        */
#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Msk (0x8UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: RADIO_EMACC_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Pos (4UL)       /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_EMACC_ERROR (Bit 4)    */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Msk (0x10UL)    /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_EMACC_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Pos (5UL)       /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_ENTRY_ERROR (Bit 5)    */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Msk (0x20UL)    /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_ENTRY_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Pos (6UL)        /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_APFM_ERROR (Bit 6)     */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Msk (0x40UL)     /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_APFM_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Pos (7UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_CNTL_APFM_ERROR (Bit 7)      */
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Msk (0x80UL)      /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_CNTL_APFM_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Pos (8UL)             /*!< BLE BLE_ERRORTYPESTAT_REG: WHITELIST_ERROR (Bit 8)          */
#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Msk (0x100UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: WHITELIST_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Pos (9UL)                /*!< BLE BLE_ERRORTYPESTAT_REG: IFS_UNDERRUN (Bit 9)             */
#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Msk (0x200UL)            /*!< BLE BLE_ERRORTYPESTAT_REG: IFS_UNDERRUN (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Pos (10UL)               /*!< BLE BLE_ERRORTYPESTAT_REG: ADV_UNDERRUN (Bit 10)            */
#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Msk (0x400UL)            /*!< BLE BLE_ERRORTYPESTAT_REG: ADV_UNDERRUN (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Pos (11UL)              /*!< BLE BLE_ERRORTYPESTAT_REG: LLCHMAP_ERROR (Bit 11)           */
#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Msk (0x800UL)           /*!< BLE BLE_ERRORTYPESTAT_REG: LLCHMAP_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Pos (12UL)             /*!< BLE BLE_ERRORTYPESTAT_REG: CSFORMAT_ERROR (Bit 12)          */
#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Msk (0x1000UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: CSFORMAT_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Pos (13UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: TXDESC_EMPTY_ERROR (Bit 13)      */
#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Msk (0x2000UL)     /*!< BLE BLE_ERRORTYPESTAT_REG: TXDESC_EMPTY_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Pos (14UL)         /*!< BLE BLE_ERRORTYPESTAT_REG: RXDESC_EMPTY_ERROR (Bit 14)      */
#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Msk (0x4000UL)     /*!< BLE BLE_ERRORTYPESTAT_REG: RXDESC_EMPTY_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Pos (15UL)           /*!< BLE BLE_ERRORTYPESTAT_REG: TXDATA_PTR_ERROR (Bit 15)        */
#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Msk (0x8000UL)       /*!< BLE BLE_ERRORTYPESTAT_REG: TXDATA_PTR_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Pos (16UL)           /*!< BLE BLE_ERRORTYPESTAT_REG: RXDATA_PTR_ERROR (Bit 16)        */
#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Msk (0x10000UL)      /*!< BLE BLE_ERRORTYPESTAT_REG: RXDATA_PTR_ERROR (Bitfield-Mask: 0x01) */
#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Pos (17UL)           /*!< BLE BLE_ERRORTYPESTAT_REG: CONCEVTIRQ_ERROR (Bit 17)        */
#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Msk (0x20000UL)      /*!< BLE BLE_ERRORTYPESTAT_REG: CONCEVTIRQ_ERROR (Bitfield-Mask: 0x01) */

/* ---------------------------  BLE_BLE_SWPROFILING_REG  -------------------------- */
#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Pos (0UL)                     /*!< BLE BLE_SWPROFILING_REG: SWPROFVAL (Bit 0)                  */
#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Msk (0xffffffffUL)            /*!< BLE BLE_SWPROFILING_REG: SWPROFVAL (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  BLE_BLE_RADIOCNTL0_REG  --------------------------- */
#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Pos (2UL)                    /*!< BLE BLE_RADIOCNTL0_REG: field246rsv (Bit 2)                 */
#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Msk (0x1cUL)                 /*!< BLE BLE_RADIOCNTL0_REG: field246rsv (Bitfield-Mask: 0x07)   */

/* ---------------------------  BLE_BLE_RADIOCNTL1_REG  --------------------------- */
#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Pos     (16UL)                    /*!< BLE BLE_RADIOCNTL1_REG: XRFSEL (Bit 16)                     */
#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Msk     (0x1f0000UL)              /*!< BLE BLE_RADIOCNTL1_REG: XRFSEL (Bitfield-Mask: 0x1f)        */

/* --------------------------  BLE_BLE_RADIOPWRUPDN_REG  -------------------------- */
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Pos  (0UL)                     /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRUP (Bit 0)                   */
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Msk  (0xffUL)                  /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRUP (Bitfield-Mask: 0xff)     */
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Pos  (8UL)                     /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRDN (Bit 8)                   */
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Msk  (0xf00UL)                 /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRDN (Bitfield-Mask: 0x0f)     */
#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Pos  (16UL)                    /*!< BLE BLE_RADIOPWRUPDN_REG: RXPWRUP (Bit 16)                  */
#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Msk  (0xff0000UL)              /*!< BLE BLE_RADIOPWRUPDN_REG: RXPWRUP (Bitfield-Mask: 0xff)     */
#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Pos (24UL)                 /*!< BLE BLE_RADIOPWRUPDN_REG: RTRIP_DELAY (Bit 24)              */
#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Msk (0x7f000000UL)         /*!< BLE BLE_RADIOPWRUPDN_REG: RTRIP_DELAY (Bitfield-Mask: 0x7f) */

/* ----------------------------  BLE_BLE_ADVCHMAP_REG  ---------------------------- */
#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Pos     (0UL)                     /*!< BLE BLE_ADVCHMAP_REG: ADVCHMAP (Bit 0)                      */
#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Msk     (0x7UL)                   /*!< BLE BLE_ADVCHMAP_REG: ADVCHMAP (Bitfield-Mask: 0x07)        */

/* -----------------------------  BLE_BLE_ADVTIM_REG  ----------------------------- */
#define BLE_BLE_ADVTIM_REG_ADVINT_Pos         (0UL)                     /*!< BLE BLE_ADVTIM_REG: ADVINT (Bit 0)                          */
#define BLE_BLE_ADVTIM_REG_ADVINT_Msk         (0x3fffUL)                /*!< BLE BLE_ADVTIM_REG: ADVINT (Bitfield-Mask: 0x3fff)          */

/* ---------------------------  BLE_BLE_ACTSCANSTAT_REG  -------------------------- */
#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Pos (0UL)                    /*!< BLE BLE_ACTSCANSTAT_REG: UPPERLIMIT (Bit 0)                 */
#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Msk (0x1ffUL)                /*!< BLE BLE_ACTSCANSTAT_REG: UPPERLIMIT (Bitfield-Mask: 0x1ff)  */
#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Pos   (16UL)                    /*!< BLE BLE_ACTSCANSTAT_REG: BACKOFF (Bit 16)                   */
#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Msk   (0x1ff0000UL)             /*!< BLE BLE_ACTSCANSTAT_REG: BACKOFF (Bitfield-Mask: 0x1ff)     */

/* ---------------------------  BLE_BLE_WLPUBADDPTR_REG  -------------------------- */
#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Pos (0UL)                   /*!< BLE BLE_WLPUBADDPTR_REG: WLPUBADDPTR (Bit 0)                */
#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Msk (0xffffUL)              /*!< BLE BLE_WLPUBADDPTR_REG: WLPUBADDPTR (Bitfield-Mask: 0xffff) */

/* --------------------------  BLE_BLE_WLPRIVADDPTR_REG  -------------------------- */
#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Pos (0UL)                 /*!< BLE BLE_WLPRIVADDPTR_REG: WLPRIVADDPTR (Bit 0)              */
#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Msk (0xffffUL)            /*!< BLE BLE_WLPRIVADDPTR_REG: WLPRIVADDPTR (Bitfield-Mask: 0xffff) */

/* -----------------------------  BLE_BLE_WLNBDEV_REG  ---------------------------- */
#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Pos      (0UL)                     /*!< BLE BLE_WLNBDEV_REG: NBPUBDEV (Bit 0)                       */
#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Msk      (0xffUL)                  /*!< BLE BLE_WLNBDEV_REG: NBPUBDEV (Bitfield-Mask: 0xff)         */
#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Pos     (8UL)                     /*!< BLE BLE_WLNBDEV_REG: NBPRIVDEV (Bit 8)                      */
#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Msk     (0xff00UL)                /*!< BLE BLE_WLNBDEV_REG: NBPRIVDEV (Bitfield-Mask: 0xff)        */

/* -----------------------------  BLE_BLE_AESCNTL_REG  ---------------------------- */
#define BLE_BLE_AESCNTL_REG_AES_START_Pos     (0UL)                     /*!< BLE BLE_AESCNTL_REG: AES_START (Bit 0)                      */
#define BLE_BLE_AESCNTL_REG_AES_START_Msk     (0x1UL)                   /*!< BLE BLE_AESCNTL_REG: AES_START (Bitfield-Mask: 0x01)        */
#define BLE_BLE_AESCNTL_REG_AES_MODE_Pos      (1UL)                     /*!< BLE BLE_AESCNTL_REG: AES_MODE (Bit 1)                       */
#define BLE_BLE_AESCNTL_REG_AES_MODE_Msk      (0x2UL)                   /*!< BLE BLE_AESCNTL_REG: AES_MODE (Bitfield-Mask: 0x01)         */

/* ---------------------------  BLE_BLE_AESKEY31_0_REG  --------------------------- */
#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Pos (0UL)                     /*!< BLE BLE_AESKEY31_0_REG: AESKEY31_0 (Bit 0)                  */
#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Msk (0xffffffffUL)            /*!< BLE BLE_AESKEY31_0_REG: AESKEY31_0 (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  BLE_BLE_AESKEY63_32_REG  -------------------------- */
#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Pos (0UL)                   /*!< BLE BLE_AESKEY63_32_REG: AESKEY63_32 (Bit 0)                */
#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Msk (0xffffffffUL)          /*!< BLE BLE_AESKEY63_32_REG: AESKEY63_32 (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  BLE_BLE_AESKEY95_64_REG  -------------------------- */
#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Pos (0UL)                   /*!< BLE BLE_AESKEY95_64_REG: AESKEY95_64 (Bit 0)                */
#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Msk (0xffffffffUL)          /*!< BLE BLE_AESKEY95_64_REG: AESKEY95_64 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  BLE_BLE_AESKEY127_96_REG  -------------------------- */
#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Pos (0UL)                 /*!< BLE BLE_AESKEY127_96_REG: AESKEY127_96 (Bit 0)              */
#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Msk (0xffffffffUL)        /*!< BLE BLE_AESKEY127_96_REG: AESKEY127_96 (Bitfield-Mask: 0xffffffff) */

/* -----------------------------  BLE_BLE_AESPTR_REG  ----------------------------- */
#define BLE_BLE_AESPTR_REG_AESPTR_Pos         (0UL)                     /*!< BLE BLE_AESPTR_REG: AESPTR (Bit 0)                          */
#define BLE_BLE_AESPTR_REG_AESPTR_Msk         (0xffffUL)                /*!< BLE BLE_AESPTR_REG: AESPTR (Bitfield-Mask: 0xffff)          */

/* ----------------------------  BLE_BLE_TXMICVAL_REG  ---------------------------- */
#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Pos     (0UL)                     /*!< BLE BLE_TXMICVAL_REG: TXMICVAL (Bit 0)                      */
#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Msk     (0xffffffffUL)            /*!< BLE BLE_TXMICVAL_REG: TXMICVAL (Bitfield-Mask: 0xffffffff)  */

/* ----------------------------  BLE_BLE_RXMICVAL_REG  ---------------------------- */
#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Pos     (0UL)                     /*!< BLE BLE_RXMICVAL_REG: RXMICVAL (Bit 0)                      */
#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Msk     (0xffffffffUL)            /*!< BLE BLE_RXMICVAL_REG: RXMICVAL (Bitfield-Mask: 0xffffffff)  */

/* ---------------------------  BLE_BLE_RFTESTCNTL_REG  --------------------------- */
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Pos   (0UL)                     /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTH (Bit 0)                    */
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Msk   (0x1ffUL)                 /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTH (Bitfield-Mask: 0x1ff)     */
#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Pos (11UL)                    /*!< BLE BLE_RFTESTCNTL_REG: TXPKTCNTEN (Bit 11)                 */
#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Msk (0x800UL)                 /*!< BLE BLE_RFTESTCNTL_REG: TXPKTCNTEN (Bitfield-Mask: 0x01)    */
#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Pos   (12UL)                    /*!< BLE BLE_RFTESTCNTL_REG: TXPLDSRC (Bit 12)                   */
#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Msk   (0x1000UL)                /*!< BLE BLE_RFTESTCNTL_REG: TXPLDSRC (Bitfield-Mask: 0x01)      */
#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Pos   (13UL)                    /*!< BLE BLE_RFTESTCNTL_REG: PRBSTYPE (Bit 13)                   */
#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Msk   (0x2000UL)                /*!< BLE BLE_RFTESTCNTL_REG: PRBSTYPE (Bitfield-Mask: 0x01)      */
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Pos (14UL)                   /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTHSRC (Bit 14)                */
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Msk (0x4000UL)               /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTHSRC (Bitfield-Mask: 0x01)   */
#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Pos (15UL)                    /*!< BLE BLE_RFTESTCNTL_REG: INFINITETX (Bit 15)                 */
#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Msk (0x8000UL)                /*!< BLE BLE_RFTESTCNTL_REG: INFINITETX (Bitfield-Mask: 0x01)    */
#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Pos (27UL)                    /*!< BLE BLE_RFTESTCNTL_REG: RXPKTCNTEN (Bit 27)                 */
#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Msk (0x8000000UL)             /*!< BLE BLE_RFTESTCNTL_REG: RXPKTCNTEN (Bitfield-Mask: 0x01)    */
#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Pos (31UL)                    /*!< BLE BLE_RFTESTCNTL_REG: INFINITERX (Bit 31)                 */
#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Msk (0x80000000UL)            /*!< BLE BLE_RFTESTCNTL_REG: INFINITERX (Bitfield-Mask: 0x01)    */

/* --------------------------  BLE_BLE_RFTESTTXSTAT_REG  -------------------------- */
#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Pos (0UL)                     /*!< BLE BLE_RFTESTTXSTAT_REG: TXPKTCNT (Bit 0)                  */
#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Msk (0xffffffffUL)            /*!< BLE BLE_RFTESTTXSTAT_REG: TXPKTCNT (Bitfield-Mask: 0xffffffff) */

/* --------------------------  BLE_BLE_RFTESTRXSTAT_REG  -------------------------- */
#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Pos (0UL)                     /*!< BLE BLE_RFTESTRXSTAT_REG: RXPKTCNT (Bit 0)                  */
#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Msk (0xffffffffUL)            /*!< BLE BLE_RFTESTRXSTAT_REG: RXPKTCNT (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  BLE_BLE_TIMGENCNTL_REG  --------------------------- */
#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Pos (0UL)                  /*!< BLE BLE_TIMGENCNTL_REG: PREFETCH_TIME (Bit 0)               */
#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Msk (0x1ffUL)              /*!< BLE BLE_TIMGENCNTL_REG: PREFETCH_TIME (Bitfield-Mask: 0x1ff) */
#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Pos (16UL)            /*!< BLE BLE_TIMGENCNTL_REG: PREFETCHABORT_TIME (Bit 16)         */
#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Msk (0x3ff0000UL)     /*!< BLE BLE_TIMGENCNTL_REG: PREFETCHABORT_TIME (Bitfield-Mask: 0x3ff) */
#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Pos    (31UL)                    /*!< BLE BLE_TIMGENCNTL_REG: APFM_EN (Bit 31)                    */
#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Msk    (0x80000000UL)            /*!< BLE BLE_TIMGENCNTL_REG: APFM_EN (Bitfield-Mask: 0x01)       */

/* ---------------------------  BLE_BLE_GROSSTIMTGT_REG  -------------------------- */
#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Pos (0UL)                   /*!< BLE BLE_GROSSTIMTGT_REG: GROSSTARGET (Bit 0)                */
#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Msk (0x7fffffUL)            /*!< BLE BLE_GROSSTIMTGT_REG: GROSSTARGET (Bitfield-Mask: 0x7fffff) */

/* ---------------------------  BLE_BLE_FINETIMTGT_REG  --------------------------- */
#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Pos (0UL)                     /*!< BLE BLE_FINETIMTGT_REG: FINETARGET (Bit 0)                  */
#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Msk (0x7ffffffUL)             /*!< BLE BLE_FINETIMTGT_REG: FINETARGET (Bitfield-Mask: 0x7ffffff) */

/* ----------------------------  BLE_BLE_SAMPLECLK_REG  --------------------------- */
#define BLE_BLE_SAMPLECLK_REG_SAMP_Pos        (0UL)                     /*!< BLE BLE_SAMPLECLK_REG: SAMP (Bit 0)                         */
#define BLE_BLE_SAMPLECLK_REG_SAMP_Msk        (0x1UL)                   /*!< BLE BLE_SAMPLECLK_REG: SAMP (Bitfield-Mask: 0x01)           */

/* ---------------------------  BLE_BLE_COEXIFCNTL0_REG  -------------------------- */
#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Pos   (0UL)                     /*!< BLE BLE_COEXIFCNTL0_REG: COEX_EN (Bit 0)                    */
#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Msk   (0x1UL)                   /*!< BLE BLE_COEXIFCNTL0_REG: COEX_EN (Bitfield-Mask: 0x01)      */
#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Pos (1UL)                    /*!< BLE BLE_COEXIFCNTL0_REG: SYNCGEN_EN (Bit 1)                 */
#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Msk (0x2UL)                  /*!< BLE BLE_COEXIFCNTL0_REG: SYNCGEN_EN (Bitfield-Mask: 0x01)   */
#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Pos (4UL)                     /*!< BLE BLE_COEXIFCNTL0_REG: WLANRXMSK (Bit 4)                  */
#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Msk (0x30UL)                  /*!< BLE BLE_COEXIFCNTL0_REG: WLANRXMSK (Bitfield-Mask: 0x03)    */
#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Pos (6UL)                     /*!< BLE BLE_COEXIFCNTL0_REG: WLANTXMSK (Bit 6)                  */
#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Msk (0xc0UL)                  /*!< BLE BLE_COEXIFCNTL0_REG: WLANTXMSK (Bitfield-Mask: 0x03)    */
#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Pos (16UL)                /*!< BLE BLE_COEXIFCNTL0_REG: WLCTXPRIOMODE (Bit 16)             */
#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Msk (0x30000UL)           /*!< BLE BLE_COEXIFCNTL0_REG: WLCTXPRIOMODE (Bitfield-Mask: 0x03) */
#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Pos (20UL)                /*!< BLE BLE_COEXIFCNTL0_REG: WLCRXPRIOMODE (Bit 20)             */
#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Msk (0x300000UL)          /*!< BLE BLE_COEXIFCNTL0_REG: WLCRXPRIOMODE (Bitfield-Mask: 0x03) */

/* ---------------------------  BLE_BLE_COEXIFCNTL1_REG  -------------------------- */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Pos (0UL)                     /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDELAY (Bit 0)                  */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Msk (0x7fUL)                  /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDELAY (Bitfield-Mask: 0x7f)    */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Pos (8UL)                  /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDURATION (Bit 8)               */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Msk (0x7f00UL)             /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDURATION (Bitfield-Mask: 0x7f) */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Pos (16UL)                    /*!< BLE BLE_COEXIFCNTL1_REG: WLCPTXTHR (Bit 16)                 */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Msk (0x1f0000UL)              /*!< BLE BLE_COEXIFCNTL1_REG: WLCPTXTHR (Bitfield-Mask: 0x1f)    */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Pos (24UL)                    /*!< BLE BLE_COEXIFCNTL1_REG: WLCPRXTHR (Bit 24)                 */
#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Msk (0x1f000000UL)            /*!< BLE BLE_COEXIFCNTL1_REG: WLCPRXTHR (Bitfield-Mask: 0x1f)    */

/* ----------------------------  BLE_BLE_BLEMPRIO0_REG  --------------------------- */
#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Pos       (0UL)                     /*!< BLE BLE_BLEMPRIO0_REG: BLEM0 (Bit 0)                        */
#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Msk       (0xfUL)                   /*!< BLE BLE_BLEMPRIO0_REG: BLEM0 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Pos       (4UL)                     /*!< BLE BLE_BLEMPRIO0_REG: BLEM1 (Bit 4)                        */
#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Msk       (0xf0UL)                  /*!< BLE BLE_BLEMPRIO0_REG: BLEM1 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Pos       (8UL)                     /*!< BLE BLE_BLEMPRIO0_REG: BLEM2 (Bit 8)                        */
#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Msk       (0xf00UL)                 /*!< BLE BLE_BLEMPRIO0_REG: BLEM2 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Pos       (12UL)                    /*!< BLE BLE_BLEMPRIO0_REG: BLEM3 (Bit 12)                       */
#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Msk       (0xf000UL)                /*!< BLE BLE_BLEMPRIO0_REG: BLEM3 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Pos       (16UL)                    /*!< BLE BLE_BLEMPRIO0_REG: BLEM4 (Bit 16)                       */
#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Msk       (0xf0000UL)               /*!< BLE BLE_BLEMPRIO0_REG: BLEM4 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Pos       (20UL)                    /*!< BLE BLE_BLEMPRIO0_REG: BLEM5 (Bit 20)                       */
#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Msk       (0xf00000UL)              /*!< BLE BLE_BLEMPRIO0_REG: BLEM5 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Pos       (24UL)                    /*!< BLE BLE_BLEMPRIO0_REG: BLEM6 (Bit 24)                       */
#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Msk       (0xf000000UL)             /*!< BLE BLE_BLEMPRIO0_REG: BLEM6 (Bitfield-Mask: 0x0f)          */
#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Pos       (28UL)                    /*!< BLE BLE_BLEMPRIO0_REG: BLEM7 (Bit 28)                       */
#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Msk       (0xf0000000UL)            /*!< BLE BLE_BLEMPRIO0_REG: BLEM7 (Bitfield-Mask: 0x0f)          */

/* ----------------------------  BLE_BLE_BLEMPRIO1_REG  --------------------------- */
#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Pos (28UL)                    /*!< BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bit 28)                 */
#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Msk (0xf0000000UL)            /*!< BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bitfield-Mask: 0x0f)    */

/* ------------------------------  BLE_BLE_CNTL2_REG  ----------------------------- */
#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Pos    (0UL)                     /*!< BLE BLE_CNTL2_REG: EMACCERRSTAT (Bit 0)                     */
#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Msk    (0x1UL)                   /*!< BLE BLE_CNTL2_REG: EMACCERRSTAT (Bitfield-Mask: 0x01)       */
#define BLE_BLE_CNTL2_REG_EMACCERRACK_Pos     (1UL)                     /*!< BLE BLE_CNTL2_REG: EMACCERRACK (Bit 1)                      */
#define BLE_BLE_CNTL2_REG_EMACCERRACK_Msk     (0x2UL)                   /*!< BLE BLE_CNTL2_REG: EMACCERRACK (Bitfield-Mask: 0x01)        */
#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Pos     (2UL)                     /*!< BLE BLE_CNTL2_REG: EMACCERRMSK (Bit 2)                      */
#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Msk     (0x4UL)                   /*!< BLE BLE_CNTL2_REG: EMACCERRMSK (Bitfield-Mask: 0x01)        */
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Pos    (3UL)                     /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bit 3)                     */
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Msk    (0x8UL)                   /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bitfield-Mask: 0x01)       */
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Pos (4UL)                    /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bit 4)                 */
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Msk (0x30UL)                 /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bitfield-Mask: 0x03)   */
#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Pos    (6UL)                     /*!< BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bit 6)                     */
#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Msk    (0x40UL)                  /*!< BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bitfield-Mask: 0x01)       */
#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Pos      (7UL)                     /*!< BLE BLE_CNTL2_REG: MON_LP_CLK (Bit 7)                       */
#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Msk      (0x80UL)                  /*!< BLE BLE_CNTL2_REG: MON_LP_CLK (Bitfield-Mask: 0x01)         */
#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Pos (8UL)                   /*!< BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bit 8)                */
#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Msk (0x100UL)               /*!< BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bitfield-Mask: 0x01)  */
#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Pos     (9UL)                     /*!< BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bit 9)                      */
#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Msk     (0x7e00UL)                /*!< BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bitfield-Mask: 0x3f)        */
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Pos (15UL)                /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bit 15)             */
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Msk (0x8000UL)            /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bitfield-Mask: 0x01) */
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Pos (16UL)               /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bit 16)            */
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Msk (0x10000UL)          /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bitfield-Mask: 0x01) */
#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Pos (17UL)                 /*!< BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bit 17)              */
#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Msk (0x20000UL)            /*!< BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bitfield-Mask: 0x01) */
#define BLE_BLE_CNTL2_REG_BB_ONLY_Pos         (18UL)                    /*!< BLE BLE_CNTL2_REG: BB_ONLY (Bit 18)                         */
#define BLE_BLE_CNTL2_REG_BB_ONLY_Msk         (0x40000UL)               /*!< BLE BLE_CNTL2_REG: BB_ONLY (Bitfield-Mask: 0x01)            */
#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Pos      (19UL)                    /*!< BLE BLE_CNTL2_REG: SW_RPL_SPI (Bit 19)                      */
#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Msk      (0x80000UL)               /*!< BLE BLE_CNTL2_REG: SW_RPL_SPI (Bitfield-Mask: 0x01)         */
#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Pos    (20UL)                    /*!< BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bit 20)                    */
#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Msk    (0x100000UL)              /*!< BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bitfield-Mask: 0x01)       */
#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Pos    (21UL)                    /*!< BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bit 21)                    */
#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Msk    (0x200000UL)              /*!< BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bitfield-Mask: 0x01)       */
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Pos (22UL)              /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bit 22)           */
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Msk (0xffc00000UL)      /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bitfield-Mask: 0x3ff) */

/* -----------------------------  BLE_BLE_EM_BASE_REG  ---------------------------- */
#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Pos (10UL)                /*!< BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bit 10)             */
#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Msk (0x1fc00UL)           /*!< BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bitfield-Mask: 0x7f) */

/* ----------------------------  BLE_BLE_DIAGCNTL2_REG  --------------------------- */
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Pos       (0UL)                     /*!< BLE BLE_DIAGCNTL2_REG: DIAG4 (Bit 0)                        */
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Msk       (0x3fUL)                  /*!< BLE BLE_DIAGCNTL2_REG: DIAG4 (Bitfield-Mask: 0x3f)          */
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Pos    (7UL)                     /*!< BLE BLE_DIAGCNTL2_REG: DIAG4_EN (Bit 7)                     */
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Msk    (0x80UL)                  /*!< BLE BLE_DIAGCNTL2_REG: DIAG4_EN (Bitfield-Mask: 0x01)       */
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Pos       (8UL)                     /*!< BLE BLE_DIAGCNTL2_REG: DIAG5 (Bit 8)                        */
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Msk       (0x3f00UL)                /*!< BLE BLE_DIAGCNTL2_REG: DIAG5 (Bitfield-Mask: 0x3f)          */
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Pos    (15UL)                    /*!< BLE BLE_DIAGCNTL2_REG: DIAG5_EN (Bit 15)                    */
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Msk    (0x8000UL)                /*!< BLE BLE_DIAGCNTL2_REG: DIAG5_EN (Bitfield-Mask: 0x01)       */
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Pos       (16UL)                    /*!< BLE BLE_DIAGCNTL2_REG: DIAG6 (Bit 16)                       */
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Msk       (0x3f0000UL)              /*!< BLE BLE_DIAGCNTL2_REG: DIAG6 (Bitfield-Mask: 0x3f)          */
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Pos    (23UL)                    /*!< BLE BLE_DIAGCNTL2_REG: DIAG6_EN (Bit 23)                    */
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Msk    (0x800000UL)              /*!< BLE BLE_DIAGCNTL2_REG: DIAG6_EN (Bitfield-Mask: 0x01)       */
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Pos       (24UL)                    /*!< BLE BLE_DIAGCNTL2_REG: DIAG7 (Bit 24)                       */
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Msk       (0x3f000000UL)            /*!< BLE BLE_DIAGCNTL2_REG: DIAG7 (Bitfield-Mask: 0x3f)          */
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Pos    (31UL)                    /*!< BLE BLE_DIAGCNTL2_REG: DIAG7_EN (Bit 31)                    */
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Msk    (0x80000000UL)            /*!< BLE BLE_DIAGCNTL2_REG: DIAG7_EN (Bitfield-Mask: 0x01)       */

/* ----------------------------  BLE_BLE_DIAGCNTL3_REG  --------------------------- */
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Pos   (0UL)                     /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_BIT (Bit 0)                    */
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Msk   (0x7UL)                   /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Pos   (3UL)                     /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_INV (Bit 3)                    */
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Msk   (0x8UL)                   /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Pos   (4UL)                     /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_BIT (Bit 4)                    */
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Msk   (0x70UL)                  /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Pos   (7UL)                     /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_INV (Bit 7)                    */
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Msk   (0x80UL)                  /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Pos   (8UL)                     /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_BIT (Bit 8)                    */
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Msk   (0x700UL)                 /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Pos   (11UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_INV (Bit 11)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Msk   (0x800UL)                 /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Pos   (12UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_BIT (Bit 12)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Msk   (0x7000UL)                /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Pos   (15UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_INV (Bit 15)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Msk   (0x8000UL)                /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Pos   (16UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_BIT (Bit 16)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Msk   (0x70000UL)               /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Pos   (19UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_INV (Bit 19)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Msk   (0x80000UL)               /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Pos   (20UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_BIT (Bit 20)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Msk   (0x700000UL)              /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Pos   (23UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_INV (Bit 23)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Msk   (0x800000UL)              /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Pos   (24UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_BIT (Bit 24)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Msk   (0x7000000UL)             /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Pos   (27UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_INV (Bit 27)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Msk   (0x8000000UL)             /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_INV (Bitfield-Mask: 0x01)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Pos   (28UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_BIT (Bit 28)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Msk   (0x70000000UL)            /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_BIT (Bitfield-Mask: 0x07)      */
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Pos   (31UL)                    /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_INV (Bit 31)                   */
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Msk   (0x80000000UL)            /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_INV (Bitfield-Mask: 0x01)      */


/* ================================================================================ */
/* ================         struct 'CACHE' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------  CACHE_CACHE_CTRL1_REG  --------------------------- */
#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos (0UL)                     /*!< CACHE CACHE_CTRL1_REG: CACHE_FLUSH (Bit 0)                  */
#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk (0x1UL)                   /*!< CACHE CACHE_CTRL1_REG: CACHE_FLUSH (Bitfield-Mask: 0x01)    */
#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos  (1UL)                     /*!< CACHE CACHE_CTRL1_REG: CACHE_RES1 (Bit 1)                   */
#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk  (0x2UL)                   /*!< CACHE CACHE_CTRL1_REG: CACHE_RES1 (Bitfield-Mask: 0x01)     */

/* --------------------------  CACHE_CACHE_LNSIZECFG_REG  ------------------------- */
#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos (0UL)                  /*!< CACHE CACHE_LNSIZECFG_REG: CACHE_LINE (Bit 0)               */
#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk (0x3UL)                /*!< CACHE CACHE_LNSIZECFG_REG: CACHE_LINE (Bitfield-Mask: 0x03) */

/* --------------------------  CACHE_CACHE_ASSOCCFG_REG  -------------------------- */
#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos (0UL)                  /*!< CACHE CACHE_ASSOCCFG_REG: CACHE_ASSOC (Bit 0)               */
#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk (0x3UL)                /*!< CACHE CACHE_ASSOCCFG_REG: CACHE_ASSOC (Bitfield-Mask: 0x03) */

/* ----------------------------  CACHE_CACHE_CTRL2_REG  --------------------------- */
#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos   (0UL)                     /*!< CACHE CACHE_CTRL2_REG: CACHE_LEN (Bit 0)                    */
#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk   (0x1ffUL)                 /*!< CACHE CACHE_CTRL2_REG: CACHE_LEN (Bitfield-Mask: 0x1ff)     */
#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos   (9UL)                     /*!< CACHE CACHE_CTRL2_REG: CACHE_WEN (Bit 9)                    */
#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk   (0x200UL)                 /*!< CACHE CACHE_CTRL2_REG: CACHE_WEN (Bitfield-Mask: 0x01)      */
#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos  (10UL)                    /*!< CACHE CACHE_CTRL2_REG: CACHE_CGEN (Bit 10)                  */
#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk  (0x400UL)                 /*!< CACHE CACHE_CTRL2_REG: CACHE_CGEN (Bitfield-Mask: 0x01)     */
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Pos (11UL)         /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_OTP_CACHED (Bit 11)      */
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Msk (0x800UL)      /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_OTP_CACHED (Bitfield-Mask: 0x01) */
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Pos (12UL)   /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_QSPIFLASH_CACHED (Bit 12) */
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Msk (0x1000UL) /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_QSPIFLASH_CACHED (Bitfield-Mask: 0x01) */

/* ----------------------------  CACHE_CACHE_CTRL3_REG  --------------------------- */
#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Pos (0UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_ASSOCIATIVITY_RESET_VALUE (Bit 0) */
#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Msk (0x3UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_ASSOCIATIVITY_RESET_VALUE (Bitfield-Mask: 0x03) */
#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Pos (2UL)     /*!< CACHE CACHE_CTRL3_REG: CACHE_LINE_SIZE_RESET_VALUE (Bit 2)  */
#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Msk (0xcUL)   /*!< CACHE CACHE_CTRL3_REG: CACHE_LINE_SIZE_RESET_VALUE (Bitfield-Mask: 0x03) */
#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Pos (4UL)      /*!< CACHE CACHE_CTRL3_REG: CACHE_RAM_SIZE_RESET_VALUE (Bit 4)   */
#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Msk (0x70UL)   /*!< CACHE CACHE_CTRL3_REG: CACHE_RAM_SIZE_RESET_VALUE (Bitfield-Mask: 0x07) */
#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Pos (7UL)          /*!< CACHE CACHE_CTRL3_REG: CACHE_CONTROLLER_RESET (Bit 7)       */
#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Msk (0x80UL)       /*!< CACHE CACHE_CTRL3_REG: CACHE_CONTROLLER_RESET (Bitfield-Mask: 0x01) */

/* --------------------------  CACHE_CACHE_MRM_HITS_REG  -------------------------- */
#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)                     /*!< CACHE CACHE_MRM_HITS_REG: MRM_HITS (Bit 0)                  */
#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0x7ffffUL)               /*!< CACHE CACHE_MRM_HITS_REG: MRM_HITS (Bitfield-Mask: 0x7ffff) */

/* -------------------------  CACHE_CACHE_MRM_MISSES_REG  ------------------------- */
#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)                 /*!< CACHE CACHE_MRM_MISSES_REG: MRM_MISSES (Bit 0)              */
#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0x3ffffUL)           /*!< CACHE CACHE_MRM_MISSES_REG: MRM_MISSES (Bitfield-Mask: 0x3ffff) */

/* --------------------------  CACHE_CACHE_MRM_CTRL_REG  -------------------------- */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)                    /*!< CACHE CACHE_MRM_CTRL_REG: MRM_START (Bit 0)                 */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)                  /*!< CACHE CACHE_MRM_CTRL_REG: MRM_START (Bitfield-Mask: 0x01)   */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)                 /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_MASK (Bit 1)              */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)               /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_MASK (Bitfield-Mask: 0x01) */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)          /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_TINT_STATUS (Bit 2)       */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)        /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01) */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Pos (3UL)         /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_THRES_STATUS (Bit 3)      */
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Msk (0x8UL)       /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_THRES_STATUS (Bitfield-Mask: 0x01) */

/* --------------------------  CACHE_CACHE_MRM_TINT_REG  -------------------------- */
#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)                     /*!< CACHE CACHE_MRM_TINT_REG: MRM_TINT (Bit 0)                  */
#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x3ffffUL)               /*!< CACHE CACHE_MRM_TINT_REG: MRM_TINT (Bitfield-Mask: 0x3ffff) */

/* --------------------------  CACHE_CACHE_MRM_THRES_REG  ------------------------- */
#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Pos (0UL)                   /*!< CACHE CACHE_MRM_THRES_REG: MRM_THRES (Bit 0)                */
#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Msk (0x3ffffUL)             /*!< CACHE CACHE_MRM_THRES_REG: MRM_THRES (Bitfield-Mask: 0x3ffff) */

/* -----------------------------  CACHE_SWD_RESET_REG  ---------------------------- */
#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)                  /*!< CACHE SWD_RESET_REG: SWD_HW_RESET_REQ (Bit 0)               */
#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)                /*!< CACHE SWD_RESET_REG: SWD_HW_RESET_REQ (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================      struct 'CHIP_VERSION' Position & Mask     ================ */
/* ================================================================================ */


/* --------------------------  CHIP_VERSION_CHIP_ID1_REG  ------------------------- */
#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL)                    /*!< CHIP_VERSION CHIP_ID1_REG: CHIP_ID1 (Bit 0)                 */
#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL)                 /*!< CHIP_VERSION CHIP_ID1_REG: CHIP_ID1 (Bitfield-Mask: 0xff)   */

/* --------------------------  CHIP_VERSION_CHIP_ID2_REG  ------------------------- */
#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL)                    /*!< CHIP_VERSION CHIP_ID2_REG: CHIP_ID2 (Bit 0)                 */
#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL)                 /*!< CHIP_VERSION CHIP_ID2_REG: CHIP_ID2 (Bitfield-Mask: 0xff)   */

/* --------------------------  CHIP_VERSION_CHIP_ID3_REG  ------------------------- */
#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL)                    /*!< CHIP_VERSION CHIP_ID3_REG: CHIP_ID3 (Bit 0)                 */
#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL)                 /*!< CHIP_VERSION CHIP_ID3_REG: CHIP_ID3 (Bitfield-Mask: 0xff)   */

/* --------------------------  CHIP_VERSION_CHIP_SWC_REG  ------------------------- */
#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL)                    /*!< CHIP_VERSION CHIP_SWC_REG: CHIP_SWC (Bit 0)                 */
#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL)                  /*!< CHIP_VERSION CHIP_SWC_REG: CHIP_SWC (Bitfield-Mask: 0x0f)   */

/* -----------------------  CHIP_VERSION_CHIP_REVISION_REG  ----------------------- */
#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Pos (0UL)            /*!< CHIP_VERSION CHIP_REVISION_REG: REVISION_ID (Bit 0)         */
#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Msk (0xffUL)         /*!< CHIP_VERSION CHIP_REVISION_REG: REVISION_ID (Bitfield-Mask: 0xff) */

/* ------------------------  CHIP_VERSION_CHIP_CONFIG1_REG  ----------------------- */
#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Pos (0UL)            /*!< CHIP_VERSION CHIP_CONFIG1_REG: CHIP_CONFIG1 (Bit 0)         */
#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Msk (0xffUL)         /*!< CHIP_VERSION CHIP_CONFIG1_REG: CHIP_CONFIG1 (Bitfield-Mask: 0xff) */

/* ------------------------  CHIP_VERSION_CHIP_CONFIG2_REG  ----------------------- */
#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Pos (0UL)            /*!< CHIP_VERSION CHIP_CONFIG2_REG: CHIP_CONFIG2 (Bit 0)         */
#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Msk (0xffUL)         /*!< CHIP_VERSION CHIP_CONFIG2_REG: CHIP_CONFIG2 (Bitfield-Mask: 0xff) */

/* ------------------------  CHIP_VERSION_CHIP_CONFIG3_REG  ----------------------- */
#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Pos (0UL)            /*!< CHIP_VERSION CHIP_CONFIG3_REG: CHIP_CONFIG3 (Bit 0)         */
#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Msk (0xffUL)         /*!< CHIP_VERSION CHIP_CONFIG3_REG: CHIP_CONFIG3 (Bitfield-Mask: 0xff) */


/* ================================================================================ */
/* ================          struct 'COEX' Position & Mask         ================ */
/* ================================================================================ */


/* -----------------------------  COEX_COEX_CTRL_REG  ----------------------------- */
#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Pos (0UL)                     /*!< COEX COEX_CTRL_REG: PRGING_ARBITER (Bit 0)                  */
#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Msk (0x1UL)                   /*!< COEX COEX_CTRL_REG: PRGING_ARBITER (Bitfield-Mask: 0x01)    */
#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Pos (1UL)                    /*!< COEX COEX_CTRL_REG: DECISION_SW_ALL (Bit 1)                 */
#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Msk (0x2UL)                  /*!< COEX COEX_CTRL_REG: DECISION_SW_ALL (Bitfield-Mask: 0x01)   */
#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Pos (2UL)                  /*!< COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bit 2)               */
#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Msk (0x4UL)                /*!< COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bitfield-Mask: 0x01) */
#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Pos (3UL)                   /*!< COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bit 3)                */
#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Msk (0x8UL)                 /*!< COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bitfield-Mask: 0x01)  */
#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Pos (4UL)                     /*!< COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bit 4)                  */
#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Msk (0x10UL)                  /*!< COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bitfield-Mask: 0x01)    */
#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Pos  (5UL)                     /*!< COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bit 5)                   */
#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Msk  (0x60UL)                  /*!< COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bitfield-Mask: 0x03)     */
#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Pos   (7UL)                     /*!< COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bit 7)                    */
#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Msk   (0x80UL)                  /*!< COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bitfield-Mask: 0x01)      */
#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Pos   (8UL)                     /*!< COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bit 8)                    */
#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Msk   (0x100UL)                 /*!< COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bitfield-Mask: 0x01)      */
#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Pos    (9UL)                     /*!< COEX COEX_CTRL_REG: SEL_BLE_PTI (Bit 9)                     */
#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Msk    (0x200UL)                 /*!< COEX COEX_CTRL_REG: SEL_BLE_PTI (Bitfield-Mask: 0x01)       */
#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Pos (10UL)                /*!< COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bit 10)             */
#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Msk (0x400UL)             /*!< COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bitfield-Mask: 0x01) */
#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Pos (11UL)                /*!< COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bit 11)             */
#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Msk (0x1800UL)            /*!< COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bitfield-Mask: 0x03) */
#define COEX_COEX_CTRL_REG_IGNORE_EXT_Pos     (13UL)                    /*!< COEX COEX_CTRL_REG: IGNORE_EXT (Bit 13)                     */
#define COEX_COEX_CTRL_REG_IGNORE_EXT_Msk     (0x2000UL)                /*!< COEX COEX_CTRL_REG: IGNORE_EXT (Bitfield-Mask: 0x01)        */
#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Pos    (14UL)                    /*!< COEX COEX_CTRL_REG: IGNORE_FTDF (Bit 14)                    */
#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Msk    (0x4000UL)                /*!< COEX COEX_CTRL_REG: IGNORE_FTDF (Bitfield-Mask: 0x01)       */
#define COEX_COEX_CTRL_REG_IGNORE_BLE_Pos     (15UL)                    /*!< COEX COEX_CTRL_REG: IGNORE_BLE (Bit 15)                     */
#define COEX_COEX_CTRL_REG_IGNORE_BLE_Msk     (0x8000UL)                /*!< COEX COEX_CTRL_REG: IGNORE_BLE (Bitfield-Mask: 0x01)        */

/* -----------------------------  COEX_COEX_STAT_REG  ----------------------------- */
#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Pos (0UL)                  /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bit 0)               */
#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk (0xfUL)                /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bitfield-Mask: 0x0f) */
#define COEX_COEX_STAT_REG_COEX_DECISION_Pos  (5UL)                     /*!< COEX COEX_STAT_REG: COEX_DECISION (Bit 5)                   */
#define COEX_COEX_STAT_REG_COEX_DECISION_Msk  (0x60UL)                  /*!< COEX COEX_STAT_REG: COEX_DECISION (Bitfield-Mask: 0x03)     */
#define COEX_COEX_STAT_REG_COEX_CLOSING_Pos   (7UL)                     /*!< COEX COEX_STAT_REG: COEX_CLOSING (Bit 7)                    */
#define COEX_COEX_STAT_REG_COEX_CLOSING_Msk   (0x80UL)                  /*!< COEX COEX_STAT_REG: COEX_CLOSING (Bitfield-Mask: 0x01)      */
#define COEX_COEX_STAT_REG_SMART_ACT_Pos      (8UL)                     /*!< COEX COEX_STAT_REG: SMART_ACT (Bit 8)                       */
#define COEX_COEX_STAT_REG_SMART_ACT_Msk      (0x100UL)                 /*!< COEX COEX_STAT_REG: SMART_ACT (Bitfield-Mask: 0x01)         */
#define COEX_COEX_STAT_REG_SMART_PRI_Pos      (9UL)                     /*!< COEX COEX_STAT_REG: SMART_PRI (Bit 9)                       */
#define COEX_COEX_STAT_REG_SMART_PRI_Msk      (0x200UL)                 /*!< COEX COEX_STAT_REG: SMART_PRI (Bitfield-Mask: 0x01)         */
#define COEX_COEX_STAT_REG_EXT_ACT0_Pos       (10UL)                    /*!< COEX COEX_STAT_REG: EXT_ACT0 (Bit 10)                       */
#define COEX_COEX_STAT_REG_EXT_ACT0_Msk       (0x400UL)                 /*!< COEX COEX_STAT_REG: EXT_ACT0 (Bitfield-Mask: 0x01)          */
#define COEX_COEX_STAT_REG_EXT_ACT1_Pos       (11UL)                    /*!< COEX COEX_STAT_REG: EXT_ACT1 (Bit 11)                       */
#define COEX_COEX_STAT_REG_EXT_ACT1_Msk       (0x800UL)                 /*!< COEX COEX_STAT_REG: EXT_ACT1 (Bitfield-Mask: 0x01)          */
#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Pos (12UL)                   /*!< COEX COEX_STAT_REG: COEX_RADIO_BUSY (Bit 12)                */
#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Msk (0x1000UL)               /*!< COEX COEX_STAT_REG: COEX_RADIO_BUSY (Bitfield-Mask: 0x01)   */
#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Pos (13UL)                   /*!< COEX COEX_STAT_REG: IGNORE_EXT_STAT (Bit 13)                */
#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Msk (0x2000UL)               /*!< COEX COEX_STAT_REG: IGNORE_EXT_STAT (Bitfield-Mask: 0x01)   */
#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Pos (14UL)                  /*!< COEX COEX_STAT_REG: IGNORE_FTDF_STAT (Bit 14)               */
#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Msk (0x4000UL)              /*!< COEX COEX_STAT_REG: IGNORE_FTDF_STAT (Bitfield-Mask: 0x01)  */
#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Pos (15UL)                   /*!< COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bit 15)                */
#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Msk (0x8000UL)               /*!< COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bitfield-Mask: 0x01)   */

/* -----------------------------  COEX_COEX_STAT2_REG  ---------------------------- */
#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Pos (0UL)        /*!< COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bit 0)     */
#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Msk (0x7UL)      /*!< COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bitfield-Mask: 0x07) */
#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Pos (3UL)                  /*!< COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bit 3)               */
#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Msk (0x8UL)                /*!< COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bitfield-Mask: 0x01) */
#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Pos (4UL)                   /*!< COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bit 4)                */
#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Msk (0x10UL)                /*!< COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bitfield-Mask: 0x01)  */
#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Pos (5UL)                   /*!< COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bit 5)                */
#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Msk (0x20UL)                /*!< COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bitfield-Mask: 0x01)  */
#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Pos (6UL)                 /*!< COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bit 6)              */
#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Msk (0x1c0UL)             /*!< COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bitfield-Mask: 0x07) */
#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Pos (9UL)                   /*!< COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bit 9)                */
#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Msk (0x200UL)               /*!< COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bitfield-Mask: 0x01)  */
#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Pos (10UL)                   /*!< COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bit 10)                */
#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Msk (0x400UL)                /*!< COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bitfield-Mask: 0x01)   */
#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Pos (11UL)                   /*!< COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bit 11)                */
#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Msk (0x800UL)                /*!< COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bitfield-Mask: 0x01)   */
#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Pos (12UL)                 /*!< COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bit 12)              */
#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Msk (0x7000UL)             /*!< COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bitfield-Mask: 0x07) */
#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Pos  (15UL)                    /*!< COEX COEX_STAT2_REG: COEX_EXT_ACT (Bit 15)                  */
#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Msk  (0x8000UL)                /*!< COEX COEX_STAT2_REG: COEX_EXT_ACT (Bitfield-Mask: 0x01)     */

/* ---------------------------  COEX_COEX_INT_MASK_REG  --------------------------- */
#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Pos (8UL)                   /*!< COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bit 8)                */
#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Msk (0x100UL)               /*!< COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01)  */
#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Pos (9UL)                /*!< COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bit 9)             */
#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Msk (0x200UL)            /*!< COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01) */

/* ---------------------------  COEX_COEX_INT_STAT_REG  --------------------------- */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Pos (0UL)                   /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bit 0)                */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Msk (0xfUL)                 /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bitfield-Mask: 0x0f)  */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Pos (5UL)                    /*!< COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bit 5)                 */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Msk (0x20UL)                 /*!< COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bitfield-Mask: 0x01)   */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Pos (6UL)                /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bit 6)             */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Msk (0x40UL)             /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bitfield-Mask: 0x01) */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Pos (7UL)                  /*!< COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bit 7)               */
#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Msk (0x80UL)               /*!< COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bitfield-Mask: 0x01) */
#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Pos (8UL)                   /*!< COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bit 8)                */
#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Msk (0x100UL)               /*!< COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01)  */
#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Pos (9UL)                /*!< COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bit 9)             */
#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Msk (0x200UL)            /*!< COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01) */

/* ----------------------------  COEX_COEX_BLE_PTI_REG  --------------------------- */
#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Pos (0UL)                    /*!< COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bit 0)                 */
#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Msk (0x7UL)                  /*!< COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bitfield-Mask: 0x07)   */

/* ---------------------------  COEX_COEX_FTDF_PTI_REG  --------------------------- */
#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Pos (0UL)                  /*!< COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bit 0)               */
#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Msk (0x7UL)                /*!< COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bitfield-Mask: 0x07) */

/* -----------------------------  COEX_COEX_PRI1_REG  ----------------------------- */
#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI1_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI1_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI1_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI1_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI2_REG  ----------------------------- */
#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI2_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI2_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI2_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI2_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI3_REG  ----------------------------- */
#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI3_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI3_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI3_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI3_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI4_REG  ----------------------------- */
#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI4_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI4_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI4_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI4_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI5_REG  ----------------------------- */
#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI5_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI5_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI5_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI5_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI6_REG  ----------------------------- */
#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI6_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI6_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI6_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI6_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI7_REG  ----------------------------- */
#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI7_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI7_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI7_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI7_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI8_REG  ----------------------------- */
#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI8_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI8_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI8_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI8_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI9_REG  ----------------------------- */
#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Pos   (0UL)                     /*!< COEX COEX_PRI9_REG: COEX_PRI_PTI (Bit 0)                    */
#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Msk   (0x7UL)                   /*!< COEX COEX_PRI9_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)      */
#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Pos   (3UL)                     /*!< COEX COEX_PRI9_REG: COEX_PRI_MAC (Bit 3)                    */
#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Msk   (0x18UL)                  /*!< COEX COEX_PRI9_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)      */

/* -----------------------------  COEX_COEX_PRI10_REG  ---------------------------- */
#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Pos  (0UL)                     /*!< COEX COEX_PRI10_REG: COEX_PRI_PTI (Bit 0)                   */
#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Msk  (0x7UL)                   /*!< COEX COEX_PRI10_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)     */
#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Pos  (3UL)                     /*!< COEX COEX_PRI10_REG: COEX_PRI_MAC (Bit 3)                   */
#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Msk  (0x18UL)                  /*!< COEX COEX_PRI10_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)     */

/* -----------------------------  COEX_COEX_PRI11_REG  ---------------------------- */
#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Pos  (0UL)                     /*!< COEX COEX_PRI11_REG: COEX_PRI_PTI (Bit 0)                   */
#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Msk  (0x7UL)                   /*!< COEX COEX_PRI11_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)     */
#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Pos  (3UL)                     /*!< COEX COEX_PRI11_REG: COEX_PRI_MAC (Bit 3)                   */
#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Msk  (0x18UL)                  /*!< COEX COEX_PRI11_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)     */

/* -----------------------------  COEX_COEX_PRI12_REG  ---------------------------- */
#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Pos  (0UL)                     /*!< COEX COEX_PRI12_REG: COEX_PRI_PTI (Bit 0)                   */
#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Msk  (0x7UL)                   /*!< COEX COEX_PRI12_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)     */
#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Pos  (3UL)                     /*!< COEX COEX_PRI12_REG: COEX_PRI_MAC (Bit 3)                   */
#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Msk  (0x18UL)                  /*!< COEX COEX_PRI12_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)     */

/* -----------------------------  COEX_COEX_PRI13_REG  ---------------------------- */
#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Pos  (0UL)                     /*!< COEX COEX_PRI13_REG: COEX_PRI_PTI (Bit 0)                   */
#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Msk  (0x7UL)                   /*!< COEX COEX_PRI13_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)     */
#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Pos  (3UL)                     /*!< COEX COEX_PRI13_REG: COEX_PRI_MAC (Bit 3)                   */
#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Msk  (0x18UL)                  /*!< COEX COEX_PRI13_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)     */

/* -----------------------------  COEX_COEX_PRI14_REG  ---------------------------- */
#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Pos  (0UL)                     /*!< COEX COEX_PRI14_REG: COEX_PRI_PTI (Bit 0)                   */
#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Msk  (0x7UL)                   /*!< COEX COEX_PRI14_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)     */
#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Pos  (3UL)                     /*!< COEX COEX_PRI14_REG: COEX_PRI_MAC (Bit 3)                   */
#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Msk  (0x18UL)                  /*!< COEX COEX_PRI14_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)     */

/* -----------------------------  COEX_COEX_PRI15_REG  ---------------------------- */
#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Pos  (0UL)                     /*!< COEX COEX_PRI15_REG: COEX_PRI_PTI (Bit 0)                   */
#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Msk  (0x7UL)                   /*!< COEX COEX_PRI15_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)     */
#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Pos  (3UL)                     /*!< COEX COEX_PRI15_REG: COEX_PRI_MAC (Bit 3)                   */
#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Msk  (0x18UL)                  /*!< COEX COEX_PRI15_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)     */


/* ================================================================================ */
/* ================        struct 'CRG_PER' Position & Mask        ================ */
/* ================================================================================ */


/* -----------------------------  CRG_PER_CLK_PER_REG  ---------------------------- */
#define CRG_PER_CLK_PER_REG_UART_ENABLE_Pos   (0UL)                     /*!< CRG_PER CLK_PER_REG: UART_ENABLE (Bit 0)                    */
#define CRG_PER_CLK_PER_REG_UART_ENABLE_Msk   (0x1UL)                   /*!< CRG_PER CLK_PER_REG: UART_ENABLE (Bitfield-Mask: 0x01)      */
#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Pos    (1UL)                     /*!< CRG_PER CLK_PER_REG: SPI_ENABLE (Bit 1)                     */
#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Msk    (0x2UL)                   /*!< CRG_PER CLK_PER_REG: SPI_ENABLE (Bitfield-Mask: 0x01)       */
#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Pos    (2UL)                     /*!< CRG_PER CLK_PER_REG: I2C_ENABLE (Bit 2)                     */
#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Msk    (0x4UL)                   /*!< CRG_PER CLK_PER_REG: I2C_ENABLE (Bitfield-Mask: 0x01)       */
#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Pos   (3UL)                     /*!< CRG_PER CLK_PER_REG: QUAD_ENABLE (Bit 3)                    */
#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Msk   (0x8UL)                   /*!< CRG_PER CLK_PER_REG: QUAD_ENABLE (Bitfield-Mask: 0x01)      */
#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Pos (4UL)                     /*!< CRG_PER CLK_PER_REG: IR_CLK_ENABLE (Bit 4)                  */
#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Msk (0x10UL)                  /*!< CRG_PER CLK_PER_REG: IR_CLK_ENABLE (Bitfield-Mask: 0x01)    */
#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Pos (5UL)                     /*!< CRG_PER CLK_PER_REG: KBSCAN_ENABLE (Bit 5)                  */
#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Msk (0x20UL)                  /*!< CRG_PER CLK_PER_REG: KBSCAN_ENABLE (Bitfield-Mask: 0x01)    */
#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Pos   (8UL)                     /*!< CRG_PER CLK_PER_REG: SPI_CLK_SEL (Bit 8)                    */
#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Msk   (0x100UL)                 /*!< CRG_PER CLK_PER_REG: SPI_CLK_SEL (Bitfield-Mask: 0x01)      */
#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Pos   (9UL)                     /*!< CRG_PER CLK_PER_REG: I2C_CLK_SEL (Bit 9)                    */
#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Msk   (0x200UL)                 /*!< CRG_PER CLK_PER_REG: I2C_CLK_SEL (Bitfield-Mask: 0x01)      */
#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Pos (10UL)                   /*!< CRG_PER CLK_PER_REG: KBSCAN_CLK_SEL (Bit 10)                */
#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Msk (0x400UL)                /*!< CRG_PER CLK_PER_REG: KBSCAN_CLK_SEL (Bitfield-Mask: 0x01)   */
#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Pos   (11UL)                    /*!< CRG_PER CLK_PER_REG: ADC_CLK_SEL (Bit 11)                   */
#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Msk   (0x800UL)                 /*!< CRG_PER CLK_PER_REG: ADC_CLK_SEL (Bitfield-Mask: 0x01)      */

/* -----------------------------  CRG_PER_PCM_DIV_REG  ---------------------------- */
#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos       (0UL)                     /*!< CRG_PER PCM_DIV_REG: PCM_DIV (Bit 0)                        */
#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk       (0xfffUL)                 /*!< CRG_PER PCM_DIV_REG: PCM_DIV (Bitfield-Mask: 0xfff)         */
#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos    (12UL)                    /*!< CRG_PER PCM_DIV_REG: CLK_PCM_EN (Bit 12)                    */
#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk    (0x1000UL)                /*!< CRG_PER PCM_DIV_REG: CLK_PCM_EN (Bitfield-Mask: 0x01)       */
#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos   (13UL)                    /*!< CRG_PER PCM_DIV_REG: PCM_SRC_SEL (Bit 13)                   */
#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk   (0x2000UL)                /*!< CRG_PER PCM_DIV_REG: PCM_SRC_SEL (Bitfield-Mask: 0x01)      */

/* ----------------------------  CRG_PER_PCM_FDIV_REG  ---------------------------- */
#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos     (0UL)                     /*!< CRG_PER PCM_FDIV_REG: PCM_FDIV (Bit 0)                      */
#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk     (0xffffUL)                /*!< CRG_PER PCM_FDIV_REG: PCM_FDIV (Bitfield-Mask: 0xffff)      */

/* -----------------------------  CRG_PER_PDM_DIV_REG  ---------------------------- */
#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos       (0UL)                     /*!< CRG_PER PDM_DIV_REG: PDM_DIV (Bit 0)                        */
#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk       (0xffUL)                  /*!< CRG_PER PDM_DIV_REG: PDM_DIV (Bitfield-Mask: 0xff)          */
#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos    (8UL)                     /*!< CRG_PER PDM_DIV_REG: CLK_PDM_EN (Bit 8)                     */
#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk    (0x100UL)                 /*!< CRG_PER PDM_DIV_REG: CLK_PDM_EN (Bitfield-Mask: 0x01)       */
#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL)                   /*!< CRG_PER PDM_DIV_REG: PDM_MASTER_MODE (Bit 9)                */
#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL)               /*!< CRG_PER PDM_DIV_REG: PDM_MASTER_MODE (Bitfield-Mask: 0x01)  */

/* -----------------------------  CRG_PER_SRC_DIV_REG  ---------------------------- */
#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos       (0UL)                     /*!< CRG_PER SRC_DIV_REG: SRC_DIV (Bit 0)                        */
#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk       (0xffUL)                  /*!< CRG_PER SRC_DIV_REG: SRC_DIV (Bitfield-Mask: 0xff)          */
#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos    (8UL)                     /*!< CRG_PER SRC_DIV_REG: CLK_SRC_EN (Bit 8)                     */
#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk    (0x100UL)                 /*!< CRG_PER SRC_DIV_REG: CLK_SRC_EN (Bitfield-Mask: 0x01)       */

/* -------------------------------  CRG_PER_EH_REG  ------------------------------- */
#define CRG_PER_EH_REG_EH_EN_Pos              (0UL)                     /*!< CRG_PER EH_REG: EH_EN (Bit 0)                               */
#define CRG_PER_EH_REG_EH_EN_Msk              (0x1UL)                   /*!< CRG_PER EH_REG: EH_EN (Bitfield-Mask: 0x01)                 */

/* -----------------------------  CRG_PER_USBPAD_REG  ----------------------------- */
#define CRG_PER_USBPAD_REG_USBPAD_EN_Pos      (0UL)                     /*!< CRG_PER USBPAD_REG: USBPAD_EN (Bit 0)                       */
#define CRG_PER_USBPAD_REG_USBPAD_EN_Msk      (0x1UL)                   /*!< CRG_PER USBPAD_REG: USBPAD_EN (Bitfield-Mask: 0x01)         */
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos (1UL)               /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW1_OFF (Bit 1)            */
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk (0x2UL)             /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW1_OFF (Bitfield-Mask: 0x01) */
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos (2UL)                /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW2_ON (Bit 2)             */
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk (0x4UL)              /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW2_ON (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================        struct 'CRG_TOP' Position & Mask        ================ */
/* ================================================================================ */


/* ----------------------------  CRG_TOP_CLK_AMBA_REG  ---------------------------- */
#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos     (0UL)                     /*!< CRG_TOP CLK_AMBA_REG: HCLK_DIV (Bit 0)                      */
#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk     (0x7UL)                   /*!< CRG_TOP CLK_AMBA_REG: HCLK_DIV (Bitfield-Mask: 0x07)        */
#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos     (4UL)                     /*!< CRG_TOP CLK_AMBA_REG: PCLK_DIV (Bit 4)                      */
#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk     (0x30UL)                  /*!< CRG_TOP CLK_AMBA_REG: PCLK_DIV (Bitfield-Mask: 0x03)        */
#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL)                   /*!< CRG_TOP CLK_AMBA_REG: AES_CLK_ENABLE (Bit 6)                */
#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL)                /*!< CRG_TOP CLK_AMBA_REG: AES_CLK_ENABLE (Bitfield-Mask: 0x01)  */
#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Pos (7UL)                   /*!< CRG_TOP CLK_AMBA_REG: ECC_CLK_ENABLE (Bit 7)                */
#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Msk (0x80UL)                /*!< CRG_TOP CLK_AMBA_REG: ECC_CLK_ENABLE (Bitfield-Mask: 0x01)  */
#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos (8UL)                  /*!< CRG_TOP CLK_AMBA_REG: TRNG_CLK_ENABLE (Bit 8)               */
#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk (0x100UL)              /*!< CRG_TOP CLK_AMBA_REG: TRNG_CLK_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos   (9UL)                     /*!< CRG_TOP CLK_AMBA_REG: OTP_ENABLE (Bit 9)                    */
#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk   (0x200UL)                 /*!< CRG_TOP CLK_AMBA_REG: OTP_ENABLE (Bitfield-Mask: 0x01)      */
#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos     (10UL)                    /*!< CRG_TOP CLK_AMBA_REG: QSPI_DIV (Bit 10)                     */
#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk     (0xc00UL)                 /*!< CRG_TOP CLK_AMBA_REG: QSPI_DIV (Bitfield-Mask: 0x03)        */
#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos  (12UL)                    /*!< CRG_TOP CLK_AMBA_REG: QSPI_ENABLE (Bit 12)                  */
#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk  (0x1000UL)                /*!< CRG_TOP CLK_AMBA_REG: QSPI_ENABLE (Bitfield-Mask: 0x01)     */

/* --------------------------  CRG_TOP_CLK_FREQ_TRIM_REG  ------------------------- */
#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Pos (0UL)                    /*!< CRG_TOP CLK_FREQ_TRIM_REG: FINE_ADJ (Bit 0)                 */
#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Msk (0xffUL)                 /*!< CRG_TOP CLK_FREQ_TRIM_REG: FINE_ADJ (Bitfield-Mask: 0xff)   */
#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Pos (8UL)                  /*!< CRG_TOP CLK_FREQ_TRIM_REG: COARSE_ADJ (Bit 8)               */
#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Msk (0x700UL)              /*!< CRG_TOP CLK_FREQ_TRIM_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */

/* ----------------------------  CRG_TOP_CLK_RADIO_REG  --------------------------- */
#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Pos    (0UL)                     /*!< CRG_TOP CLK_RADIO_REG: RFCU_DIV (Bit 0)                     */
#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Msk    (0x3UL)                   /*!< CRG_TOP CLK_RADIO_REG: RFCU_DIV (Bitfield-Mask: 0x03)       */
#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (3UL)                     /*!< CRG_TOP CLK_RADIO_REG: RFCU_ENABLE (Bit 3)                  */
#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x8UL)                   /*!< CRG_TOP CLK_RADIO_REG: RFCU_ENABLE (Bitfield-Mask: 0x01)    */
#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Pos     (4UL)                     /*!< CRG_TOP CLK_RADIO_REG: BLE_DIV (Bit 4)                      */
#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Msk     (0x30UL)                  /*!< CRG_TOP CLK_RADIO_REG: BLE_DIV (Bitfield-Mask: 0x03)        */
#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Pos (6UL)                    /*!< CRG_TOP CLK_RADIO_REG: BLE_LP_RESET (Bit 6)                 */
#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Msk (0x40UL)                 /*!< CRG_TOP CLK_RADIO_REG: BLE_LP_RESET (Bitfield-Mask: 0x01)   */
#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Pos  (7UL)                     /*!< CRG_TOP CLK_RADIO_REG: BLE_ENABLE (Bit 7)                   */
#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Msk  (0x80UL)                  /*!< CRG_TOP CLK_RADIO_REG: BLE_ENABLE (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Pos (8UL)                    /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_DIV (Bit 8)                 */
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Msk (0x300UL)                /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_DIV (Bitfield-Mask: 0x03)   */
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Pos (11UL)                /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_ENABLE (Bit 11)             */
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Msk (0x800UL)             /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_ENABLE (Bitfield-Mask: 0x01) */

/* ----------------------------  CRG_TOP_CLK_CTRL_REG  ---------------------------- */
#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos  (0UL)                     /*!< CRG_TOP CLK_CTRL_REG: SYS_CLK_SEL (Bit 0)                   */
#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk  (0x3UL)                   /*!< CRG_TOP CLK_CTRL_REG: SYS_CLK_SEL (Bitfield-Mask: 0x03)     */
#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Pos (2UL)                  /*!< CRG_TOP CLK_CTRL_REG: XTAL16M_DISABLE (Bit 2)               */
#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Msk (0x4UL)                /*!< CRG_TOP CLK_CTRL_REG: XTAL16M_DISABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Pos (3UL)                     /*!< CRG_TOP CLK_CTRL_REG: XTAL32M_MODE (Bit 3)                  */
#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Msk (0x8UL)                   /*!< CRG_TOP CLK_CTRL_REG: XTAL32M_MODE (Bitfield-Mask: 0x01)    */
#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos  (4UL)                     /*!< CRG_TOP CLK_CTRL_REG: USB_CLK_SRC (Bit 4)                   */
#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk  (0x10UL)                  /*!< CRG_TOP CLK_CTRL_REG: USB_CLK_SRC (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Pos     (5UL)                     /*!< CRG_TOP CLK_CTRL_REG: PLL_DIV2 (Bit 5)                      */
#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Msk     (0x20UL)                  /*!< CRG_TOP CLK_CTRL_REG: PLL_DIV2 (Bitfield-Mask: 0x01)        */
#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Pos (6UL)                /*!< CRG_TOP CLK_CTRL_REG: DIVN_XTAL32M_MODE (Bit 6)             */
#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Msk (0x40UL)             /*!< CRG_TOP CLK_CTRL_REG: DIVN_XTAL32M_MODE (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Pos (7UL)                  /*!< CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bit 7)               */
#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Msk (0x80UL)               /*!< CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Pos (8UL)                    /*!< CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bit 8)                 */
#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Msk (0x300UL)                /*!< CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bitfield-Mask: 0x03)   */
#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Pos (10UL)                  /*!< CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bit 10)               */
#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Msk (0x400UL)               /*!< CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bitfield-Mask: 0x01)  */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Pos (12UL)                  /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bit 12)               */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Msk (0x1000UL)              /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bitfield-Mask: 0x01)  */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Pos (13UL)                /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bit 13)             */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Msk (0x2000UL)            /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Pos (14UL)              /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_XTAL16M (Bit 14)           */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Msk (0x4000UL)          /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_XTAL16M (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos (15UL)               /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_PLL96M (Bit 15)            */
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk (0x8000UL)           /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_PLL96M (Bitfield-Mask: 0x01) */

/* -----------------------------  CRG_TOP_CLK_TMR_REG  ---------------------------- */
#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Pos      (0UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR0_DIV (Bit 0)                       */
#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk      (0x3UL)                   /*!< CRG_TOP CLK_TMR_REG: TMR0_DIV (Bitfield-Mask: 0x03)         */
#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Pos   (2UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR0_ENABLE (Bit 2)                    */
#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk   (0x4UL)                   /*!< CRG_TOP CLK_TMR_REG: TMR0_ENABLE (Bitfield-Mask: 0x01)      */
#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Pos  (3UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR0_CLK_SEL (Bit 3)                   */
#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk  (0x8UL)                   /*!< CRG_TOP CLK_TMR_REG: TMR0_CLK_SEL (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Pos      (4UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR1_DIV (Bit 4)                       */
#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Msk      (0x30UL)                  /*!< CRG_TOP CLK_TMR_REG: TMR1_DIV (Bitfield-Mask: 0x03)         */
#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Pos   (6UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR1_ENABLE (Bit 6)                    */
#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Msk   (0x40UL)                  /*!< CRG_TOP CLK_TMR_REG: TMR1_ENABLE (Bitfield-Mask: 0x01)      */
#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Pos  (7UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR1_CLK_SEL (Bit 7)                   */
#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Msk  (0x80UL)                  /*!< CRG_TOP CLK_TMR_REG: TMR1_CLK_SEL (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Pos      (8UL)                     /*!< CRG_TOP CLK_TMR_REG: TMR2_DIV (Bit 8)                       */
#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Msk      (0x300UL)                 /*!< CRG_TOP CLK_TMR_REG: TMR2_DIV (Bitfield-Mask: 0x03)         */
#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Pos   (10UL)                    /*!< CRG_TOP CLK_TMR_REG: TMR2_ENABLE (Bit 10)                   */
#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Msk   (0x400UL)                 /*!< CRG_TOP CLK_TMR_REG: TMR2_ENABLE (Bitfield-Mask: 0x01)      */
#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Pos  (11UL)                    /*!< CRG_TOP CLK_TMR_REG: TMR2_CLK_SEL (Bit 11)                  */
#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Msk  (0x800UL)                 /*!< CRG_TOP CLK_TMR_REG: TMR2_CLK_SEL (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Pos (12UL)                    /*!< CRG_TOP CLK_TMR_REG: BREATH_ENABLE (Bit 12)                 */
#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Msk (0x1000UL)                /*!< CRG_TOP CLK_TMR_REG: BREATH_ENABLE (Bitfield-Mask: 0x01)    */
#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (13UL)                  /*!< CRG_TOP CLK_TMR_REG: WAKEUPCT_ENABLE (Bit 13)               */
#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x2000UL)              /*!< CRG_TOP CLK_TMR_REG: WAKEUPCT_ENABLE (Bitfield-Mask: 0x01)  */
#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Pos (14UL)                /*!< CRG_TOP CLK_TMR_REG: P06_TMR1_PWM_MODE (Bit 14)             */
#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Msk (0x4000UL)            /*!< CRG_TOP CLK_TMR_REG: P06_TMR1_PWM_MODE (Bitfield-Mask: 0x01) */

/* ----------------------------  CRG_TOP_PMU_CTRL_REG  ---------------------------- */
#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL)                     /*!< CRG_TOP PMU_CTRL_REG: PERIPH_SLEEP (Bit 0)                  */
#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL)                   /*!< CRG_TOP PMU_CTRL_REG: PERIPH_SLEEP (Bitfield-Mask: 0x01)    */
#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos  (1UL)                     /*!< CRG_TOP PMU_CTRL_REG: RADIO_SLEEP (Bit 1)                   */
#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk  (0x2UL)                   /*!< CRG_TOP PMU_CTRL_REG: RADIO_SLEEP (Bitfield-Mask: 0x01)     */
#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos    (2UL)                     /*!< CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bit 2)                     */
#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Msk    (0x4UL)                   /*!< CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bitfield-Mask: 0x01)       */
#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos   (3UL)                     /*!< CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bit 3)                    */
#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Msk   (0x8UL)                   /*!< CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bitfield-Mask: 0x01)      */
#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL)                   /*!< CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bit 4)                */
#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL)                /*!< CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bitfield-Mask: 0x01)  */
#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL)                  /*!< CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bit 5)               */
#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL)               /*!< CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bitfield-Mask: 0x01) */
#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Pos (6UL)                     /*!< CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bit 6)                  */
#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Msk (0xc0UL)                  /*!< CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bitfield-Mask: 0x03)    */
#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Pos   (8UL)                     /*!< CRG_TOP PMU_CTRL_REG: RETAIN_RAM (Bit 8)                    */
#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Msk   (0x1f00UL)                /*!< CRG_TOP PMU_CTRL_REG: RETAIN_RAM (Bitfield-Mask: 0x1f)      */
#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos (13UL)                  /*!< CRG_TOP PMU_CTRL_REG: ENABLE_CLKLESS (Bit 13)               */
#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk (0x2000UL)              /*!< CRG_TOP PMU_CTRL_REG: ENABLE_CLKLESS (Bitfield-Mask: 0x01)  */
#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (14UL)                    /*!< CRG_TOP PMU_CTRL_REG: RETAIN_CACHE (Bit 14)                 */
#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x4000UL)                /*!< CRG_TOP PMU_CTRL_REG: RETAIN_CACHE (Bitfield-Mask: 0x01)    */
#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Pos (15UL)                   /*!< CRG_TOP PMU_CTRL_REG: RETAIN_ECCRAM (Bit 15)                */
#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Msk (0x8000UL)               /*!< CRG_TOP PMU_CTRL_REG: RETAIN_ECCRAM (Bitfield-Mask: 0x01)   */

/* ----------------------------  CRG_TOP_SYS_CTRL_REG  ---------------------------- */
#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos   (0UL)                     /*!< CRG_TOP SYS_CTRL_REG: REMAP_ADR0 (Bit 0)                    */
#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk   (0x7UL)                   /*!< CRG_TOP SYS_CTRL_REG: REMAP_ADR0 (Bitfield-Mask: 0x07)      */
#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Pos   (3UL)                     /*!< CRG_TOP SYS_CTRL_REG: REMAP_RAMS (Bit 3)                    */
#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Msk   (0x18UL)                  /*!< CRG_TOP SYS_CTRL_REG: REMAP_RAMS (Bitfield-Mask: 0x03)      */
#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Pos (5UL)                     /*!< CRG_TOP SYS_CTRL_REG: PAD_LATCH_EN (Bit 5)                  */
#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Msk (0x20UL)                  /*!< CRG_TOP SYS_CTRL_REG: PAD_LATCH_EN (Bitfield-Mask: 0x01)    */
#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Pos (6UL)                   /*!< CRG_TOP SYS_CTRL_REG: OTPC_RESET_REQ (Bit 6)                */
#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Msk (0x40UL)                /*!< CRG_TOP SYS_CTRL_REG: OTPC_RESET_REQ (Bitfield-Mask: 0x01)  */
#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL)                  /*!< CRG_TOP SYS_CTRL_REG: DEBUGGER_ENABLE (Bit 7)               */
#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL)               /*!< CRG_TOP SYS_CTRL_REG: DEBUGGER_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Pos      (8UL)                     /*!< CRG_TOP SYS_CTRL_REG: DRA_OFF (Bit 8)                       */
#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Msk      (0x100UL)                 /*!< CRG_TOP SYS_CTRL_REG: DRA_OFF (Bitfield-Mask: 0x01)         */
#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos (9UL)                  /*!< CRG_TOP SYS_CTRL_REG: TIMEOUT_DISABLE (Bit 9)               */
#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk (0x200UL)              /*!< CRG_TOP SYS_CTRL_REG: TIMEOUT_DISABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL)                    /*!< CRG_TOP SYS_CTRL_REG: CACHERAM_MUX (Bit 10)                 */
#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL)                 /*!< CRG_TOP SYS_CTRL_REG: CACHERAM_MUX (Bitfield-Mask: 0x01)    */
#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Pos    (11UL)                    /*!< CRG_TOP SYS_CTRL_REG: DEV_PHASE (Bit 11)                    */
#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Msk    (0x800UL)                 /*!< CRG_TOP SYS_CTRL_REG: DEV_PHASE (Bitfield-Mask: 0x01)       */
#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos    (12UL)                    /*!< CRG_TOP SYS_CTRL_REG: QSPI_INIT (Bit 12)                    */
#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk    (0x1000UL)                /*!< CRG_TOP SYS_CTRL_REG: QSPI_INIT (Bitfield-Mask: 0x01)       */
#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Pos     (13UL)                    /*!< CRG_TOP SYS_CTRL_REG: OTP_COPY (Bit 13)                     */
#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Msk     (0x2000UL)                /*!< CRG_TOP SYS_CTRL_REG: OTP_COPY (Bitfield-Mask: 0x01)        */
#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (14UL)                   /*!< CRG_TOP SYS_CTRL_REG: REMAP_INTVECT (Bit 14)                */
#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x4000UL)               /*!< CRG_TOP SYS_CTRL_REG: REMAP_INTVECT (Bitfield-Mask: 0x01)   */
#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos     (15UL)                    /*!< CRG_TOP SYS_CTRL_REG: SW_RESET (Bit 15)                     */
#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk     (0x8000UL)                /*!< CRG_TOP SYS_CTRL_REG: SW_RESET (Bitfield-Mask: 0x01)        */

/* ----------------------------  CRG_TOP_SYS_STAT_REG  ---------------------------- */
#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos  (0UL)                     /*!< CRG_TOP SYS_STAT_REG: RAD_IS_DOWN (Bit 0)                   */
#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk  (0x1UL)                   /*!< CRG_TOP SYS_STAT_REG: RAD_IS_DOWN (Bitfield-Mask: 0x01)     */
#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos    (1UL)                     /*!< CRG_TOP SYS_STAT_REG: RAD_IS_UP (Bit 1)                     */
#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk    (0x2UL)                   /*!< CRG_TOP SYS_STAT_REG: RAD_IS_UP (Bitfield-Mask: 0x01)       */
#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos  (2UL)                     /*!< CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bit 2)                   */
#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk  (0x4UL)                   /*!< CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bitfield-Mask: 0x01)     */
#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos    (3UL)                     /*!< CRG_TOP SYS_STAT_REG: PER_IS_UP (Bit 3)                     */
#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk    (0x8UL)                   /*!< CRG_TOP SYS_STAT_REG: PER_IS_UP (Bitfield-Mask: 0x01)       */
#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Pos   (4UL)                     /*!< CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bit 4)                    */
#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Msk   (0x10UL)                  /*!< CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bitfield-Mask: 0x01)      */
#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (5UL)                    /*!< CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bit 5)                 */
#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x20UL)                 /*!< CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bitfield-Mask: 0x01)   */
#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Pos (6UL)                /*!< CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bit 6)             */
#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Msk (0x40UL)             /*!< CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bitfield-Mask: 0x01) */
#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Pos (7UL)              /*!< CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bit 7)           */
#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Msk (0x80UL)           /*!< CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bitfield-Mask: 0x01) */
#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Pos  (8UL)                     /*!< CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bit 8)                   */
#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Msk  (0x100UL)                 /*!< CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bitfield-Mask: 0x01)     */
#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Pos    (9UL)                     /*!< CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bit 9)                     */
#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Msk    (0x200UL)                 /*!< CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bitfield-Mask: 0x01)       */
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Pos (10UL)                    /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_DOWN (Bit 10)                 */
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Msk (0x400UL)                 /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_DOWN (Bitfield-Mask: 0x01)    */
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Pos   (11UL)                    /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_UP (Bit 11)                   */
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Msk   (0x800UL)                 /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_UP (Bitfield-Mask: 0x01)      */

/* ----------------------------  CRG_TOP_TRIM_CTRL_REG  --------------------------- */
#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Pos (0UL)                    /*!< CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bit 0)                 */
#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Msk (0x3fUL)                 /*!< CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bitfield-Mask: 0x3f)   */
#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos (6UL)                /*!< CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bit 6)             */
#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk (0xc0UL)             /*!< CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bitfield-Mask: 0x03) */
#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos (8UL)                   /*!< CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bit 8)                */
#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk (0x3f00UL)              /*!< CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bitfield-Mask: 0x3f)  */

/* -----------------------------  CRG_TOP_CLK_32K_REG  ---------------------------- */
#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Pos (0UL)                    /*!< CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bit 0)                 */
#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Msk (0x1UL)                  /*!< CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bitfield-Mask: 0x01)   */
#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Pos (1UL)                     /*!< CRG_TOP CLK_32K_REG: XTAL32K_RBIAS (Bit 1)                  */
#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Msk (0x6UL)                   /*!< CRG_TOP CLK_32K_REG: XTAL32K_RBIAS (Bitfield-Mask: 0x03)    */
#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Pos   (3UL)                     /*!< CRG_TOP CLK_32K_REG: XTAL32K_CUR (Bit 3)                    */
#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Msk   (0x78UL)                  /*!< CRG_TOP CLK_32K_REG: XTAL32K_CUR (Bitfield-Mask: 0x0f)      */
#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Pos  (7UL)                     /*!< CRG_TOP CLK_32K_REG: RC32K_ENABLE (Bit 7)                   */
#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Msk  (0x80UL)                  /*!< CRG_TOP CLK_32K_REG: RC32K_ENABLE (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Pos    (8UL)                     /*!< CRG_TOP CLK_32K_REG: RC32K_TRIM (Bit 8)                     */
#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Msk    (0xf00UL)                 /*!< CRG_TOP CLK_32K_REG: RC32K_TRIM (Bitfield-Mask: 0x0f)       */
#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Pos (12UL)           /*!< CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bit 12)        */
#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x1000UL)       /*!< CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Pos (13UL)       /*!< CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bit 13)    */
#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Msk (0x2000UL)   /*!< CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bitfield-Mask: 0x01) */

/* -----------------------------  CRG_TOP_CLK_16M_REG  ---------------------------- */
#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Pos  (0UL)                     /*!< CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bit 0)                   */
#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk  (0x1UL)                   /*!< CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bitfield-Mask: 0x01)     */
#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Pos    (1UL)                     /*!< CRG_TOP CLK_16M_REG: RC16M_TRIM (Bit 1)                     */
#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Msk    (0x1eUL)                  /*!< CRG_TOP CLK_16M_REG: RC16M_TRIM (Bitfield-Mask: 0x0f)       */
#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Pos (5UL)                    /*!< CRG_TOP CLK_16M_REG: XTAL16_CUR_SET (Bit 5)                 */
#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Msk (0xe0UL)                 /*!< CRG_TOP CLK_16M_REG: XTAL16_CUR_SET (Bitfield-Mask: 0x07)   */
#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Pos (8UL)                /*!< CRG_TOP CLK_16M_REG: XTAL16_MAX_CURRENT (Bit 8)             */
#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Msk (0x100UL)            /*!< CRG_TOP CLK_16M_REG: XTAL16_MAX_CURRENT (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Pos (9UL)             /*!< CRG_TOP CLK_16M_REG: XTAL16_EXT_CLK_ENABLE (Bit 9)          */
#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Msk (0x200UL)         /*!< CRG_TOP CLK_16M_REG: XTAL16_EXT_CLK_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Pos (10UL)                  /*!< CRG_TOP CLK_16M_REG: XTAL16_AMP_TRIM (Bit 10)               */
#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Msk (0x1c00UL)              /*!< CRG_TOP CLK_16M_REG: XTAL16_AMP_TRIM (Bitfield-Mask: 0x07)  */
#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Pos (13UL)          /*!< CRG_TOP CLK_16M_REG: XTAL16_SPIKE_FLT_BYPASS (Bit 13)       */
#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Msk (0x2000UL)      /*!< CRG_TOP CLK_16M_REG: XTAL16_SPIKE_FLT_BYPASS (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Pos (14UL)              /*!< CRG_TOP CLK_16M_REG: XTAL16_HPASS_FLT_EN (Bit 14)           */
#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Msk (0x4000UL)          /*!< CRG_TOP CLK_16M_REG: XTAL16_HPASS_FLT_EN (Bitfield-Mask: 0x01) */
#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Pos (15UL)            /*!< CRG_TOP CLK_16M_REG: RC16M_STARTUP_DISABLE (Bit 15)         */
#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Msk (0x8000UL)        /*!< CRG_TOP CLK_16M_REG: RC16M_STARTUP_DISABLE (Bitfield-Mask: 0x01) */

/* ---------------------------  CRG_TOP_CLK_RCX20K_REG  --------------------------- */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Pos (0UL)                    /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_TRIM (Bit 0)                 */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Msk (0xfUL)                  /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_TRIM (Bitfield-Mask: 0x0f)   */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Pos (4UL)                     /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_NTC (Bit 4)                  */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Msk (0xf0UL)                  /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_NTC (Bitfield-Mask: 0x0f)    */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Pos (8UL)                    /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_BIAS (Bit 8)                 */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Msk (0x300UL)                /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_BIAS (Bitfield-Mask: 0x03)   */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Pos (10UL)                   /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_LOWF (Bit 10)                */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Msk (0x400UL)                /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_LOWF (Bitfield-Mask: 0x01)   */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Pos (11UL)                 /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_ENABLE (Bit 11)              */
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Msk (0x800UL)              /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_ENABLE (Bitfield-Mask: 0x01) */

/* -----------------------------  CRG_TOP_BANDGAP_REG  ---------------------------- */
#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos      (0UL)                     /*!< CRG_TOP BANDGAP_REG: BGR_TRIM (Bit 0)                       */
#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk      (0x1fUL)                  /*!< CRG_TOP BANDGAP_REG: BGR_TRIM (Bitfield-Mask: 0x1f)         */
#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos     (5UL)                     /*!< CRG_TOP BANDGAP_REG: BGR_ITRIM (Bit 5)                      */
#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk     (0x3e0UL)                 /*!< CRG_TOP BANDGAP_REG: BGR_ITRIM (Bitfield-Mask: 0x1f)        */
#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Pos (10UL)                   /*!< CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bit 10)                */
#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Msk (0x3c00UL)               /*!< CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bitfield-Mask: 0x0f)   */
#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Pos (14UL)             /*!< CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bit 14)          */
#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Msk (0x4000UL)         /*!< CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bitfield-Mask: 0x01) */

/* ---------------------------  CRG_TOP_ANA_STATUS_REG  --------------------------- */
#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos (0UL)                   /*!< CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bit 0)                */
#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk (0x1UL)                 /*!< CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bitfield-Mask: 0x01)  */
#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Pos (1UL)                   /*!< CRG_TOP ANA_STATUS_REG: COMP_VBAT_OK (Bit 1)                */
#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Msk (0x2UL)                 /*!< CRG_TOP ANA_STATUS_REG: COMP_VBAT_OK (Bitfield-Mask: 0x01)  */
#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos (2UL)                 /*!< CRG_TOP ANA_STATUS_REG: VBUS_AVAILABLE (Bit 2)              */
#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk (0x4UL)               /*!< CRG_TOP ANA_STATUS_REG: VBUS_AVAILABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Pos     (3UL)                     /*!< CRG_TOP ANA_STATUS_REG: NEWBAT (Bit 3)                      */
#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Msk     (0x8UL)                   /*!< CRG_TOP ANA_STATUS_REG: NEWBAT (Bitfield-Mask: 0x01)        */
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Pos (4UL)             /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_VBAT_OK (Bit 4)          */
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Msk (0x10UL)          /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Pos (5UL)              /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_USB_OK (Bit 5)           */
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Msk (0x20UL)           /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_USB_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (6UL)                     /*!< CRG_TOP ANA_STATUS_REG: BANDGAP_OK (Bit 6)                  */
#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x40UL)                  /*!< CRG_TOP ANA_STATUS_REG: BANDGAP_OK (Bitfield-Mask: 0x01)    */
#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Pos (7UL)                  /*!< CRG_TOP ANA_STATUS_REG: COMP_VDD_HIGH (Bit 7)               */
#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Msk (0x80UL)               /*!< CRG_TOP ANA_STATUS_REG: COMP_VDD_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (8UL)                    /*!< CRG_TOP ANA_STATUS_REG: LDO_CORE_OK (Bit 8)                 */
#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x100UL)                /*!< CRG_TOP ANA_STATUS_REG: LDO_CORE_OK (Bitfield-Mask: 0x01)   */
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Pos (9UL)                  /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_PA_OK (Bit 9)               */
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Msk (0x200UL)              /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_PA_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Pos (10UL)              /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_FLASH_OK (Bit 10)           */
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Msk (0x400UL)           /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos (11UL)                /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_HIGH (Bit 11)             */
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk (0x800UL)             /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos (12UL)                 /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_LOW (Bit 12)              */
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk (0x1000UL)             /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_LOW (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Pos (13UL)                 /*!< CRG_TOP ANA_STATUS_REG: COMP_V33_HIGH (Bit 13)              */
#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Msk (0x2000UL)             /*!< CRG_TOP ANA_STATUS_REG: COMP_V33_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Pos (14UL)           /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_FLASH_HIGH (Bit 14)        */
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Msk (0x4000UL)       /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Pos (15UL)              /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_PA_HIGH (Bit 15)           */
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Msk (0x8000UL)          /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01) */

/* -------------------------  CRG_TOP_STARTUP_STATUS_REG  ------------------------- */
#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Pos (0UL)              /*!< CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bit 0)           */
#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Msk (0x1UL)            /*!< CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos (1UL)                  /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bit 1)               */
#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk (0x2UL)                /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Pos (2UL)      /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bit 2)   */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Msk (0x4UL)    /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Pos (3UL)       /*!< CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bit 3)    */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Msk (0x8UL)     /*!< CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Pos (4UL)             /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_CORE_OK (Bit 4)          */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Msk (0x10UL)          /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_CORE_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Pos (5UL)           /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_PA_OK (Bit 5)        */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Msk (0x20UL)        /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_PA_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Pos (6UL)           /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VDD_HIGH (Bit 6)        */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Msk (0x40UL)        /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VDD_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Pos (7UL)           /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_V33_HIGH (Bit 7)        */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Msk (0x80UL)        /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_V33_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Pos (8UL)          /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_HIGH (Bit 8)       */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Msk (0x100UL)      /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Pos (9UL)           /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_LOW (Bit 9)        */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Msk (0x200UL)       /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_LOW (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Pos (10UL)       /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bit 10)    */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Msk (0x400UL)    /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Pos (11UL)    /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bit 11) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Msk (0x800UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos (12UL)       /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bit 12)    */
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk (0x1000UL)   /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01) */
#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Pos (13UL)             /*!< CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bit 13)          */
#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Msk (0xe000UL)         /*!< CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bitfield-Mask: 0x07) */

/* --------------------------  CRG_TOP_VBUS_IRQ_MASK_REG  ------------------------- */
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos (0UL)            /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bit 0)         */
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk (0x1UL)          /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bitfield-Mask: 0x01) */
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos (1UL)            /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_RISE (Bit 1)         */
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk (0x2UL)          /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_RISE (Bitfield-Mask: 0x01) */

/* -------------------------  CRG_TOP_VBUS_IRQ_CLEAR_REG  ------------------------- */
#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos (0UL)             /*!< CRG_TOP VBUS_IRQ_CLEAR_REG: VBUS_IRQ_CLEAR (Bit 0)          */
#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk (0xffffUL)        /*!< CRG_TOP VBUS_IRQ_CLEAR_REG: VBUS_IRQ_CLEAR (Bitfield-Mask: 0xffff) */

/* ----------------------------  CRG_TOP_BOD_CTRL_REG  ---------------------------- */
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Pos (0UL)                     /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bit 0)                  */
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Msk (0x3UL)                   /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bitfield-Mask: 0x03)    */
#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Pos (2UL)                     /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bit 2)                  */
#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Msk (0xcUL)                   /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bitfield-Mask: 0x03)    */
#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Pos (4UL)                     /*!< CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bit 4)                  */
#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Msk (0x30UL)                  /*!< CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bitfield-Mask: 0x03)    */
#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Pos (6UL)                     /*!< CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bit 6)                  */
#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Msk (0xc0UL)                  /*!< CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bitfield-Mask: 0x03)    */
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Pos  (8UL)                     /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bit 8)                   */
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Msk  (0x700UL)                 /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bitfield-Mask: 0x07)     */

/* ----------------------------  CRG_TOP_BOD_CTRL2_REG  --------------------------- */
#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Pos (0UL)                    /*!< CRG_TOP BOD_CTRL2_REG: BOD_RESET_EN (Bit 0)                 */
#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Msk (0x1UL)                  /*!< CRG_TOP BOD_CTRL2_REG: BOD_RESET_EN (Bitfield-Mask: 0x01)   */
#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Pos  (1UL)                     /*!< CRG_TOP BOD_CTRL2_REG: BOD_VDD_EN (Bit 1)                   */
#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Msk  (0x2UL)                   /*!< CRG_TOP BOD_CTRL2_REG: BOD_VDD_EN (Bitfield-Mask: 0x01)     */
#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Pos  (2UL)                     /*!< CRG_TOP BOD_CTRL2_REG: BOD_V33_EN (Bit 2)                   */
#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Msk  (0x4UL)                   /*!< CRG_TOP BOD_CTRL2_REG: BOD_V33_EN (Bitfield-Mask: 0x01)     */
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Pos (3UL)                   /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_PA_EN (Bit 3)                */
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Msk (0x8UL)                 /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_PA_EN (Bitfield-Mask: 0x01)  */
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Pos (4UL)                /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bit 4)             */
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Msk (0x10UL)             /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bitfield-Mask: 0x01) */
#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Pos (5UL)                     /*!< CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bit 5)                  */
#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Msk (0x20UL)                  /*!< CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bitfield-Mask: 0x01)    */
#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Pos  (6UL)                     /*!< CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bit 6)                   */
#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Msk  (0x40UL)                  /*!< CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bitfield-Mask: 0x01)     */

/* ---------------------------  CRG_TOP_BOD_STATUS_REG  --------------------------- */
#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Pos (0UL)                    /*!< CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bit 0)                 */
#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Msk (0x1UL)                  /*!< CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bitfield-Mask: 0x01)   */
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Pos (1UL)                 /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_PA_LOW (Bit 1)              */
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Msk (0x2UL)               /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_PA_LOW (Bitfield-Mask: 0x01) */
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Pos (2UL)              /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_FLASH_LOW (Bit 2)           */
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Msk (0x4UL)            /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_FLASH_LOW (Bitfield-Mask: 0x01) */
#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Pos (3UL)                    /*!< CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bit 3)                 */
#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Msk (0x8UL)                  /*!< CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bitfield-Mask: 0x01)   */
#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Pos (4UL)                   /*!< CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bit 4)                */
#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Msk (0x10UL)                /*!< CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bitfield-Mask: 0x01)  */
#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Pos (5UL)                    /*!< CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bit 5)                 */
#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Msk (0x20UL)                 /*!< CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bitfield-Mask: 0x01)   */

/* ----------------------------  CRG_TOP_LDO_CTRL1_REG  --------------------------- */
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Pos (0UL)                 /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bit 0)              */
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Msk (0x3UL)               /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bitfield-Mask: 0x03) */
#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Pos (2UL)              /*!< CRG_TOP LDO_CTRL1_REG: LDO_VBAT_RET_LEVEL (Bit 2)           */
#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Msk (0xcUL)            /*!< CRG_TOP LDO_CTRL1_REG: LDO_VBAT_RET_LEVEL (Bitfield-Mask: 0x03) */
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Pos (4UL)           /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_VBAT_LEVEL (Bit 4)        */
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Msk (0x30UL)        /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_VBAT_LEVEL (Bitfield-Mask: 0x03) */
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Pos (6UL)            /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_USB_LEVEL (Bit 6)         */
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Msk (0xc0UL)         /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_USB_LEVEL (Bitfield-Mask: 0x03) */
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Pos (8UL)                 /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_SETVDD (Bit 8)              */
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Msk (0x700UL)             /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_SETVDD (Bitfield-Mask: 0x07) */
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Pos (11UL)               /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_SETVDD (Bit 11)            */
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Msk (0x3800UL)           /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_SETVDD (Bitfield-Mask: 0x07) */
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Pos (14UL)               /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_ENABLE (Bit 14)            */
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Msk (0x4000UL)           /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_ENABLE (Bitfield-Mask: 0x01) */

/* ----------------------------  CRG_TOP_LDO_CTRL2_REG  --------------------------- */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Pos  (0UL)                     /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V2_ON (Bit 0)                   */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Msk  (0x1UL)                   /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V2_ON (Bitfield-Mask: 0x01)     */
#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Pos  (1UL)                     /*!< CRG_TOP LDO_CTRL2_REG: LDO_3V3_ON (Bit 1)                   */
#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Msk  (0x2UL)                   /*!< CRG_TOP LDO_CTRL2_REG: LDO_3V3_ON (Bitfield-Mask: 0x01)     */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Pos (2UL)                /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_ON (Bit 2)             */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Msk (0x4UL)              /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_ON (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Pos (3UL)                   /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_ON (Bit 3)                */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Msk (0x8UL)                 /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_ON (Bitfield-Mask: 0x01)  */
#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Pos (4UL)            /*!< CRG_TOP LDO_CTRL2_REG: LDO_VBAT_RET_DISABLE (Bit 4)         */
#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Msk (0x10UL)         /*!< CRG_TOP LDO_CTRL2_REG: LDO_VBAT_RET_DISABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Pos (5UL)       /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_RET_DISABLE (Bit 5)    */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Msk (0x20UL)    /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_RET_DISABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Pos (6UL)          /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_RET_DISABLE (Bit 6)       */
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Msk (0x40UL)       /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_RET_DISABLE (Bitfield-Mask: 0x01) */

/* ---------------------------  CRG_TOP_SLEEP_TIMER_REG  -------------------------- */
#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Pos (0UL)                   /*!< CRG_TOP SLEEP_TIMER_REG: SLEEP_TIMER (Bit 0)                */
#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Msk (0xffffUL)              /*!< CRG_TOP SLEEP_TIMER_REG: SLEEP_TIMER (Bitfield-Mask: 0xffff) */

/* ---------------------------  CRG_TOP_POWER_CTRL_REG  --------------------------- */
#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Pos (0UL)                    /*!< CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bit 0)                 */
#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Msk (0x7UL)                  /*!< CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bitfield-Mask: 0x07)   */

/* --------------------------  CRG_TOP_POR_VBAT_CTRL_REG  ------------------------- */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos (0UL)          /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bit 0)       */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk (0xfUL)        /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f) */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos (4UL)         /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bit 4)      */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk (0xf0UL)      /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f) */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos (8UL)           /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bit 8)        */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk (0xf00UL)       /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f) */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos (12UL)            /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bit 12)         */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk (0x1000UL)        /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos (13UL)            /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bit 13)         */
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk (0x2000UL)        /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bitfield-Mask: 0x01) */

/* --------------------------  CRG_TOP_XTALRDY_CTRL_REG  -------------------------- */
#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos (0UL)                  /*!< CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bit 0)               */
#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk (0xffUL)               /*!< CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bitfield-Mask: 0xff) */

/* --------------------------  CRG_TOP_XTALRDY_STAT_REG  -------------------------- */
#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Pos (0UL)                 /*!< CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bit 0)              */
#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Msk (0xffUL)              /*!< CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bitfield-Mask: 0xff) */

/* ----------------------------  CRG_TOP_LDO_CTRL3_REG  --------------------------- */
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Pos (0UL)             /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bit 0)          */
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Msk (0x1UL)           /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Pos (1UL)          /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bit 1)       */
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Msk (0x2UL)        /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Pos (2UL)        /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bit 2)     */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Msk (0x4UL)      /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Pos (3UL)     /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bit 3)  */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Msk (0x8UL)   /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Pos (4UL)           /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bit 4)        */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Msk (0x10UL)        /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos (5UL)        /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bit 5)     */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk (0x20UL)     /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bitfield-Mask: 0x01) */

/* --------------------------  CRG_TOP_XTAL16M_START_REG  ------------------------- */
#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos (0UL)                    /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bit 0)                 */
#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk (0xffUL)                 /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bitfield-Mask: 0xff)   */
#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Pos (8UL)                  /*!< CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bit 8)               */
#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Msk (0x700UL)              /*!< CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */

/* --------------------------  CRG_TOP_XTAL16M_RAMP_REG  -------------------------- */
#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Pos (0UL)                     /*!< CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bit 0)                  */
#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Msk (0xffUL)                  /*!< CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bitfield-Mask: 0xff)    */
#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Pos (8UL)                   /*!< CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bit 8)                */
#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Msk (0x700UL)               /*!< CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bitfield-Mask: 0x07)  */

/* -------------------------  CRG_TOP_XTAL16M_TRSTAT_REG  ------------------------- */
#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Pos (0UL)             /*!< CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bit 0)          */
#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Msk (0x7fffUL)        /*!< CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bitfield-Mask: 0x7fff) */

/* ---------------------------  CRG_TOP_RESET_STAT_REG  --------------------------- */
#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL)                   /*!< CRG_TOP RESET_STAT_REG: PORESET_STAT (Bit 0)                */
#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL)                 /*!< CRG_TOP RESET_STAT_REG: PORESET_STAT (Bitfield-Mask: 0x01)  */
#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL)                   /*!< CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bit 1)                */
#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL)                 /*!< CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bitfield-Mask: 0x01)  */
#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL)                   /*!< CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bit 2)                */
#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL)                 /*!< CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bitfield-Mask: 0x01)  */
#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL)                 /*!< CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bit 3)              */
#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL)               /*!< CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bitfield-Mask: 0x01) */
#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL)               /*!< CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bit 4)            */
#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL)            /*!< CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bitfield-Mask: 0x01) */

/* ---------------------------  CRG_TOP_FORCE_SLEEP_REG  -------------------------- */
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Pos (0UL)              /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bit 0)           */
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Msk (0x1UL)            /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bitfield-Mask: 0x01) */
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Pos (1UL)               /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_BLE_SLEEP (Bit 1)            */
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Msk (0x2UL)             /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_BLE_SLEEP (Bitfield-Mask: 0x01) */

/* --------------------------  CRG_TOP_LDOS_DISABLE_REG  -------------------------- */
#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Pos (0UL)                 /*!< CRG_TOP LDOS_DISABLE_REG: LDOS_DISABLE (Bit 0)              */
#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Msk (0x1UL)               /*!< CRG_TOP LDOS_DISABLE_REG: LDOS_DISABLE (Bitfield-Mask: 0x01) */

/* ----------------------------  CRG_TOP_AON_SPARE_REG  --------------------------- */
#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Pos (0UL)              /*!< CRG_TOP AON_SPARE_REG: OSC16_HOLD_AMP_REG (Bit 0)           */
#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Msk (0x1UL)            /*!< CRG_TOP AON_SPARE_REG: OSC16_HOLD_AMP_REG (Bitfield-Mask: 0x01) */
#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Pos (1UL)                /*!< CRG_TOP AON_SPARE_REG: OSC16_SH_DISABLE (Bit 1)             */
#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Msk (0x2UL)              /*!< CRG_TOP AON_SPARE_REG: OSC16_SH_DISABLE (Bitfield-Mask: 0x01) */
#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Pos (2UL)                   /*!< CRG_TOP AON_SPARE_REG: EN_BATSYS_RET (Bit 2)                */
#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Msk (0x4UL)                 /*!< CRG_TOP AON_SPARE_REG: EN_BATSYS_RET (Bitfield-Mask: 0x01)  */
#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Pos (3UL)                   /*!< CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bit 3)                */
#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Msk (0x8UL)                 /*!< CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bitfield-Mask: 0x01)  */

/* ---------------------------  CRG_TOP_SECURE_BOOT_REG  -------------------------- */
#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (0UL)                   /*!< CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bit 0)                */
#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x1UL)                 /*!< CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bitfield-Mask: 0x01)  */
#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos (1UL)            /*!< CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bit 1)         */
#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk (0x2UL)          /*!< CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01) */

/* -------------------------  CRG_TOP_PMU_RESET_RAIL_REG  ------------------------- */
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Pos (0UL)                  /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bit 0)               */
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Msk (0x1UL)                /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01) */
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Pos (1UL)                  /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bit 1)               */
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Msk (0x2UL)                /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01) */
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Pos (2UL)                 /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bit 2)              */
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Msk (0x4UL)               /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01) */

/* -------------------------  CRG_TOP_DISCHARGE_RAIL_REG  ------------------------- */
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos (0UL)                  /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bit 0)               */
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk (0x1UL)                /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01) */
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos (1UL)                  /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bit 1)               */
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk (0x2UL)                /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01) */
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos (2UL)                 /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bit 2)              */
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk (0x4UL)               /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================          struct 'DCDC' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------  DCDC_DCDC_CTRL_0_REG  ---------------------------- */
#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Pos    (0UL)                     /*!< DCDC DCDC_CTRL_0_REG: DCDC_MODE (Bit 0)                     */
#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Msk    (0x3UL)                   /*!< DCDC DCDC_CTRL_0_REG: DCDC_MODE (Bitfield-Mask: 0x03)       */
#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Pos (2UL)                   /*!< DCDC DCDC_CTRL_0_REG: DCDC_FW_ENABLE (Bit 2)                */
#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Msk (0x4UL)                 /*!< DCDC DCDC_CTRL_0_REG: DCDC_FW_ENABLE (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Pos (3UL)                    /*!< DCDC DCDC_CTRL_0_REG: DCDC_PRIORITY (Bit 3)                 */
#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Msk (0x7f8UL)                /*!< DCDC DCDC_CTRL_0_REG: DCDC_PRIORITY (Bitfield-Mask: 0xff)   */
#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Pos (11UL)               /*!< DCDC DCDC_CTRL_0_REG: DCDC_IDLE_CLK_DIV (Bit 11)            */
#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Msk (0x1800UL)           /*!< DCDC DCDC_CTRL_0_REG: DCDC_IDLE_CLK_DIV (Bitfield-Mask: 0x03) */
#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Pos (13UL)           /*!< DCDC DCDC_CTRL_0_REG: DCDC_BROWNOUT_LV_MODE (Bit 13)        */
#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Msk (0x2000UL)       /*!< DCDC DCDC_CTRL_0_REG: DCDC_BROWNOUT_LV_MODE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Pos (14UL)               /*!< DCDC DCDC_CTRL_0_REG: DCDC_FAST_STARTUP (Bit 14)            */
#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Msk (0x4000UL)           /*!< DCDC DCDC_CTRL_0_REG: DCDC_FAST_STARTUP (Bitfield-Mask: 0x01) */

/* ----------------------------  DCDC_DCDC_CTRL_1_REG  ---------------------------- */
#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Pos (0UL)                     /*!< DCDC DCDC_CTRL_1_REG: DCDC_TIMEOUT (Bit 0)                  */
#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Msk (0x1fUL)                  /*!< DCDC DCDC_CTRL_1_REG: DCDC_TIMEOUT (Bitfield-Mask: 0x1f)    */
#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Pos (5UL)        /*!< DCDC DCDC_CTRL_1_REG: DCDC_GLOBAL_MAX_IDLE_TIME (Bit 5)     */
#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Msk (0x7e0UL)    /*!< DCDC DCDC_CTRL_1_REG: DCDC_GLOBAL_MAX_IDLE_TIME (Bitfield-Mask: 0x3f) */
#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Pos (11UL)              /*!< DCDC DCDC_CTRL_1_REG: DCDC_STARTUP_DELAY (Bit 11)           */
#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Msk (0xf800UL)          /*!< DCDC DCDC_CTRL_1_REG: DCDC_STARTUP_DELAY (Bitfield-Mask: 0x1f) */

/* ----------------------------  DCDC_DCDC_CTRL_2_REG  ---------------------------- */
#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Pos (0UL)                  /*!< DCDC DCDC_CTRL_2_REG: DCDC_HSGND_TRIM (Bit 0)               */
#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Msk (0x7UL)                /*!< DCDC DCDC_CTRL_2_REG: DCDC_HSGND_TRIM (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Pos (3UL)                  /*!< DCDC DCDC_CTRL_2_REG: DCDC_LSSUP_TRIM (Bit 3)               */
#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Msk (0x38UL)               /*!< DCDC DCDC_CTRL_2_REG: DCDC_LSSUP_TRIM (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Pos    (6UL)                     /*!< DCDC DCDC_CTRL_2_REG: DCDC_TUNE (Bit 6)                     */
#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Msk    (0xc0UL)                  /*!< DCDC DCDC_CTRL_2_REG: DCDC_TUNE (Bitfield-Mask: 0x03)       */
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Pos (8UL)             /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_RES (Bit 8)          */
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Msk (0xf00UL)         /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_RES (Bitfield-Mask: 0x0f) */
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos (12UL)           /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_TRIG (Bit 12)        */
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk (0xf000UL)       /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_TRIG (Bitfield-Mask: 0x0f) */

/* -----------------------------  DCDC_DCDC_V14_0_REG  ---------------------------- */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Pos (0UL)              /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MIN (Bit 0)           */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Msk (0x1fUL)           /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos (5UL)           /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MAX_HV (Bit 5)        */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk (0x3e0UL)       /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Pos (10UL)                 /*!< DCDC DCDC_V14_0_REG: DCDC_V14_VOLTAGE (Bit 10)              */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Msk (0x7c00UL)             /*!< DCDC DCDC_V14_0_REG: DCDC_V14_VOLTAGE (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Pos (15UL)            /*!< DCDC DCDC_V14_0_REG: DCDC_V14_FAST_RAMPING (Bit 15)         */
#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Msk (0x8000UL)        /*!< DCDC DCDC_V14_0_REG: DCDC_V14_FAST_RAMPING (Bitfield-Mask: 0x01) */

/* -----------------------------  DCDC_DCDC_V14_1_REG  ---------------------------- */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Pos (0UL)                 /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_MIN (Bit 0)              */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Msk (0x1fUL)              /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Pos (5UL)                /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_HYST (Bit 5)             */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Msk (0x3e0UL)            /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_HYST (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos (10UL)          /*!< DCDC DCDC_V14_1_REG: DCDC_V14_CUR_LIM_MAX_LV (Bit 10)       */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk (0x3c00UL)      /*!< DCDC DCDC_V14_1_REG: DCDC_V14_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Pos (14UL)               /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_LV (Bit 14)            */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Msk (0x4000UL)           /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_LV (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Pos (15UL)               /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_HV (Bit 15)            */
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Msk (0x8000UL)           /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_HV (Bitfield-Mask: 0x01) */

/* -----------------------------  DCDC_DCDC_V18_0_REG  ---------------------------- */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Pos (0UL)              /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MIN (Bit 0)           */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Msk (0x1fUL)           /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos (5UL)           /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MAX_HV (Bit 5)        */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk (0x3e0UL)       /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Pos (10UL)                 /*!< DCDC DCDC_V18_0_REG: DCDC_V18_VOLTAGE (Bit 10)              */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Msk (0x7c00UL)             /*!< DCDC DCDC_V18_0_REG: DCDC_V18_VOLTAGE (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Pos (15UL)            /*!< DCDC DCDC_V18_0_REG: DCDC_V18_FAST_RAMPING (Bit 15)         */
#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Msk (0x8000UL)        /*!< DCDC DCDC_V18_0_REG: DCDC_V18_FAST_RAMPING (Bitfield-Mask: 0x01) */

/* -----------------------------  DCDC_DCDC_V18_1_REG  ---------------------------- */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Pos (0UL)                 /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_MIN (Bit 0)              */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Msk (0x1fUL)              /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Pos (5UL)                /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_HYST (Bit 5)             */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Msk (0x3e0UL)            /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_HYST (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos (10UL)          /*!< DCDC DCDC_V18_1_REG: DCDC_V18_CUR_LIM_MAX_LV (Bit 10)       */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk (0x3c00UL)      /*!< DCDC DCDC_V18_1_REG: DCDC_V18_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Pos (14UL)               /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_LV (Bit 14)            */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Msk (0x4000UL)           /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_LV (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Pos (15UL)               /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_HV (Bit 15)            */
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Msk (0x8000UL)           /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_HV (Bitfield-Mask: 0x01) */

/* -----------------------------  DCDC_DCDC_VDD_0_REG  ---------------------------- */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Pos (0UL)              /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MIN (Bit 0)           */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Msk (0x1fUL)           /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos (5UL)           /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MAX_HV (Bit 5)        */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk (0x3e0UL)       /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Pos (10UL)                 /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_VOLTAGE (Bit 10)              */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Msk (0x7c00UL)             /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_VOLTAGE (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Pos (15UL)            /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_FAST_RAMPING (Bit 15)         */
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Msk (0x8000UL)        /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_FAST_RAMPING (Bitfield-Mask: 0x01) */

/* -----------------------------  DCDC_DCDC_VDD_1_REG  ---------------------------- */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Pos (0UL)                 /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_MIN (Bit 0)              */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Msk (0x1fUL)              /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Pos (5UL)                /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_HYST (Bit 5)             */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Msk (0x3e0UL)            /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_HYST (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos (10UL)          /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_CUR_LIM_MAX_LV (Bit 10)       */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk (0x3c00UL)      /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Pos (14UL)               /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_LV (Bit 14)            */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Msk (0x4000UL)           /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_LV (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Pos (15UL)               /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_HV (Bit 15)            */
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Msk (0x8000UL)           /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_HV (Bitfield-Mask: 0x01) */

/* ----------------------------  DCDC_DCDC_V18P_0_REG  ---------------------------- */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Pos (0UL)            /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MIN (Bit 0)         */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Msk (0x1fUL)         /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos (5UL)         /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MAX_HV (Bit 5)      */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk (0x3e0UL)     /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Pos (10UL)               /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_VOLTAGE (Bit 10)            */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Msk (0x7c00UL)           /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_VOLTAGE (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Pos (15UL)          /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_FAST_RAMPING (Bit 15)       */
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Msk (0x8000UL)      /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_FAST_RAMPING (Bitfield-Mask: 0x01) */

/* ----------------------------  DCDC_DCDC_V18P_1_REG  ---------------------------- */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Pos (0UL)               /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_MIN (Bit 0)            */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Msk (0x1fUL)            /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_MIN (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Pos (5UL)              /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_HYST (Bit 5)           */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Msk (0x3e0UL)          /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_HYST (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos (10UL)        /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_CUR_LIM_MAX_LV (Bit 10)     */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk (0x3c00UL)    /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Pos (14UL)             /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_LV (Bit 14)          */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Msk (0x4000UL)         /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_LV (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Pos (15UL)             /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_HV (Bit 15)          */
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Msk (0x8000UL)         /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_HV (Bitfield-Mask: 0x01) */

/* -----------------------------  DCDC_DCDC_RET_0_REG  ---------------------------- */
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Pos (0UL)              /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_CUR_LIM_RET (Bit 0)           */
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Msk (0x1fUL)           /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_CUR_LIM_RET (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Pos (5UL)               /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_RET_CYCLES (Bit 5)            */
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Msk (0xe0UL)            /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_RET_CYCLES (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Pos (8UL)             /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_CUR_LIM_RET (Bit 8)          */
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Msk (0x1f00UL)        /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_CUR_LIM_RET (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Pos (13UL)             /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_RET_CYCLES (Bit 13)          */
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Msk (0xe000UL)         /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_RET_CYCLES (Bitfield-Mask: 0x07) */

/* -----------------------------  DCDC_DCDC_RET_1_REG  ---------------------------- */
#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Pos (0UL)              /*!< DCDC DCDC_RET_1_REG: DCDC_V14_CUR_LIM_RET (Bit 0)           */
#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Msk (0x1fUL)           /*!< DCDC DCDC_RET_1_REG: DCDC_V14_CUR_LIM_RET (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Pos (5UL)               /*!< DCDC DCDC_RET_1_REG: DCDC_V14_RET_CYCLES (Bit 5)            */
#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Msk (0xe0UL)            /*!< DCDC DCDC_RET_1_REG: DCDC_V14_RET_CYCLES (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Pos (8UL)              /*!< DCDC DCDC_RET_1_REG: DCDC_V18_CUR_LIM_RET (Bit 8)           */
#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Msk (0x1f00UL)         /*!< DCDC DCDC_RET_1_REG: DCDC_V18_CUR_LIM_RET (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Pos (13UL)              /*!< DCDC DCDC_RET_1_REG: DCDC_V18_RET_CYCLES (Bit 13)           */
#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Msk (0xe000UL)          /*!< DCDC DCDC_RET_1_REG: DCDC_V18_RET_CYCLES (Bitfield-Mask: 0x07) */

/* -----------------------------  DCDC_DCDC_TRIM_REG  ----------------------------- */
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Pos (0UL)                   /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_TRIM (Bit 0)                */
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Msk (0x3fUL)                /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_TRIM (Bitfield-Mask: 0x3f)  */
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Pos (6UL)               /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_MAN_TRIM (Bit 6)            */
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Msk (0x40UL)            /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_MAN_TRIM (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Pos (7UL)                   /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_TRIM (Bit 7)                */
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Msk (0x1f80UL)              /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_TRIM (Bitfield-Mask: 0x3f)  */
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Pos (13UL)              /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_MAN_TRIM (Bit 13)           */
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Msk (0x2000UL)          /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_MAN_TRIM (Bitfield-Mask: 0x01) */

/* ----------------------------  DCDC_DCDC_TEST_0_REG  ---------------------------- */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Pos (0UL)                   /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_PSW (Bit 0)                */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Msk (0x1UL)                 /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_PSW (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Pos (1UL)                   /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_NSW (Bit 1)                */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Msk (0x2UL)                 /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_NSW (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Pos (2UL)                    /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_FW (Bit 2)                 */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Msk (0x4UL)                  /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_FW (Bitfield-Mask: 0x01)   */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Pos (3UL)                   /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V14 (Bit 3)                */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Msk (0x8UL)                 /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V14 (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Pos (4UL)                   /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18 (Bit 4)                */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Msk (0x10UL)                /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18 (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Pos (5UL)                   /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_VDD (Bit 5)                */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Msk (0x20UL)                /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_VDD (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Pos (6UL)                  /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18P (Bit 6)               */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Msk (0x40UL)               /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18P (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Pos (7UL)                  /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_IDLE (Bit 7)               */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Msk (0x80UL)               /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_IDLE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Pos (8UL)                    /*!< DCDC DCDC_TEST_0_REG: DCDC_ANA_TEST (Bit 8)                 */
#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Msk (0x700UL)                /*!< DCDC DCDC_TEST_0_REG: DCDC_ANA_TEST (Bitfield-Mask: 0x07)   */
#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Pos (11UL)             /*!< DCDC DCDC_TEST_0_REG: DCDC_OUTPUT_MONITOR (Bit 11)          */
#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Msk (0x3800UL)         /*!< DCDC DCDC_TEST_0_REG: DCDC_OUTPUT_MONITOR (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Pos (14UL)              /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_CURRENT (Bit 14)           */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Msk (0x4000UL)          /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_CURRENT (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Pos (15UL)             /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_COMP_CLK (Bit 15)          */
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Msk (0x8000UL)         /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_COMP_CLK (Bitfield-Mask: 0x01) */

/* ----------------------------  DCDC_DCDC_TEST_1_REG  ---------------------------- */
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Pos (0UL)                    /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_REG (Bit 0)                 */
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Msk (0xfUL)                  /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_REG (Bitfield-Mask: 0x0f)   */
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Pos (4UL)                /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_CURRENT (Bit 4)             */
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Msk (0x1f0UL)            /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_CURRENT (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Pos (9UL)                    /*!< DCDC DCDC_TEST_1_REG: DCDC_COMP_CLK (Bit 9)                 */
#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Msk (0x1e00UL)               /*!< DCDC DCDC_TEST_1_REG: DCDC_COMP_CLK (Bitfield-Mask: 0x0f)   */

/* ---------------------------  DCDC_DCDC_STATUS_0_REG  --------------------------- */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Pos (0UL)              /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_0 (Bit 0)           */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Msk (0x7UL)            /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_0 (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Pos (3UL)              /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_1 (Bit 3)           */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Msk (0x38UL)           /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_1 (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Pos (6UL)              /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_2 (Bit 6)           */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Msk (0x1c0UL)          /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_2 (Bitfield-Mask: 0x07) */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Pos (9UL)              /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_3 (Bit 9)           */
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Msk (0xe00UL)          /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_3 (Bitfield-Mask: 0x07) */

/* ---------------------------  DCDC_DCDC_STATUS_1_REG  --------------------------- */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Pos (0UL)                   /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_NOK (Bit 0)                */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Msk (0x1UL)                 /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_NOK (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Pos (1UL)                   /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_NOK (Bit 1)                */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Msk (0x2UL)                 /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_NOK (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Pos (2UL)                   /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_NOK (Bit 2)                */
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Msk (0x4UL)                 /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_NOK (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Pos (3UL)                  /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_NOK (Bit 3)               */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Msk (0x8UL)                /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_NOK (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Pos (4UL)                    /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_OK (Bit 4)                 */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Msk (0x10UL)                 /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_OK (Bitfield-Mask: 0x01)   */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Pos (5UL)                    /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_OK (Bit 5)                 */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Msk (0x20UL)                 /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_OK (Bitfield-Mask: 0x01)   */
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Pos (6UL)                    /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_OK (Bit 6)                 */
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Msk (0x40UL)                 /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_OK (Bitfield-Mask: 0x01)   */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Pos (7UL)                   /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_OK (Bit 7)                */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Msk (0x80UL)                /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_OK (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Pos (8UL)             /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_AVAILABLE (Bit 8)          */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Msk (0x100UL)         /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_AVAILABLE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Pos (9UL)             /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_AVAILABLE (Bit 9)          */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Msk (0x200UL)         /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_AVAILABLE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Pos (10UL)            /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_AVAILABLE (Bit 10)         */
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Msk (0x400UL)         /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_AVAILABLE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Pos (11UL)           /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_AVAILABLE (Bit 11)        */
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Msk (0x800UL)        /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_AVAILABLE (Bitfield-Mask: 0x01) */

/* ---------------------------  DCDC_DCDC_STATUS_2_REG  --------------------------- */
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Pos (0UL)                    /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP (Bit 0)                 */
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Msk (0x1UL)                  /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP (Bitfield-Mask: 0x01)   */
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Pos (1UL)                    /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP (Bit 1)                 */
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Msk (0x2UL)                  /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP (Bitfield-Mask: 0x01)   */
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Pos (2UL)                  /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_N (Bit 2)               */
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Msk (0x4UL)                /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_N (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Pos (3UL)                  /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_P (Bit 3)               */
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Msk (0x8UL)                /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_P (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Pos (4UL)                  /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_N (Bit 4)               */
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Msk (0x10UL)               /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_N (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Pos (5UL)                  /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_P (Bit 5)               */
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Msk (0x20UL)               /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_P (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Pos (6UL)                 /*!< DCDC DCDC_STATUS_2_REG: DCDC_PSW_STATE (Bit 6)              */
#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Msk (0x40UL)              /*!< DCDC DCDC_STATUS_2_REG: DCDC_PSW_STATE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Pos (7UL)                 /*!< DCDC DCDC_STATUS_2_REG: DCDC_NSW_STATE (Bit 7)              */
#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Msk (0x80UL)              /*!< DCDC DCDC_STATUS_2_REG: DCDC_NSW_STATE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Pos (8UL)              /*!< DCDC DCDC_STATUS_2_REG: DCDC_V14_SW_STATE (Bit 8)           */
#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Msk (0x100UL)          /*!< DCDC DCDC_STATUS_2_REG: DCDC_V14_SW_STATE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Pos (9UL)              /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18_SW_STATE (Bit 9)           */
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Msk (0x200UL)          /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18_SW_STATE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Pos (10UL)             /*!< DCDC DCDC_STATUS_2_REG: DCDC_VDD_SW_STATE (Bit 10)          */
#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Msk (0x400UL)          /*!< DCDC DCDC_STATUS_2_REG: DCDC_VDD_SW_STATE (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Pos (11UL)            /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18P_SW_STATE (Bit 11)         */
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Msk (0x800UL)         /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18P_SW_STATE (Bitfield-Mask: 0x01) */

/* ---------------------------  DCDC_DCDC_STATUS_3_REG  --------------------------- */
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Pos (0UL)                 /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_VDD (Bit 0)              */
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Msk (0x1fUL)              /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_VDD (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Pos (5UL)                /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bit 5)             */
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Msk (0x3e0UL)            /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Pos (10UL)                  /*!< DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bit 10)               */
#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Msk (0x400UL)               /*!< DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bitfield-Mask: 0x01)  */
#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Pos (11UL)         /*!< DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bit 11)      */
#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Msk (0x800UL)      /*!< DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01) */

/* ---------------------------  DCDC_DCDC_STATUS_4_REG  --------------------------- */
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Pos (0UL)                 /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bit 0)              */
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Msk (0x1fUL)              /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bitfield-Mask: 0x1f) */
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Pos (5UL)                 /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V18 (Bit 5)              */
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Msk (0x3e0UL)             /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V18 (Bitfield-Mask: 0x1f) */

/* ----------------------------  DCDC_DCDC_TRIM_0_REG  ---------------------------- */
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Pos (0UL)                  /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_N (Bit 0)               */
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Msk (0x3fUL)               /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_N (Bitfield-Mask: 0x3f) */
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Pos (6UL)                  /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_P (Bit 6)               */
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Msk (0xfc0UL)              /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_P (Bitfield-Mask: 0x3f) */

/* ----------------------------  DCDC_DCDC_TRIM_1_REG  ---------------------------- */
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Pos (0UL)                  /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_N (Bit 0)               */
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Msk (0x3fUL)               /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_N (Bitfield-Mask: 0x3f) */
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Pos (6UL)                  /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_P (Bit 6)               */
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Msk (0xfc0UL)              /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_P (Bitfield-Mask: 0x3f) */

/* ----------------------------  DCDC_DCDC_TRIM_2_REG  ---------------------------- */
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Pos (0UL)                  /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_N (Bit 0)               */
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Msk (0x3fUL)               /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_N (Bitfield-Mask: 0x3f) */
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Pos (6UL)                  /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_P (Bit 6)               */
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Msk (0xfc0UL)              /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_P (Bitfield-Mask: 0x3f) */

/* ----------------------------  DCDC_DCDC_TRIM_3_REG  ---------------------------- */
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Pos (0UL)                 /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_N (Bit 0)              */
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Msk (0x3fUL)              /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_N (Bitfield-Mask: 0x3f) */
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Pos (6UL)                 /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_P (Bit 6)              */
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Msk (0xfc0UL)             /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_P (Bitfield-Mask: 0x3f) */

/* --------------------------  DCDC_DCDC_IRQ_STATUS_REG  -------------------------- */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos (0UL)  /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V14_TIMEOUT_IRQ_STATUS (Bit 0) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk (0x1UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V14_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos (1UL)  /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18_TIMEOUT_IRQ_STATUS (Bit 1) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk (0x2UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos (2UL)  /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_VDD_TIMEOUT_IRQ_STATUS (Bit 2) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk (0x4UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_VDD_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos (3UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18P_TIMEOUT_IRQ_STATUS (Bit 3) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk (0x8UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18P_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Pos (4UL)    /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_BROWN_OUT_IRQ_STATUS (Bit 4) */
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Msk (0x10UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_BROWN_OUT_IRQ_STATUS (Bitfield-Mask: 0x01) */

/* ---------------------------  DCDC_DCDC_IRQ_CLEAR_REG  -------------------------- */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos (0UL)    /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V14_TIMEOUT_IRQ_CLEAR (Bit 0) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk (0x1UL)  /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V14_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos (1UL)    /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18_TIMEOUT_IRQ_CLEAR (Bit 1) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk (0x2UL)  /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos (2UL)    /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bit 2) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk (0x4UL)  /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos (3UL)   /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bit 3) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk (0x8UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Pos (4UL)      /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_BROWN_OUT_IRQ_CLEAR (Bit 4)   */
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Msk (0x10UL)   /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_BROWN_OUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */

/* ---------------------------  DCDC_DCDC_IRQ_MASK_REG  --------------------------- */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos (0UL)      /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V14_TIMEOUT_IRQ_MASK (Bit 0)   */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk (0x1UL)    /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V14_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos (1UL)      /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18_TIMEOUT_IRQ_MASK (Bit 1)   */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk (0x2UL)    /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos (2UL)      /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_VDD_TIMEOUT_IRQ_MASK (Bit 2)   */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk (0x4UL)    /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_VDD_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos (3UL)     /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18P_TIMEOUT_IRQ_MASK (Bit 3)  */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk (0x8UL)   /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18P_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Pos (4UL)        /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_BROWN_OUT_IRQ_MASK (Bit 4)     */
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Msk (0x10UL)     /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_BROWN_OUT_IRQ_MASK (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================          struct 'DEM' Position & Mask          ================ */
/* ================================================================================ */


/* -----------------------------  DEM_RF_DEM_CTRL_REG  ---------------------------- */
#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Pos    (0UL)                     /*!< DEM RF_DEM_CTRL_REG: RXDATA_INV (Bit 0)                     */
#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Msk    (0x1UL)                   /*!< DEM RF_DEM_CTRL_REG: RXDATA_INV (Bitfield-Mask: 0x01)       */
#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Pos   (1UL)                     /*!< DEM RF_DEM_CTRL_REG: DEM_HSI_POL (Bit 1)                    */
#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Msk   (0x2UL)                   /*!< DEM RF_DEM_CTRL_REG: DEM_HSI_POL (Bitfield-Mask: 0x01)      */
#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Pos  (2UL)                     /*!< DEM RF_DEM_CTRL_REG: MATCH0101_TH (Bit 2)                   */
#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Msk  (0x3cUL)                  /*!< DEM RF_DEM_CTRL_REG: MATCH0101_TH (Bitfield-Mask: 0x0f)     */
#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Pos      (6UL)                     /*!< DEM RF_DEM_CTRL_REG: EQUAL_EN (Bit 6)                       */
#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Msk      (0x40UL)                  /*!< DEM RF_DEM_CTRL_REG: EQUAL_EN (Bitfield-Mask: 0x01)         */
#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Pos    (7UL)                     /*!< DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bit 7)                     */
#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Msk    (0x80UL)                  /*!< DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bitfield-Mask: 0x01)       */
#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Pos     (8UL)                     /*!< DEM RF_DEM_CTRL_REG: IQCORR_EN (Bit 8)                      */
#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Msk     (0x100UL)                 /*!< DEM RF_DEM_CTRL_REG: IQCORR_EN (Bitfield-Mask: 0x01)        */
#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Pos (9UL)                     /*!< DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bit 9)                  */
#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Msk (0x200UL)                 /*!< DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bitfield-Mask: 0x01)    */
#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Pos (10UL)                    /*!< DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bit 10)                 */
#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Msk (0x400UL)                 /*!< DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bitfield-Mask: 0x01)    */
#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Pos     (11UL)                    /*!< DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bit 11)                     */
#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Msk     (0x3800UL)                /*!< DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bitfield-Mask: 0x07)        */

/* ----------------------------  DEM_RF_AGC_LUT_01_REG  --------------------------- */
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Pos  (0UL)                     /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bit 0)                   */
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Msk  (0x7UL)                   /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Pos  (3UL)                     /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN0 (Bit 3)                   */
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Msk  (0x38UL)                  /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN0 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Pos   (6UL)                     /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN0 (Bit 6)                    */
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Msk   (0xc0UL)                  /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN0 (Bitfield-Mask: 0x03)      */
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Pos  (8UL)                     /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN1 (Bit 8)                   */
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Msk  (0x700UL)                 /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN1 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Pos  (11UL)                    /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN1 (Bit 11)                  */
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Msk  (0x3800UL)                /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN1 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Pos   (14UL)                    /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN1 (Bit 14)                   */
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Msk   (0xc000UL)                /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN1 (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_AGC_LUT_23_REG  --------------------------- */
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Pos  (0UL)                     /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN2 (Bit 0)                   */
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Msk  (0x7UL)                   /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN2 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Pos  (3UL)                     /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN2 (Bit 3)                   */
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Msk  (0x38UL)                  /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN2 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Pos   (6UL)                     /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN2 (Bit 6)                    */
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Msk   (0xc0UL)                  /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN2 (Bitfield-Mask: 0x03)      */
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Pos  (8UL)                     /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN3 (Bit 8)                   */
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Msk  (0x700UL)                 /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN3 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Pos  (11UL)                    /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN3 (Bit 11)                  */
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Msk  (0x3800UL)                /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN3 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Pos   (14UL)                    /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN3 (Bit 14)                   */
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Msk   (0xc000UL)                /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN3 (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_AGC_LUT_45_REG  --------------------------- */
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Pos  (0UL)                     /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN4 (Bit 0)                   */
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Msk  (0x7UL)                   /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN4 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Pos  (3UL)                     /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN4 (Bit 3)                   */
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Msk  (0x38UL)                  /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN4 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Pos   (6UL)                     /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN4 (Bit 6)                    */
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Msk   (0xc0UL)                  /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN4 (Bitfield-Mask: 0x03)      */
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Pos  (8UL)                     /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN5 (Bit 8)                   */
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Msk  (0x700UL)                 /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN5 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Pos  (11UL)                    /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN5 (Bit 11)                  */
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Msk  (0x3800UL)                /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN5 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Pos   (14UL)                    /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN5 (Bit 14)                   */
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Msk   (0xc000UL)                /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN5 (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_AGC_LUT_67_REG  --------------------------- */
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Pos  (0UL)                     /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN6 (Bit 0)                   */
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Msk  (0x7UL)                   /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN6 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Pos  (3UL)                     /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN6 (Bit 3)                   */
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Msk  (0x38UL)                  /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN6 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Pos   (6UL)                     /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN6 (Bit 6)                    */
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Msk   (0xc0UL)                  /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN6 (Bitfield-Mask: 0x03)      */
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Pos  (8UL)                     /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN7 (Bit 8)                   */
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Msk  (0x700UL)                 /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN7 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Pos  (11UL)                    /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN7 (Bit 11)                  */
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Msk  (0x3800UL)                /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN7 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Pos   (14UL)                    /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN7 (Bit 14)                   */
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Msk   (0xc000UL)                /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN7 (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_AGC_LUT_89_REG  --------------------------- */
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Pos  (0UL)                     /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN8 (Bit 0)                   */
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Msk  (0x7UL)                   /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN8 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Pos  (3UL)                     /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN8 (Bit 3)                   */
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Msk  (0x38UL)                  /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN8 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Pos   (6UL)                     /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN8 (Bit 6)                    */
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Msk   (0xc0UL)                  /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN8 (Bitfield-Mask: 0x03)      */
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Pos  (8UL)                     /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN9 (Bit 8)                   */
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Msk  (0x700UL)                 /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN9 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Pos  (11UL)                    /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN9 (Bit 11)                  */
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Msk  (0x3800UL)                /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN9 (Bitfield-Mask: 0x07)     */
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Pos   (14UL)                    /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN9 (Bit 14)                   */
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Msk   (0xc000UL)                /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN9 (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_AGC_CTRL1_REG  ---------------------------- */
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Pos   (0UL)                     /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_LOW (Bit 0)                    */
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Msk   (0x7fUL)                  /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_LOW (Bitfield-Mask: 0x7f)      */
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Pos  (7UL)                     /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_HIGH (Bit 7)                   */
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Msk  (0x3f80UL)                /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_HIGH (Bitfield-Mask: 0x7f)     */
#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Pos     (14UL)                    /*!< DEM RF_AGC_CTRL1_REG: AGC_MODE (Bit 14)                     */
#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Msk     (0xc000UL)                /*!< DEM RF_AGC_CTRL1_REG: AGC_MODE (Bitfield-Mask: 0x03)        */

/* ----------------------------  DEM_RF_AGC_CTRL2_REG  ---------------------------- */
#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Pos      (0UL)                     /*!< DEM RF_AGC_CTRL2_REG: RSSI_TH (Bit 0)                       */
#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Msk      (0x3fUL)                  /*!< DEM RF_AGC_CTRL2_REG: RSSI_TH (Bitfield-Mask: 0x3f)         */
#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Pos  (6UL)                     /*!< DEM RF_AGC_CTRL2_REG: EN_FRZ_GAIN (Bit 6)                   */
#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Msk  (0x40UL)                  /*!< DEM RF_AGC_CTRL2_REG: EN_FRZ_GAIN (Bitfield-Mask: 0x01)     */
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Pos (7UL)                   /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_SEL (Bit 7)                */
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Msk (0x80UL)                /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_SEL (Bitfield-Mask: 0x01)  */
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Pos (8UL)                    /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_WR (Bit 8)                 */
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Msk (0xf00UL)                /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_WR (Bitfield-Mask: 0x0f)   */
#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Pos     (12UL)                    /*!< DEM RF_AGC_CTRL2_REG: SLOW_AGC (Bit 12)                     */
#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Msk     (0x1000UL)                /*!< DEM RF_AGC_CTRL2_REG: SLOW_AGC (Bitfield-Mask: 0x01)        */

/* -----------------------------  DEM_RF_AFC_CTRL_REG  ---------------------------- */
#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Pos      (0UL)                     /*!< DEM RF_AFC_CTRL_REG: AFC_MODE (Bit 0)                       */
#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Msk      (0xfUL)                   /*!< DEM RF_AFC_CTRL_REG: AFC_MODE (Bitfield-Mask: 0x0f)         */
#define DEM_RF_AFC_CTRL_REG_POLE1_Pos         (4UL)                     /*!< DEM RF_AFC_CTRL_REG: POLE1 (Bit 4)                          */
#define DEM_RF_AFC_CTRL_REG_POLE1_Msk         (0x30UL)                  /*!< DEM RF_AFC_CTRL_REG: POLE1 (Bitfield-Mask: 0x03)            */
#define DEM_RF_AFC_CTRL_REG_POLE2_Pos         (6UL)                     /*!< DEM RF_AFC_CTRL_REG: POLE2 (Bit 6)                          */
#define DEM_RF_AFC_CTRL_REG_POLE2_Msk         (0xc0UL)                  /*!< DEM RF_AFC_CTRL_REG: POLE2 (Bitfield-Mask: 0x03)            */
#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Pos      (8UL)                     /*!< DEM RF_AFC_CTRL_REG: PAD_MODE (Bit 8)                       */
#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Msk      (0x300UL)                 /*!< DEM RF_AFC_CTRL_REG: PAD_MODE (Bitfield-Mask: 0x03)         */
#define DEM_RF_AFC_CTRL_REG_APD_MODE_Pos      (10UL)                    /*!< DEM RF_AFC_CTRL_REG: APD_MODE (Bit 10)                      */
#define DEM_RF_AFC_CTRL_REG_APD_MODE_Msk      (0x1c00UL)                /*!< DEM RF_AFC_CTRL_REG: APD_MODE (Bitfield-Mask: 0x07)         */

/* -------------------------  DEM_RF_DC_OFFSET_CTRL1_REG  ------------------------- */
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Pos (0UL)              /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bit 0)           */
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Msk (0xffUL)           /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bitfield-Mask: 0xff) */
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Pos (8UL)              /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_Q_WR (Bit 8)           */
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Msk (0xff00UL)         /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_Q_WR (Bitfield-Mask: 0xff) */

/* -------------------------  DEM_RF_DC_OFFSET_CTRL2_REG  ------------------------- */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Pos (0UL)               /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCOFFSET_SEL (Bit 0)            */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Msk (0x1UL)             /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCOFFSET_SEL (Bitfield-Mask: 0x01) */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Pos (1UL)                /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_EN (Bit 1)             */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Msk (0x2UL)              /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_EN (Bitfield-Mask: 0x01) */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Pos (2UL)                     /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPOLE (Bit 2)                  */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Msk (0xcUL)                   /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPOLE (Bitfield-Mask: 0x03)    */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Pos (4UL)                    /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNSTEP (Bit 4)                 */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Msk (0x70UL)                 /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNSTEP (Bitfield-Mask: 0x07)   */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Pos (7UL)                    /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bit 7)                 */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Msk (0x180UL)                /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bitfield-Mask: 0x03)   */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Pos (9UL)              /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bit 9)           */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Msk (0x200UL)          /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bitfield-Mask: 0x01) */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Pos (10UL)            /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bit 10)         */
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Msk (0x400UL)         /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bitfield-Mask: 0x01) */

/* -------------------------  DEM_RF_DC_OFFSET_CTRL3_REG  ------------------------- */
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Pos (0UL)                   /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bit 0)                */
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Msk (0xffUL)                /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bitfield-Mask: 0xff)  */
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Pos (8UL)                   /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_Q (Bit 8)                */
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Msk (0xff00UL)              /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_Q (Bitfield-Mask: 0xff)  */

/* -------------------------  DEM_RF_DC_OFFSET_CTRL4_REG  ------------------------- */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Pos (0UL)         /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL0 (Bit 0)      */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Msk (0xfUL)       /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL0 (Bitfield-Mask: 0x0f) */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Pos (4UL)         /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL1 (Bit 4)      */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Msk (0xf0UL)      /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL1 (Bitfield-Mask: 0x0f) */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Pos (8UL)         /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL2 (Bit 8)      */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Msk (0xf00UL)     /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL2 (Bitfield-Mask: 0x0f) */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Pos (12UL)        /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL3 (Bit 12)     */
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Msk (0xf000UL)    /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL3 (Bitfield-Mask: 0x0f) */

/* ----------------------------  DEM_RF_AGC_RESULT_REG  --------------------------- */
#define DEM_RF_AGC_RESULT_REG_AFC_RD_Pos      (0UL)                     /*!< DEM RF_AGC_RESULT_REG: AFC_RD (Bit 0)                       */
#define DEM_RF_AGC_RESULT_REG_AFC_RD_Msk      (0xffUL)                  /*!< DEM RF_AGC_RESULT_REG: AFC_RD (Bitfield-Mask: 0xff)         */
#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Pos (8UL)                   /*!< DEM RF_AGC_RESULT_REG: AGCSETTING_RD (Bit 8)                */
#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Msk (0xf00UL)               /*!< DEM RF_AGC_RESULT_REG: AGCSETTING_RD (Bitfield-Mask: 0x0f)  */

/* ---------------------------  DEM_RF_RSSI_RESULT_REG  --------------------------- */
#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Pos (0UL)                     /*!< DEM RF_RSSI_RESULT_REG: RSSI_PH_RD (Bit 0)                  */
#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Msk (0x3fUL)                  /*!< DEM RF_RSSI_RESULT_REG: RSSI_PH_RD (Bitfield-Mask: 0x3f)    */
#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Pos (6UL)                    /*!< DEM RF_RSSI_RESULT_REG: RSSI_AVG_RD (Bit 6)                 */
#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Msk (0xffc0UL)               /*!< DEM RF_RSSI_RESULT_REG: RSSI_AVG_RD (Bitfield-Mask: 0x3ff)  */

/* -------------------------  DEM_RF_DC_OFFSET_RESULT_REG  ------------------------ */
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Pos (0UL)             /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_I_RD (Bit 0)          */
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Msk (0xffUL)          /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_I_RD (Bitfield-Mask: 0xff) */
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Pos (8UL)             /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_Q_RD (Bit 8)          */
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Msk (0xff00UL)        /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_Q_RD (Bitfield-Mask: 0xff) */

/* --------------------------  DEM_RF_RSSI_COMP_CTRL_REG  ------------------------- */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Pos (0UL)                 /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP01 (Bit 0)              */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Msk (0xfUL)               /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP01 (Bitfield-Mask: 0x0f) */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Pos (4UL)                 /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP10 (Bit 4)              */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Msk (0xf0UL)              /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP10 (Bitfield-Mask: 0x0f) */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Pos (8UL)                 /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP11 (Bit 8)              */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Msk (0xf00UL)             /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP11 (Bitfield-Mask: 0x0f) */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Pos (12UL)                /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP00 (Bit 12)             */
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Msk (0xf000UL)            /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP00 (Bitfield-Mask: 0x0f) */

/* ----------------------------  DEM_RF_FTDF_CTRL1_REG  --------------------------- */
#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Pos    (0UL)                     /*!< DEM RF_FTDF_CTRL1_REG: CFE_BIAS (Bit 0)                     */
#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Msk    (0x3ffUL)                 /*!< DEM RF_FTDF_CTRL1_REG: CFE_BIAS (Bitfield-Mask: 0x3ff)      */
#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Pos    (10UL)                    /*!< DEM RF_FTDF_CTRL1_REG: CFE_MODE (Bit 10)                    */
#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Msk    (0xc00UL)                 /*!< DEM RF_FTDF_CTRL1_REG: CFE_MODE (Bitfield-Mask: 0x03)       */
#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Pos   (12UL)                    /*!< DEM RF_FTDF_CTRL1_REG: CFE_NSTEP (Bit 12)                   */
#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Msk   (0x3000UL)                /*!< DEM RF_FTDF_CTRL1_REG: CFE_NSTEP (Bitfield-Mask: 0x03)      */
#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Pos (14UL)               /*!< DEM RF_FTDF_CTRL1_REG: CHSEL_FILT_MODE2 (Bit 14)            */
#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Msk (0xc000UL)           /*!< DEM RF_FTDF_CTRL1_REG: CHSEL_FILT_MODE2 (Bitfield-Mask: 0x03) */

/* ----------------------------  DEM_RF_FTDF_CTRL2_REG  --------------------------- */
#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Pos      (0UL)                     /*!< DEM RF_FTDF_CTRL2_REG: CORRTH (Bit 0)                       */
#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Msk      (0x3fUL)                  /*!< DEM RF_FTDF_CTRL2_REG: CORRTH (Bitfield-Mask: 0x3f)         */
#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Pos     (6UL)                     /*!< DEM RF_FTDF_CTRL2_REG: NORM_EN (Bit 6)                      */
#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Msk     (0x40UL)                  /*!< DEM RF_FTDF_CTRL2_REG: NORM_EN (Bitfield-Mask: 0x01)        */
#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Pos     (7UL)                     /*!< DEM RF_FTDF_CTRL2_REG: PD_MODE (Bit 7)                      */
#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Msk     (0x80UL)                  /*!< DEM RF_FTDF_CTRL2_REG: PD_MODE (Bitfield-Mask: 0x01)        */
#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Pos    (8UL)                     /*!< DEM RF_FTDF_CTRL2_REG: PD_NPEAK (Bit 8)                     */
#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Msk    (0x700UL)                 /*!< DEM RF_FTDF_CTRL2_REG: PD_NPEAK (Bitfield-Mask: 0x07)       */
#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Pos     (11UL)                    /*!< DEM RF_FTDF_CTRL2_REG: PD_NWIN (Bit 11)                     */
#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Msk     (0x3800UL)                /*!< DEM RF_FTDF_CTRL2_REG: PD_NWIN (Bitfield-Mask: 0x07)        */
#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Pos   (14UL)                    /*!< DEM RF_FTDF_CTRL2_REG: PD_OFFSET (Bit 14)                   */
#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Msk   (0xc000UL)                /*!< DEM RF_FTDF_CTRL2_REG: PD_OFFSET (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_FTDF_CTRL3_REG  --------------------------- */
#define DEM_RF_FTDF_CTRL3_REG_FIF_Pos         (0UL)                     /*!< DEM RF_FTDF_CTRL3_REG: FIF (Bit 0)                          */
#define DEM_RF_FTDF_CTRL3_REG_FIF_Msk         (0x1ffUL)                 /*!< DEM RF_FTDF_CTRL3_REG: FIF (Bitfield-Mask: 0x1ff)           */
#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Pos (9UL)                     /*!< DEM RF_FTDF_CTRL3_REG: FTDF_DDC_EN (Bit 9)                  */
#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Msk (0x200UL)                 /*!< DEM RF_FTDF_CTRL3_REG: FTDF_DDC_EN (Bitfield-Mask: 0x01)    */
#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Pos (10UL)                  /*!< DEM RF_FTDF_CTRL3_REG: MATCH_FILT_EN (Bit 10)               */
#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Msk (0x400UL)               /*!< DEM RF_FTDF_CTRL3_REG: MATCH_FILT_EN (Bitfield-Mask: 0x01)  */
#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Pos (11UL)                 /*!< DEM RF_FTDF_CTRL3_REG: TIMING_CORR_EN (Bit 11)              */
#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Msk (0x800UL)              /*!< DEM RF_FTDF_CTRL3_REG: TIMING_CORR_EN (Bitfield-Mask: 0x01) */
#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Pos (12UL)               /*!< DEM RF_FTDF_CTRL3_REG: CHSEL_FILT_MODE1 (Bit 12)            */
#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Msk (0x3000UL)           /*!< DEM RF_FTDF_CTRL3_REG: CHSEL_FILT_MODE1 (Bitfield-Mask: 0x03) */
#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Pos   (14UL)                    /*!< DEM RF_FTDF_CTRL3_REG: DS_OFFSET (Bit 14)                   */
#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Msk   (0xc000UL)                /*!< DEM RF_FTDF_CTRL3_REG: DS_OFFSET (Bitfield-Mask: 0x03)      */

/* ----------------------------  DEM_RF_FTDF_CTRL4_REG  --------------------------- */
#define DEM_RF_FTDF_CTRL4_REG_SFD0_Pos        (0UL)                     /*!< DEM RF_FTDF_CTRL4_REG: SFD0 (Bit 0)                         */
#define DEM_RF_FTDF_CTRL4_REG_SFD0_Msk        (0xfUL)                   /*!< DEM RF_FTDF_CTRL4_REG: SFD0 (Bitfield-Mask: 0x0f)           */
#define DEM_RF_FTDF_CTRL4_REG_SFD1_Pos        (4UL)                     /*!< DEM RF_FTDF_CTRL4_REG: SFD1 (Bit 4)                         */
#define DEM_RF_FTDF_CTRL4_REG_SFD1_Msk        (0xf0UL)                  /*!< DEM RF_FTDF_CTRL4_REG: SFD1 (Bitfield-Mask: 0x0f)           */
#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Pos (8UL)                 /*!< DEM RF_FTDF_CTRL4_REG: LQI_PREAMBLE_EN (Bit 8)              */
#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Msk (0x100UL)             /*!< DEM RF_FTDF_CTRL4_REG: LQI_PREAMBLE_EN (Bitfield-Mask: 0x01) */
#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Pos (9UL)                   /*!< DEM RF_FTDF_CTRL4_REG: LQI_SYMBOL_EN (Bit 9)                */
#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Msk (0x200UL)               /*!< DEM RF_FTDF_CTRL4_REG: LQI_SYMBOL_EN (Bitfield-Mask: 0x01)  */
#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Pos (10UL)                  /*!< DEM RF_FTDF_CTRL4_REG: LQI_CORRTH_EN (Bit 10)               */
#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Msk (0x400UL)               /*!< DEM RF_FTDF_CTRL4_REG: LQI_CORRTH_EN (Bitfield-Mask: 0x01)  */
#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Pos   (11UL)                    /*!< DEM RF_FTDF_CTRL4_REG: LQI_SCALE (Bit 11)                   */
#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Msk   (0x1800UL)                /*!< DEM RF_FTDF_CTRL4_REG: LQI_SCALE (Bitfield-Mask: 0x03)      */
#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Pos (13UL)                   /*!< DEM RF_FTDF_CTRL4_REG: FTDF_HSI_POL (Bit 13)                */
#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Msk (0x2000UL)               /*!< DEM RF_FTDF_CTRL4_REG: FTDF_HSI_POL (Bitfield-Mask: 0x01)   */
#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Pos    (14UL)                    /*!< DEM RF_FTDF_CTRL4_REG: CCA_MODE (Bit 14)                    */
#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Msk    (0x4000UL)                /*!< DEM RF_FTDF_CTRL4_REG: CCA_MODE (Bitfield-Mask: 0x01)       */
#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Pos (15UL)                    /*!< DEM RF_FTDF_CTRL4_REG: SO_FTDF_SEL (Bit 15)                 */
#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Msk (0x8000UL)                /*!< DEM RF_FTDF_CTRL4_REG: SO_FTDF_SEL (Bitfield-Mask: 0x01)    */

/* ------------------------  DEM_RF_FTDF_LOOP_GAIN_PD_REG  ------------------------ */
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Pos (0UL)                 /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KP_LF_PD (Bit 0)              */
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Msk (0xffUL)              /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KP_LF_PD (Bitfield-Mask: 0xff) */
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Pos (8UL)                 /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KI_LF_PD (Bit 8)              */
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Msk (0xff00UL)            /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KI_LF_PD (Bitfield-Mask: 0xff) */

/* ------------------------  DEM_RF_FTDF_LOOP_GAIN_DS_REG  ------------------------ */
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Pos (0UL)                 /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KP_LF_DS (Bit 0)              */
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Msk (0xffUL)              /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KP_LF_DS (Bitfield-Mask: 0xff) */
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Pos (8UL)                 /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KI_LF_DS (Bit 8)              */
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Msk (0xff00UL)            /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KI_LF_DS (Bitfield-Mask: 0xff) */

/* ----------------------------  DEM_RF_FTDF_CTRL5_REG  --------------------------- */
#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Pos      (0UL)                     /*!< DEM RF_FTDF_CTRL5_REG: RSSITH (Bit 0)                       */
#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Msk      (0x1fffUL)                /*!< DEM RF_FTDF_CTRL5_REG: RSSITH (Bitfield-Mask: 0x1fff)       */
#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Pos (13UL)                   /*!< DEM RF_FTDF_CTRL5_REG: FTDF_DDC_INV (Bit 13)                */
#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Msk (0x2000UL)               /*!< DEM RF_FTDF_CTRL5_REG: FTDF_DDC_INV (Bitfield-Mask: 0x01)   */
#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Pos  (14UL)                    /*!< DEM RF_FTDF_CTRL5_REG: FSSS_CLEAR (Bit 14)                  */
#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Msk  (0x4000UL)                /*!< DEM RF_FTDF_CTRL5_REG: FSSS_CLEAR (Bitfield-Mask: 0x01)     */
#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Pos (15UL)                  /*!< DEM RF_FTDF_CTRL5_REG: DS_OFFSET_SEL (Bit 15)               */
#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Msk (0x8000UL)              /*!< DEM RF_FTDF_CTRL5_REG: DS_OFFSET_SEL (Bitfield-Mask: 0x01)  */

/* --------------------------  DEM_RF_FTDF_COBI_LOW_REG  -------------------------- */
#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Pos     (0UL)                     /*!< DEM RF_FTDF_COBI_LOW_REG: COBI (Bit 0)                      */
#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Msk     (0xffffUL)                /*!< DEM RF_FTDF_COBI_LOW_REG: COBI (Bitfield-Mask: 0xffff)      */

/* --------------------------  DEM_RF_FTDF_COBI_HIGH_REG  ------------------------- */
#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Pos    (0UL)                     /*!< DEM RF_FTDF_COBI_HIGH_REG: COBI (Bit 0)                     */
#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Msk    (0xffffUL)                /*!< DEM RF_FTDF_COBI_HIGH_REG: COBI (Bitfield-Mask: 0xffff)     */

/* ---------------------------  DEM_RF_DEM_TESTMODE_REG  -------------------------- */
#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Pos (0UL)                  /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bit 0)               */
#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk (0x3ffUL)              /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bitfield-Mask: 0x3ff) */

/* --------------------------  DEM_RF_DEM_IQCORRECT_REG  -------------------------- */
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Pos (0UL)                  /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bit 0)               */
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Msk (0xffUL)               /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bitfield-Mask: 0xff) */
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Pos (8UL)                 /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_ALPHA (Bit 8)              */
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Msk (0xff00UL)            /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_ALPHA (Bitfield-Mask: 0xff) */

/* ---------------------------  DEM_RF_PAD_CNT_CTRL_REG  -------------------------- */
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Pos (0UL)                 /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_POS_LIMIT (Bit 0)              */
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Msk (0x7fUL)              /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_POS_LIMIT (Bitfield-Mask: 0x7f) */
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Pos (7UL)                 /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_NEG_LIMIT (Bit 7)              */
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Msk (0x3f80UL)            /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_NEG_LIMIT (Bitfield-Mask: 0x7f) */
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Pos (14UL)              /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_CLEAR_COUNT (Bit 14)           */
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Msk (0x4000UL)          /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_CLEAR_COUNT (Bitfield-Mask: 0x01) */

/* --------------------------  DEM_RF_PAD_CNT_RESULT_REG  ------------------------- */
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Pos (0UL)              /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_POS_CNT_RD (Bit 0)           */
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Msk (0xffUL)           /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_POS_CNT_RD (Bitfield-Mask: 0xff) */
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Pos (8UL)              /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_NEG_CNT_RD (Bit 8)           */
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Msk (0xff00UL)         /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_NEG_CNT_RD (Bitfield-Mask: 0xff) */

/* --------------------------  DEM_RF_FSSS_I_RESULT_REG  -------------------------- */
#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Pos (0UL)                    /*!< DEM RF_FSSS_I_RESULT_REG: FSSS_I_RD (Bit 0)                 */
#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Msk (0xffffUL)               /*!< DEM RF_FSSS_I_RESULT_REG: FSSS_I_RD (Bitfield-Mask: 0xffff) */

/* --------------------------  DEM_RF_FSSS_Q_RESULT_REG  -------------------------- */
#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Pos (0UL)                    /*!< DEM RF_FSSS_Q_RESULT_REG: FSSS_Q_RD (Bit 0)                 */
#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Msk (0xffffUL)               /*!< DEM RF_FSSS_Q_RESULT_REG: FSSS_Q_RD (Bitfield-Mask: 0xffff) */

/* -------------------------  DEM_RF_FSSS_MAG_RESULT_REG  ------------------------- */
#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Pos (0UL)                /*!< DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bit 0)             */
#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Msk (0xffffUL)           /*!< DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bitfield-Mask: 0xffff) */

/* ----------------------------  DEM_RF_CCA_RSSITH_REG  --------------------------- */
#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Pos  (0UL)                     /*!< DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bit 0)                   */
#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Msk  (0x1fffUL)                /*!< DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bitfield-Mask: 0x1fff)   */
#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Pos (13UL)             /*!< DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bit 13)          */
#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Msk (0xe000UL)         /*!< DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bitfield-Mask: 0x07) */

/* -------------------------  DEM_RF_FTDF_SIGDET_CTRL_REG  ------------------------ */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Pos (0UL)               /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bit 0)            */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Msk (0x3UL)             /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bitfield-Mask: 0x03) */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Pos (2UL)          /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bit 2)       */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Msk (0xfcUL)       /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bitfield-Mask: 0x3f) */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Pos (8UL)               /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bit 8)            */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Msk (0x100UL)           /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bitfield-Mask: 0x01) */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Pos (9UL)           /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bit 9)        */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Msk (0x600UL)       /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bitfield-Mask: 0x03) */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Pos (11UL)          /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bit 11)       */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Msk (0x1800UL)      /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bitfield-Mask: 0x03) */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Pos (13UL)             /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bit 13)          */
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Msk (0x6000UL)         /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bitfield-Mask: 0x03) */


/* ================================================================================ */
/* ================          struct 'DMA' Position & Mask          ================ */
/* ================================================================================ */


/* ----------------------------  DMA_DMA0_A_STARTL_REG  --------------------------- */
#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Pos (0UL)                   /*!< DMA DMA0_A_STARTL_REG: DMA0_A_STARTL (Bit 0)                */
#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA0_A_STARTL_REG: DMA0_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA0_A_STARTH_REG  --------------------------- */
#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Pos (0UL)                   /*!< DMA DMA0_A_STARTH_REG: DMA0_A_STARTH (Bit 0)                */
#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA0_A_STARTH_REG: DMA0_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA0_B_STARTL_REG  --------------------------- */
#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Pos (0UL)                   /*!< DMA DMA0_B_STARTL_REG: DMA0_B_STARTL (Bit 0)                */
#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA0_B_STARTL_REG: DMA0_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA0_B_STARTH_REG  --------------------------- */
#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Pos (0UL)                   /*!< DMA DMA0_B_STARTH_REG: DMA0_B_STARTH (Bit 0)                */
#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA0_B_STARTH_REG: DMA0_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA0_INT_REG  ------------------------------ */
#define DMA_DMA0_INT_REG_DMA0_INT_Pos         (0UL)                     /*!< DMA DMA0_INT_REG: DMA0_INT (Bit 0)                          */
#define DMA_DMA0_INT_REG_DMA0_INT_Msk         (0xffffUL)                /*!< DMA DMA0_INT_REG: DMA0_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA0_LEN_REG  ------------------------------ */
#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos         (0UL)                     /*!< DMA DMA0_LEN_REG: DMA0_LEN (Bit 0)                          */
#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk         (0xffffUL)                /*!< DMA DMA0_LEN_REG: DMA0_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA0_CTRL_REG  ----------------------------- */
#define DMA_DMA0_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA0_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA0_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA0_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA0_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA0_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA0_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA0_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA0_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA0_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA0_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA0_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA0_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA0_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA0_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA0_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA0_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA0_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA0_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA0_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA0_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA0_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA0_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA0_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA0_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA0_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA0_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA0_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA0_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA0_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA0_IDX_REG  ------------------------------ */
#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos         (0UL)                     /*!< DMA DMA0_IDX_REG: DMA0_IDX (Bit 0)                          */
#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk         (0xffffUL)                /*!< DMA DMA0_IDX_REG: DMA0_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA1_A_STARTL_REG  --------------------------- */
#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Pos (0UL)                   /*!< DMA DMA1_A_STARTL_REG: DMA1_A_STARTL (Bit 0)                */
#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA1_A_STARTL_REG: DMA1_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA1_A_STARTH_REG  --------------------------- */
#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Pos (0UL)                   /*!< DMA DMA1_A_STARTH_REG: DMA1_A_STARTH (Bit 0)                */
#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA1_A_STARTH_REG: DMA1_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA1_B_STARTL_REG  --------------------------- */
#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Pos (0UL)                   /*!< DMA DMA1_B_STARTL_REG: DMA1_B_STARTL (Bit 0)                */
#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA1_B_STARTL_REG: DMA1_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA1_B_STARTH_REG  --------------------------- */
#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Pos (0UL)                   /*!< DMA DMA1_B_STARTH_REG: DMA1_B_STARTH (Bit 0)                */
#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA1_B_STARTH_REG: DMA1_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA1_INT_REG  ------------------------------ */
#define DMA_DMA1_INT_REG_DMA1_INT_Pos         (0UL)                     /*!< DMA DMA1_INT_REG: DMA1_INT (Bit 0)                          */
#define DMA_DMA1_INT_REG_DMA1_INT_Msk         (0xffffUL)                /*!< DMA DMA1_INT_REG: DMA1_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA1_LEN_REG  ------------------------------ */
#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos         (0UL)                     /*!< DMA DMA1_LEN_REG: DMA1_LEN (Bit 0)                          */
#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk         (0xffffUL)                /*!< DMA DMA1_LEN_REG: DMA1_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA1_CTRL_REG  ----------------------------- */
#define DMA_DMA1_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA1_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA1_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA1_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA1_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA1_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA1_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA1_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA1_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA1_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA1_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA1_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA1_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA1_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA1_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA1_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA1_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA1_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA1_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA1_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA1_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA1_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA1_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA1_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA1_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA1_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA1_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA1_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA1_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA1_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA1_IDX_REG  ------------------------------ */
#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos         (0UL)                     /*!< DMA DMA1_IDX_REG: DMA1_IDX (Bit 0)                          */
#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk         (0xffffUL)                /*!< DMA DMA1_IDX_REG: DMA1_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA2_A_STARTL_REG  --------------------------- */
#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Pos (0UL)                   /*!< DMA DMA2_A_STARTL_REG: DMA2_A_STARTL (Bit 0)                */
#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA2_A_STARTL_REG: DMA2_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA2_A_STARTH_REG  --------------------------- */
#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Pos (0UL)                   /*!< DMA DMA2_A_STARTH_REG: DMA2_A_STARTH (Bit 0)                */
#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA2_A_STARTH_REG: DMA2_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA2_B_STARTL_REG  --------------------------- */
#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Pos (0UL)                   /*!< DMA DMA2_B_STARTL_REG: DMA2_B_STARTL (Bit 0)                */
#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA2_B_STARTL_REG: DMA2_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA2_B_STARTH_REG  --------------------------- */
#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Pos (0UL)                   /*!< DMA DMA2_B_STARTH_REG: DMA2_B_STARTH (Bit 0)                */
#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA2_B_STARTH_REG: DMA2_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA2_INT_REG  ------------------------------ */
#define DMA_DMA2_INT_REG_DMA2_INT_Pos         (0UL)                     /*!< DMA DMA2_INT_REG: DMA2_INT (Bit 0)                          */
#define DMA_DMA2_INT_REG_DMA2_INT_Msk         (0xffffUL)                /*!< DMA DMA2_INT_REG: DMA2_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA2_LEN_REG  ------------------------------ */
#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos         (0UL)                     /*!< DMA DMA2_LEN_REG: DMA2_LEN (Bit 0)                          */
#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk         (0xffffUL)                /*!< DMA DMA2_LEN_REG: DMA2_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA2_CTRL_REG  ----------------------------- */
#define DMA_DMA2_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA2_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA2_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA2_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA2_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA2_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA2_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA2_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA2_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA2_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA2_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA2_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA2_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA2_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA2_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA2_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA2_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA2_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA2_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA2_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA2_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA2_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA2_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA2_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA2_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA2_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA2_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA2_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA2_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA2_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA2_IDX_REG  ------------------------------ */
#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos         (0UL)                     /*!< DMA DMA2_IDX_REG: DMA2_IDX (Bit 0)                          */
#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk         (0xffffUL)                /*!< DMA DMA2_IDX_REG: DMA2_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA3_A_STARTL_REG  --------------------------- */
#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Pos (0UL)                   /*!< DMA DMA3_A_STARTL_REG: DMA3_A_STARTL (Bit 0)                */
#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA3_A_STARTL_REG: DMA3_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA3_A_STARTH_REG  --------------------------- */
#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Pos (0UL)                   /*!< DMA DMA3_A_STARTH_REG: DMA3_A_STARTH (Bit 0)                */
#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA3_A_STARTH_REG: DMA3_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA3_B_STARTL_REG  --------------------------- */
#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Pos (0UL)                   /*!< DMA DMA3_B_STARTL_REG: DMA3_B_STARTL (Bit 0)                */
#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA3_B_STARTL_REG: DMA3_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA3_B_STARTH_REG  --------------------------- */
#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Pos (0UL)                   /*!< DMA DMA3_B_STARTH_REG: DMA3_B_STARTH (Bit 0)                */
#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA3_B_STARTH_REG: DMA3_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA3_INT_REG  ------------------------------ */
#define DMA_DMA3_INT_REG_DMA3_INT_Pos         (0UL)                     /*!< DMA DMA3_INT_REG: DMA3_INT (Bit 0)                          */
#define DMA_DMA3_INT_REG_DMA3_INT_Msk         (0xffffUL)                /*!< DMA DMA3_INT_REG: DMA3_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA3_LEN_REG  ------------------------------ */
#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos         (0UL)                     /*!< DMA DMA3_LEN_REG: DMA3_LEN (Bit 0)                          */
#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk         (0xffffUL)                /*!< DMA DMA3_LEN_REG: DMA3_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA3_CTRL_REG  ----------------------------- */
#define DMA_DMA3_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA3_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA3_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA3_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA3_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA3_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA3_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA3_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA3_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA3_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA3_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA3_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA3_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA3_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA3_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA3_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA3_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA3_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA3_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA3_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA3_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA3_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA3_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA3_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA3_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA3_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA3_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA3_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA3_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA3_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA3_IDX_REG  ------------------------------ */
#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos         (0UL)                     /*!< DMA DMA3_IDX_REG: DMA3_IDX (Bit 0)                          */
#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk         (0xffffUL)                /*!< DMA DMA3_IDX_REG: DMA3_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA4_A_STARTL_REG  --------------------------- */
#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Pos (0UL)                   /*!< DMA DMA4_A_STARTL_REG: DMA4_A_STARTL (Bit 0)                */
#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA4_A_STARTL_REG: DMA4_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA4_A_STARTH_REG  --------------------------- */
#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Pos (0UL)                   /*!< DMA DMA4_A_STARTH_REG: DMA4_A_STARTH (Bit 0)                */
#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA4_A_STARTH_REG: DMA4_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA4_B_STARTL_REG  --------------------------- */
#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Pos (0UL)                   /*!< DMA DMA4_B_STARTL_REG: DMA4_B_STARTL (Bit 0)                */
#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA4_B_STARTL_REG: DMA4_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA4_B_STARTH_REG  --------------------------- */
#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Pos (0UL)                   /*!< DMA DMA4_B_STARTH_REG: DMA4_B_STARTH (Bit 0)                */
#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA4_B_STARTH_REG: DMA4_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA4_INT_REG  ------------------------------ */
#define DMA_DMA4_INT_REG_DMA4_INT_Pos         (0UL)                     /*!< DMA DMA4_INT_REG: DMA4_INT (Bit 0)                          */
#define DMA_DMA4_INT_REG_DMA4_INT_Msk         (0xffffUL)                /*!< DMA DMA4_INT_REG: DMA4_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA4_LEN_REG  ------------------------------ */
#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos         (0UL)                     /*!< DMA DMA4_LEN_REG: DMA4_LEN (Bit 0)                          */
#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk         (0xffffUL)                /*!< DMA DMA4_LEN_REG: DMA4_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA4_CTRL_REG  ----------------------------- */
#define DMA_DMA4_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA4_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA4_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA4_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA4_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA4_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA4_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA4_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA4_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA4_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA4_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA4_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA4_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA4_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA4_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA4_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA4_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA4_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA4_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA4_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA4_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA4_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA4_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA4_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA4_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA4_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA4_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA4_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA4_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA4_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA4_IDX_REG  ------------------------------ */
#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos         (0UL)                     /*!< DMA DMA4_IDX_REG: DMA4_IDX (Bit 0)                          */
#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk         (0xffffUL)                /*!< DMA DMA4_IDX_REG: DMA4_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA5_A_STARTL_REG  --------------------------- */
#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Pos (0UL)                   /*!< DMA DMA5_A_STARTL_REG: DMA5_A_STARTL (Bit 0)                */
#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA5_A_STARTL_REG: DMA5_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA5_A_STARTH_REG  --------------------------- */
#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Pos (0UL)                   /*!< DMA DMA5_A_STARTH_REG: DMA5_A_STARTH (Bit 0)                */
#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA5_A_STARTH_REG: DMA5_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA5_B_STARTL_REG  --------------------------- */
#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Pos (0UL)                   /*!< DMA DMA5_B_STARTL_REG: DMA5_B_STARTL (Bit 0)                */
#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA5_B_STARTL_REG: DMA5_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA5_B_STARTH_REG  --------------------------- */
#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Pos (0UL)                   /*!< DMA DMA5_B_STARTH_REG: DMA5_B_STARTH (Bit 0)                */
#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA5_B_STARTH_REG: DMA5_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA5_INT_REG  ------------------------------ */
#define DMA_DMA5_INT_REG_DMA5_INT_Pos         (0UL)                     /*!< DMA DMA5_INT_REG: DMA5_INT (Bit 0)                          */
#define DMA_DMA5_INT_REG_DMA5_INT_Msk         (0xffffUL)                /*!< DMA DMA5_INT_REG: DMA5_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA5_LEN_REG  ------------------------------ */
#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos         (0UL)                     /*!< DMA DMA5_LEN_REG: DMA5_LEN (Bit 0)                          */
#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk         (0xffffUL)                /*!< DMA DMA5_LEN_REG: DMA5_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA5_CTRL_REG  ----------------------------- */
#define DMA_DMA5_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA5_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA5_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA5_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA5_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA5_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA5_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA5_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA5_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA5_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA5_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA5_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA5_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA5_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA5_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA5_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA5_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA5_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA5_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA5_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA5_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA5_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA5_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA5_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA5_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA5_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA5_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA5_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA5_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA5_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA5_IDX_REG  ------------------------------ */
#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos         (0UL)                     /*!< DMA DMA5_IDX_REG: DMA5_IDX (Bit 0)                          */
#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk         (0xffffUL)                /*!< DMA DMA5_IDX_REG: DMA5_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA6_A_STARTL_REG  --------------------------- */
#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Pos (0UL)                   /*!< DMA DMA6_A_STARTL_REG: DMA6_A_STARTL (Bit 0)                */
#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA6_A_STARTL_REG: DMA6_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA6_A_STARTH_REG  --------------------------- */
#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Pos (0UL)                   /*!< DMA DMA6_A_STARTH_REG: DMA6_A_STARTH (Bit 0)                */
#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA6_A_STARTH_REG: DMA6_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA6_B_STARTL_REG  --------------------------- */
#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Pos (0UL)                   /*!< DMA DMA6_B_STARTL_REG: DMA6_B_STARTL (Bit 0)                */
#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA6_B_STARTL_REG: DMA6_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA6_B_STARTH_REG  --------------------------- */
#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Pos (0UL)                   /*!< DMA DMA6_B_STARTH_REG: DMA6_B_STARTH (Bit 0)                */
#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA6_B_STARTH_REG: DMA6_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA6_INT_REG  ------------------------------ */
#define DMA_DMA6_INT_REG_DMA6_INT_Pos         (0UL)                     /*!< DMA DMA6_INT_REG: DMA6_INT (Bit 0)                          */
#define DMA_DMA6_INT_REG_DMA6_INT_Msk         (0xffffUL)                /*!< DMA DMA6_INT_REG: DMA6_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA6_LEN_REG  ------------------------------ */
#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos         (0UL)                     /*!< DMA DMA6_LEN_REG: DMA6_LEN (Bit 0)                          */
#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk         (0xffffUL)                /*!< DMA DMA6_LEN_REG: DMA6_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA6_CTRL_REG  ----------------------------- */
#define DMA_DMA6_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA6_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA6_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA6_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA6_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA6_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA6_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA6_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA6_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA6_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA6_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA6_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA6_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA6_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA6_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA6_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA6_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA6_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA6_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA6_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA6_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA6_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA6_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA6_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA6_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA6_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA6_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA6_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA6_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA6_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA6_IDX_REG  ------------------------------ */
#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos         (0UL)                     /*!< DMA DMA6_IDX_REG: DMA6_IDX (Bit 0)                          */
#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk         (0xffffUL)                /*!< DMA DMA6_IDX_REG: DMA6_IDX (Bitfield-Mask: 0xffff)          */

/* ----------------------------  DMA_DMA7_A_STARTL_REG  --------------------------- */
#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Pos (0UL)                   /*!< DMA DMA7_A_STARTL_REG: DMA7_A_STARTL (Bit 0)                */
#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Msk (0xffffUL)              /*!< DMA DMA7_A_STARTL_REG: DMA7_A_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA7_A_STARTH_REG  --------------------------- */
#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Pos (0UL)                   /*!< DMA DMA7_A_STARTH_REG: DMA7_A_STARTH (Bit 0)                */
#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Msk (0xffffUL)              /*!< DMA DMA7_A_STARTH_REG: DMA7_A_STARTH (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA7_B_STARTL_REG  --------------------------- */
#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Pos (0UL)                   /*!< DMA DMA7_B_STARTL_REG: DMA7_B_STARTL (Bit 0)                */
#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Msk (0xffffUL)              /*!< DMA DMA7_B_STARTL_REG: DMA7_B_STARTL (Bitfield-Mask: 0xffff) */

/* ----------------------------  DMA_DMA7_B_STARTH_REG  --------------------------- */
#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Pos (0UL)                   /*!< DMA DMA7_B_STARTH_REG: DMA7_B_STARTH (Bit 0)                */
#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Msk (0xffffUL)              /*!< DMA DMA7_B_STARTH_REG: DMA7_B_STARTH (Bitfield-Mask: 0xffff) */

/* ------------------------------  DMA_DMA7_INT_REG  ------------------------------ */
#define DMA_DMA7_INT_REG_DMA7_INT_Pos         (0UL)                     /*!< DMA DMA7_INT_REG: DMA7_INT (Bit 0)                          */
#define DMA_DMA7_INT_REG_DMA7_INT_Msk         (0xffffUL)                /*!< DMA DMA7_INT_REG: DMA7_INT (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA7_LEN_REG  ------------------------------ */
#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos         (0UL)                     /*!< DMA DMA7_LEN_REG: DMA7_LEN (Bit 0)                          */
#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk         (0xffffUL)                /*!< DMA DMA7_LEN_REG: DMA7_LEN (Bitfield-Mask: 0xffff)          */

/* ------------------------------  DMA_DMA7_CTRL_REG  ----------------------------- */
#define DMA_DMA7_CTRL_REG_DMA_ON_Pos          (0UL)                     /*!< DMA DMA7_CTRL_REG: DMA_ON (Bit 0)                           */
#define DMA_DMA7_CTRL_REG_DMA_ON_Msk          (0x1UL)                   /*!< DMA DMA7_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)             */
#define DMA_DMA7_CTRL_REG_BW_Pos              (1UL)                     /*!< DMA DMA7_CTRL_REG: BW (Bit 1)                               */
#define DMA_DMA7_CTRL_REG_BW_Msk              (0x6UL)                   /*!< DMA DMA7_CTRL_REG: BW (Bitfield-Mask: 0x03)                 */
#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Pos      (3UL)                     /*!< DMA DMA7_CTRL_REG: IRQ_ENABLE (Bit 3)                       */
#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Msk      (0x8UL)                   /*!< DMA DMA7_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos       (4UL)                     /*!< DMA DMA7_CTRL_REG: DREQ_MODE (Bit 4)                        */
#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk       (0x10UL)                  /*!< DMA DMA7_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)          */
#define DMA_DMA7_CTRL_REG_BINC_Pos            (5UL)                     /*!< DMA DMA7_CTRL_REG: BINC (Bit 5)                             */
#define DMA_DMA7_CTRL_REG_BINC_Msk            (0x20UL)                  /*!< DMA DMA7_CTRL_REG: BINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA7_CTRL_REG_AINC_Pos            (6UL)                     /*!< DMA DMA7_CTRL_REG: AINC (Bit 6)                             */
#define DMA_DMA7_CTRL_REG_AINC_Msk            (0x40UL)                  /*!< DMA DMA7_CTRL_REG: AINC (Bitfield-Mask: 0x01)               */
#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos        (7UL)                     /*!< DMA DMA7_CTRL_REG: CIRCULAR (Bit 7)                         */
#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk        (0x80UL)                  /*!< DMA DMA7_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)           */
#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos        (8UL)                     /*!< DMA DMA7_CTRL_REG: DMA_PRIO (Bit 8)                         */
#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk        (0x700UL)                 /*!< DMA DMA7_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)           */
#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos        (11UL)                    /*!< DMA DMA7_CTRL_REG: DMA_IDLE (Bit 11)                        */
#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk        (0x800UL)                 /*!< DMA DMA7_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)           */
#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos        (12UL)                    /*!< DMA DMA7_CTRL_REG: DMA_INIT (Bit 12)                        */
#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk        (0x1000UL)                /*!< DMA DMA7_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)           */
#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos       (13UL)                    /*!< DMA DMA7_CTRL_REG: REQ_SENSE (Bit 13)                       */
#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk       (0x2000UL)                /*!< DMA DMA7_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)          */

/* ------------------------------  DMA_DMA7_IDX_REG  ------------------------------ */
#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos         (0UL)                     /*!< DMA DMA7_IDX_REG: DMA7_IDX (Bit 0)                          */
#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk         (0xffffUL)                /*!< DMA DMA7_IDX_REG: DMA7_IDX (Bitfield-Mask: 0xffff)          */

/* -----------------------------  DMA_DMA_REQ_MUX_REG  ---------------------------- */
#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos     (0UL)                     /*!< DMA DMA_REQ_MUX_REG: DMA01_SEL (Bit 0)                      */
#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk     (0xfUL)                   /*!< DMA DMA_REQ_MUX_REG: DMA01_SEL (Bitfield-Mask: 0x0f)        */
#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos     (4UL)                     /*!< DMA DMA_REQ_MUX_REG: DMA23_SEL (Bit 4)                      */
#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk     (0xf0UL)                  /*!< DMA DMA_REQ_MUX_REG: DMA23_SEL (Bitfield-Mask: 0x0f)        */
#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos     (8UL)                     /*!< DMA DMA_REQ_MUX_REG: DMA45_SEL (Bit 8)                      */
#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk     (0xf00UL)                 /*!< DMA DMA_REQ_MUX_REG: DMA45_SEL (Bitfield-Mask: 0x0f)        */
#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos     (12UL)                    /*!< DMA DMA_REQ_MUX_REG: DMA67_SEL (Bit 12)                     */
#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk     (0xf000UL)                /*!< DMA DMA_REQ_MUX_REG: DMA67_SEL (Bitfield-Mask: 0x0f)        */

/* ---------------------------  DMA_DMA_INT_STATUS_REG  --------------------------- */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH0 (Bit 0)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL)                  /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH0 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH1 (Bit 1)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL)                  /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH1 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH2 (Bit 2)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL)                  /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH2 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH3 (Bit 3)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL)                  /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH3 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH4 (Bit 4)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL)                 /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH4 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH5 (Bit 5)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL)                 /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH5 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos (6UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH6 (Bit 6)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk (0x40UL)                 /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH6 (Bitfield-Mask: 0x01)   */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos (7UL)                    /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH7 (Bit 7)                 */
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk (0x80UL)                 /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH7 (Bitfield-Mask: 0x01)   */

/* ----------------------------  DMA_DMA_CLEAR_INT_REG  --------------------------- */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH0 (Bit 0)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL)               /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH1 (Bit 1)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL)               /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH2 (Bit 2)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL)               /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH3 (Bit 3)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL)               /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH4 (Bit 4)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL)              /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH5 (Bit 5)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL)              /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos (6UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH6 (Bit 6)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk (0x40UL)              /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01) */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos (7UL)                 /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH7 (Bit 7)              */
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk (0x80UL)              /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================          struct 'ECC' Position & Mask          ================ */
/* ================================================================================ */


/* -----------------------------  ECC_ECC_CONFIG_REG  ----------------------------- */
#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Pos     (0UL)                     /*!< ECC ECC_CONFIG_REG: ECC_OpPtrA (Bit 0)                      */
#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Msk     (0x1fUL)                  /*!< ECC ECC_CONFIG_REG: ECC_OpPtrA (Bitfield-Mask: 0x1f)        */
#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Pos     (8UL)                     /*!< ECC ECC_CONFIG_REG: ECC_OpPtrB (Bit 8)                      */
#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Msk     (0x1f00UL)                /*!< ECC ECC_CONFIG_REG: ECC_OpPtrB (Bitfield-Mask: 0x1f)        */
#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Pos     (16UL)                    /*!< ECC ECC_CONFIG_REG: ECC_OpPtrC (Bit 16)                     */
#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Msk     (0x1f0000UL)              /*!< ECC ECC_CONFIG_REG: ECC_OpPtrC (Bitfield-Mask: 0x1f)        */

/* -----------------------------  ECC_ECC_COMMAND_REG  ---------------------------- */
#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Pos (0UL)                 /*!< ECC ECC_COMMAND_REG: ECC_TypeOperation (Bit 0)              */
#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Msk (0x7fUL)              /*!< ECC ECC_COMMAND_REG: ECC_TypeOperation (Bitfield-Mask: 0x7f) */
#define ECC_ECC_COMMAND_REG_ECC_Field_Pos     (7UL)                     /*!< ECC ECC_COMMAND_REG: ECC_Field (Bit 7)                      */
#define ECC_ECC_COMMAND_REG_ECC_Field_Msk     (0x80UL)                  /*!< ECC ECC_COMMAND_REG: ECC_Field (Bitfield-Mask: 0x01)        */
#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Pos (8UL)                /*!< ECC ECC_COMMAND_REG: ECC_SizeOfOperands (Bit 8)             */
#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Msk (0xff00UL)           /*!< ECC ECC_COMMAND_REG: ECC_SizeOfOperands (Bitfield-Mask: 0xff) */
#define ECC_ECC_COMMAND_REG_ECC_SignA_Pos     (29UL)                    /*!< ECC ECC_COMMAND_REG: ECC_SignA (Bit 29)                     */
#define ECC_ECC_COMMAND_REG_ECC_SignA_Msk     (0x20000000UL)            /*!< ECC ECC_COMMAND_REG: ECC_SignA (Bitfield-Mask: 0x01)        */
#define ECC_ECC_COMMAND_REG_ECC_SignB_Pos     (30UL)                    /*!< ECC ECC_COMMAND_REG: ECC_SignB (Bit 30)                     */
#define ECC_ECC_COMMAND_REG_ECC_SignB_Msk     (0x40000000UL)            /*!< ECC ECC_COMMAND_REG: ECC_SignB (Bitfield-Mask: 0x01)        */
#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Pos    (31UL)                    /*!< ECC ECC_COMMAND_REG: ECC_CalcR2 (Bit 31)                    */
#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Msk    (0x80000000UL)            /*!< ECC ECC_COMMAND_REG: ECC_CalcR2 (Bitfield-Mask: 0x01)       */

/* -----------------------------  ECC_ECC_CONTROL_REG  ---------------------------- */
#define ECC_ECC_CONTROL_REG_ECC_Start_Pos     (0UL)                     /*!< ECC ECC_CONTROL_REG: ECC_Start (Bit 0)                      */
#define ECC_ECC_CONTROL_REG_ECC_Start_Msk     (0x1UL)                   /*!< ECC ECC_CONTROL_REG: ECC_Start (Bitfield-Mask: 0x01)        */

/* -----------------------------  ECC_ECC_STATUS_REG  ----------------------------- */
#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Pos (0UL)                   /*!< ECC ECC_STATUS_REG: ECC_Fail_Address (Bit 0)                */
#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Msk (0xfUL)                 /*!< ECC ECC_STATUS_REG: ECC_Fail_Address (Bitfield-Mask: 0x0f)  */
#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Pos (4UL)            /*!< ECC ECC_STATUS_REG: ECC_Point_Px_NotOnCurve (Bit 4)         */
#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Msk (0x10UL)         /*!< ECC ECC_STATUS_REG: ECC_Point_Px_NotOnCurve (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Pos (5UL)            /*!< ECC ECC_STATUS_REG: ECC_Point_Px_AtInfinity (Bit 5)         */
#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Msk (0x20UL)         /*!< ECC ECC_STATUS_REG: ECC_Point_Px_AtInfinity (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Pos (6UL)                /*!< ECC ECC_STATUS_REG: ECC_Couple_NotValid (Bit 6)             */
#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Msk (0x40UL)             /*!< ECC ECC_STATUS_REG: ECC_Couple_NotValid (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Pos (7UL)               /*!< ECC ECC_STATUS_REG: ECC_Param_n_NotValid (Bit 7)            */
#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Msk (0x80UL)            /*!< ECC ECC_STATUS_REG: ECC_Param_n_NotValid (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Pos (9UL)             /*!< ECC ECC_STATUS_REG: ECC_Signature_NotValid (Bit 9)          */
#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Msk (0x200UL)         /*!< ECC ECC_STATUS_REG: ECC_Signature_NotValid (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Pos (10UL)             /*!< ECC ECC_STATUS_REG: ECC_Param_AB_NotValid (Bit 10)          */
#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Msk (0x400UL)          /*!< ECC ECC_STATUS_REG: ECC_Param_AB_NotValid (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Pos (11UL)                 /*!< ECC ECC_STATUS_REG: ECC_NotInvertible (Bit 11)              */
#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Msk (0x800UL)              /*!< ECC ECC_STATUS_REG: ECC_NotInvertible (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Pos (12UL)           /*!< ECC ECC_STATUS_REG: ECC_PrimalityTestResult (Bit 12)        */
#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Msk (0x1000UL)       /*!< ECC ECC_STATUS_REG: ECC_PrimalityTestResult (Bitfield-Mask: 0x01) */
#define ECC_ECC_STATUS_REG_ECC_Busy_Pos       (16UL)                    /*!< ECC ECC_STATUS_REG: ECC_Busy (Bit 16)                       */
#define ECC_ECC_STATUS_REG_ECC_Busy_Msk       (0x10000UL)               /*!< ECC ECC_STATUS_REG: ECC_Busy (Bitfield-Mask: 0x01)          */

/* -----------------------------  ECC_ECC_VERSION_REG  ---------------------------- */
#define ECC_ECC_VERSION_REG_ECC_SVN_Pos       (0UL)                     /*!< ECC ECC_VERSION_REG: ECC_SVN (Bit 0)                        */
#define ECC_ECC_VERSION_REG_ECC_SVN_Msk       (0xffUL)                  /*!< ECC ECC_VERSION_REG: ECC_SVN (Bitfield-Mask: 0xff)          */
#define ECC_ECC_VERSION_REG_ECC_HVN_Pos       (8UL)                     /*!< ECC ECC_VERSION_REG: ECC_HVN (Bit 8)                        */
#define ECC_ECC_VERSION_REG_ECC_HVN_Msk       (0xff00UL)                /*!< ECC ECC_VERSION_REG: ECC_HVN (Bitfield-Mask: 0xff)          */


/* ================================================================================ */
/* ================          struct 'FTDF' Position & Mask         ================ */
/* ================================================================================ */


/* --------------------------  FTDF_FTDF_TX_FIFO_0_0_REG  ------------------------- */
#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_TX_FIFO_0_0_REG: TX_FIFO (Bit 0)                  */
#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_TX_FIFO_0_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_TX_FIFO_1_0_REG  ------------------------- */
#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_TX_FIFO_1_0_REG: TX_FIFO (Bit 0)                  */
#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_TX_FIFO_1_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_TX_FIFO_2_0_REG  ------------------------- */
#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_TX_FIFO_2_0_REG: TX_FIFO (Bit 0)                  */
#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_TX_FIFO_2_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_TX_FIFO_3_0_REG  ------------------------- */
#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_TX_FIFO_3_0_REG: TX_FIFO (Bit 0)                  */
#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_TX_FIFO_3_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_0_0_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Pos (0UL)           /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAME_LENGTH (Bit 0)        */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Msk (0x7fUL)        /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Pos (7UL)        /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_DEM_PTI (Bit 7)     */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Msk (0x780UL)    /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Pos (11UL)            /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CN (Bit 11)         */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Msk (0x7800UL)        /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Pos (15UL)        /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CALCAP (Bit 15)     */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Msk (0x78000UL)   /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL)  /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Pos (22UL)           /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_HSI (Bit 22)        */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Msk (0x400000UL)     /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Pos (23UL)             /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAMETYPE (Bit 23)          */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Msk (0x3800000UL)      /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAMETYPE (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Pos (26UL)            /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CSMACA_ENA (Bit 26)         */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Msk (0x4000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Pos (28UL)            /*!< FTDF FTDF_TX_META_DATA_0_0_REG: ACKREQUEST (Bit 28)         */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Msk (0x10000000UL)    /*!< FTDF FTDF_TX_META_DATA_0_0_REG: ACKREQUEST (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Pos (30UL)             /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CRC16_ENA (Bit 30)          */
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Msk (0x40000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CRC16_ENA (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_1_0_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Pos (0UL)                  /*!< FTDF FTDF_TX_META_DATA_1_0_REG: MACSN (Bit 0)               */
#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Msk (0xffUL)               /*!< FTDF FTDF_TX_META_DATA_1_0_REG: MACSN (Bitfield-Mask: 0xff) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_0_1_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Pos (0UL)           /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAME_LENGTH (Bit 0)        */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Msk (0x7fUL)        /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Pos (7UL)        /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_DEM_PTI (Bit 7)     */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Msk (0x780UL)    /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Pos (11UL)            /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CN (Bit 11)         */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Msk (0x7800UL)        /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Pos (15UL)        /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CALCAP (Bit 15)     */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Msk (0x78000UL)   /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL)  /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Pos (22UL)           /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_HSI (Bit 22)        */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Msk (0x400000UL)     /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Pos (23UL)             /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAMETYPE (Bit 23)          */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Msk (0x3800000UL)      /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAMETYPE (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Pos (26UL)            /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CSMACA_ENA (Bit 26)         */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Msk (0x4000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Pos (28UL)            /*!< FTDF FTDF_TX_META_DATA_0_1_REG: ACKREQUEST (Bit 28)         */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Msk (0x10000000UL)    /*!< FTDF FTDF_TX_META_DATA_0_1_REG: ACKREQUEST (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Pos (30UL)             /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CRC16_ENA (Bit 30)          */
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Msk (0x40000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CRC16_ENA (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_1_1_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Pos (0UL)                  /*!< FTDF FTDF_TX_META_DATA_1_1_REG: MACSN (Bit 0)               */
#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Msk (0xffUL)               /*!< FTDF FTDF_TX_META_DATA_1_1_REG: MACSN (Bitfield-Mask: 0xff) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_0_2_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Pos (0UL)           /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAME_LENGTH (Bit 0)        */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Msk (0x7fUL)        /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Pos (7UL)        /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_DEM_PTI (Bit 7)     */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Msk (0x780UL)    /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Pos (11UL)            /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CN (Bit 11)         */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Msk (0x7800UL)        /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Pos (15UL)        /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CALCAP (Bit 15)     */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Msk (0x78000UL)   /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL)  /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Pos (22UL)           /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_HSI (Bit 22)        */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Msk (0x400000UL)     /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Pos (23UL)             /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAMETYPE (Bit 23)          */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Msk (0x3800000UL)      /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAMETYPE (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Pos (26UL)            /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CSMACA_ENA (Bit 26)         */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Msk (0x4000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Pos (28UL)            /*!< FTDF FTDF_TX_META_DATA_0_2_REG: ACKREQUEST (Bit 28)         */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Msk (0x10000000UL)    /*!< FTDF FTDF_TX_META_DATA_0_2_REG: ACKREQUEST (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Pos (30UL)             /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CRC16_ENA (Bit 30)          */
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Msk (0x40000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CRC16_ENA (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_1_2_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Pos (0UL)                  /*!< FTDF FTDF_TX_META_DATA_1_2_REG: MACSN (Bit 0)               */
#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Msk (0xffUL)               /*!< FTDF FTDF_TX_META_DATA_1_2_REG: MACSN (Bitfield-Mask: 0xff) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_0_3_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Pos (0UL)           /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAME_LENGTH (Bit 0)        */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Msk (0x7fUL)        /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Pos (7UL)        /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_DEM_PTI (Bit 7)     */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Msk (0x780UL)    /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Pos (11UL)            /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CN (Bit 11)         */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Msk (0x7800UL)        /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Pos (15UL)        /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CALCAP (Bit 15)     */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Msk (0x78000UL)   /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL)  /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Pos (22UL)           /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_HSI (Bit 22)        */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Msk (0x400000UL)     /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Pos (23UL)             /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAMETYPE (Bit 23)          */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Msk (0x3800000UL)      /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAMETYPE (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Pos (26UL)            /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CSMACA_ENA (Bit 26)         */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Msk (0x4000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Pos (28UL)            /*!< FTDF FTDF_TX_META_DATA_0_3_REG: ACKREQUEST (Bit 28)         */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Msk (0x10000000UL)    /*!< FTDF FTDF_TX_META_DATA_0_3_REG: ACKREQUEST (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Pos (30UL)             /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CRC16_ENA (Bit 30)          */
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Msk (0x40000000UL)     /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CRC16_ENA (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_META_DATA_1_3_REG  ----------------------- */
#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Pos (0UL)                  /*!< FTDF FTDF_TX_META_DATA_1_3_REG: MACSN (Bit 0)               */
#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Msk (0xffUL)               /*!< FTDF FTDF_TX_META_DATA_1_3_REG: MACSN (Bitfield-Mask: 0xff) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_0_0_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Pos (0UL)        /*!< FTDF FTDF_TX_RETURN_STATUS_0_0_REG: TXTIMESTAMP (Bit 0)     */
#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_0_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_1_0_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Pos (0UL)            /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: ACKFAIL (Bit 0)         */
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Msk (0x1UL)          /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: ACKFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Pos (1UL)         /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACAFAIL (Bit 1)      */
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Msk (0x2UL)       /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Pos (2UL)    /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACANRRETRIES (Bit 2) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_0_1_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Pos (0UL)        /*!< FTDF FTDF_TX_RETURN_STATUS_0_1_REG: TXTIMESTAMP (Bit 0)     */
#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_1_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_1_1_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Pos (0UL)            /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: ACKFAIL (Bit 0)         */
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Msk (0x1UL)          /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: ACKFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Pos (1UL)         /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACAFAIL (Bit 1)      */
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Msk (0x2UL)       /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Pos (2UL)    /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACANRRETRIES (Bit 2) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_0_2_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Pos (0UL)        /*!< FTDF FTDF_TX_RETURN_STATUS_0_2_REG: TXTIMESTAMP (Bit 0)     */
#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_2_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_1_2_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Pos (0UL)            /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: ACKFAIL (Bit 0)         */
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Msk (0x1UL)          /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: ACKFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Pos (1UL)         /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACAFAIL (Bit 1)      */
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Msk (0x2UL)       /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Pos (2UL)    /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACANRRETRIES (Bit 2) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_0_3_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Pos (0UL)        /*!< FTDF FTDF_TX_RETURN_STATUS_0_3_REG: TXTIMESTAMP (Bit 0)     */
#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_3_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* ---------------------  FTDF_FTDF_TX_RETURN_STATUS_1_3_REG  --------------------- */
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Pos (0UL)            /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: ACKFAIL (Bit 0)         */
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Msk (0x1UL)          /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: ACKFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Pos (1UL)         /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACAFAIL (Bit 1)      */
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Msk (0x2UL)       /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Pos (2UL)    /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACANRRETRIES (Bit 2) */
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */

/* --------------------------  FTDF_FTDF_RX_META_0_0_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_0_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_0_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_0_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_0_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_0_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_0_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_0_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_0_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_0_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_0_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_0_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_0_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_0_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_0_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_0_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_1_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_1_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_1_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_1_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_1_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_1_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_1_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_1_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_1_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_1_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_1_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_1_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_1_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_1_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_1_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_1_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_2_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_2_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_2_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_2_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_2_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_2_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_2_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_2_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_2_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_2_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_2_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_2_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_2_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_2_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_2_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_2_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_3_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_3_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_3_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_3_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_3_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_3_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_3_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_3_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_3_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_3_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_3_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_3_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_3_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_3_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_3_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_3_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_4_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_4_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_4_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_4_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_4_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_4_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_4_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_4_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_4_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_4_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_4_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_4_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_4_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_4_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_4_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_4_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_5_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_5_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_5_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_5_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_5_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_5_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_5_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_5_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_5_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_5_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_5_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_5_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_5_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_5_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_5_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_5_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_6_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_6_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_6_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_6_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_6_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_6_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_6_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_6_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_6_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_6_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_6_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_6_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_6_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_6_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_6_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_6_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_META_0_7_REG  ------------------------- */
#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Pos (0UL)                /*!< FTDF FTDF_RX_META_0_7_REG: RX_TIMESTAMP (Bit 0)             */
#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Msk (0xffffffffUL)       /*!< FTDF FTDF_RX_META_0_7_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_META_1_7_REG  ------------------------- */
#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Pos (0UL)                 /*!< FTDF FTDF_RX_META_1_7_REG: CRC16_ERROR (Bit 0)              */
#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Msk (0x1UL)               /*!< FTDF FTDF_RX_META_1_7_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Pos (2UL)          /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_TYPE_ERROR (Bit 2)       */
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL)        /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Pos (3UL)       /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_VERSION_ERROR (Bit 3)    */
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL)     /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Pos (4UL)                /*!< FTDF FTDF_RX_META_1_7_REG: DPANID_ERROR (Bit 4)             */
#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Msk (0x10UL)             /*!< FTDF FTDF_RX_META_1_7_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Pos (5UL)                 /*!< FTDF FTDF_RX_META_1_7_REG: DADDR_ERROR (Bit 5)              */
#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Msk (0x20UL)              /*!< FTDF FTDF_RX_META_1_7_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Pos (6UL)                /*!< FTDF FTDF_RX_META_1_7_REG: SPANID_ERROR (Bit 6)             */
#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Msk (0x40UL)             /*!< FTDF FTDF_RX_META_1_7_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Pos (7UL)         /*!< FTDF FTDF_RX_META_1_7_REG: ISPANID_COORD_ERROR (Bit 7)      */
#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Msk (0x80UL)      /*!< FTDF FTDF_RX_META_1_7_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Pos (8UL)           /*!< FTDF FTDF_RX_META_1_7_REG: QUALITY_INDICATOR (Bit 8)        */
#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Msk (0xff00UL)      /*!< FTDF FTDF_RX_META_1_7_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_0_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_0_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_0_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_1_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_1_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_1_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_2_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_2_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_2_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_3_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_3_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_3_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_4_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_4_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_4_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_5_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_5_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_5_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_6_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_6_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_6_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_RX_FIFO_7_0_REG  ------------------------- */
#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Pos (0UL)                     /*!< FTDF FTDF_RX_FIFO_7_0_REG: RX_FIFO (Bit 0)                  */
#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Msk (0xffffffffUL)            /*!< FTDF FTDF_RX_FIFO_7_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_REL_NAME_0_REG  -------------------------- */
#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Pos (0UL)                     /*!< FTDF FTDF_REL_NAME_0_REG: REL_NAME (Bit 0)                  */
#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Msk (0xffffffffUL)            /*!< FTDF FTDF_REL_NAME_0_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_REL_NAME_1_REG  -------------------------- */
#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Pos (0UL)                     /*!< FTDF FTDF_REL_NAME_1_REG: REL_NAME (Bit 0)                  */
#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Msk (0xffffffffUL)            /*!< FTDF FTDF_REL_NAME_1_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_REL_NAME_2_REG  -------------------------- */
#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Pos (0UL)                     /*!< FTDF FTDF_REL_NAME_2_REG: REL_NAME (Bit 0)                  */
#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Msk (0xffffffffUL)            /*!< FTDF FTDF_REL_NAME_2_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_REL_NAME_3_REG  -------------------------- */
#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Pos (0UL)                     /*!< FTDF FTDF_REL_NAME_3_REG: REL_NAME (Bit 0)                  */
#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Msk (0xffffffffUL)            /*!< FTDF FTDF_REL_NAME_3_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_BUILDTIME_0_REG  ------------------------- */
#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Pos (0UL)                   /*!< FTDF FTDF_BUILDTIME_0_REG: BUILDTIME (Bit 0)                */
#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Msk (0xffffffffUL)          /*!< FTDF FTDF_BUILDTIME_0_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_BUILDTIME_1_REG  ------------------------- */
#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Pos (0UL)                   /*!< FTDF FTDF_BUILDTIME_1_REG: BUILDTIME (Bit 0)                */
#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Msk (0xffffffffUL)          /*!< FTDF FTDF_BUILDTIME_1_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_BUILDTIME_2_REG  ------------------------- */
#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Pos (0UL)                   /*!< FTDF FTDF_BUILDTIME_2_REG: BUILDTIME (Bit 0)                */
#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Msk (0xffffffffUL)          /*!< FTDF FTDF_BUILDTIME_2_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_BUILDTIME_3_REG  ------------------------- */
#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Pos (0UL)                   /*!< FTDF FTDF_BUILDTIME_3_REG: BUILDTIME (Bit 0)                */
#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Msk (0xffffffffUL)          /*!< FTDF FTDF_BUILDTIME_3_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_GLOB_CONTROL_0_REG  ------------------------ */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Pos (1UL)         /*!< FTDF FTDF_GLOB_CONTROL_0_REG: ISPANCOORDINATOR (Bit 1)      */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Msk (0x2UL)       /*!< FTDF FTDF_GLOB_CONTROL_0_REG: ISPANCOORDINATOR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Pos (2UL)               /*!< FTDF FTDF_GLOB_CONTROL_0_REG: RX_DMA_REQ (Bit 2)            */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Msk (0x4UL)             /*!< FTDF FTDF_GLOB_CONTROL_0_REG: RX_DMA_REQ (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Pos (3UL)               /*!< FTDF FTDF_GLOB_CONTROL_0_REG: TX_DMA_REQ (Bit 3)            */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Msk (0x8UL)             /*!< FTDF FTDF_GLOB_CONTROL_0_REG: TX_DMA_REQ (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Pos (8UL)         /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACSIMPLEADDRESS (Bit 8)      */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Msk (0xff00UL)    /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACSIMPLEADDRESS (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Pos (17UL)            /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACLEENABLED (Bit 17)         */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Msk (0x20000UL)       /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACLEENABLED (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Pos (18UL)          /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACTSCHENABLED (Bit 18)       */
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Msk (0x40000UL)     /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACTSCHENABLED (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_GLOB_CONTROL_1_REG  ------------------------ */
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Pos (0UL)                 /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACPANID (Bit 0)              */
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Msk (0xffffUL)            /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACPANID (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Pos (16UL)         /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACSHORTADDRESS (Bit 16)      */
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Msk (0xffff0000UL) /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACSHORTADDRESS (Bitfield-Mask: 0xffff) */

/* ------------------------  FTDF_FTDF_GLOB_CONTROL_2_REG  ------------------------ */
#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Pos (0UL)       /*!< FTDF FTDF_GLOB_CONTROL_2_REG: AEXTENDEDADDRESS_L (Bit 0)    */
#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Msk (0xffffffffUL) /*!< FTDF FTDF_GLOB_CONTROL_2_REG: AEXTENDEDADDRESS_L (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_GLOB_CONTROL_3_REG  ------------------------ */
#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Pos (0UL)       /*!< FTDF FTDF_GLOB_CONTROL_3_REG: AEXTENDEDADDRESS_H (Bit 0)    */
#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Msk (0xffffffffUL) /*!< FTDF FTDF_GLOB_CONTROL_3_REG: AEXTENDEDADDRESS_H (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_0_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Pos (1UL)             /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bit 1)          */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Msk (0x1fffffeUL)     /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bitfield-Mask: 0xffffff) */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Pos (25UL)              /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bit 25)           */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Msk (0x2000000UL)       /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Pos (27UL)                  /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bit 27)               */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Msk (0x78000000UL)          /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bitfield-Mask: 0x0f)  */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Pos (31UL)             /*!< FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bit 31)          */
#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Msk (0x80000000UL)     /*!< FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_TXPIPEPROPDELAY_REG  ----------------------- */
#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Pos (0UL)         /*!< FTDF FTDF_TXPIPEPROPDELAY_REG: TXPIPEPROPDELAY (Bit 0)      */
#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Msk (0xffUL)      /*!< FTDF FTDF_TXPIPEPROPDELAY_REG: TXPIPEPROPDELAY (Bitfield-Mask: 0xff) */

/* ----------------------  FTDF_FTDF_MACACKWAITDURATION_REG  ---------------------- */
#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Pos (0UL)   /*!< FTDF FTDF_MACACKWAITDURATION_REG: MACACKWAITDURATION (Bit 0) */
#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Msk (0xffUL) /*!< FTDF FTDF_MACACKWAITDURATION_REG: MACACKWAITDURATION (Bitfield-Mask: 0xff) */

/* ---------------------  FTDF_FTDF_MACENHACKWAITDURATION_REG  -------------------- */
#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Pos (0UL) /*!< FTDF FTDF_MACENHACKWAITDURATION_REG: MACENHACKWAITDURATION (Bit 0) */
#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Msk (0xffffUL) /*!< FTDF FTDF_MACENHACKWAITDURATION_REG: MACENHACKWAITDURATION (Bitfield-Mask: 0xffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_1_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Pos (0UL)        /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_DEM_PTI (Bit 0)     */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Msk (0xfUL)      /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Pos (4UL)             /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CN (Bit 4)          */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Msk (0xf0UL)          /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Pos (8UL)         /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CALCAP (Bit 8)      */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Msk (0xf00UL)     /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Pos (12UL)  /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_RF_GPIO_PINS (Bit 12) */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Msk (0x7000UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Pos (15UL)           /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_HSI (Bit 15)        */
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Msk (0x8000UL)       /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_HSI (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_2_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Pos (0UL)             /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANENABLE (Bit 0)          */
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Msk (0x1UL)           /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANENABLE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Pos (8UL)           /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANDURATION (Bit 8)        */
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Msk (0xffffff00UL)  /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANDURATION (Bitfield-Mask: 0xffffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_3_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bit 0) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Pos (16UL)             /*!< FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bit 16)          */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Msk (0xff0000UL)       /*!< FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bit 24) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Msk (0x1000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Pos (25UL)             /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bit 25)          */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Msk (0x2000000UL)      /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Pos (26UL)          /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bit 26)       */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Msk (0x4000000UL)   /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Pos (27UL)        /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bit 27)     */
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Msk (0x8000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_OS_REG  ----------------------- */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Pos (0UL)         /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bit 0)      */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Msk (0x1UL)       /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Pos (1UL)                /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bit 1)             */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Msk (0x2UL)              /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Pos (2UL)               /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bit 2)            */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Msk (0x4UL)             /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Pos (3UL)      /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bit 3)   */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Msk (0x8UL)    /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Pos (4UL)    /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bit 4) */
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Msk (0x10UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bitfield-Mask: 0x01) */

/* ----------------------  FTDF_FTDF_LMAC_CONTROL_STATUS_REG  --------------------- */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Pos (1UL)     /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bit 1)  */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Msk (0x2UL)   /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Pos (2UL)             /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CCASTAT (Bit 2)          */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Msk (0x4UL)           /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CCASTAT (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Pos (6UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bit 6) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Pos (8UL)         /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bit 8)      */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Msk (0xff00UL)    /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Pos (16UL)    /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bit 16) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Msk (0x70000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Pos (19UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bit 19) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Msk (0x80000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Pos (24UL)    /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bit 24) */
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Msk (0xff000000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bitfield-Mask: 0xff) */

/* -------------------------  FTDF_FTDF_EVENTCURRVAL_REG  ------------------------- */
#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Pos (0UL)               /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bit 0)            */
#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk (0x1ffffffUL)       /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bitfield-Mask: 0x1ffffff) */

/* -----------------------  FTDF_FTDF_TIMESTAMPCURRVAL_REG  ----------------------- */
#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Pos (0UL)       /*!< FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bit 0)    */
#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_4_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Pos (0UL)             /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYSLEEPWAIT (Bit 0)          */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Msk (0xffUL)          /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYSLEEPWAIT (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Pos (8UL)          /*!< FTDF FTDF_LMAC_CONTROL_4_REG: RXPIPEPROPDELAY (Bit 8)       */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Msk (0xff00UL)     /*!< FTDF FTDF_LMAC_CONTROL_4_REG: RXPIPEPROPDELAY (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Pos (16UL)      /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_DEM_PTI (Bit 16)   */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Pos (20UL)           /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CN (Bit 20)        */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Msk (0xf00000UL)     /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Pos (24UL)       /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CALCAP (Bit 24)    */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Msk (0xf000000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Pos (28UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_RF_GPIO_PINS (Bit 28) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Msk (0x70000000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Pos (31UL)          /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_HSI (Bit 31)       */
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Msk (0x80000000UL)  /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_HSI (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_5_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Pos (0UL)       /*!< FTDF FTDF_LMAC_CONTROL_5_REG: ACK_RESPONSE_DELAY (Bit 0)    */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Msk (0xffUL)    /*!< FTDF FTDF_LMAC_CONTROL_5_REG: ACK_RESPONSE_DELAY (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Pos (8UL)              /*!< FTDF FTDF_LMAC_CONTROL_5_REG: CCASTATWAIT (Bit 8)           */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Msk (0xf00UL)          /*!< FTDF FTDF_LMAC_CONTROL_5_REG: CCASTATWAIT (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Pos (16UL)   /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_DEM_PTI (Bit 16) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Pos (20UL)        /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CN (Bit 20)     */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Msk (0xf00000UL)  /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Pos (24UL)    /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CALCAP (Bit 24) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Msk (0xf000000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Pos (28UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_RF_GPIO_PINS (Bit 28) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Msk (0x70000000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Pos (31UL)       /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_HSI (Bit 31)    */
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_HSI (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_6_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Pos (0UL)               /*!< FTDF FTDF_LMAC_CONTROL_6_REG: LIFSPERIOD (Bit 0)            */
#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Msk (0xffUL)            /*!< FTDF FTDF_LMAC_CONTROL_6_REG: LIFSPERIOD (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Pos (8UL)               /*!< FTDF FTDF_LMAC_CONTROL_6_REG: SIFSPERIOD (Bit 8)            */
#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Msk (0xff00UL)          /*!< FTDF FTDF_LMAC_CONTROL_6_REG: SIFSPERIOD (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Pos (16UL)             /*!< FTDF FTDF_LMAC_CONTROL_6_REG: WUIFSPERIOD (Bit 16)          */
#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Msk (0xff0000UL)       /*!< FTDF FTDF_LMAC_CONTROL_6_REG: WUIFSPERIOD (Bitfield-Mask: 0xff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_11_REG  ----------------------- */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Pos (0UL)     /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bit 0)  */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Pos (16UL)      /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bit 16)   */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Msk (0x10000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Pos (17UL)         /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bit 17)      */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Msk (0xe0000UL)    /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Pos (24UL)   /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bit 24) */
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Msk (0xff000000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bitfield-Mask: 0xff) */

/* ----------------------  FTDF_FTDF_LMAC_CONTROL_DELTA_REG  ---------------------- */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Pos (1UL)    /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bit 1) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Msk (0x2UL)  /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Pos (2UL)      /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYNCTIMESTAMP_E (Bit 2)   */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Msk (0x4UL)    /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYNCTIMESTAMP_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Pos (3UL)      /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIMETHR_E (Bit 3)   */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Msk (0x8UL)    /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIMETHR_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Pos (4UL)     /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIME2THR_E (Bit 4)  */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Msk (0x10UL)  /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIME2THR_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Pos (5UL)    /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: GETGENERATORVAL_E (Bit 5) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Msk (0x20UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: GETGENERATORVAL_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Pos (6UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: WAKEUPTIMERENABLESTATUS_D (Bit 6) */
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: WAKEUPTIMERENABLESTATUS_D (Bitfield-Mask: 0x01) */

/* ---------------------  FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG  -------------------- */
#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Pos (0UL) /*!< FTDF FTDF_TIMESTAMPCURRPHASEVAL_REG: TIMESTAMPCURRPHASEVAL (Bit 0) */
#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Msk (0xffUL) /*!< FTDF FTDF_TIMESTAMPCURRPHASEVAL_REG: TIMESTAMPCURRPHASEVAL (Bitfield-Mask: 0xff) */

/* ----------------------  FTDF_FTDF_MACTSTXACKDELAYVAL_REG  ---------------------- */
#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Pos (0UL)   /*!< FTDF FTDF_MACTSTXACKDELAYVAL_REG: MACTSTXACKDELAYVAL (Bit 0) */
#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Msk (0xffffUL) /*!< FTDF FTDF_MACTSTXACKDELAYVAL_REG: MACTSTXACKDELAYVAL (Bitfield-Mask: 0xffff) */

/* -----------------------  FTDF_FTDF_LMAC_CONTROL_MASK_REG  ---------------------- */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Pos (1UL)     /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: LMACREADY4SLEEP_M (Bit 1)  */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Msk (0x2UL)   /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: LMACREADY4SLEEP_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Pos (2UL)       /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYNCTIMESTAMP_M (Bit 2)    */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Msk (0x4UL)     /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYNCTIMESTAMP_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Pos (3UL)       /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIMETHR_M (Bit 3)    */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Msk (0x8UL)     /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIMETHR_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Pos (4UL)      /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIME2THR_M (Bit 4)   */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Msk (0x10UL)   /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIME2THR_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Pos (5UL)     /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: GETGENERATORVAL_M (Bit 5)  */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Msk (0x20UL)  /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: GETGENERATORVAL_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Pos (6UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: WAKEUPTIMERENABLESTATUS_M (Bit 6) */
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: WAKEUPTIMERENABLESTATUS_M (Bitfield-Mask: 0x01) */

/* --------------------------  FTDF_FTDF_LMAC_EVENT_REG  -------------------------- */
#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Pos (0UL)                /*!< FTDF FTDF_LMAC_EVENT_REG: EDSCANREADY_E (Bit 0)             */
#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Msk (0x1UL)              /*!< FTDF FTDF_LMAC_EVENT_REG: EDSCANREADY_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Pos (1UL)                    /*!< FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bit 1)                 */
#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Msk (0x2UL)                  /*!< FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bitfield-Mask: 0x01)   */
#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Pos (2UL)             /*!< FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bit 2)          */
#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Msk (0x4UL)           /*!< FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Pos (3UL)             /*!< FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bit 3)          */
#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Msk (0x8UL)           /*!< FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bitfield-Mask: 0x01) */

/* ---------------------------  FTDF_FTDF_LMAC_MASK_REG  -------------------------- */
#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Pos (0UL)                 /*!< FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bit 0)              */
#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Msk (0x1UL)               /*!< FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Pos (1UL)                     /*!< FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bit 1)                  */
#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Msk (0x2UL)                   /*!< FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bitfield-Mask: 0x01)    */
#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Pos (2UL)              /*!< FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bit 2)           */
#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Msk (0x4UL)            /*!< FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Pos (3UL)              /*!< FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bit 3)           */
#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Msk (0x8UL)            /*!< FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_LMAC_MANUAL_1_REG  ------------------------ */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Pos (0UL)          /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bit 0)       */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Msk (0x1UL)        /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Pos (1UL)        /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_EN (Bit 1)     */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Msk (0x2UL)      /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_EN (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Pos (2UL)         /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_EN (Bit 2)      */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Msk (0x4UL)       /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_EN (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Pos (3UL)         /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_EN (Bit 3)      */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Msk (0x8UL)       /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_EN (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Pos (4UL)    /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_PIPE_EN (Bit 4) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Msk (0x10UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_PIPE_EN (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Pos (5UL)    /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_ED_REQUEST (Bit 5) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Msk (0x20UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_ED_REQUEST (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Pos (6UL)     /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_FRM_NR (Bit 6)  */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Msk (0xc0UL)  /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_FRM_NR (Bitfield-Mask: 0x03) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Pos (8UL)           /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PTI (Bit 8)        */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Msk (0xf00UL)       /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Pos (16UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_DEM_PTI (Bit 16) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_DEM_PTI (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Pos (20UL)  /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CN (Bit 20) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Msk (0xf00000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CN (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Pos (24UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CALCAP (Bit 24) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Msk (0xf000000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CALCAP (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Pos (28UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS (Bit 28) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Msk (0x70000000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Pos (31UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_HSI (Bit 31) */
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_HSI (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_LMAC_MANUAL_OS_REG  ------------------------ */
#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Pos (0UL)     /*!< FTDF FTDF_LMAC_MANUAL_OS_REG: LMAC_MANUAL_TX_START (Bit 0)  */
#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Msk (0x1UL)   /*!< FTDF FTDF_LMAC_MANUAL_OS_REG: LMAC_MANUAL_TX_START (Bitfield-Mask: 0x01) */

/* ----------------------  FTDF_FTDF_LMAC_MANUAL_STATUS_REG  ---------------------- */
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Pos (0UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_CCA_STAT (Bit 0) */
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Msk (0x1UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_CCA_STAT (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Pos (8UL)  /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_ED_STAT (Bit 8) */
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Msk (0xff00UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_ED_STAT (Bitfield-Mask: 0xff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_7_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Pos (0UL)              /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACWUPERIOD (Bit 0)           */
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Msk (0xffffUL)         /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACWUPERIOD (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Pos (16UL)      /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACCSLSAMPLEPERIOD (Bit 16)   */
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Msk (0xffff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACCSLSAMPLEPERIOD (Bitfield-Mask: 0xffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_8_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Pos (0UL)    /*!< FTDF FTDF_LMAC_CONTROL_8_REG: MACCSLSTARTSAMPLETIME (Bit 0) */
#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Msk (0xffffffffUL) /*!< FTDF FTDF_LMAC_CONTROL_8_REG: MACCSLSTARTSAMPLETIME (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_9_REG  ------------------------ */
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Pos (0UL)         /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLDATAPERIOD (Bit 0)      */
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Msk (0xffffUL)    /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLDATAPERIOD (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLFRAMEPENDINGWAITT (Bit 16) */
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Msk (0xffff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLFRAMEPENDINGWAITT (Bitfield-Mask: 0xffff) */

/* ------------------------  FTDF_FTDF_LMAC_CONTROL_10_REG  ----------------------- */
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Pos (0UL)       /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACWURZCORRECTION (Bit 0)    */
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Msk (0xffUL)    /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACWURZCORRECTION (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Pos (16UL)         /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACCSLMARGINRZ (Bit 16)      */
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Msk (0xf0000UL)    /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACCSLMARGINRZ (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Pos (28UL)           /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACRZZEROVAL (Bit 28)        */
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Msk (0xf0000000UL)   /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACRZZEROVAL (Bitfield-Mask: 0x0f) */

/* --------------------------  FTDF_FTDF_SECURITY_0_REG  -------------------------- */
#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Pos (1UL)                     /*!< FTDF FTDF_SECURITY_0_REG: SECTXRXN (Bit 1)                  */
#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Msk (0x2UL)                   /*!< FTDF FTDF_SECURITY_0_REG: SECTXRXN (Bitfield-Mask: 0x01)    */
#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Pos (8UL)                     /*!< FTDF FTDF_SECURITY_0_REG: SECENTRY (Bit 8)                  */
#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Msk (0xf00UL)                 /*!< FTDF FTDF_SECURITY_0_REG: SECENTRY (Bitfield-Mask: 0x0f)    */
#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Pos (16UL)                  /*!< FTDF FTDF_SECURITY_0_REG: SECALENGTH (Bit 16)               */
#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Msk (0x7f0000UL)            /*!< FTDF FTDF_SECURITY_0_REG: SECALENGTH (Bitfield-Mask: 0x7f)  */
#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Pos (24UL)                  /*!< FTDF FTDF_SECURITY_0_REG: SECMLENGTH (Bit 24)               */
#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Msk (0x7f000000UL)          /*!< FTDF FTDF_SECURITY_0_REG: SECMLENGTH (Bitfield-Mask: 0x7f)  */
#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Pos (31UL)                  /*!< FTDF FTDF_SECURITY_0_REG: SECENCDECN (Bit 31)               */
#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Msk (0x80000000UL)          /*!< FTDF FTDF_SECURITY_0_REG: SECENCDECN (Bitfield-Mask: 0x01)  */

/* --------------------------  FTDF_FTDF_SECURITY_1_REG  -------------------------- */
#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Pos (0UL)                 /*!< FTDF FTDF_SECURITY_1_REG: SECAUTHFLAGS (Bit 0)              */
#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Msk (0xffUL)              /*!< FTDF FTDF_SECURITY_1_REG: SECAUTHFLAGS (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Pos (8UL)                 /*!< FTDF FTDF_SECURITY_1_REG: SECENCRFLAGS (Bit 8)              */
#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Msk (0xff00UL)            /*!< FTDF FTDF_SECURITY_1_REG: SECENCRFLAGS (Bitfield-Mask: 0xff) */

/* ---------------------------  FTDF_FTDF_SECKEY_0_REG  --------------------------- */
#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Pos   (0UL)                     /*!< FTDF FTDF_SECKEY_0_REG: SECKEY_0 (Bit 0)                    */
#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Msk   (0xffffffffUL)            /*!< FTDF FTDF_SECKEY_0_REG: SECKEY_0 (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  FTDF_FTDF_SECKEY_1_REG  --------------------------- */
#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Pos   (0UL)                     /*!< FTDF FTDF_SECKEY_1_REG: SECKEY_1 (Bit 0)                    */
#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Msk   (0xffffffffUL)            /*!< FTDF FTDF_SECKEY_1_REG: SECKEY_1 (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  FTDF_FTDF_SECKEY_2_REG  --------------------------- */
#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Pos   (0UL)                     /*!< FTDF FTDF_SECKEY_2_REG: SECKEY_2 (Bit 0)                    */
#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Msk   (0xffffffffUL)            /*!< FTDF FTDF_SECKEY_2_REG: SECKEY_2 (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  FTDF_FTDF_SECKEY_3_REG  --------------------------- */
#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Pos   (0UL)                     /*!< FTDF FTDF_SECKEY_3_REG: SECKEY_3 (Bit 0)                    */
#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Msk   (0xffffffffUL)            /*!< FTDF FTDF_SECKEY_3_REG: SECKEY_3 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_SECNONCE_0_REG  -------------------------- */
#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Pos (0UL)                   /*!< FTDF FTDF_SECNONCE_0_REG: SECNONCE_0 (Bit 0)                */
#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Msk (0xffffffffUL)          /*!< FTDF FTDF_SECNONCE_0_REG: SECNONCE_0 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_SECNONCE_1_REG  -------------------------- */
#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Pos (0UL)                   /*!< FTDF FTDF_SECNONCE_1_REG: SECNONCE_1 (Bit 0)                */
#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Msk (0xffffffffUL)          /*!< FTDF FTDF_SECNONCE_1_REG: SECNONCE_1 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_SECNONCE_2_REG  -------------------------- */
#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Pos (0UL)                   /*!< FTDF FTDF_SECNONCE_2_REG: SECNONCE_2 (Bit 0)                */
#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Msk (0xffffffffUL)          /*!< FTDF FTDF_SECNONCE_2_REG: SECNONCE_2 (Bitfield-Mask: 0xffffffff) */

/* --------------------------  FTDF_FTDF_SECNONCE_3_REG  -------------------------- */
#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Pos (0UL)                   /*!< FTDF FTDF_SECNONCE_3_REG: SECNONCE_3 (Bit 0)                */
#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Msk (0xffUL)                /*!< FTDF FTDF_SECNONCE_3_REG: SECNONCE_3 (Bitfield-Mask: 0xff)  */

/* --------------------------  FTDF_FTDF_SECURITY_OS_REG  ------------------------- */
#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Pos (0UL)                    /*!< FTDF FTDF_SECURITY_OS_REG: SECABORT (Bit 0)                 */
#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Msk (0x1UL)                  /*!< FTDF FTDF_SECURITY_OS_REG: SECABORT (Bitfield-Mask: 0x01)   */
#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Pos (1UL)                    /*!< FTDF FTDF_SECURITY_OS_REG: SECSTART (Bit 1)                 */
#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Msk (0x2UL)                  /*!< FTDF FTDF_SECURITY_OS_REG: SECSTART (Bitfield-Mask: 0x01)   */

/* ------------------------  FTDF_FTDF_SECURITY_STATUS_REG  ----------------------- */
#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Pos (0UL)                 /*!< FTDF FTDF_SECURITY_STATUS_REG: SECBUSY (Bit 0)              */
#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Msk (0x1UL)               /*!< FTDF FTDF_SECURITY_STATUS_REG: SECBUSY (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Pos (1UL)             /*!< FTDF FTDF_SECURITY_STATUS_REG: SECAUTHFAIL (Bit 1)          */
#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Msk (0x2UL)           /*!< FTDF FTDF_SECURITY_STATUS_REG: SECAUTHFAIL (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_SECURITY_EVENT_REG  ------------------------ */
#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Pos (0UL)               /*!< FTDF FTDF_SECURITY_EVENT_REG: SECREADY_E (Bit 0)            */
#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Msk (0x1UL)             /*!< FTDF FTDF_SECURITY_EVENT_REG: SECREADY_E (Bitfield-Mask: 0x01) */

/* ----------------------  FTDF_FTDF_SECURITY_EVENTMASK_REG  ---------------------- */
#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Pos (0UL)           /*!< FTDF FTDF_SECURITY_EVENTMASK_REG: SECREADY_M (Bit 0)        */
#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Msk (0x1UL)         /*!< FTDF FTDF_SECURITY_EVENTMASK_REG: SECREADY_M (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_TSCH_CONTROL_0_REG  ------------------------ */
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Pos (0UL)          /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSTXACKDELAY (Bit 0)       */
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Msk (0xffffUL)     /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSTXACKDELAY (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Pos (16UL)             /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSRXWAIT (Bit 16)          */
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Msk (0xffff0000UL)     /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSRXWAIT (Bitfield-Mask: 0xffff) */

/* ------------------------  FTDF_FTDF_TSCH_CONTROL_1_REG  ------------------------ */
#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Pos (0UL)                /*!< FTDF FTDF_TSCH_CONTROL_1_REG: MACTSRXTX (Bit 0)             */
#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Msk (0xffffUL)           /*!< FTDF FTDF_TSCH_CONTROL_1_REG: MACTSRXTX (Bitfield-Mask: 0xffff) */

/* ------------------------  FTDF_FTDF_TSCH_CONTROL_2_REG  ------------------------ */
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Pos (0UL)          /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSRXACKDELAY (Bit 0)       */
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Msk (0xffffUL)     /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSRXACKDELAY (Bitfield-Mask: 0xffff) */
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Pos (16UL)            /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSACKWAIT (Bit 16)         */
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Msk (0xffff0000UL)    /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSACKWAIT (Bitfield-Mask: 0xffff) */

/* -----------------------  FTDF_FTDF_PHY_PARAMETERS_0_REG  ----------------------- */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Pos (0UL)             /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_0 (Bit 0)          */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Msk (0x7UL)           /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_0 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Pos (4UL)             /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_1 (Bit 4)          */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Msk (0x70UL)          /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_1 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Pos (8UL)             /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_2 (Bit 8)          */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Msk (0x700UL)         /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_2 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Pos (12UL)            /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_3 (Bit 12)         */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Msk (0x7000UL)        /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_3 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Pos (16UL)            /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_4 (Bit 16)         */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Msk (0x70000UL)       /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_4 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Pos (20UL)            /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_5 (Bit 20)         */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Msk (0x700000UL)      /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_5 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Pos (24UL)            /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_6 (Bit 24)         */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Msk (0x7000000UL)     /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_6 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Pos (28UL)            /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_7 (Bit 28)         */
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Msk (0x70000000UL)    /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_7 (Bitfield-Mask: 0x07) */

/* -----------------------  FTDF_FTDF_PHY_PARAMETERS_1_REG  ----------------------- */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Pos (0UL)             /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_0 (Bit 0)          */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Msk (0x7UL)           /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_0 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Pos (4UL)             /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_1 (Bit 4)          */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Msk (0x70UL)          /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_1 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Pos (8UL)             /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_2 (Bit 8)          */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Msk (0x700UL)         /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_2 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Pos (12UL)            /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_3 (Bit 12)         */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Msk (0x7000UL)        /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_3 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Pos (16UL)            /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_4 (Bit 16)         */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Msk (0x70000UL)       /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_4 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Pos (20UL)            /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_5 (Bit 20)         */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Msk (0x700000UL)      /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_5 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Pos (24UL)            /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_6 (Bit 24)         */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Msk (0x7000000UL)     /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_6 (Bitfield-Mask: 0x07) */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Pos (28UL)            /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_7 (Bit 28)         */
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Msk (0x70000000UL)    /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_7 (Bitfield-Mask: 0x07) */

/* -----------------------  FTDF_FTDF_PHY_PARAMETERS_2_REG  ----------------------- */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Pos (0UL)           /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXSTARTUP (Bit 0)        */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Msk (0xffUL)        /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXSTARTUP (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Pos (8UL)           /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXLATENCY (Bit 8)        */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Msk (0xff00UL)      /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXLATENCY (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Pos (16UL)           /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXFINISH (Bit 16)        */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Msk (0xff0000UL)     /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXFINISH (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Pos (24UL)            /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTRXWAIT (Bit 24)         */
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Msk (0xff000000UL)    /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTRXWAIT (Bitfield-Mask: 0xff) */

/* -----------------------  FTDF_FTDF_PHY_PARAMETERS_3_REG  ----------------------- */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Pos (0UL)           /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXSTARTUP (Bit 0)        */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Msk (0xffUL)        /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXSTARTUP (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Pos (8UL)           /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bit 8)        */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Msk (0xff00UL)      /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Pos (16UL)             /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bit 16)          */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Msk (0xff0000UL)       /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Pos (24UL)     /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bit 24)  */
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Msk (0x1000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_RX_CONTROL_0_REG  ------------------------- */
#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Pos (0UL)       /*!< FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bit 0)    */
#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Msk (0x1UL)     /*!< FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Pos (1UL)               /*!< FTDF FTDF_RX_CONTROL_0_REG: RXBEACONONLY (Bit 1)            */
#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Msk (0x2UL)             /*!< FTDF FTDF_RX_CONTROL_0_REG: RXBEACONONLY (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Pos (2UL)         /*!< FTDF FTDF_RX_CONTROL_0_REG: RXCOORDREALIGNONLY (Bit 2)      */
#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Msk (0x4UL)       /*!< FTDF FTDF_RX_CONTROL_0_REG: RXCOORDREALIGNONLY (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Pos (3UL)            /*!< FTDF FTDF_RX_CONTROL_0_REG: RX_READ_BUF_PTR (Bit 3)         */
#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Msk (0x78UL)         /*!< FTDF FTDF_RX_CONTROL_0_REG: RX_READ_BUF_PTR (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Pos (7UL)          /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXFRMPENDINGCA (Bit 7)       */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Msk (0x80UL)       /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXFRMPENDINGCA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Pos (8UL)          /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKREQUESTCA (Bit 8)       */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Msk (0x100UL)      /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKREQUESTCA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Pos (9UL)      /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSCRCERROR (Bit 9)   */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Msk (0x200UL)  /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSCRCERROR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Pos (10UL)          /*!< FTDF FTDF_RX_CONTROL_0_REG: DISDATAREQUESTCA (Bit 10)       */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Msk (0x400UL)       /*!< FTDF FTDF_RX_CONTROL_0_REG: DISDATAREQUESTCA (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Pos (11UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSRESFRAMEVERSION (Bit 11) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Msk (0x800UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSRESFRAMEVERSION (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Pos (12UL)  /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDPANID (Bit 12) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Msk (0x1000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDPANID (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Pos (13UL)   /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDADDR (Bit 13) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Msk (0x2000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDADDR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Pos (14UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSBEACONWRONGPANID (Bit 14) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Msk (0x4000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSBEACONWRONGPANID (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Pos (15UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSTOPANCOORDINATOR (Bit 15) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Msk (0x8000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSTOPANCOORDINATOR (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Pos (16UL)      /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSFRMTYPE (Bit 16)   */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Msk (0xff0000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSFRMTYPE (Bitfield-Mask: 0xff) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Pos (24UL)       /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWAKEUP (Bit 24)    */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Msk (0x1000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWAKEUP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Pos (25UL)             /*!< FTDF FTDF_RX_CONTROL_0_REG: MACPASSWAKEUP (Bit 25)          */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Msk (0x2000000UL)      /*!< FTDF FTDF_RX_CONTROL_0_REG: MACPASSWAKEUP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Pos (26UL)      /*!< FTDF FTDF_RX_CONTROL_0_REG: MACIMPLICITBROADCAST (Bit 26)   */
#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Msk (0x4000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACIMPLICITBROADCAST (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Pos (27UL)        /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKRECEIVEDCA (Bit 27)     */
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Msk (0x8000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKRECEIVEDCA (Bitfield-Mask: 0x01) */

/* ---------------------------  FTDF_FTDF_RX_EVENT_REG  --------------------------- */
#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Pos    (0UL)                     /*!< FTDF FTDF_RX_EVENT_REG: RXSOF_E (Bit 0)                     */
#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Msk    (0x1UL)                   /*!< FTDF FTDF_RX_EVENT_REG: RXSOF_E (Bitfield-Mask: 0x01)       */
#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Pos (1UL)                  /*!< FTDF FTDF_RX_EVENT_REG: RX_OVERFLOW_E (Bit 1)               */
#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Msk (0x2UL)                /*!< FTDF FTDF_RX_EVENT_REG: RX_OVERFLOW_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Pos (2UL)                 /*!< FTDF FTDF_RX_EVENT_REG: RX_BUF_AVAIL_E (Bit 2)              */
#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Msk (0x4UL)               /*!< FTDF FTDF_RX_EVENT_REG: RX_BUF_AVAIL_E (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Pos   (3UL)                     /*!< FTDF FTDF_RX_EVENT_REG: RXBYTE_E (Bit 3)                    */
#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Msk   (0x8UL)                   /*!< FTDF FTDF_RX_EVENT_REG: RXBYTE_E (Bitfield-Mask: 0x01)      */

/* ----------------------------  FTDF_FTDF_RX_MASK_REG  --------------------------- */
#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Pos     (0UL)                     /*!< FTDF FTDF_RX_MASK_REG: RXSOF_M (Bit 0)                      */
#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Msk     (0x1UL)                   /*!< FTDF FTDF_RX_MASK_REG: RXSOF_M (Bitfield-Mask: 0x01)        */
#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Pos (1UL)                   /*!< FTDF FTDF_RX_MASK_REG: RX_OVERFLOW_M (Bit 1)                */
#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Msk (0x2UL)                 /*!< FTDF FTDF_RX_MASK_REG: RX_OVERFLOW_M (Bitfield-Mask: 0x01)  */
#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Pos (2UL)                  /*!< FTDF FTDF_RX_MASK_REG: RX_BUF_AVAIL_M (Bit 2)               */
#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Msk (0x4UL)                /*!< FTDF FTDF_RX_MASK_REG: RX_BUF_AVAIL_M (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Pos    (3UL)                     /*!< FTDF FTDF_RX_MASK_REG: RXBYTE_M (Bit 3)                     */
#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Msk    (0x8UL)                   /*!< FTDF FTDF_RX_MASK_REG: RXBYTE_M (Bitfield-Mask: 0x01)       */

/* ---------------------------  FTDF_FTDF_RX_STATUS_REG  -------------------------- */
#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Pos (0UL)               /*!< FTDF FTDF_RX_STATUS_REG: RX_BUFF_IS_FULL (Bit 0)            */
#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Msk (0x1UL)             /*!< FTDF FTDF_RX_STATUS_REG: RX_BUFF_IS_FULL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Pos (1UL)              /*!< FTDF FTDF_RX_STATUS_REG: RX_WRITE_BUF_PTR (Bit 1)           */
#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Msk (0x1eUL)           /*!< FTDF FTDF_RX_STATUS_REG: RX_WRITE_BUF_PTR (Bitfield-Mask: 0x0f) */

/* ---------------------  FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG  -------------------- */
#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Pos (0UL) /*!< FTDF FTDF_SYMBOLTIMESNAPSHOTVAL_REG: SYMBOLTIMESNAPSHOTVAL (Bit 0) */
#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_SYMBOLTIMESNAPSHOTVAL_REG: SYMBOLTIMESNAPSHOTVAL (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_RX_STATUS_DELTA_REG  ----------------------- */
#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Pos (0UL)       /*!< FTDF FTDF_RX_STATUS_DELTA_REG: RX_BUFF_IS_FULL_D (Bit 0)    */
#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Msk (0x1UL)     /*!< FTDF FTDF_RX_STATUS_DELTA_REG: RX_BUFF_IS_FULL_D (Bitfield-Mask: 0x01) */

/* ------------------------  FTDF_FTDF_RX_STATUS_MASK_REG  ------------------------ */
#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Pos (0UL)        /*!< FTDF FTDF_RX_STATUS_MASK_REG: RX_BUFF_IS_FULL_M (Bit 0)     */
#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Msk (0x1UL)      /*!< FTDF FTDF_RX_STATUS_MASK_REG: RX_BUFF_IS_FULL_M (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_TX_CONTROL_0_REG  ------------------------- */
#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Pos (0UL)       /*!< FTDF FTDF_TX_CONTROL_0_REG: DBGTXTRANSPARENTMODE (Bit 0)    */
#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Msk (0x1UL)     /*!< FTDF FTDF_TX_CONTROL_0_REG: DBGTXTRANSPARENTMODE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Pos (4UL)                   /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXBE (Bit 4)                */
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Msk (0xf0UL)                /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXBE (Bitfield-Mask: 0x0f)  */
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Pos (8UL)                   /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMINBE (Bit 8)                */
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Msk (0xf00UL)               /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMINBE (Bitfield-Mask: 0x0f)  */
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Pos (12UL)        /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXCSMABACKOFFS (Bit 12)     */
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Msk (0x7000UL)    /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXCSMABACKOFFS (Bitfield-Mask: 0x07) */

/* ----------------------------  FTDF_FTDF_FTDF_CE_REG  --------------------------- */
#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Pos     (0UL)                     /*!< FTDF FTDF_FTDF_CE_REG: FTDF_CE (Bit 0)                      */
#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Msk     (0x3fUL)                  /*!< FTDF FTDF_FTDF_CE_REG: FTDF_CE (Bitfield-Mask: 0x3f)        */

/* ----------------------------  FTDF_FTDF_FTDF_CM_REG  --------------------------- */
#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Pos     (0UL)                     /*!< FTDF FTDF_FTDF_CM_REG: FTDF_CM (Bit 0)                      */
#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Msk     (0x3fUL)                  /*!< FTDF FTDF_FTDF_CM_REG: FTDF_CM (Bitfield-Mask: 0x3f)        */

/* -----------------------  FTDF_FTDF_SYNCTIMESTAMPTHR_REG  ----------------------- */
#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Pos (0UL)       /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bit 0)    */
#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk (0x1ffffffUL) /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bitfield-Mask: 0x1ffffff) */

/* -----------------------  FTDF_FTDF_SYNCTIMESTAMPVAL_REG  ----------------------- */
#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Pos (0UL)       /*!< FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bit 0)    */
#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_TIMER_CONTROL_1_REG  ----------------------- */
#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Pos (1UL)        /*!< FTDF FTDF_TIMER_CONTROL_1_REG: SYNCTIMESTAMPENA (Bit 1)     */
#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Msk (0x2UL)      /*!< FTDF FTDF_TIMER_CONTROL_1_REG: SYNCTIMESTAMPENA (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_MACTXSTDACKFRMCNT_REG  ---------------------- */
#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Pos (0UL)     /*!< FTDF FTDF_MACTXSTDACKFRMCNT_REG: MACTXSTDACKFRMCNT (Bit 0)  */
#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACTXSTDACKFRMCNT_REG: MACTXSTDACKFRMCNT (Bitfield-Mask: 0xffffffff) */

/* ----------------------  FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG  --------------------- */
#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Pos (0UL) /*!< FTDF FTDF_MACRXSTDACKFRMOKCNT_REG: MACRXSTDACKFRMOKCNT (Bit 0) */
#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACRXSTDACKFRMOKCNT_REG: MACRXSTDACKFRMOKCNT (Bitfield-Mask: 0xffffffff) */

/* ----------------------  FTDF_FTDF_MACRXADDRFAILFRMCNT_REG  --------------------- */
#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Pos (0UL) /*!< FTDF FTDF_MACRXADDRFAILFRMCNT_REG: MACRXADDRFAILFRMCNT (Bit 0) */
#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACRXADDRFAILFRMCNT_REG: MACRXADDRFAILFRMCNT (Bitfield-Mask: 0xffffffff) */

/* -----------------------  FTDF_FTDF_MACRXUNSUPFRMCNT_REG  ----------------------- */
#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Pos (0UL)       /*!< FTDF FTDF_MACRXUNSUPFRMCNT_REG: MACRXUNSUPFRMCNT (Bit 0)    */
#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACRXUNSUPFRMCNT_REG: MACRXUNSUPFRMCNT (Bitfield-Mask: 0xffffffff) */

/* ---------------------  FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG  -------------------- */
#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Pos (0UL) /*!< FTDF FTDF_SYNCTIMESTAMPPHASEVAL_REG: SYNCTIMESTAMPPHASEVAL (Bit 0) */
#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Msk (0xffUL) /*!< FTDF FTDF_SYNCTIMESTAMPPHASEVAL_REG: SYNCTIMESTAMPPHASEVAL (Bitfield-Mask: 0xff) */

/* -----------------------  FTDF_FTDF_MACFCSERRORCOUNT_REG  ----------------------- */
#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Pos (0UL)       /*!< FTDF FTDF_MACFCSERRORCOUNT_REG: MACFCSERRORCOUNT (Bit 0)    */
#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACFCSERRORCOUNT_REG: MACFCSERRORCOUNT (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  FTDF_FTDF_LMACRESET_REG  -------------------------- */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Pos (0UL)             /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_CONTROL (Bit 0)          */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Msk (0x1UL)           /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_CONTROL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Pos (1UL)                  /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_RX (Bit 1)               */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Msk (0x2UL)                /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_RX (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Pos (2UL)                  /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TX (Bit 2)               */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Msk (0x4UL)                /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TX (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Pos (3UL)                 /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_AHB (Bit 3)              */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Msk (0x8UL)               /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_AHB (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Pos (4UL)                /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_OREG (Bit 4)             */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Msk (0x10UL)             /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_OREG (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Pos (6UL)               /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TSTIM (Bit 6)            */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Msk (0x40UL)            /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TSTIM (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Pos (7UL)                 /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_SEC (Bit 7)              */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Msk (0x80UL)              /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_SEC (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Pos (9UL)               /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_COUNT (Bit 9)            */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Msk (0x200UL)           /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_COUNT (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Pos (10UL)            /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TIMCTRL (Bit 10)         */
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Msk (0x400UL)         /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TIMCTRL (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Pos (16UL)          /*!< FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bit 16)       */
#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Msk (0x10000UL)     /*!< FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_WAKEUP_CONTROL_OS_REG  ---------------------- */
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Pos (0UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bit 0) */
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Msk (0x1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Pos (1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bit 1) */
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Msk (0x2UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_SYMBOLTIMETHR_REG  ------------------------ */
#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Pos (0UL)             /*!< FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bit 0)          */
#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Msk (0xffffffffUL)    /*!< FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_SYMBOLTIME2THR_REG  ------------------------ */
#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Pos (0UL)           /*!< FTDF FTDF_SYMBOLTIME2THR_REG: SYMBOLTIME2THR (Bit 0)        */
#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Msk (0xffffffffUL)  /*!< FTDF FTDF_SYMBOLTIME2THR_REG: SYMBOLTIME2THR (Bitfield-Mask: 0xffffffff) */

/* -------------------------  FTDF_FTDF_DEBUGCONTROL_REG  ------------------------- */
#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Pos (8UL)               /*!< FTDF FTDF_DEBUGCONTROL_REG: DBG_RX_INPUT (Bit 8)            */
#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Msk (0x100UL)           /*!< FTDF FTDF_DEBUGCONTROL_REG: DBG_RX_INPUT (Bitfield-Mask: 0x01) */

/* ---------------------------  FTDF_FTDF_TXBYTE_E_REG  --------------------------- */
#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Pos   (0UL)                     /*!< FTDF FTDF_TXBYTE_E_REG: TXBYTE_E (Bit 0)                    */
#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Msk   (0x1UL)                   /*!< FTDF FTDF_TXBYTE_E_REG: TXBYTE_E (Bitfield-Mask: 0x01)      */
#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Pos (1UL)               /*!< FTDF FTDF_TXBYTE_E_REG: TX_LAST_SYMBOL_E (Bit 1)            */
#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Msk (0x2UL)             /*!< FTDF FTDF_TXBYTE_E_REG: TX_LAST_SYMBOL_E (Bitfield-Mask: 0x01) */

/* ---------------------------  FTDF_FTDF_TXBYTE_M_REG  --------------------------- */
#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Pos   (0UL)                     /*!< FTDF FTDF_TXBYTE_M_REG: TXBYTE_M (Bit 0)                    */
#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Msk   (0x1UL)                   /*!< FTDF FTDF_TXBYTE_M_REG: TXBYTE_M (Bitfield-Mask: 0x01)      */
#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Pos (1UL)               /*!< FTDF FTDF_TXBYTE_M_REG: TX_LAST_SYMBOL_M (Bit 1)            */
#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Msk (0x2UL)             /*!< FTDF FTDF_TXBYTE_M_REG: TX_LAST_SYMBOL_M (Bitfield-Mask: 0x01) */

/* --------------------------  FTDF_FTDF_TX_FLAG_S_0_REG  ------------------------- */
#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Pos (0UL)                /*!< FTDF FTDF_TX_FLAG_S_0_REG: TX_FLAG_STAT (Bit 0)             */
#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Msk (0x1UL)              /*!< FTDF FTDF_TX_FLAG_S_0_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_E_0_REG: TX_FLAG_CLEAR_E (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_E_0_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_M_0_REG: TX_FLAG_CLEAR_M (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_M_0_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_TX_PRIORITY_0_REG  ------------------------ */
#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Pos (0UL)               /*!< FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bit 0)            */
#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Msk (0xfUL)             /*!< FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Pos (4UL)                  /*!< FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bit 4)               */
#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Msk (0x10UL)               /*!< FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Pos (8UL)                    /*!< FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bit 8)                 */
#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Msk (0xf00UL)                /*!< FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bitfield-Mask: 0x0f)   */

/* --------------------------  FTDF_FTDF_TX_FLAG_S_1_REG  ------------------------- */
#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Pos (0UL)                /*!< FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bit 0)             */
#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Msk (0x1UL)              /*!< FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_E_1_REG: TX_FLAG_CLEAR_E (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_E_1_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_M_1_REG: TX_FLAG_CLEAR_M (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_M_1_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_TX_PRIORITY_1_REG  ------------------------ */
#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Pos (0UL)               /*!< FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bit 0)            */
#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Msk (0xfUL)             /*!< FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Pos (4UL)                  /*!< FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bit 4)               */
#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Msk (0x10UL)               /*!< FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Pos (8UL)                    /*!< FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bit 8)                 */
#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Msk (0xf00UL)                /*!< FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bitfield-Mask: 0x0f)   */

/* --------------------------  FTDF_FTDF_TX_FLAG_S_2_REG  ------------------------- */
#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Pos (0UL)                /*!< FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bit 0)             */
#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Msk (0x1UL)              /*!< FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_E_2_REG: TX_FLAG_CLEAR_E (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_E_2_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_M_2_REG: TX_FLAG_CLEAR_M (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_M_2_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_TX_PRIORITY_2_REG  ------------------------ */
#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Pos (0UL)               /*!< FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bit 0)            */
#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Msk (0xfUL)             /*!< FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Pos (4UL)                  /*!< FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bit 4)               */
#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Msk (0x10UL)               /*!< FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Pos (8UL)                    /*!< FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bit 8)                 */
#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Msk (0xf00UL)                /*!< FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bitfield-Mask: 0x0f)   */

/* --------------------------  FTDF_FTDF_TX_FLAG_S_3_REG  ------------------------- */
#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Pos (0UL)                /*!< FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bit 0)             */
#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Msk (0x1UL)              /*!< FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_E_3_REG: TX_FLAG_CLEAR_E (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_E_3_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */

/* -----------------------  FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG  ---------------------- */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Pos (0UL)       /*!< FTDF FTDF_TX_FLAG_CLEAR_M_3_REG: TX_FLAG_CLEAR_M (Bit 0)    */
#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Msk (0x1UL)     /*!< FTDF FTDF_TX_FLAG_CLEAR_M_3_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */

/* -------------------------  FTDF_FTDF_TX_PRIORITY_3_REG  ------------------------ */
#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Pos (0UL)               /*!< FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bit 0)            */
#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Msk (0xfUL)             /*!< FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Pos (4UL)                  /*!< FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bit 4)               */
#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Msk (0x10UL)               /*!< FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Pos (8UL)                    /*!< FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bit 8)                 */
#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Msk (0xf00UL)                /*!< FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bitfield-Mask: 0x0f)   */

/* ---------------------------  FTDF_FTDF_TX_SET_OS_REG  -------------------------- */
#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Pos (0UL)                   /*!< FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bit 0)                */
#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Msk (0xfUL)                 /*!< FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bitfield-Mask: 0x0f)  */

/* --------------------------  FTDF_FTDF_TX_CLEAR_OS_REG  ------------------------- */
#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Pos (0UL)               /*!< FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bit 0)            */
#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Msk (0xfUL)             /*!< FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bitfield-Mask: 0x0f) */

/* ------------------------  FTDF_FTDF_WAKEUP_CONTROL_REG  ------------------------ */
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Pos (0UL)             /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bit 0)          */
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Msk (0x1ffffffUL)     /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bitfield-Mask: 0x1ffffff) */
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos (29UL)            /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bit 29)         */
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk (0x20000000UL)    /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bitfield-Mask: 0x01) */
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Pos (30UL)             /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bit 30)          */
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Msk (0xc0000000UL)     /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bitfield-Mask: 0x03) */

/* -------------------------  FTDF_FTDF_LONG_ADDR_0_0_REG  ------------------------ */
#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Pos (0UL)                  /*!< FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bit 0)               */
#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Msk (0xffffffffUL)         /*!< FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bitfield-Mask: 0xffffffff) */

/* -------------------------  FTDF_FTDF_LONG_ADDR_1_0_REG  ------------------------ */
#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Pos (0UL)                  /*!< FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bit 0)               */
#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Msk (0xffffffffUL)         /*!< FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bitfield-Mask: 0xffffffff) */

/* ------------------------  FTDF_FTDF_SIZE_AND_VAL_0_REG  ------------------------ */
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Pos (0UL)                 /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bit 0)              */
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Msk (0xfUL)               /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bitfield-Mask: 0x0f) */
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Pos (4UL)            /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bit 4)         */
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Msk (0x10UL)         /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================       struct 'GP_TIMERS' Position & Mask       ================ */
/* ================================================================================ */


/* --------------------------  GP_TIMERS_TIMER0_CTRL_REG  ------------------------- */
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Pos (0UL)                   /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CTRL (Bit 0)                */
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Msk (0x1UL)                 /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CTRL (Bitfield-Mask: 0x01)  */
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Pos (1UL)                /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_SEL (Bit 1)             */
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Msk (0x2UL)              /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_SEL (Bitfield-Mask: 0x01) */
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Pos (2UL)                /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_DIV (Bit 2)             */
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Msk (0x4UL)              /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_DIV (Bitfield-Mask: 0x01) */
#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Pos (3UL)                    /*!< GP_TIMERS TIMER0_CTRL_REG: PWM_MODE (Bit 3)                 */
#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Msk (0x8UL)                  /*!< GP_TIMERS TIMER0_CTRL_REG: PWM_MODE (Bitfield-Mask: 0x01)   */

/* ---------------------------  GP_TIMERS_TIMER0_ON_REG  -------------------------- */
#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Pos   (0UL)                     /*!< GP_TIMERS TIMER0_ON_REG: TIM0_ON (Bit 0)                    */
#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Msk   (0xffffUL)                /*!< GP_TIMERS TIMER0_ON_REG: TIM0_ON (Bitfield-Mask: 0xffff)    */

/* ------------------------  GP_TIMERS_TIMER0_RELOAD_M_REG  ----------------------- */
#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Pos (0UL)                  /*!< GP_TIMERS TIMER0_RELOAD_M_REG: TIM0_M (Bit 0)               */
#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Msk (0xffffUL)             /*!< GP_TIMERS TIMER0_RELOAD_M_REG: TIM0_M (Bitfield-Mask: 0xffff) */

/* ------------------------  GP_TIMERS_TIMER0_RELOAD_N_REG  ----------------------- */
#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Pos (0UL)                  /*!< GP_TIMERS TIMER0_RELOAD_N_REG: TIM0_N (Bit 0)               */
#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Msk (0xffffUL)             /*!< GP_TIMERS TIMER0_RELOAD_N_REG: TIM0_N (Bitfield-Mask: 0xffff) */

/* -------------------------  GP_TIMERS_PWM2_START_CYCLE  ------------------------- */
#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Pos (0UL)                /*!< GP_TIMERS PWM2_START_CYCLE: START_CYCLE (Bit 0)             */
#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Msk (0x3fffUL)           /*!< GP_TIMERS PWM2_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff) */

/* -------------------------  GP_TIMERS_PWM3_START_CYCLE  ------------------------- */
#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Pos (0UL)                /*!< GP_TIMERS PWM3_START_CYCLE: START_CYCLE (Bit 0)             */
#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Msk (0x3fffUL)           /*!< GP_TIMERS PWM3_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff) */

/* -------------------------  GP_TIMERS_PWM4_START_CYCLE  ------------------------- */
#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Pos (0UL)                /*!< GP_TIMERS PWM4_START_CYCLE: START_CYCLE (Bit 0)             */
#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Msk (0x3fffUL)           /*!< GP_TIMERS PWM4_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff) */

/* --------------------------  GP_TIMERS_PWM2_END_CYCLE  -------------------------- */
#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Pos (0UL)                    /*!< GP_TIMERS PWM2_END_CYCLE: END_CYCLE (Bit 0)                 */
#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Msk (0x3fffUL)               /*!< GP_TIMERS PWM2_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff) */

/* --------------------------  GP_TIMERS_PWM3_END_CYCLE  -------------------------- */
#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Pos (0UL)                    /*!< GP_TIMERS PWM3_END_CYCLE: END_CYCLE (Bit 0)                 */
#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Msk (0x3fffUL)               /*!< GP_TIMERS PWM3_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff) */

/* --------------------------  GP_TIMERS_PWM4_END_CYCLE  -------------------------- */
#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Pos (0UL)                    /*!< GP_TIMERS PWM4_END_CYCLE: END_CYCLE (Bit 0)                 */
#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Msk (0x3fffUL)               /*!< GP_TIMERS PWM4_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff) */

/* -----------------------  GP_TIMERS_TRIPLE_PWM_FREQUENCY  ----------------------- */
#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Pos (0UL)                   /*!< GP_TIMERS TRIPLE_PWM_FREQUENCY: FREQ (Bit 0)                */
#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Msk (0x3fffUL)              /*!< GP_TIMERS TRIPLE_PWM_FREQUENCY: FREQ (Bitfield-Mask: 0x3fff) */

/* ------------------------  GP_TIMERS_TRIPLE_PWM_CTRL_REG  ----------------------- */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Pos (0UL)       /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_ENABLE (Bit 0)    */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Msk (0x1UL)     /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_ENABLE (Bitfield-Mask: 0x01) */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Pos (1UL)             /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bit 1)          */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Msk (0x2UL)           /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bitfield-Mask: 0x01) */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Pos (2UL)             /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bit 2)          */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Msk (0x4UL)           /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bitfield-Mask: 0x01) */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Pos (3UL)      /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bit 3)   */
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Msk (0x8UL)    /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bitfield-Mask: 0x01) */

/* --------------------------  GP_TIMERS_BREATH_CFG_REG  -------------------------- */
#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Pos (0UL)                     /*!< GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bit 0)                  */
#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Msk (0xffUL)                  /*!< GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bitfield-Mask: 0xff)    */
#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Pos (8UL)                    /*!< GP_TIMERS BREATH_CFG_REG: BRTH_STEP (Bit 8)                 */
#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Msk (0xff00UL)               /*!< GP_TIMERS BREATH_CFG_REG: BRTH_STEP (Bitfield-Mask: 0xff)   */

/* ------------------------  GP_TIMERS_BREATH_DUTY_MAX_REG  ----------------------- */
#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Pos (0UL)           /*!< GP_TIMERS BREATH_DUTY_MAX_REG: BRTH_DUTY_MAX (Bit 0)        */
#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Msk (0xffUL)        /*!< GP_TIMERS BREATH_DUTY_MAX_REG: BRTH_DUTY_MAX (Bitfield-Mask: 0xff) */

/* ------------------------  GP_TIMERS_BREATH_DUTY_MIN_REG  ----------------------- */
#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Pos (0UL)           /*!< GP_TIMERS BREATH_DUTY_MIN_REG: BRTH_DUTY_MIN (Bit 0)        */
#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Msk (0xffUL)        /*!< GP_TIMERS BREATH_DUTY_MIN_REG: BRTH_DUTY_MIN (Bitfield-Mask: 0xff) */

/* --------------------------  GP_TIMERS_BREATH_CTRL_REG  ------------------------- */
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Pos (0UL)                     /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_EN (Bit 0)                  */
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Msk (0x1UL)                   /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_EN (Bitfield-Mask: 0x01)    */
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Pos (1UL)                /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_PWM_POL (Bit 1)             */
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Msk (0x2UL)              /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_PWM_POL (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================         struct 'GPADC' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------  GPADC_GP_ADC_CTRL_REG  --------------------------- */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos   (0UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_EN (Bit 0)                    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk   (0x1UL)                   /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_EN (Bitfield-Mask: 0x01)      */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL)                    /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_START (Bit 1)                 */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL)                  /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_START (Bitfield-Mask: 0x01)   */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CONT (Bit 2)                  */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL)                   /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CONT (Bitfield-Mask: 0x01)    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos (3UL)                  /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CLK_SEL (Bit 3)               */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk (0x8UL)                /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CLK_SEL (Bitfield-Mask: 0x01) */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos  (4UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_INT (Bit 4)                   */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk  (0x10UL)                  /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_INT (Bitfield-Mask: 0x01)     */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MINT (Bit 5)                  */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL)                  /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MINT (Bitfield-Mask: 0x01)    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos   (6UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SE (Bit 6)                    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk   (0x40UL)                  /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SE (Bitfield-Mask: 0x01)      */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MUTE (Bit 7)                  */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL)                  /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MUTE (Bitfield-Mask: 0x01)    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos  (8UL)                     /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SEL (Bit 8)                   */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk  (0x1f00UL)                /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SEL (Bitfield-Mask: 0x1f)     */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (13UL)                    /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SIGN (Bit 13)                 */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x2000UL)                /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SIGN (Bitfield-Mask: 0x01)    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (14UL)                    /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CHOP (Bit 14)                 */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x4000UL)                /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CHOP (Bitfield-Mask: 0x01)    */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos (15UL)                /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_LDO_ZERO (Bit 15)             */
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk (0x8000UL)            /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_LDO_ZERO (Bitfield-Mask: 0x01) */

/* ---------------------------  GPADC_GP_ADC_CTRL2_REG  --------------------------- */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos (0UL)                  /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_ATTN3X (Bit 0)               */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk (0x1UL)                /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_ATTN3X (Bitfield-Mask: 0x01) */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos (1UL)                    /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_IDYN (Bit 1)                 */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk (0x2UL)                  /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_IDYN (Bitfield-Mask: 0x01)   */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL)                    /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_I20U (Bit 2)                 */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL)                  /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_I20U (Bitfield-Mask: 0x01)   */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos (3UL)                  /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_DMA_EN (Bit 3)               */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk (0x8UL)                /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_DMA_EN (Bitfield-Mask: 0x01) */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (5UL)                /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_CONV_NRS (Bit 5)             */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0xe0UL)             /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_CONV_NRS (Bitfield-Mask: 0x07) */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (8UL)               /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_SMPL_TIME (Bit 8)            */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0xf00UL)           /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f) */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (12UL)              /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_STORE_DEL (Bit 12)           */
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xf000UL)          /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_STORE_DEL (Bitfield-Mask: 0x0f) */

/* ---------------------------  GPADC_GP_ADC_CTRL3_REG  --------------------------- */
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL)                  /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_EN_DEL (Bit 0)               */
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL)               /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_EN_DEL (Bitfield-Mask: 0xff) */
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL)                /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_INTERVAL (Bit 8)             */
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL)           /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_INTERVAL (Bitfield-Mask: 0xff) */

/* ----------------------------  GPADC_GP_ADC_OFFP_REG  --------------------------- */
#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL)                     /*!< GPADC GP_ADC_OFFP_REG: GP_ADC_OFFP (Bit 0)                  */
#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL)                 /*!< GPADC GP_ADC_OFFP_REG: GP_ADC_OFFP (Bitfield-Mask: 0x3ff)   */

/* ----------------------------  GPADC_GP_ADC_OFFN_REG  --------------------------- */
#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL)                     /*!< GPADC GP_ADC_OFFN_REG: GP_ADC_OFFN (Bit 0)                  */
#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL)                 /*!< GPADC GP_ADC_OFFN_REG: GP_ADC_OFFN (Bitfield-Mask: 0x3ff)   */

/* -------------------------  GPADC_GP_ADC_CLEAR_INT_REG  ------------------------- */
#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL)             /*!< GPADC GP_ADC_CLEAR_INT_REG: GP_ADC_CLR_INT (Bit 0)          */
#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL)        /*!< GPADC GP_ADC_CLEAR_INT_REG: GP_ADC_CLR_INT (Bitfield-Mask: 0xffff) */

/* ---------------------------  GPADC_GP_ADC_RESULT_REG  -------------------------- */
#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL)                    /*!< GPADC GP_ADC_RESULT_REG: GP_ADC_VAL (Bit 0)                 */
#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL)               /*!< GPADC GP_ADC_RESULT_REG: GP_ADC_VAL (Bitfield-Mask: 0xffff) */


/* ================================================================================ */
/* ================          struct 'GPIO' Position & Mask         ================ */
/* ================================================================================ */


/* ------------------------------  GPIO_P0_DATA_REG  ------------------------------ */
#define GPIO_P0_DATA_REG_P0_DATA_Pos          (0UL)                     /*!< GPIO P0_DATA_REG: P0_DATA (Bit 0)                           */
#define GPIO_P0_DATA_REG_P0_DATA_Msk          (0xffUL)                  /*!< GPIO P0_DATA_REG: P0_DATA (Bitfield-Mask: 0xff)             */

/* ------------------------------  GPIO_P1_DATA_REG  ------------------------------ */
#define GPIO_P1_DATA_REG_P1_DATA_Pos          (0UL)                     /*!< GPIO P1_DATA_REG: P1_DATA (Bit 0)                           */
#define GPIO_P1_DATA_REG_P1_DATA_Msk          (0xffUL)                  /*!< GPIO P1_DATA_REG: P1_DATA (Bitfield-Mask: 0xff)             */

/* ------------------------------  GPIO_P2_DATA_REG  ------------------------------ */
#define GPIO_P2_DATA_REG_P2_DATA_Pos          (0UL)                     /*!< GPIO P2_DATA_REG: P2_DATA (Bit 0)                           */
#define GPIO_P2_DATA_REG_P2_DATA_Msk          (0x1fUL)                  /*!< GPIO P2_DATA_REG: P2_DATA (Bitfield-Mask: 0x1f)             */

/* ------------------------------  GPIO_P3_DATA_REG  ------------------------------ */
#define GPIO_P3_DATA_REG_P3_DATA_Pos          (0UL)                     /*!< GPIO P3_DATA_REG: P3_DATA (Bit 0)                           */
#define GPIO_P3_DATA_REG_P3_DATA_Msk          (0xffUL)                  /*!< GPIO P3_DATA_REG: P3_DATA (Bitfield-Mask: 0xff)             */

/* ------------------------------  GPIO_P4_DATA_REG  ------------------------------ */
#define GPIO_P4_DATA_REG_P4_DATA_Pos          (0UL)                     /*!< GPIO P4_DATA_REG: P4_DATA (Bit 0)                           */
#define GPIO_P4_DATA_REG_P4_DATA_Msk          (0xffUL)                  /*!< GPIO P4_DATA_REG: P4_DATA (Bitfield-Mask: 0xff)             */

/* ----------------------------  GPIO_P0_SET_DATA_REG  ---------------------------- */
#define GPIO_P0_SET_DATA_REG_P0_SET_Pos       (0UL)                     /*!< GPIO P0_SET_DATA_REG: P0_SET (Bit 0)                        */
#define GPIO_P0_SET_DATA_REG_P0_SET_Msk       (0xffUL)                  /*!< GPIO P0_SET_DATA_REG: P0_SET (Bitfield-Mask: 0xff)          */

/* ----------------------------  GPIO_P1_SET_DATA_REG  ---------------------------- */
#define GPIO_P1_SET_DATA_REG_P1_SET_Pos       (0UL)                     /*!< GPIO P1_SET_DATA_REG: P1_SET (Bit 0)                        */
#define GPIO_P1_SET_DATA_REG_P1_SET_Msk       (0xffUL)                  /*!< GPIO P1_SET_DATA_REG: P1_SET (Bitfield-Mask: 0xff)          */

/* ----------------------------  GPIO_P2_SET_DATA_REG  ---------------------------- */
#define GPIO_P2_SET_DATA_REG_P2_SET_Pos       (0UL)                     /*!< GPIO P2_SET_DATA_REG: P2_SET (Bit 0)                        */
#define GPIO_P2_SET_DATA_REG_P2_SET_Msk       (0x1fUL)                  /*!< GPIO P2_SET_DATA_REG: P2_SET (Bitfield-Mask: 0x1f)          */

/* ----------------------------  GPIO_P3_SET_DATA_REG  ---------------------------- */
#define GPIO_P3_SET_DATA_REG_P3_SET_Pos       (0UL)                     /*!< GPIO P3_SET_DATA_REG: P3_SET (Bit 0)                        */
#define GPIO_P3_SET_DATA_REG_P3_SET_Msk       (0xffUL)                  /*!< GPIO P3_SET_DATA_REG: P3_SET (Bitfield-Mask: 0xff)          */

/* ----------------------------  GPIO_P4_SET_DATA_REG  ---------------------------- */
#define GPIO_P4_SET_DATA_REG_P4_SET_Pos       (0UL)                     /*!< GPIO P4_SET_DATA_REG: P4_SET (Bit 0)                        */
#define GPIO_P4_SET_DATA_REG_P4_SET_Msk       (0xffUL)                  /*!< GPIO P4_SET_DATA_REG: P4_SET (Bitfield-Mask: 0xff)          */

/* ---------------------------  GPIO_P0_RESET_DATA_REG  --------------------------- */
#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos   (0UL)                     /*!< GPIO P0_RESET_DATA_REG: P0_RESET (Bit 0)                    */
#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk   (0xffUL)                  /*!< GPIO P0_RESET_DATA_REG: P0_RESET (Bitfield-Mask: 0xff)      */

/* ---------------------------  GPIO_P1_RESET_DATA_REG  --------------------------- */
#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos   (0UL)                     /*!< GPIO P1_RESET_DATA_REG: P1_RESET (Bit 0)                    */
#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk   (0xffUL)                  /*!< GPIO P1_RESET_DATA_REG: P1_RESET (Bitfield-Mask: 0xff)      */

/* ---------------------------  GPIO_P2_RESET_DATA_REG  --------------------------- */
#define GPIO_P2_RESET_DATA_REG_P2_RESET_Pos   (0UL)                     /*!< GPIO P2_RESET_DATA_REG: P2_RESET (Bit 0)                    */
#define GPIO_P2_RESET_DATA_REG_P2_RESET_Msk   (0x1fUL)                  /*!< GPIO P2_RESET_DATA_REG: P2_RESET (Bitfield-Mask: 0x1f)      */

/* ---------------------------  GPIO_P3_RESET_DATA_REG  --------------------------- */
#define GPIO_P3_RESET_DATA_REG_P3_RESET_Pos   (0UL)                     /*!< GPIO P3_RESET_DATA_REG: P3_RESET (Bit 0)                    */
#define GPIO_P3_RESET_DATA_REG_P3_RESET_Msk   (0xffUL)                  /*!< GPIO P3_RESET_DATA_REG: P3_RESET (Bitfield-Mask: 0xff)      */

/* ---------------------------  GPIO_P4_RESET_DATA_REG  --------------------------- */
#define GPIO_P4_RESET_DATA_REG_P4_RESET_Pos   (0UL)                     /*!< GPIO P4_RESET_DATA_REG: P4_RESET (Bit 0)                    */
#define GPIO_P4_RESET_DATA_REG_P4_RESET_Msk   (0xffUL)                  /*!< GPIO P4_RESET_DATA_REG: P4_RESET (Bitfield-Mask: 0xff)      */

/* ------------------------------  GPIO_P00_MODE_REG  ----------------------------- */
#define GPIO_P00_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P00_MODE_REG: PID (Bit 0)                              */
#define GPIO_P00_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P00_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P00_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P00_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P00_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P00_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P00_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P00_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P00_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P00_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P01_MODE_REG  ----------------------------- */
#define GPIO_P01_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P01_MODE_REG: PID (Bit 0)                              */
#define GPIO_P01_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P01_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P01_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P01_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P01_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P01_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P01_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P01_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P01_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P01_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P02_MODE_REG  ----------------------------- */
#define GPIO_P02_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P02_MODE_REG: PID (Bit 0)                              */
#define GPIO_P02_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P02_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P02_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P02_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P02_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P02_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P02_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P02_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P02_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P02_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P03_MODE_REG  ----------------------------- */
#define GPIO_P03_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P03_MODE_REG: PID (Bit 0)                              */
#define GPIO_P03_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P03_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P03_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P03_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P03_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P03_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P03_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P03_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P03_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P03_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P04_MODE_REG  ----------------------------- */
#define GPIO_P04_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P04_MODE_REG: PID (Bit 0)                              */
#define GPIO_P04_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P04_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P04_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P04_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P04_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P04_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P04_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P04_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P04_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P04_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P05_MODE_REG  ----------------------------- */
#define GPIO_P05_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P05_MODE_REG: PID (Bit 0)                              */
#define GPIO_P05_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P05_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P05_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P05_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P05_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P05_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P05_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P05_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P05_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P05_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P06_MODE_REG  ----------------------------- */
#define GPIO_P06_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P06_MODE_REG: PID (Bit 0)                              */
#define GPIO_P06_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P06_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P06_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P06_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P06_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P06_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P06_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P06_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P06_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P06_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P07_MODE_REG  ----------------------------- */
#define GPIO_P07_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P07_MODE_REG: PID (Bit 0)                              */
#define GPIO_P07_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P07_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P07_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P07_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P07_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P07_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P07_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P07_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P07_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P07_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P10_MODE_REG  ----------------------------- */
#define GPIO_P10_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P10_MODE_REG: PID (Bit 0)                              */
#define GPIO_P10_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P10_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P10_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P10_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P10_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P10_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P10_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P10_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P10_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P10_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P11_MODE_REG  ----------------------------- */
#define GPIO_P11_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P11_MODE_REG: PID (Bit 0)                              */
#define GPIO_P11_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P11_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P11_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P11_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P11_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P11_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P11_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P11_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P11_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P11_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P12_MODE_REG  ----------------------------- */
#define GPIO_P12_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P12_MODE_REG: PID (Bit 0)                              */
#define GPIO_P12_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P12_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P12_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P12_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P12_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P12_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P12_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P12_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P12_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P12_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P13_MODE_REG  ----------------------------- */
#define GPIO_P13_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P13_MODE_REG: PID (Bit 0)                              */
#define GPIO_P13_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P13_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P13_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P13_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P13_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P13_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P13_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P13_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P13_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P13_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P14_MODE_REG  ----------------------------- */
#define GPIO_P14_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P14_MODE_REG: PID (Bit 0)                              */
#define GPIO_P14_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P14_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P14_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P14_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P14_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P14_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P14_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P14_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P14_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P14_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P15_MODE_REG  ----------------------------- */
#define GPIO_P15_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P15_MODE_REG: PID (Bit 0)                              */
#define GPIO_P15_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P15_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P15_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P15_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P15_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P15_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P15_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P15_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P15_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P15_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P16_MODE_REG  ----------------------------- */
#define GPIO_P16_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P16_MODE_REG: PID (Bit 0)                              */
#define GPIO_P16_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P16_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P16_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P16_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P16_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P16_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P16_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P16_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P16_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P16_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P17_MODE_REG  ----------------------------- */
#define GPIO_P17_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P17_MODE_REG: PID (Bit 0)                              */
#define GPIO_P17_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P17_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P17_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P17_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P17_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P17_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P17_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P17_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P17_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P17_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P20_MODE_REG  ----------------------------- */
#define GPIO_P20_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P20_MODE_REG: PID (Bit 0)                              */
#define GPIO_P20_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P20_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P20_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P20_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P20_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P20_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P20_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P20_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P20_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P20_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P21_MODE_REG  ----------------------------- */
#define GPIO_P21_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P21_MODE_REG: PID (Bit 0)                              */
#define GPIO_P21_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P21_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P21_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P21_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P21_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P21_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P21_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P21_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P21_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P21_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P22_MODE_REG  ----------------------------- */
#define GPIO_P22_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P22_MODE_REG: PID (Bit 0)                              */
#define GPIO_P22_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P22_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P22_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P22_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P22_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P22_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P22_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P22_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P22_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P22_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P23_MODE_REG  ----------------------------- */
#define GPIO_P23_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P23_MODE_REG: PID (Bit 0)                              */
#define GPIO_P23_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P23_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P23_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P23_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P23_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P23_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P23_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P23_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P23_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P23_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P24_MODE_REG  ----------------------------- */
#define GPIO_P24_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P24_MODE_REG: PID (Bit 0)                              */
#define GPIO_P24_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P24_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P24_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P24_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P24_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P24_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P24_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P24_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P24_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P24_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P30_MODE_REG  ----------------------------- */
#define GPIO_P30_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P30_MODE_REG: PID (Bit 0)                              */
#define GPIO_P30_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P30_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P30_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P30_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P30_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P30_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P30_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P30_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P30_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P30_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P31_MODE_REG  ----------------------------- */
#define GPIO_P31_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P31_MODE_REG: PID (Bit 0)                              */
#define GPIO_P31_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P31_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P31_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P31_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P31_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P31_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P31_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P31_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P31_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P31_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P32_MODE_REG  ----------------------------- */
#define GPIO_P32_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P32_MODE_REG: PID (Bit 0)                              */
#define GPIO_P32_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P32_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P32_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P32_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P32_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P32_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P32_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P32_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P32_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P32_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P33_MODE_REG  ----------------------------- */
#define GPIO_P33_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P33_MODE_REG: PID (Bit 0)                              */
#define GPIO_P33_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P33_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P33_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P33_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P33_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P33_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P33_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P33_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P33_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P33_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P34_MODE_REG  ----------------------------- */
#define GPIO_P34_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P34_MODE_REG: PID (Bit 0)                              */
#define GPIO_P34_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P34_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P34_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P34_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P34_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P34_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P34_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P34_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P34_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P34_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P35_MODE_REG  ----------------------------- */
#define GPIO_P35_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P35_MODE_REG: PID (Bit 0)                              */
#define GPIO_P35_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P35_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P35_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P35_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P35_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P35_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P35_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P35_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P35_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P35_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P36_MODE_REG  ----------------------------- */
#define GPIO_P36_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P36_MODE_REG: PID (Bit 0)                              */
#define GPIO_P36_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P36_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P36_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P36_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P36_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P36_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P36_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P36_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P36_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P36_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P37_MODE_REG  ----------------------------- */
#define GPIO_P37_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P37_MODE_REG: PID (Bit 0)                              */
#define GPIO_P37_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P37_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P37_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P37_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P37_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P37_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P37_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P37_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P37_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P37_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P40_MODE_REG  ----------------------------- */
#define GPIO_P40_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P40_MODE_REG: PID (Bit 0)                              */
#define GPIO_P40_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P40_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P40_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P40_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P40_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P40_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P40_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P40_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P40_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P40_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P41_MODE_REG  ----------------------------- */
#define GPIO_P41_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P41_MODE_REG: PID (Bit 0)                              */
#define GPIO_P41_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P41_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P41_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P41_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P41_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P41_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P41_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P41_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P41_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P41_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P42_MODE_REG  ----------------------------- */
#define GPIO_P42_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P42_MODE_REG: PID (Bit 0)                              */
#define GPIO_P42_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P42_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P42_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P42_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P42_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P42_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P42_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P42_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P42_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P42_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P43_MODE_REG  ----------------------------- */
#define GPIO_P43_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P43_MODE_REG: PID (Bit 0)                              */
#define GPIO_P43_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P43_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P43_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P43_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P43_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P43_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P43_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P43_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P43_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P43_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P44_MODE_REG  ----------------------------- */
#define GPIO_P44_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P44_MODE_REG: PID (Bit 0)                              */
#define GPIO_P44_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P44_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P44_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P44_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P44_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P44_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P44_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P44_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P44_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P44_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P45_MODE_REG  ----------------------------- */
#define GPIO_P45_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P45_MODE_REG: PID (Bit 0)                              */
#define GPIO_P45_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P45_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P45_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P45_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P45_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P45_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P45_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P45_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P45_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P45_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P46_MODE_REG  ----------------------------- */
#define GPIO_P46_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P46_MODE_REG: PID (Bit 0)                              */
#define GPIO_P46_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P46_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P46_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P46_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P46_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P46_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P46_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P46_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P46_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P46_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ------------------------------  GPIO_P47_MODE_REG  ----------------------------- */
#define GPIO_P47_MODE_REG_PID_Pos             (0UL)                     /*!< GPIO P47_MODE_REG: PID (Bit 0)                              */
#define GPIO_P47_MODE_REG_PID_Msk             (0x3fUL)                  /*!< GPIO P47_MODE_REG: PID (Bitfield-Mask: 0x3f)                */
#define GPIO_P47_MODE_REG_PUPD_Pos            (8UL)                     /*!< GPIO P47_MODE_REG: PUPD (Bit 8)                             */
#define GPIO_P47_MODE_REG_PUPD_Msk            (0x300UL)                 /*!< GPIO P47_MODE_REG: PUPD (Bitfield-Mask: 0x03)               */
#define GPIO_P47_MODE_REG_PPOD_Pos            (10UL)                    /*!< GPIO P47_MODE_REG: PPOD (Bit 10)                            */
#define GPIO_P47_MODE_REG_PPOD_Msk            (0x400UL)                 /*!< GPIO P47_MODE_REG: PPOD (Bitfield-Mask: 0x01)               */

/* ---------------------------  GPIO_P0_PADPWR_CTRL_REG  -------------------------- */
#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos (6UL)                   /*!< GPIO P0_PADPWR_CTRL_REG: P0_OUT_CTRL (Bit 6)                */
#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk (0xc0UL)                /*!< GPIO P0_PADPWR_CTRL_REG: P0_OUT_CTRL (Bitfield-Mask: 0x03)  */

/* ---------------------------  GPIO_P1_PADPWR_CTRL_REG  -------------------------- */
#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos (0UL)                   /*!< GPIO P1_PADPWR_CTRL_REG: P1_OUT_CTRL (Bit 0)                */
#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk (0xffUL)                /*!< GPIO P1_PADPWR_CTRL_REG: P1_OUT_CTRL (Bitfield-Mask: 0xff)  */

/* ---------------------------  GPIO_P2_PADPWR_CTRL_REG  -------------------------- */
#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Pos (0UL)                   /*!< GPIO P2_PADPWR_CTRL_REG: P2_OUT_CTRL (Bit 0)                */
#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Msk (0x1fUL)                /*!< GPIO P2_PADPWR_CTRL_REG: P2_OUT_CTRL (Bitfield-Mask: 0x1f)  */

/* ---------------------------  GPIO_P3_PADPWR_CTRL_REG  -------------------------- */
#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Pos (0UL)                   /*!< GPIO P3_PADPWR_CTRL_REG: P3_OUT_CTRL (Bit 0)                */
#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Msk (0xffUL)                /*!< GPIO P3_PADPWR_CTRL_REG: P3_OUT_CTRL (Bitfield-Mask: 0xff)  */

/* ---------------------------  GPIO_P4_PADPWR_CTRL_REG  -------------------------- */
#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Pos (0UL)                   /*!< GPIO P4_PADPWR_CTRL_REG: P4_OUT_CTRL (Bit 0)                */
#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Msk (0xffUL)                /*!< GPIO P4_PADPWR_CTRL_REG: P4_OUT_CTRL (Bitfield-Mask: 0xff)  */

/* ------------------------------  GPIO_GPIO_CLK_SEL  ----------------------------- */
#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Pos  (0UL)                     /*!< GPIO GPIO_CLK_SEL: FUNC_CLOCK_SEL (Bit 0)                   */
#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Msk  (0x7UL)                   /*!< GPIO GPIO_CLK_SEL: FUNC_CLOCK_SEL (Bitfield-Mask: 0x07)     */

/* -----------------------------  GPIO_BIST_CTRL_REG  ----------------------------- */
#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Pos (0UL)                    /*!< GPIO BIST_CTRL_REG: RAM_BIST_CONFIG (Bit 0)                 */
#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Msk (0x3UL)                  /*!< GPIO BIST_CTRL_REG: RAM_BIST_CONFIG (Bitfield-Mask: 0x03)   */
#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Pos (2UL)                   /*!< GPIO BIST_CTRL_REG: RAM_BIST_PATTERN (Bit 2)                */
#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Msk (0xcUL)                 /*!< GPIO BIST_CTRL_REG: RAM_BIST_PATTERN (Bitfield-Mask: 0x03)  */
#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Pos (4UL)                     /*!< GPIO BIST_CTRL_REG: ROMBIST_ENABLE (Bit 4)                  */
#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Msk (0x10UL)                  /*!< GPIO BIST_CTRL_REG: ROMBIST_ENABLE (Bitfield-Mask: 0x01)    */
#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Pos (5UL)                     /*!< GPIO BIST_CTRL_REG: RAMBIST_ENABLE (Bit 5)                  */
#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Msk (0x20UL)                  /*!< GPIO BIST_CTRL_REG: RAMBIST_ENABLE (Bitfield-Mask: 0x01)    */
#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Pos (6UL)                  /*!< GPIO BIST_CTRL_REG: SYSRAMBIST_ENABLE (Bit 6)               */
#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Msk (0x40UL)               /*!< GPIO BIST_CTRL_REG: SYSRAMBIST_ENABLE (Bitfield-Mask: 0x01) */
#define GPIO_BIST_CTRL_REG_SHOW_BIST_Pos      (7UL)                     /*!< GPIO BIST_CTRL_REG: SHOW_BIST (Bit 7)                       */
#define GPIO_BIST_CTRL_REG_SHOW_BIST_Msk      (0x80UL)                  /*!< GPIO BIST_CTRL_REG: SHOW_BIST (Bitfield-Mask: 0x01)         */

/* --------------------------  GPIO_RAMBIST_STATUS1_REG  -------------------------- */
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Pos (0UL)        /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_LINE_FAIL (Bit 0)     */
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Msk (0x1UL)      /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Pos (1UL)             /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_FAIL (Bit 1)          */
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Msk (0x2UL)           /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Pos (2UL)             /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_BUSY (Bit 2)          */
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Msk (0x4UL)           /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Pos (3UL)         /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_LINE_FAIL (Bit 3)      */
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Msk (0x8UL)       /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Pos (4UL)              /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_FAIL (Bit 4)           */
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Msk (0x10UL)           /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Pos (5UL)              /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_BUSY (Bit 5)           */
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Msk (0x20UL)           /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Pos (6UL)         /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_LINE_FAIL (Bit 6)      */
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Msk (0x40UL)      /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Pos (7UL)              /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_FAIL (Bit 7)           */
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Msk (0x80UL)           /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Pos (8UL)              /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_BUSY (Bit 8)           */
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Msk (0x100UL)          /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Pos (9UL)        /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_LINE_FAIL (Bit 9)     */
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Msk (0x200UL)    /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Pos (10UL)            /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_FAIL (Bit 10)         */
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Msk (0x400UL)         /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Pos (11UL)            /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_BUSY (Bit 11)         */
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Msk (0x800UL)         /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Pos (12UL)      /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_LINE_FAIL (Bit 12)   */
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Msk (0x1000UL)  /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Pos (13UL)           /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_FAIL (Bit 13)        */
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Msk (0x2000UL)       /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Pos (14UL)           /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_BUSY (Bit 14)        */
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Msk (0x4000UL)       /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Pos (15UL)               /*!< GPIO RAMBIST_STATUS1_REG: ROM_BIST_BUSY (Bit 15)            */
#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Msk (0x8000UL)           /*!< GPIO RAMBIST_STATUS1_REG: ROM_BIST_BUSY (Bitfield-Mask: 0x01) */

/* --------------------------  GPIO_RAMBIST_STATUS2_REG  -------------------------- */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Pos (0UL)    /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_LINE_FAIL (Bit 0) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Msk (0x1UL)  /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Pos (1UL)         /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_FAIL (Bit 1)      */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Msk (0x2UL)       /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Pos (2UL)         /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_BUSY (Bit 2)      */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Msk (0x4UL)       /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Pos (3UL)    /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_LINE_FAIL (Bit 3) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Msk (0x8UL)  /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Pos (4UL)         /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_FAIL (Bit 4)      */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Msk (0x10UL)      /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Pos (5UL)         /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_BUSY (Bit 5)      */
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Msk (0x20UL)      /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Pos (6UL)   /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_LINE_FAIL (Bit 6) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Msk (0x40UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Pos (7UL)        /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_FAIL (Bit 7)     */
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Msk (0x80UL)     /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Pos (8UL)        /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_BUSY (Bit 8)     */
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Msk (0x100UL)    /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Pos (9UL)    /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_LINE_FAIL (Bit 9) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Msk (0x200UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Pos (10UL)        /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_FAIL (Bit 10)     */
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Msk (0x400UL)     /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Pos (11UL)        /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_BUSY (Bit 11)     */
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Msk (0x800UL)     /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_BUSY (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Pos (12UL)    /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_LINE_FAIL (Bit 12) */
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Msk (0x1000UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Pos (13UL)         /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_FAIL (Bit 13)      */
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Msk (0x2000UL)     /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Pos (14UL)         /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bit 14)      */
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Msk (0x4000UL)     /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bitfield-Mask: 0x01) */

/* --------------------------  GPIO_RAMBIST_STATUS3_REG  -------------------------- */
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Pos (0UL)    /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bit 0) */
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Msk (0x1UL)  /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Pos (1UL)         /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bit 1)      */
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Msk (0x2UL)       /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bitfield-Mask: 0x01) */
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Pos (2UL)         /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bit 2)      */
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Msk (0x4UL)       /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bitfield-Mask: 0x01) */

/* --------------------------  GPIO_ROMBIST_RESULTL_REG  -------------------------- */
#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Pos (0UL)              /*!< GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bit 0)           */
#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Msk (0xffffUL)         /*!< GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bitfield-Mask: 0xffff) */

/* --------------------------  GPIO_ROMBIST_RESULTH_REG  -------------------------- */
#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Pos (0UL)              /*!< GPIO ROMBIST_RESULTH_REG: ROMBIST_RESULTH (Bit 0)           */
#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Msk (0xffffUL)         /*!< GPIO ROMBIST_RESULTH_REG: ROMBIST_RESULTH (Bitfield-Mask: 0xffff) */

/* -----------------------------  GPIO_TEST_CTRL_REG  ----------------------------- */
#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Pos    (0UL)                     /*!< GPIO TEST_CTRL_REG: SHOW_CLOCKS (Bit 0)                     */
#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Msk    (0x1UL)                   /*!< GPIO TEST_CTRL_REG: SHOW_CLOCKS (Bitfield-Mask: 0x01)       */
#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Pos    (1UL)                     /*!< GPIO TEST_CTRL_REG: ENABLE_RFPT (Bit 1)                     */
#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Msk    (0x2UL)                   /*!< GPIO TEST_CTRL_REG: ENABLE_RFPT (Bitfield-Mask: 0x01)       */
#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Pos (2UL)                  /*!< GPIO TEST_CTRL_REG: SHOW_PLL_TEST_OUT (Bit 2)               */
#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Msk (0x4UL)                /*!< GPIO TEST_CTRL_REG: SHOW_PLL_TEST_OUT (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Pos (3UL)                  /*!< GPIO TEST_CTRL_REG: SHOW_DCDC_TESTBUS (Bit 3)               */
#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Msk (0x8UL)                /*!< GPIO TEST_CTRL_REG: SHOW_DCDC_TESTBUS (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Pos (4UL)                /*!< GPIO TEST_CTRL_REG: XTAL16M_CAP_TEST_EN (Bit 4)             */
#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Msk (0x10UL)             /*!< GPIO TEST_CTRL_REG: XTAL16M_CAP_TEST_EN (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Pos     (5UL)                     /*!< GPIO TEST_CTRL_REG: SHOW_IF_RO (Bit 5)                      */
#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Msk     (0x20UL)                  /*!< GPIO TEST_CTRL_REG: SHOW_IF_RO (Bitfield-Mask: 0x01)        */
#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Pos   (6UL)                     /*!< GPIO TEST_CTRL_REG: PLL_TST_MODE (Bit 6)                    */
#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Msk   (0x40UL)                  /*!< GPIO TEST_CTRL_REG: PLL_TST_MODE (Bitfield-Mask: 0x01)      */
#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Pos (7UL)                     /*!< GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bit 7)                  */
#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Msk (0x80UL)                  /*!< GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bitfield-Mask: 0x01)    */
#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Pos (8UL)                   /*!< GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bit 8)                */
#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Msk (0x700UL)               /*!< GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bitfield-Mask: 0x07)  */
#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Pos (12UL)                   /*!< GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bit 12)                */
#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Msk (0x3000UL)               /*!< GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bitfield-Mask: 0x03)   */
#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Pos (14UL)              /*!< GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bit 14)           */
#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Msk (0x4000UL)          /*!< GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bitfield-Mask: 0x01) */

/* -----------------------------  GPIO_TEST_CTRL2_REG  ---------------------------- */
#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Pos (0UL)                  /*!< GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bit 0)               */
#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Msk (0xfUL)                /*!< GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bitfield-Mask: 0x0f) */
#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Pos (8UL)                /*!< GPIO TEST_CTRL2_REG: RF_IN_TESTMUX_CTRL (Bit 8)             */
#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Msk (0x300UL)            /*!< GPIO TEST_CTRL2_REG: RF_IN_TESTMUX_CTRL (Bitfield-Mask: 0x03) */

/* -----------------------------  GPIO_TEST_CTRL3_REG  ---------------------------- */
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Pos (0UL)                   /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bit 0)                */
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Msk (0x3fUL)                /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bitfield-Mask: 0x3f)  */
#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Pos (6UL)              /*!< GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bit 6)           */
#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Msk (0x40UL)           /*!< GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Pos (8UL)                 /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bit 8)              */
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Msk (0xff00UL)            /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bitfield-Mask: 0xff) */

/* -----------------------------  GPIO_TEST_CTRL4_REG  ---------------------------- */
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Pos (0UL)                    /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_SEL (Bit 0)                 */
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Msk (0x7UL)                  /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_SEL (Bitfield-Mask: 0x07)   */
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Pos (8UL)                  /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_PARAM (Bit 8)               */
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Msk (0xff00UL)             /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_PARAM (Bitfield-Mask: 0xff) */

/* -----------------------------  GPIO_TEST_CTRL5_REG  ---------------------------- */
#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Pos (0UL)                   /*!< GPIO TEST_CTRL5_REG: TEST_BUS_TO_AVS (Bit 0)                */
#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Msk (0x1UL)                 /*!< GPIO TEST_CTRL5_REG: TEST_BUS_TO_AVS (Bitfield-Mask: 0x01)  */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Pos  (1UL)                     /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V4 (Bit 1)                   */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Msk  (0x2UL)                   /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V4 (Bitfield-Mask: 0x01)     */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Pos (2UL)                /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_FLASH (Bit 2)             */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Msk (0x4UL)              /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_FLASH (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Pos (3UL)                     /*!< GPIO TEST_CTRL5_REG: TEST_LDO_CORE (Bit 3)                  */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Msk (0x8UL)                   /*!< GPIO TEST_CTRL5_REG: TEST_LDO_CORE (Bitfield-Mask: 0x01)    */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Pos (4UL)                   /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_PA (Bit 4)                */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Msk (0x10UL)                /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_PA (Bitfield-Mask: 0x01)  */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Pos  (5UL)                     /*!< GPIO TEST_CTRL5_REG: TEST_LDO_ADC (Bit 5)                   */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Msk  (0x20UL)                  /*!< GPIO TEST_CTRL5_REG: TEST_LDO_ADC (Bitfield-Mask: 0x01)     */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Pos  (6UL)                     /*!< GPIO TEST_CTRL5_REG: TEST_LDO_PLL (Bit 6)                   */
#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Msk  (0x40UL)                  /*!< GPIO TEST_CTRL5_REG: TEST_LDO_PLL (Bitfield-Mask: 0x01)     */
#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Pos (7UL)               /*!< GPIO TEST_CTRL5_REG: TEST_BANDGAP_I_TEST (Bit 7)            */
#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Msk (0x80UL)            /*!< GPIO TEST_CTRL5_REG: TEST_BANDGAP_I_TEST (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Pos (8UL)                    /*!< GPIO TEST_CTRL5_REG: TEST_SIMO_BUCK (Bit 8)                 */
#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Msk (0x100UL)                /*!< GPIO TEST_CTRL5_REG: TEST_SIMO_BUCK (Bitfield-Mask: 0x01)   */
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Pos (9UL)                 /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_OUT (Bit 9)              */
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Msk (0x200UL)             /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_OUT (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Pos (10UL)                 /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_IN (Bit 10)              */
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Msk (0x400UL)              /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_IN (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Pos (11UL)                 /*!< GPIO TEST_CTRL5_REG: TEST_I_DCDC_FILT (Bit 11)              */
#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Msk (0x800UL)              /*!< GPIO TEST_CTRL5_REG: TEST_I_DCDC_FILT (Bitfield-Mask: 0x01) */
#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Pos  (12UL)                    /*!< GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bit 12)                  */
#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Msk  (0x1000UL)                /*!< GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bitfield-Mask: 0x01)     */
#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Pos (13UL)                  /*!< GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bit 13)               */
#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Msk (0x2000UL)              /*!< GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bitfield-Mask: 0x01)  */
#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Pos (14UL)            /*!< GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bit 14)         */
#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Msk (0x4000UL)        /*!< GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================         struct 'GPREG' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------  GPREG_SET_FREEZE_REG  ---------------------------- */
#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos  (0UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_WKUPTIM (Bit 0)                   */
#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk  (0x1UL)                   /*!< GPREG SET_FREEZE_REG: FRZ_WKUPTIM (Bitfield-Mask: 0x01)     */
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Pos   (1UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM0 (Bit 1)                    */
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk   (0x2UL)                   /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM0 (Bitfield-Mask: 0x01)      */
#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Pos   (2UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_BLETIM (Bit 2)                    */
#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Msk   (0x4UL)                   /*!< GPREG SET_FREEZE_REG: FRZ_BLETIM (Bitfield-Mask: 0x01)      */
#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Pos     (3UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_WDOG (Bit 3)                      */
#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk     (0x8UL)                   /*!< GPREG SET_FREEZE_REG: FRZ_WDOG (Bitfield-Mask: 0x01)        */
#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos      (4UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_USB (Bit 4)                       */
#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk      (0x10UL)                  /*!< GPREG SET_FREEZE_REG: FRZ_USB (Bitfield-Mask: 0x01)         */
#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos      (5UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_DMA (Bit 5)                       */
#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk      (0x20UL)                  /*!< GPREG SET_FREEZE_REG: FRZ_DMA (Bitfield-Mask: 0x01)         */
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Pos   (6UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM1 (Bit 6)                    */
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk   (0x40UL)                  /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM1 (Bitfield-Mask: 0x01)      */
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos   (7UL)                     /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM2 (Bit 7)                    */
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk   (0x80UL)                  /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM2 (Bitfield-Mask: 0x01)      */

/* ---------------------------  GPREG_RESET_FREEZE_REG  --------------------------- */
#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)                    /*!< GPREG RESET_FREEZE_REG: FRZ_WKUPTIM (Bit 0)                 */
#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)                  /*!< GPREG RESET_FREEZE_REG: FRZ_WKUPTIM (Bitfield-Mask: 0x01)   */
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Pos (1UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM0 (Bit 1)                  */
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Msk (0x2UL)                   /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM0 (Bitfield-Mask: 0x01)    */
#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Pos (2UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_BLETIM (Bit 2)                  */
#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Msk (0x4UL)                   /*!< GPREG RESET_FREEZE_REG: FRZ_BLETIM (Bitfield-Mask: 0x01)    */
#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Pos   (3UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_WDOG (Bit 3)                    */
#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk   (0x8UL)                   /*!< GPREG RESET_FREEZE_REG: FRZ_WDOG (Bitfield-Mask: 0x01)      */
#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos    (4UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_USB (Bit 4)                     */
#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk    (0x10UL)                  /*!< GPREG RESET_FREEZE_REG: FRZ_USB (Bitfield-Mask: 0x01)       */
#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos    (5UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_DMA (Bit 5)                     */
#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk    (0x20UL)                  /*!< GPREG RESET_FREEZE_REG: FRZ_DMA (Bitfield-Mask: 0x01)       */
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Pos (6UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM1 (Bit 6)                  */
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk (0x40UL)                  /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM1 (Bitfield-Mask: 0x01)    */
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (7UL)                     /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM2 (Bit 7)                  */
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x80UL)                  /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM2 (Bitfield-Mask: 0x01)    */

/* -------------------------------  GPREG_DEBUG_REG  ------------------------------ */
#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Pos  (0UL)                     /*!< GPREG DEBUG_REG: DEBUGS_FREEZE_EN (Bit 0)                   */
#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Msk  (0x1UL)                   /*!< GPREG DEBUG_REG: DEBUGS_FREEZE_EN (Bitfield-Mask: 0x01)     */

/* -----------------------------  GPREG_GP_STATUS_REG  ---------------------------- */
#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos     (0UL)                     /*!< GPREG GP_STATUS_REG: CAL_PHASE (Bit 0)                      */
#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk     (0x1UL)                   /*!< GPREG GP_STATUS_REG: CAL_PHASE (Bitfield-Mask: 0x01)        */

/* ----------------------------  GPREG_GP_CONTROL_REG  ---------------------------- */
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Pos (0UL)                   /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_REQ (Bit 0)                */
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Msk (0x1UL)                 /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_REQ (Bitfield-Mask: 0x01)  */
#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Pos (1UL)            /*!< GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bit 1)         */
#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Msk (0x2UL)          /*!< GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01) */
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Pos (2UL)                /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bit 2)             */
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Msk (0x4UL)              /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bitfield-Mask: 0x01) */

/* ---------------------------  GPREG_ECC_BASE_ADDR_REG  -------------------------- */
#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Pos (0UL)                 /*!< GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bit 0)              */
#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Msk (0x7fUL)              /*!< GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bitfield-Mask: 0x7f) */

/* ----------------------------  GPREG_LED_CONTROL_REG  --------------------------- */
#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Pos (0UL)                    /*!< GPREG LED_CONTROL_REG: LED1_SRC_SEL (Bit 0)                 */
#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Msk (0x1UL)                  /*!< GPREG LED_CONTROL_REG: LED1_SRC_SEL (Bitfield-Mask: 0x01)   */
#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Pos (1UL)                    /*!< GPREG LED_CONTROL_REG: LED2_SRC_SEL (Bit 1)                 */
#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Msk (0x2UL)                  /*!< GPREG LED_CONTROL_REG: LED2_SRC_SEL (Bitfield-Mask: 0x01)   */
#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Pos (2UL)                    /*!< GPREG LED_CONTROL_REG: LED3_SRC_SEL (Bit 2)                 */
#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Msk (0x4UL)                  /*!< GPREG LED_CONTROL_REG: LED3_SRC_SEL (Bitfield-Mask: 0x01)   */
#define GPREG_LED_CONTROL_REG_LED1_EN_Pos     (3UL)                     /*!< GPREG LED_CONTROL_REG: LED1_EN (Bit 3)                      */
#define GPREG_LED_CONTROL_REG_LED1_EN_Msk     (0x8UL)                   /*!< GPREG LED_CONTROL_REG: LED1_EN (Bitfield-Mask: 0x01)        */
#define GPREG_LED_CONTROL_REG_LED2_EN_Pos     (4UL)                     /*!< GPREG LED_CONTROL_REG: LED2_EN (Bit 4)                      */
#define GPREG_LED_CONTROL_REG_LED2_EN_Msk     (0x10UL)                  /*!< GPREG LED_CONTROL_REG: LED2_EN (Bitfield-Mask: 0x01)        */
#define GPREG_LED_CONTROL_REG_LED3_EN_Pos     (5UL)                     /*!< GPREG LED_CONTROL_REG: LED3_EN (Bit 5)                      */
#define GPREG_LED_CONTROL_REG_LED3_EN_Msk     (0x20UL)                  /*!< GPREG LED_CONTROL_REG: LED3_EN (Bitfield-Mask: 0x01)        */
#define GPREG_LED_CONTROL_REG_LED_TRIM_Pos    (6UL)                     /*!< GPREG LED_CONTROL_REG: LED_TRIM (Bit 6)                     */
#define GPREG_LED_CONTROL_REG_LED_TRIM_Msk    (0x3c0UL)                 /*!< GPREG LED_CONTROL_REG: LED_TRIM (Bitfield-Mask: 0x0f)       */

/* -------------------------  GPREG_BLE_FINECNT_SAMP_REG  ------------------------- */
#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Pos (0UL)           /*!< GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bit 0)        */
#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Msk (0x3ffUL)       /*!< GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bitfield-Mask: 0x3ff) */

/* ---------------------------  GPREG_PLL_SYS_CTRL1_REG  -------------------------- */
#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Pos    (0UL)                     /*!< GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bit 0)                     */
#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Msk    (0x1UL)                   /*!< GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bitfield-Mask: 0x01)       */
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos (1UL)                /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_ENABLE (Bit 1)             */
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk (0x2UL)              /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_ENABLE (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos (2UL)             /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_VREF_HOLD (Bit 2)          */
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk (0x4UL)           /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_VREF_HOLD (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Pos (8UL)                     /*!< GPREG PLL_SYS_CTRL1_REG: PLL_R_DIV (Bit 8)                  */
#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Msk (0x7f00UL)                /*!< GPREG PLL_SYS_CTRL1_REG: PLL_R_DIV (Bitfield-Mask: 0x7f)    */

/* ---------------------------  GPREG_PLL_SYS_CTRL2_REG  -------------------------- */
#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Pos (0UL)                     /*!< GPREG PLL_SYS_CTRL2_REG: PLL_N_DIV (Bit 0)                  */
#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Msk (0x7fUL)                  /*!< GPREG PLL_SYS_CTRL2_REG: PLL_N_DIV (Bitfield-Mask: 0x7f)    */
#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Pos (12UL)                  /*!< GPREG PLL_SYS_CTRL2_REG: PLL_DEL_SEL (Bit 12)               */
#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Msk (0x3000UL)              /*!< GPREG PLL_SYS_CTRL2_REG: PLL_DEL_SEL (Bitfield-Mask: 0x03)  */
#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Pos (14UL)          /*!< GPREG PLL_SYS_CTRL2_REG: PLL_SEL_MIN_CUR_INT (Bit 14)       */
#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Msk (0x4000UL)      /*!< GPREG PLL_SYS_CTRL2_REG: PLL_SEL_MIN_CUR_INT (Bitfield-Mask: 0x01) */

/* ---------------------------  GPREG_PLL_SYS_CTRL3_REG  -------------------------- */
#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Pos (0UL)                   /*!< GPREG PLL_SYS_CTRL3_REG: PLL_ICP_SEL (Bit 0)                */
#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Msk (0x1fUL)                /*!< GPREG PLL_SYS_CTRL3_REG: PLL_ICP_SEL (Bitfield-Mask: 0x1f)  */
#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Pos (10UL)                /*!< GPREG PLL_SYS_CTRL3_REG: PLL_START_DEL (Bit 10)             */
#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Msk (0x7c00UL)            /*!< GPREG PLL_SYS_CTRL3_REG: PLL_START_DEL (Bitfield-Mask: 0x1f) */
#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Pos (15UL)                  /*!< GPREG PLL_SYS_CTRL3_REG: PLL_RECALIB (Bit 15)               */
#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Msk (0x8000UL)              /*!< GPREG PLL_SYS_CTRL3_REG: PLL_RECALIB (Bitfield-Mask: 0x01)  */

/* --------------------------  GPREG_PLL_SYS_STATUS_REG  -------------------------- */
#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos (0UL)                /*!< GPREG PLL_SYS_STATUS_REG: PLL_LOCK_FINE (Bit 0)             */
#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk (0x1UL)              /*!< GPREG PLL_SYS_STATUS_REG: PLL_LOCK_FINE (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos (1UL)                   /*!< GPREG PLL_SYS_STATUS_REG: LDO_PLL_OK (Bit 1)                */
#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk (0x2UL)                 /*!< GPREG PLL_SYS_STATUS_REG: LDO_PLL_OK (Bitfield-Mask: 0x01)  */
#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Pos (5UL)         /*!< GPREG PLL_SYS_STATUS_REG: PLL_PLL_BEST_MIN_CUR (Bit 5)      */
#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Msk (0x7e0UL)     /*!< GPREG PLL_SYS_STATUS_REG: PLL_PLL_BEST_MIN_CUR (Bitfield-Mask: 0x3f) */
#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Pos (11UL)              /*!< GPREG PLL_SYS_STATUS_REG: PLL_CALIBR_END (Bit 11)           */
#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Msk (0x800UL)           /*!< GPREG PLL_SYS_STATUS_REG: PLL_CALIBR_END (Bitfield-Mask: 0x01) */

/* ---------------------------  GPREG_PLL_SYS_TEST_REG  --------------------------- */
#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Pos (0UL)               /*!< GPREG PLL_SYS_TEST_REG: PLL_DIS_LOOPFILT (Bit 0)            */
#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Msk (0x1UL)             /*!< GPREG PLL_SYS_TEST_REG: PLL_DIS_LOOPFILT (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Pos (1UL)                /*!< GPREG PLL_SYS_TEST_REG: PLL_MIN_CURRENT (Bit 1)             */
#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Msk (0x7eUL)             /*!< GPREG PLL_SYS_TEST_REG: PLL_MIN_CURRENT (Bitfield-Mask: 0x3f) */
#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Pos (7UL)                  /*!< GPREG PLL_SYS_TEST_REG: PLL_TEST_VCTR (Bit 7)               */
#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Msk (0x80UL)               /*!< GPREG PLL_SYS_TEST_REG: PLL_TEST_VCTR (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Pos (8UL)                  /*!< GPREG PLL_SYS_TEST_REG: PLL_OPEN_LOOP (Bit 8)               */
#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Msk (0x100UL)              /*!< GPREG PLL_SYS_TEST_REG: PLL_OPEN_LOOP (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Pos (9UL)                     /*!< GPREG PLL_SYS_TEST_REG: PLL_CHANGE (Bit 9)                  */
#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Msk (0x200UL)                 /*!< GPREG PLL_SYS_TEST_REG: PLL_CHANGE (Bitfield-Mask: 0x01)    */
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Pos (10UL)            /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_N_DIV_TEST (Bit 10)         */
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Msk (0x400UL)         /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_N_DIV_TEST (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Pos (11UL)            /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_R_DIV_TEST (Bit 11)         */
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Msk (0x800UL)         /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_R_DIV_TEST (Bitfield-Mask: 0x01) */
#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Pos (13UL)          /*!< GPREG PLL_SYS_TEST_REG: PLL_LOCK_DET_RES_CNT (Bit 13)       */
#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Msk (0xe000UL)      /*!< GPREG PLL_SYS_TEST_REG: PLL_LOCK_DET_RES_CNT (Bitfield-Mask: 0x07) */


/* ================================================================================ */
/* ================          struct 'I2C' Position & Mask          ================ */
/* ================================================================================ */


/* -------------------------------  I2C_I2C_CON_REG  ------------------------------ */
#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos   (0UL)                     /*!< I2C I2C_CON_REG: I2C_MASTER_MODE (Bit 0)                    */
#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk   (0x1UL)                   /*!< I2C I2C_CON_REG: I2C_MASTER_MODE (Bitfield-Mask: 0x01)      */
#define I2C_I2C_CON_REG_I2C_SPEED_Pos         (1UL)                     /*!< I2C I2C_CON_REG: I2C_SPEED (Bit 1)                          */
#define I2C_I2C_CON_REG_I2C_SPEED_Msk         (0x6UL)                   /*!< I2C I2C_CON_REG: I2C_SPEED (Bitfield-Mask: 0x03)            */
#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)                   /*!< I2C I2C_CON_REG: I2C_10BITADDR_SLAVE (Bit 3)                */
#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)                 /*!< I2C I2C_CON_REG: I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01)  */
#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)                  /*!< I2C I2C_CON_REG: I2C_10BITADDR_MASTER (Bit 4)               */
#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)               /*!< I2C I2C_CON_REG: I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */
#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos    (5UL)                     /*!< I2C I2C_CON_REG: I2C_RESTART_EN (Bit 5)                     */
#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk    (0x20UL)                  /*!< I2C I2C_CON_REG: I2C_RESTART_EN (Bitfield-Mask: 0x01)       */
#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)                     /*!< I2C I2C_CON_REG: I2C_SLAVE_DISABLE (Bit 6)                  */
#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)                  /*!< I2C I2C_CON_REG: I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)    */

/* -------------------------------  I2C_I2C_TAR_REG  ------------------------------ */
#define I2C_I2C_TAR_REG_IC_TAR_Pos            (0UL)                     /*!< I2C I2C_TAR_REG: IC_TAR (Bit 0)                             */
#define I2C_I2C_TAR_REG_IC_TAR_Msk            (0x3ffUL)                 /*!< I2C I2C_TAR_REG: IC_TAR (Bitfield-Mask: 0x3ff)              */
#define I2C_I2C_TAR_REG_GC_OR_START_Pos       (10UL)                    /*!< I2C I2C_TAR_REG: GC_OR_START (Bit 10)                       */
#define I2C_I2C_TAR_REG_GC_OR_START_Msk       (0x400UL)                 /*!< I2C I2C_TAR_REG: GC_OR_START (Bitfield-Mask: 0x01)          */
#define I2C_I2C_TAR_REG_SPECIAL_Pos           (11UL)                    /*!< I2C I2C_TAR_REG: SPECIAL (Bit 11)                           */
#define I2C_I2C_TAR_REG_SPECIAL_Msk           (0x800UL)                 /*!< I2C I2C_TAR_REG: SPECIAL (Bitfield-Mask: 0x01)              */

/* -------------------------------  I2C_I2C_SAR_REG  ------------------------------ */
#define I2C_I2C_SAR_REG_IC_SAR_Pos            (0UL)                     /*!< I2C I2C_SAR_REG: IC_SAR (Bit 0)                             */
#define I2C_I2C_SAR_REG_IC_SAR_Msk            (0x3ffUL)                 /*!< I2C I2C_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff)              */

/* ----------------------------  I2C_I2C_DATA_CMD_REG  ---------------------------- */
#define I2C_I2C_DATA_CMD_REG_DAT_Pos          (0UL)                     /*!< I2C I2C_DATA_CMD_REG: DAT (Bit 0)                           */
#define I2C_I2C_DATA_CMD_REG_DAT_Msk          (0xffUL)                  /*!< I2C I2C_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff)             */
#define I2C_I2C_DATA_CMD_REG_CMD_Pos          (8UL)                     /*!< I2C I2C_DATA_CMD_REG: CMD (Bit 8)                           */
#define I2C_I2C_DATA_CMD_REG_CMD_Msk          (0x100UL)                 /*!< I2C I2C_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01)             */
#define I2C_I2C_DATA_CMD_REG_STOP_Pos         (9UL)                     /*!< I2C I2C_DATA_CMD_REG: STOP (Bit 9)                          */
#define I2C_I2C_DATA_CMD_REG_STOP_Msk         (0x200UL)                 /*!< I2C I2C_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01)            */
#define I2C_I2C_DATA_CMD_REG_RESTART_Pos      (10UL)                    /*!< I2C I2C_DATA_CMD_REG: RESTART (Bit 10)                      */
#define I2C_I2C_DATA_CMD_REG_RESTART_Msk      (0x400UL)                 /*!< I2C I2C_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01)         */

/* ---------------------------  I2C_I2C_SS_SCL_HCNT_REG  -------------------------- */
#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)                /*!< I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0)             */
#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)           /*!< I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C_I2C_SS_SCL_LCNT_REG  -------------------------- */
#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)                /*!< I2C I2C_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bit 0)             */
#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)           /*!< I2C I2C_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C_I2C_FS_SCL_HCNT_REG  -------------------------- */
#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)                /*!< I2C I2C_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bit 0)             */
#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)           /*!< I2C I2C_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C_I2C_FS_SCL_LCNT_REG  -------------------------- */
#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)                /*!< I2C I2C_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bit 0)             */
#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)           /*!< I2C I2C_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */

/* ----------------------------  I2C_I2C_INTR_STAT_REG  --------------------------- */
#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos  (0UL)                     /*!< I2C I2C_INTR_STAT_REG: R_RX_UNDER (Bit 0)                   */
#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk  (0x1UL)                   /*!< I2C I2C_INTR_STAT_REG: R_RX_UNDER (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos   (1UL)                     /*!< I2C I2C_INTR_STAT_REG: R_RX_OVER (Bit 1)                    */
#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk   (0x2UL)                   /*!< I2C I2C_INTR_STAT_REG: R_RX_OVER (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos   (2UL)                     /*!< I2C I2C_INTR_STAT_REG: R_RX_FULL (Bit 2)                    */
#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk   (0x4UL)                   /*!< I2C I2C_INTR_STAT_REG: R_RX_FULL (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos   (3UL)                     /*!< I2C I2C_INTR_STAT_REG: R_TX_OVER (Bit 3)                    */
#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk   (0x8UL)                   /*!< I2C I2C_INTR_STAT_REG: R_TX_OVER (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos  (4UL)                     /*!< I2C I2C_INTR_STAT_REG: R_TX_EMPTY (Bit 4)                   */
#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk  (0x10UL)                  /*!< I2C I2C_INTR_STAT_REG: R_TX_EMPTY (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos    (5UL)                     /*!< I2C I2C_INTR_STAT_REG: R_RD_REQ (Bit 5)                     */
#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk    (0x20UL)                  /*!< I2C I2C_INTR_STAT_REG: R_RD_REQ (Bitfield-Mask: 0x01)       */
#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos   (6UL)                     /*!< I2C I2C_INTR_STAT_REG: R_TX_ABRT (Bit 6)                    */
#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk   (0x40UL)                  /*!< I2C I2C_INTR_STAT_REG: R_TX_ABRT (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos   (7UL)                     /*!< I2C I2C_INTR_STAT_REG: R_RX_DONE (Bit 7)                    */
#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk   (0x80UL)                  /*!< I2C I2C_INTR_STAT_REG: R_RX_DONE (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos  (8UL)                     /*!< I2C I2C_INTR_STAT_REG: R_ACTIVITY (Bit 8)                   */
#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk  (0x100UL)                 /*!< I2C I2C_INTR_STAT_REG: R_ACTIVITY (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos  (9UL)                     /*!< I2C I2C_INTR_STAT_REG: R_STOP_DET (Bit 9)                   */
#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk  (0x200UL)                 /*!< I2C I2C_INTR_STAT_REG: R_STOP_DET (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL)                    /*!< I2C I2C_INTR_STAT_REG: R_START_DET (Bit 10)                 */
#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL)                 /*!< I2C I2C_INTR_STAT_REG: R_START_DET (Bitfield-Mask: 0x01)    */
#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos  (11UL)                    /*!< I2C I2C_INTR_STAT_REG: R_GEN_CALL (Bit 11)                  */
#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk  (0x800UL)                 /*!< I2C I2C_INTR_STAT_REG: R_GEN_CALL (Bitfield-Mask: 0x01)     */

/* ----------------------------  I2C_I2C_INTR_MASK_REG  --------------------------- */
#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos  (0UL)                     /*!< I2C I2C_INTR_MASK_REG: M_RX_UNDER (Bit 0)                   */
#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk  (0x1UL)                   /*!< I2C I2C_INTR_MASK_REG: M_RX_UNDER (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos   (1UL)                     /*!< I2C I2C_INTR_MASK_REG: M_RX_OVER (Bit 1)                    */
#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk   (0x2UL)                   /*!< I2C I2C_INTR_MASK_REG: M_RX_OVER (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos   (2UL)                     /*!< I2C I2C_INTR_MASK_REG: M_RX_FULL (Bit 2)                    */
#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk   (0x4UL)                   /*!< I2C I2C_INTR_MASK_REG: M_RX_FULL (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos   (3UL)                     /*!< I2C I2C_INTR_MASK_REG: M_TX_OVER (Bit 3)                    */
#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk   (0x8UL)                   /*!< I2C I2C_INTR_MASK_REG: M_TX_OVER (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos  (4UL)                     /*!< I2C I2C_INTR_MASK_REG: M_TX_EMPTY (Bit 4)                   */
#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk  (0x10UL)                  /*!< I2C I2C_INTR_MASK_REG: M_TX_EMPTY (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos    (5UL)                     /*!< I2C I2C_INTR_MASK_REG: M_RD_REQ (Bit 5)                     */
#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk    (0x20UL)                  /*!< I2C I2C_INTR_MASK_REG: M_RD_REQ (Bitfield-Mask: 0x01)       */
#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos   (6UL)                     /*!< I2C I2C_INTR_MASK_REG: M_TX_ABRT (Bit 6)                    */
#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk   (0x40UL)                  /*!< I2C I2C_INTR_MASK_REG: M_TX_ABRT (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos   (7UL)                     /*!< I2C I2C_INTR_MASK_REG: M_RX_DONE (Bit 7)                    */
#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk   (0x80UL)                  /*!< I2C I2C_INTR_MASK_REG: M_RX_DONE (Bitfield-Mask: 0x01)      */
#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos  (8UL)                     /*!< I2C I2C_INTR_MASK_REG: M_ACTIVITY (Bit 8)                   */
#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk  (0x100UL)                 /*!< I2C I2C_INTR_MASK_REG: M_ACTIVITY (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos  (9UL)                     /*!< I2C I2C_INTR_MASK_REG: M_STOP_DET (Bit 9)                   */
#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk  (0x200UL)                 /*!< I2C I2C_INTR_MASK_REG: M_STOP_DET (Bitfield-Mask: 0x01)     */
#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL)                    /*!< I2C I2C_INTR_MASK_REG: M_START_DET (Bit 10)                 */
#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL)                 /*!< I2C I2C_INTR_MASK_REG: M_START_DET (Bitfield-Mask: 0x01)    */
#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos  (11UL)                    /*!< I2C I2C_INTR_MASK_REG: M_GEN_CALL (Bit 11)                  */
#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk  (0x800UL)                 /*!< I2C I2C_INTR_MASK_REG: M_GEN_CALL (Bitfield-Mask: 0x01)     */

/* --------------------------  I2C_I2C_RAW_INTR_STAT_REG  ------------------------- */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)                    /*!< I2C I2C_RAW_INTR_STAT_REG: RX_UNDER (Bit 0)                 */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)                  /*!< I2C I2C_RAW_INTR_STAT_REG: RX_UNDER (Bitfield-Mask: 0x01)   */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)                     /*!< I2C I2C_RAW_INTR_STAT_REG: RX_OVER (Bit 1)                  */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)                   /*!< I2C I2C_RAW_INTR_STAT_REG: RX_OVER (Bitfield-Mask: 0x01)    */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)                     /*!< I2C I2C_RAW_INTR_STAT_REG: RX_FULL (Bit 2)                  */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)                   /*!< I2C I2C_RAW_INTR_STAT_REG: RX_FULL (Bitfield-Mask: 0x01)    */
#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)                     /*!< I2C I2C_RAW_INTR_STAT_REG: TX_OVER (Bit 3)                  */
#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)                   /*!< I2C I2C_RAW_INTR_STAT_REG: TX_OVER (Bitfield-Mask: 0x01)    */
#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)                    /*!< I2C I2C_RAW_INTR_STAT_REG: TX_EMPTY (Bit 4)                 */
#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)                 /*!< I2C I2C_RAW_INTR_STAT_REG: TX_EMPTY (Bitfield-Mask: 0x01)   */
#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos  (5UL)                     /*!< I2C I2C_RAW_INTR_STAT_REG: RD_REQ (Bit 5)                   */
#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk  (0x20UL)                  /*!< I2C I2C_RAW_INTR_STAT_REG: RD_REQ (Bitfield-Mask: 0x01)     */
#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)                     /*!< I2C I2C_RAW_INTR_STAT_REG: TX_ABRT (Bit 6)                  */
#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)                  /*!< I2C I2C_RAW_INTR_STAT_REG: TX_ABRT (Bitfield-Mask: 0x01)    */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)                     /*!< I2C I2C_RAW_INTR_STAT_REG: RX_DONE (Bit 7)                  */
#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)                  /*!< I2C I2C_RAW_INTR_STAT_REG: RX_DONE (Bitfield-Mask: 0x01)    */
#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)                    /*!< I2C I2C_RAW_INTR_STAT_REG: ACTIVITY (Bit 8)                 */
#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)                /*!< I2C I2C_RAW_INTR_STAT_REG: ACTIVITY (Bitfield-Mask: 0x01)   */
#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)                    /*!< I2C I2C_RAW_INTR_STAT_REG: STOP_DET (Bit 9)                 */
#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)                /*!< I2C I2C_RAW_INTR_STAT_REG: STOP_DET (Bitfield-Mask: 0x01)   */
#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL)                  /*!< I2C I2C_RAW_INTR_STAT_REG: START_DET (Bit 10)               */
#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)               /*!< I2C I2C_RAW_INTR_STAT_REG: START_DET (Bitfield-Mask: 0x01)  */
#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)                   /*!< I2C I2C_RAW_INTR_STAT_REG: GEN_CALL (Bit 11)                */
#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)                /*!< I2C I2C_RAW_INTR_STAT_REG: GEN_CALL (Bitfield-Mask: 0x01)   */

/* ------------------------------  I2C_I2C_RX_TL_REG  ----------------------------- */
#define I2C_I2C_RX_TL_REG_RX_TL_Pos           (0UL)                     /*!< I2C I2C_RX_TL_REG: RX_TL (Bit 0)                            */
#define I2C_I2C_RX_TL_REG_RX_TL_Msk           (0x1fUL)                  /*!< I2C I2C_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f)              */

/* ------------------------------  I2C_I2C_TX_TL_REG  ----------------------------- */
#define I2C_I2C_TX_TL_REG_TX_TL_Pos           (0UL)                     /*!< I2C I2C_TX_TL_REG: TX_TL (Bit 0)                            */
#define I2C_I2C_TX_TL_REG_TX_TL_Msk           (0x1fUL)                  /*!< I2C I2C_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f)              */

/* ----------------------------  I2C_I2C_CLR_INTR_REG  ---------------------------- */
#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos     (0UL)                     /*!< I2C I2C_CLR_INTR_REG: CLR_INTR (Bit 0)                      */
#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk     (0x1UL)                   /*!< I2C I2C_CLR_INTR_REG: CLR_INTR (Bitfield-Mask: 0x01)        */

/* --------------------------  I2C_I2C_CLR_RX_UNDER_REG  -------------------------- */
#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)                 /*!< I2C I2C_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bit 0)              */
#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)               /*!< I2C I2C_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bitfield-Mask: 0x01) */

/* ---------------------------  I2C_I2C_CLR_RX_OVER_REG  -------------------------- */
#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)                   /*!< I2C I2C_CLR_RX_OVER_REG: CLR_RX_OVER (Bit 0)                */
#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)                 /*!< I2C I2C_CLR_RX_OVER_REG: CLR_RX_OVER (Bitfield-Mask: 0x01)  */

/* ---------------------------  I2C_I2C_CLR_TX_OVER_REG  -------------------------- */
#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)                   /*!< I2C I2C_CLR_TX_OVER_REG: CLR_TX_OVER (Bit 0)                */
#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)                 /*!< I2C I2C_CLR_TX_OVER_REG: CLR_TX_OVER (Bitfield-Mask: 0x01)  */

/* ---------------------------  I2C_I2C_CLR_RD_REQ_REG  --------------------------- */
#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)                     /*!< I2C I2C_CLR_RD_REQ_REG: CLR_RD_REQ (Bit 0)                  */
#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)                   /*!< I2C I2C_CLR_RD_REQ_REG: CLR_RD_REQ (Bitfield-Mask: 0x01)    */

/* ---------------------------  I2C_I2C_CLR_TX_ABRT_REG  -------------------------- */
#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)                   /*!< I2C I2C_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bit 0)                */
#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)                 /*!< I2C I2C_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bitfield-Mask: 0x01)  */

/* ---------------------------  I2C_I2C_CLR_RX_DONE_REG  -------------------------- */
#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)                   /*!< I2C I2C_CLR_RX_DONE_REG: CLR_RX_DONE (Bit 0)                */
#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)                 /*!< I2C I2C_CLR_RX_DONE_REG: CLR_RX_DONE (Bitfield-Mask: 0x01)  */

/* --------------------------  I2C_I2C_CLR_ACTIVITY_REG  -------------------------- */
#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)                 /*!< I2C I2C_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bit 0)              */
#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)               /*!< I2C I2C_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */

/* --------------------------  I2C_I2C_CLR_STOP_DET_REG  -------------------------- */
#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos (0UL)                 /*!< I2C I2C_CLR_STOP_DET_REG: CLR_ACTIVITY (Bit 0)              */
#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk (0x1UL)               /*!< I2C I2C_CLR_STOP_DET_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */

/* --------------------------  I2C_I2C_CLR_START_DET_REG  ------------------------- */
#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)               /*!< I2C I2C_CLR_START_DET_REG: CLR_START_DET (Bit 0)            */
#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)             /*!< I2C I2C_CLR_START_DET_REG: CLR_START_DET (Bitfield-Mask: 0x01) */

/* --------------------------  I2C_I2C_CLR_GEN_CALL_REG  -------------------------- */
#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)                 /*!< I2C I2C_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bit 0)              */
#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)               /*!< I2C I2C_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bitfield-Mask: 0x01) */

/* -----------------------------  I2C_I2C_ENABLE_REG  ----------------------------- */
#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Pos    (0UL)                     /*!< I2C I2C_ENABLE_REG: CTRL_ENABLE (Bit 0)                     */
#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Msk    (0x1UL)                   /*!< I2C I2C_ENABLE_REG: CTRL_ENABLE (Bitfield-Mask: 0x01)       */

/* -----------------------------  I2C_I2C_STATUS_REG  ----------------------------- */
#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos   (0UL)                     /*!< I2C I2C_STATUS_REG: I2C_ACTIVITY (Bit 0)                    */
#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk   (0x1UL)                   /*!< I2C I2C_STATUS_REG: I2C_ACTIVITY (Bitfield-Mask: 0x01)      */
#define I2C_I2C_STATUS_REG_TFNF_Pos           (1UL)                     /*!< I2C I2C_STATUS_REG: TFNF (Bit 1)                            */
#define I2C_I2C_STATUS_REG_TFNF_Msk           (0x2UL)                   /*!< I2C I2C_STATUS_REG: TFNF (Bitfield-Mask: 0x01)              */
#define I2C_I2C_STATUS_REG_TFE_Pos            (2UL)                     /*!< I2C I2C_STATUS_REG: TFE (Bit 2)                             */
#define I2C_I2C_STATUS_REG_TFE_Msk            (0x4UL)                   /*!< I2C I2C_STATUS_REG: TFE (Bitfield-Mask: 0x01)               */
#define I2C_I2C_STATUS_REG_RFNE_Pos           (3UL)                     /*!< I2C I2C_STATUS_REG: RFNE (Bit 3)                            */
#define I2C_I2C_STATUS_REG_RFNE_Msk           (0x8UL)                   /*!< I2C I2C_STATUS_REG: RFNE (Bitfield-Mask: 0x01)              */
#define I2C_I2C_STATUS_REG_RFF_Pos            (4UL)                     /*!< I2C I2C_STATUS_REG: RFF (Bit 4)                             */
#define I2C_I2C_STATUS_REG_RFF_Msk            (0x10UL)                  /*!< I2C I2C_STATUS_REG: RFF (Bitfield-Mask: 0x01)               */
#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos   (5UL)                     /*!< I2C I2C_STATUS_REG: MST_ACTIVITY (Bit 5)                    */
#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk   (0x20UL)                  /*!< I2C I2C_STATUS_REG: MST_ACTIVITY (Bitfield-Mask: 0x01)      */
#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos   (6UL)                     /*!< I2C I2C_STATUS_REG: SLV_ACTIVITY (Bit 6)                    */
#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk   (0x40UL)                  /*!< I2C I2C_STATUS_REG: SLV_ACTIVITY (Bitfield-Mask: 0x01)      */

/* ------------------------------  I2C_I2C_TXFLR_REG  ----------------------------- */
#define I2C_I2C_TXFLR_REG_TXFLR_Pos           (0UL)                     /*!< I2C I2C_TXFLR_REG: TXFLR (Bit 0)                            */
#define I2C_I2C_TXFLR_REG_TXFLR_Msk           (0x3fUL)                  /*!< I2C I2C_TXFLR_REG: TXFLR (Bitfield-Mask: 0x3f)              */

/* ------------------------------  I2C_I2C_RXFLR_REG  ----------------------------- */
#define I2C_I2C_RXFLR_REG_RXFLR_Pos           (0UL)                     /*!< I2C I2C_RXFLR_REG: RXFLR (Bit 0)                            */
#define I2C_I2C_RXFLR_REG_RXFLR_Msk           (0x3fUL)                  /*!< I2C I2C_RXFLR_REG: RXFLR (Bitfield-Mask: 0x3f)              */

/* ----------------------------  I2C_I2C_SDA_HOLD_REG  ---------------------------- */
#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Pos  (0UL)                     /*!< I2C I2C_SDA_HOLD_REG: IC_SDA_HOLD (Bit 0)                   */
#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Msk  (0xffffUL)                /*!< I2C I2C_SDA_HOLD_REG: IC_SDA_HOLD (Bitfield-Mask: 0xffff)   */

/* -------------------------  I2C_I2C_TX_ABRT_SOURCE_REG  ------------------------- */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)         /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bit 0)      */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL)       /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)         /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bit 1)      */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL)       /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)         /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bit 2)      */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL)       /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)          /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bit 3)       */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)        /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)           /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bit 4)        */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)        /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)            /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bit 5)         */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)         /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)             /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bit 6)          */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)          /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)          /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bit 7)       */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL)       /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)            /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bit 8)         */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)        /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)         /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bit 9)      */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL)     /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL)       /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bit 10)    */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL)    /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)           /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bit 11)        */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)        /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)                  /*!< I2C I2C_TX_ABRT_SOURCE_REG: ARB_LOST (Bit 12)               */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)              /*!< I2C I2C_TX_ABRT_SOURCE_REG: ARB_LOST (Bitfield-Mask: 0x01)  */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL)      /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bit 13)   */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL)  /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)          /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bit 14)       */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL)      /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)           /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bit 15)        */
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL)       /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */

/* -----------------------------  I2C_I2C_DMA_CR_REG  ----------------------------- */
#define I2C_I2C_DMA_CR_REG_RDMAE_Pos          (0UL)                     /*!< I2C I2C_DMA_CR_REG: RDMAE (Bit 0)                           */
#define I2C_I2C_DMA_CR_REG_RDMAE_Msk          (0x1UL)                   /*!< I2C I2C_DMA_CR_REG: RDMAE (Bitfield-Mask: 0x01)             */
#define I2C_I2C_DMA_CR_REG_TDMAE_Pos          (1UL)                     /*!< I2C I2C_DMA_CR_REG: TDMAE (Bit 1)                           */
#define I2C_I2C_DMA_CR_REG_TDMAE_Msk          (0x2UL)                   /*!< I2C I2C_DMA_CR_REG: TDMAE (Bitfield-Mask: 0x01)             */

/* ----------------------------  I2C_I2C_DMA_TDLR_REG  ---------------------------- */
#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos       (0UL)                     /*!< I2C I2C_DMA_TDLR_REG: DMATDL (Bit 0)                        */
#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk       (0x1fUL)                  /*!< I2C I2C_DMA_TDLR_REG: DMATDL (Bitfield-Mask: 0x1f)          */

/* ----------------------------  I2C_I2C_DMA_RDLR_REG  ---------------------------- */
#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos       (0UL)                     /*!< I2C I2C_DMA_RDLR_REG: DMARDL (Bit 0)                        */
#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk       (0x1fUL)                  /*!< I2C I2C_DMA_RDLR_REG: DMARDL (Bitfield-Mask: 0x1f)          */

/* ----------------------------  I2C_I2C_SDA_SETUP_REG  --------------------------- */
#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos   (0UL)                     /*!< I2C I2C_SDA_SETUP_REG: SDA_SETUP (Bit 0)                    */
#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk   (0xffUL)                  /*!< I2C I2C_SDA_SETUP_REG: SDA_SETUP (Bitfield-Mask: 0xff)      */

/* ------------------------  I2C_I2C_ACK_GENERAL_CALL_REG  ------------------------ */
#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)             /*!< I2C I2C_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bit 0)          */
#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)           /*!< I2C I2C_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bitfield-Mask: 0x01) */

/* --------------------------  I2C_I2C_ENABLE_STATUS_REG  ------------------------- */
#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos   (0UL)                     /*!< I2C I2C_ENABLE_STATUS_REG: IC_EN (Bit 0)                    */
#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk   (0x1UL)                   /*!< I2C I2C_ENABLE_STATUS_REG: IC_EN (Bitfield-Mask: 0x01)      */
#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL)     /*!< I2C I2C_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bit 1)  */
#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL)   /*!< I2C I2C_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */
#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)            /*!< I2C I2C_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bit 2)         */
#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)          /*!< I2C I2C_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */

/* --------------------------  I2C_I2C_IC_FS_SPKLEN_REG  -------------------------- */
#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos (0UL)                 /*!< I2C I2C_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bit 0)              */
#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk (0xffUL)              /*!< I2C I2C_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bitfield-Mask: 0xff) */

/* ---------------------------  I2C_I2C_COMP_PARAM1_REG  -------------------------- */
#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos (0UL)                /*!< I2C I2C_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bit 0)             */
#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk (0xffffUL)           /*!< I2C I2C_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C_I2C_COMP_PARAM2_REG  -------------------------- */
#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos (0UL)                /*!< I2C I2C_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bit 0)             */
#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk (0xffffUL)           /*!< I2C I2C_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bitfield-Mask: 0xffff) */

/* --------------------------  I2C_I2C_COMP_VERSION_REG  -------------------------- */
#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Pos (0UL)              /*!< I2C I2C_COMP_VERSION_REG: IC_COMP_VERSION (Bit 0)           */
#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Msk (0xffffUL)         /*!< I2C I2C_COMP_VERSION_REG: IC_COMP_VERSION (Bitfield-Mask: 0xffff) */

/* ----------------------------  I2C_I2C_COMP2_VERSION  --------------------------- */
#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Pos (0UL)                /*!< I2C I2C_COMP2_VERSION: IC_COMP2_VERSION (Bit 0)             */
#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Msk (0xffffUL)           /*!< I2C I2C_COMP2_VERSION: IC_COMP2_VERSION (Bitfield-Mask: 0xffff) */

/* ----------------------------  I2C_I2C_COMP_TYPE_REG  --------------------------- */
#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Pos (0UL)                    /*!< I2C I2C_COMP_TYPE_REG: IC_COMP_TYPE (Bit 0)                 */
#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Msk (0xffffUL)               /*!< I2C I2C_COMP_TYPE_REG: IC_COMP_TYPE (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C_I2C_COMP_TYPE2_REG  --------------------------- */
#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos (0UL)                  /*!< I2C I2C_COMP_TYPE2_REG: IC_COMP2_TYPE (Bit 0)               */
#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk (0xffffUL)             /*!< I2C I2C_COMP_TYPE2_REG: IC_COMP2_TYPE (Bitfield-Mask: 0xffff) */


/* ================================================================================ */
/* ================          struct 'I2C2' Position & Mask         ================ */
/* ================================================================================ */


/* ------------------------------  I2C2_I2C2_CON_REG  ----------------------------- */
#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos (0UL)                     /*!< I2C2 I2C2_CON_REG: I2C_MASTER_MODE (Bit 0)                  */
#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk (0x1UL)                   /*!< I2C2 I2C2_CON_REG: I2C_MASTER_MODE (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos       (1UL)                     /*!< I2C2 I2C2_CON_REG: I2C_SPEED (Bit 1)                        */
#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk       (0x6UL)                   /*!< I2C2 I2C2_CON_REG: I2C_SPEED (Bitfield-Mask: 0x03)          */
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)                 /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_SLAVE (Bit 3)              */
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)               /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)                /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_MASTER (Bit 4)             */
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)             /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos  (5UL)                     /*!< I2C2 I2C2_CON_REG: I2C_RESTART_EN (Bit 5)                   */
#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk  (0x20UL)                  /*!< I2C2 I2C2_CON_REG: I2C_RESTART_EN (Bitfield-Mask: 0x01)     */
#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)                   /*!< I2C2 I2C2_CON_REG: I2C_SLAVE_DISABLE (Bit 6)                */
#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)                /*!< I2C2 I2C2_CON_REG: I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)  */

/* ------------------------------  I2C2_I2C2_TAR_REG  ----------------------------- */
#define I2C2_I2C2_TAR_REG_IC_TAR_Pos          (0UL)                     /*!< I2C2 I2C2_TAR_REG: IC_TAR (Bit 0)                           */
#define I2C2_I2C2_TAR_REG_IC_TAR_Msk          (0x3ffUL)                 /*!< I2C2 I2C2_TAR_REG: IC_TAR (Bitfield-Mask: 0x3ff)            */
#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos     (10UL)                    /*!< I2C2 I2C2_TAR_REG: GC_OR_START (Bit 10)                     */
#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk     (0x400UL)                 /*!< I2C2 I2C2_TAR_REG: GC_OR_START (Bitfield-Mask: 0x01)        */
#define I2C2_I2C2_TAR_REG_SPECIAL_Pos         (11UL)                    /*!< I2C2 I2C2_TAR_REG: SPECIAL (Bit 11)                         */
#define I2C2_I2C2_TAR_REG_SPECIAL_Msk         (0x800UL)                 /*!< I2C2 I2C2_TAR_REG: SPECIAL (Bitfield-Mask: 0x01)            */

/* ------------------------------  I2C2_I2C2_SAR_REG  ----------------------------- */
#define I2C2_I2C2_SAR_REG_IC_SAR_Pos          (0UL)                     /*!< I2C2 I2C2_SAR_REG: IC_SAR (Bit 0)                           */
#define I2C2_I2C2_SAR_REG_IC_SAR_Msk          (0x3ffUL)                 /*!< I2C2 I2C2_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff)            */

/* ---------------------------  I2C2_I2C2_DATA_CMD_REG  --------------------------- */
#define I2C2_I2C2_DATA_CMD_REG_DAT_Pos        (0UL)                     /*!< I2C2 I2C2_DATA_CMD_REG: DAT (Bit 0)                         */
#define I2C2_I2C2_DATA_CMD_REG_DAT_Msk        (0xffUL)                  /*!< I2C2 I2C2_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff)           */
#define I2C2_I2C2_DATA_CMD_REG_CMD_Pos        (8UL)                     /*!< I2C2 I2C2_DATA_CMD_REG: CMD (Bit 8)                         */
#define I2C2_I2C2_DATA_CMD_REG_CMD_Msk        (0x100UL)                 /*!< I2C2 I2C2_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01)           */
#define I2C2_I2C2_DATA_CMD_REG_STOP_Pos       (9UL)                     /*!< I2C2 I2C2_DATA_CMD_REG: STOP (Bit 9)                        */
#define I2C2_I2C2_DATA_CMD_REG_STOP_Msk       (0x200UL)                 /*!< I2C2 I2C2_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01)          */
#define I2C2_I2C2_DATA_CMD_REG_RESTART_Pos    (10UL)                    /*!< I2C2 I2C2_DATA_CMD_REG: RESTART (Bit 10)                    */
#define I2C2_I2C2_DATA_CMD_REG_RESTART_Msk    (0x400UL)                 /*!< I2C2 I2C2_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01)       */

/* --------------------------  I2C2_I2C2_SS_SCL_HCNT_REG  ------------------------- */
#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)              /*!< I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0)           */
#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)         /*!< I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */

/* --------------------------  I2C2_I2C2_SS_SCL_LCNT_REG  ------------------------- */
#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)              /*!< I2C2 I2C2_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bit 0)           */
#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)         /*!< I2C2 I2C2_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */

/* --------------------------  I2C2_I2C2_FS_SCL_HCNT_REG  ------------------------- */
#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)              /*!< I2C2 I2C2_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bit 0)           */
#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)         /*!< I2C2 I2C2_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */

/* --------------------------  I2C2_I2C2_FS_SCL_LCNT_REG  ------------------------- */
#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)              /*!< I2C2 I2C2_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bit 0)           */
#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)         /*!< I2C2 I2C2_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C2_I2C2_INTR_STAT_REG  -------------------------- */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos (0UL)                    /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_UNDER (Bit 0)                 */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL)                  /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_UNDER (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos (1UL)                     /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_OVER (Bit 1)                  */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL)                   /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_OVER (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos (2UL)                     /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_FULL (Bit 2)                  */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL)                   /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_FULL (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos (3UL)                     /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_OVER (Bit 3)                  */
#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL)                   /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_OVER (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL)                    /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_EMPTY (Bit 4)                 */
#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL)                 /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_EMPTY (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos  (5UL)                     /*!< I2C2 I2C2_INTR_STAT_REG: R_RD_REQ (Bit 5)                   */
#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk  (0x20UL)                  /*!< I2C2 I2C2_INTR_STAT_REG: R_RD_REQ (Bitfield-Mask: 0x01)     */
#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos (6UL)                     /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_ABRT (Bit 6)                  */
#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL)                  /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_ABRT (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos (7UL)                     /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_DONE (Bit 7)                  */
#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL)                  /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_DONE (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos (8UL)                    /*!< I2C2 I2C2_INTR_STAT_REG: R_ACTIVITY (Bit 8)                 */
#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL)                /*!< I2C2 I2C2_INTR_STAT_REG: R_ACTIVITY (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos (9UL)                    /*!< I2C2 I2C2_INTR_STAT_REG: R_STOP_DET (Bit 9)                 */
#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL)                /*!< I2C2 I2C2_INTR_STAT_REG: R_STOP_DET (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos (10UL)                  /*!< I2C2 I2C2_INTR_STAT_REG: R_START_DET (Bit 10)               */
#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk (0x400UL)               /*!< I2C2 I2C2_INTR_STAT_REG: R_START_DET (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos (11UL)                   /*!< I2C2 I2C2_INTR_STAT_REG: R_GEN_CALL (Bit 11)                */
#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL)                /*!< I2C2 I2C2_INTR_STAT_REG: R_GEN_CALL (Bitfield-Mask: 0x01)   */

/* ---------------------------  I2C2_I2C2_INTR_MASK_REG  -------------------------- */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos (0UL)                    /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_UNDER (Bit 0)                 */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL)                  /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_UNDER (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos (1UL)                     /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_OVER (Bit 1)                  */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL)                   /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_OVER (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos (2UL)                     /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_FULL (Bit 2)                  */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL)                   /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_FULL (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos (3UL)                     /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_OVER (Bit 3)                  */
#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL)                   /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_OVER (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL)                    /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_EMPTY (Bit 4)                 */
#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL)                 /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_EMPTY (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos  (5UL)                     /*!< I2C2 I2C2_INTR_MASK_REG: M_RD_REQ (Bit 5)                   */
#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk  (0x20UL)                  /*!< I2C2 I2C2_INTR_MASK_REG: M_RD_REQ (Bitfield-Mask: 0x01)     */
#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos (6UL)                     /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_ABRT (Bit 6)                  */
#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL)                  /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_ABRT (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos (7UL)                     /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_DONE (Bit 7)                  */
#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL)                  /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_DONE (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos (8UL)                    /*!< I2C2 I2C2_INTR_MASK_REG: M_ACTIVITY (Bit 8)                 */
#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL)                /*!< I2C2 I2C2_INTR_MASK_REG: M_ACTIVITY (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos (9UL)                    /*!< I2C2 I2C2_INTR_MASK_REG: M_STOP_DET (Bit 9)                 */
#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL)                /*!< I2C2 I2C2_INTR_MASK_REG: M_STOP_DET (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos (10UL)                  /*!< I2C2 I2C2_INTR_MASK_REG: M_START_DET (Bit 10)               */
#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk (0x400UL)               /*!< I2C2 I2C2_INTR_MASK_REG: M_START_DET (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos (11UL)                   /*!< I2C2 I2C2_INTR_MASK_REG: M_GEN_CALL (Bit 11)                */
#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL)                /*!< I2C2 I2C2_INTR_MASK_REG: M_GEN_CALL (Bitfield-Mask: 0x01)   */

/* -------------------------  I2C2_I2C2_RAW_INTR_STAT_REG  ------------------------ */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)                  /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_UNDER (Bit 0)               */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)                /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_UNDER (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)                   /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_OVER (Bit 1)                */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)                 /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_OVER (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)                   /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_FULL (Bit 2)                */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)                 /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_FULL (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)                   /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_OVER (Bit 3)                */
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)                 /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_OVER (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)                  /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_EMPTY (Bit 4)               */
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)               /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_EMPTY (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL)                    /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RD_REQ (Bit 5)                 */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL)                 /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RD_REQ (Bitfield-Mask: 0x01)   */
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)                   /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_ABRT (Bit 6)                */
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)                /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_ABRT (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)                   /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_DONE (Bit 7)                */
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)                /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_DONE (Bitfield-Mask: 0x01)  */
#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)                  /*!< I2C2 I2C2_RAW_INTR_STAT_REG: ACTIVITY (Bit 8)               */
#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)              /*!< I2C2 I2C2_RAW_INTR_STAT_REG: ACTIVITY (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)                  /*!< I2C2 I2C2_RAW_INTR_STAT_REG: STOP_DET (Bit 9)               */
#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)              /*!< I2C2 I2C2_RAW_INTR_STAT_REG: STOP_DET (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos (10UL)                /*!< I2C2 I2C2_RAW_INTR_STAT_REG: START_DET (Bit 10)             */
#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)             /*!< I2C2 I2C2_RAW_INTR_STAT_REG: START_DET (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)                 /*!< I2C2 I2C2_RAW_INTR_STAT_REG: GEN_CALL (Bit 11)              */
#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)              /*!< I2C2 I2C2_RAW_INTR_STAT_REG: GEN_CALL (Bitfield-Mask: 0x01) */

/* -----------------------------  I2C2_I2C2_RX_TL_REG  ---------------------------- */
#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos         (0UL)                     /*!< I2C2 I2C2_RX_TL_REG: RX_TL (Bit 0)                          */
#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk         (0x1fUL)                  /*!< I2C2 I2C2_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f)            */

/* -----------------------------  I2C2_I2C2_TX_TL_REG  ---------------------------- */
#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos         (0UL)                     /*!< I2C2 I2C2_TX_TL_REG: TX_TL (Bit 0)                          */
#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk         (0x1fUL)                  /*!< I2C2 I2C2_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f)            */

/* ---------------------------  I2C2_I2C2_CLR_INTR_REG  --------------------------- */
#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos   (0UL)                     /*!< I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bit 0)                    */
#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk   (0x1UL)                   /*!< I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bitfield-Mask: 0x01)      */

/* -------------------------  I2C2_I2C2_CLR_RX_UNDER_REG  ------------------------- */
#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)               /*!< I2C2 I2C2_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bit 0)            */
#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)             /*!< I2C2 I2C2_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bitfield-Mask: 0x01) */

/* --------------------------  I2C2_I2C2_CLR_RX_OVER_REG  ------------------------- */
#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)                 /*!< I2C2 I2C2_CLR_RX_OVER_REG: CLR_RX_OVER (Bit 0)              */
#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)               /*!< I2C2 I2C2_CLR_RX_OVER_REG: CLR_RX_OVER (Bitfield-Mask: 0x01) */

/* --------------------------  I2C2_I2C2_CLR_TX_OVER_REG  ------------------------- */
#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)                 /*!< I2C2 I2C2_CLR_TX_OVER_REG: CLR_TX_OVER (Bit 0)              */
#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)               /*!< I2C2 I2C2_CLR_TX_OVER_REG: CLR_TX_OVER (Bitfield-Mask: 0x01) */

/* --------------------------  I2C2_I2C2_CLR_RD_REQ_REG  -------------------------- */
#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)                   /*!< I2C2 I2C2_CLR_RD_REQ_REG: CLR_RD_REQ (Bit 0)                */
#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)                 /*!< I2C2 I2C2_CLR_RD_REQ_REG: CLR_RD_REQ (Bitfield-Mask: 0x01)  */

/* --------------------------  I2C2_I2C2_CLR_TX_ABRT_REG  ------------------------- */
#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)                 /*!< I2C2 I2C2_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bit 0)              */
#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)               /*!< I2C2 I2C2_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bitfield-Mask: 0x01) */

/* --------------------------  I2C2_I2C2_CLR_RX_DONE_REG  ------------------------- */
#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)                 /*!< I2C2 I2C2_CLR_RX_DONE_REG: CLR_RX_DONE (Bit 0)              */
#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)               /*!< I2C2 I2C2_CLR_RX_DONE_REG: CLR_RX_DONE (Bitfield-Mask: 0x01) */

/* -------------------------  I2C2_I2C2_CLR_ACTIVITY_REG  ------------------------- */
#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)               /*!< I2C2 I2C2_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bit 0)            */
#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)             /*!< I2C2 I2C2_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */

/* -------------------------  I2C2_I2C2_CLR_STOP_DET_REG  ------------------------- */
#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos (0UL)               /*!< I2C2 I2C2_CLR_STOP_DET_REG: CLR_ACTIVITY (Bit 0)            */
#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk (0x1UL)             /*!< I2C2 I2C2_CLR_STOP_DET_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */

/* -------------------------  I2C2_I2C2_CLR_START_DET_REG  ------------------------ */
#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)             /*!< I2C2 I2C2_CLR_START_DET_REG: CLR_START_DET (Bit 0)          */
#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)           /*!< I2C2 I2C2_CLR_START_DET_REG: CLR_START_DET (Bitfield-Mask: 0x01) */

/* -------------------------  I2C2_I2C2_CLR_GEN_CALL_REG  ------------------------- */
#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)               /*!< I2C2 I2C2_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bit 0)            */
#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)             /*!< I2C2 I2C2_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bitfield-Mask: 0x01) */

/* ----------------------------  I2C2_I2C2_ENABLE_REG  ---------------------------- */
#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Pos  (0UL)                     /*!< I2C2 I2C2_ENABLE_REG: CTRL_ENABLE (Bit 0)                   */
#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Msk  (0x1UL)                   /*!< I2C2 I2C2_ENABLE_REG: CTRL_ENABLE (Bitfield-Mask: 0x01)     */

/* ----------------------------  I2C2_I2C2_STATUS_REG  ---------------------------- */
#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos (0UL)                     /*!< I2C2 I2C2_STATUS_REG: I2C_ACTIVITY (Bit 0)                  */
#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL)                   /*!< I2C2 I2C2_STATUS_REG: I2C_ACTIVITY (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_STATUS_REG_TFNF_Pos         (1UL)                     /*!< I2C2 I2C2_STATUS_REG: TFNF (Bit 1)                          */
#define I2C2_I2C2_STATUS_REG_TFNF_Msk         (0x2UL)                   /*!< I2C2 I2C2_STATUS_REG: TFNF (Bitfield-Mask: 0x01)            */
#define I2C2_I2C2_STATUS_REG_TFE_Pos          (2UL)                     /*!< I2C2 I2C2_STATUS_REG: TFE (Bit 2)                           */
#define I2C2_I2C2_STATUS_REG_TFE_Msk          (0x4UL)                   /*!< I2C2 I2C2_STATUS_REG: TFE (Bitfield-Mask: 0x01)             */
#define I2C2_I2C2_STATUS_REG_RFNE_Pos         (3UL)                     /*!< I2C2 I2C2_STATUS_REG: RFNE (Bit 3)                          */
#define I2C2_I2C2_STATUS_REG_RFNE_Msk         (0x8UL)                   /*!< I2C2 I2C2_STATUS_REG: RFNE (Bitfield-Mask: 0x01)            */
#define I2C2_I2C2_STATUS_REG_RFF_Pos          (4UL)                     /*!< I2C2 I2C2_STATUS_REG: RFF (Bit 4)                           */
#define I2C2_I2C2_STATUS_REG_RFF_Msk          (0x10UL)                  /*!< I2C2 I2C2_STATUS_REG: RFF (Bitfield-Mask: 0x01)             */
#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos (5UL)                     /*!< I2C2 I2C2_STATUS_REG: MST_ACTIVITY (Bit 5)                  */
#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk (0x20UL)                  /*!< I2C2 I2C2_STATUS_REG: MST_ACTIVITY (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos (6UL)                     /*!< I2C2 I2C2_STATUS_REG: SLV_ACTIVITY (Bit 6)                  */
#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL)                  /*!< I2C2 I2C2_STATUS_REG: SLV_ACTIVITY (Bitfield-Mask: 0x01)    */

/* -----------------------------  I2C2_I2C2_TXFLR_REG  ---------------------------- */
#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos         (0UL)                     /*!< I2C2 I2C2_TXFLR_REG: TXFLR (Bit 0)                          */
#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk         (0x3fUL)                  /*!< I2C2 I2C2_TXFLR_REG: TXFLR (Bitfield-Mask: 0x3f)            */

/* -----------------------------  I2C2_I2C2_RXFLR_REG  ---------------------------- */
#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos         (0UL)                     /*!< I2C2 I2C2_RXFLR_REG: RXFLR (Bit 0)                          */
#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk         (0x3fUL)                  /*!< I2C2 I2C2_RXFLR_REG: RXFLR (Bitfield-Mask: 0x3f)            */

/* ---------------------------  I2C2_I2C2_SDA_HOLD_REG  --------------------------- */
#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Pos (0UL)                    /*!< I2C2 I2C2_SDA_HOLD_REG: IC_SDA_HOLD (Bit 0)                 */
#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Msk (0xffffUL)               /*!< I2C2 I2C2_SDA_HOLD_REG: IC_SDA_HOLD (Bitfield-Mask: 0xffff) */

/* ------------------------  I2C2_I2C2_TX_ABRT_SOURCE_REG  ------------------------ */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)       /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bit 0)    */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL)     /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)       /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bit 1)    */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL)     /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)       /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bit 2)    */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL)     /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)        /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bit 3)     */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)      /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)         /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bit 4)      */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)      /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)          /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bit 5)       */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)       /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)           /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bit 6)        */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)        /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)        /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bit 7)     */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL)     /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)          /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bit 8)       */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)      /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)       /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bit 9)    */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL)   /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL)     /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bit 10)  */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL)  /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)         /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bit 11)      */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)      /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)                /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ARB_LOST (Bit 12)             */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)            /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ARB_LOST (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL)    /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bit 13) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)        /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bit 14)     */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL)    /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)         /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bit 15)      */
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL)     /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */

/* ----------------------------  I2C2_I2C2_DMA_CR_REG  ---------------------------- */
#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos        (0UL)                     /*!< I2C2 I2C2_DMA_CR_REG: RDMAE (Bit 0)                         */
#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk        (0x1UL)                   /*!< I2C2 I2C2_DMA_CR_REG: RDMAE (Bitfield-Mask: 0x01)           */
#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos        (1UL)                     /*!< I2C2 I2C2_DMA_CR_REG: TDMAE (Bit 1)                         */
#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk        (0x2UL)                   /*!< I2C2 I2C2_DMA_CR_REG: TDMAE (Bitfield-Mask: 0x01)           */

/* ---------------------------  I2C2_I2C2_DMA_TDLR_REG  --------------------------- */
#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos     (0UL)                     /*!< I2C2 I2C2_DMA_TDLR_REG: DMATDL (Bit 0)                      */
#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk     (0x1fUL)                  /*!< I2C2 I2C2_DMA_TDLR_REG: DMATDL (Bitfield-Mask: 0x1f)        */

/* ---------------------------  I2C2_I2C2_DMA_RDLR_REG  --------------------------- */
#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos     (0UL)                     /*!< I2C2 I2C2_DMA_RDLR_REG: DMARDL (Bit 0)                      */
#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk     (0x1fUL)                  /*!< I2C2 I2C2_DMA_RDLR_REG: DMARDL (Bitfield-Mask: 0x1f)        */

/* ---------------------------  I2C2_I2C2_SDA_SETUP_REG  -------------------------- */
#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos (0UL)                     /*!< I2C2 I2C2_SDA_SETUP_REG: SDA_SETUP (Bit 0)                  */
#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL)                  /*!< I2C2 I2C2_SDA_SETUP_REG: SDA_SETUP (Bitfield-Mask: 0xff)    */

/* -----------------------  I2C2_I2C2_ACK_GENERAL_CALL_REG  ----------------------- */
#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)           /*!< I2C2 I2C2_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bit 0)        */
#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)         /*!< I2C2 I2C2_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bitfield-Mask: 0x01) */

/* -------------------------  I2C2_I2C2_ENABLE_STATUS_REG  ------------------------ */
#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos (0UL)                     /*!< I2C2 I2C2_ENABLE_STATUS_REG: IC_EN (Bit 0)                  */
#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL)                   /*!< I2C2 I2C2_ENABLE_STATUS_REG: IC_EN (Bitfield-Mask: 0x01)    */
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL)   /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bit 1) */
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)          /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bit 2)       */
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)        /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */

/* -------------------------  I2C2_I2C2_IC_FS_SPKLEN_REG  ------------------------- */
#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos (0UL)               /*!< I2C2 I2C2_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bit 0)            */
#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk (0xffUL)            /*!< I2C2 I2C2_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bitfield-Mask: 0xff) */

/* --------------------------  I2C2_I2C2_COMP_PARAM1_REG  ------------------------- */
#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos (0UL)              /*!< I2C2 I2C2_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bit 0)           */
#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk (0xffffUL)         /*!< I2C2 I2C2_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bitfield-Mask: 0xffff) */

/* --------------------------  I2C2_I2C2_COMP_PARAM2_REG  ------------------------- */
#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos (0UL)              /*!< I2C2 I2C2_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bit 0)           */
#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk (0xffffUL)         /*!< I2C2 I2C2_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bitfield-Mask: 0xffff) */

/* -------------------------  I2C2_I2C2_COMP_VERSION_REG  ------------------------- */
#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Pos (0UL)            /*!< I2C2 I2C2_COMP_VERSION_REG: IC_COMP_VERSION (Bit 0)         */
#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Msk (0xffffUL)       /*!< I2C2 I2C2_COMP_VERSION_REG: IC_COMP_VERSION (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C2_I2C2_COMP2_VERSION  -------------------------- */
#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Pos (0UL)              /*!< I2C2 I2C2_COMP2_VERSION: IC_COMP2_VERSION (Bit 0)           */
#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Msk (0xffffUL)         /*!< I2C2 I2C2_COMP2_VERSION: IC_COMP2_VERSION (Bitfield-Mask: 0xffff) */

/* ---------------------------  I2C2_I2C2_COMP_TYPE_REG  -------------------------- */
#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Pos (0UL)                  /*!< I2C2 I2C2_COMP_TYPE_REG: IC_COMP_TYPE (Bit 0)               */
#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Msk (0xffffUL)             /*!< I2C2 I2C2_COMP_TYPE_REG: IC_COMP_TYPE (Bitfield-Mask: 0xffff) */

/* --------------------------  I2C2_I2C2_COMP_TYPE2_REG  -------------------------- */
#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos (0UL)                /*!< I2C2 I2C2_COMP_TYPE2_REG: IC_COMP2_TYPE (Bit 0)             */
#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk (0xffffUL)           /*!< I2C2 I2C2_COMP_TYPE2_REG: IC_COMP2_TYPE (Bitfield-Mask: 0xffff) */


/* ================================================================================ */
/* ================           struct 'IR' Position & Mask          ================ */
/* ================================================================================ */


/* --------------------------  IR_IR_FREQ_CARRIER_ON_REG  ------------------------- */
#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Pos (0UL)          /*!< IR IR_FREQ_CARRIER_ON_REG: IR_FREQ_CARRIER_ON (Bit 0)       */
#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Msk (0x3ffUL)      /*!< IR IR_FREQ_CARRIER_ON_REG: IR_FREQ_CARRIER_ON (Bitfield-Mask: 0x3ff) */

/* -------------------------  IR_IR_FREQ_CARRIER_OFF_REG  ------------------------- */
#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Pos (0UL)        /*!< IR IR_FREQ_CARRIER_OFF_REG: IR_FREQ_CARRIER_OFF (Bit 0)     */
#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Msk (0x3ffUL)    /*!< IR IR_FREQ_CARRIER_OFF_REG: IR_FREQ_CARRIER_OFF (Bitfield-Mask: 0x3ff) */

/* --------------------------  IR_IR_LOGIC_ONE_TIME_REG  -------------------------- */
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Pos (0UL)           /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_SPACE (Bit 0)        */
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Msk (0xffUL)        /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_SPACE (Bitfield-Mask: 0xff) */
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Pos (8UL)            /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_MARK (Bit 8)         */
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Msk (0xff00UL)       /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_MARK (Bitfield-Mask: 0xff) */

/* --------------------------  IR_IR_LOGIC_ZERO_TIME_REG  ------------------------- */
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Pos (0UL)         /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_SPACE (Bit 0)      */
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Msk (0xffUL)      /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_SPACE (Bitfield-Mask: 0xff) */
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Pos (8UL)          /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_MARK (Bit 8)       */
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Msk (0xff00UL)     /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_MARK (Bitfield-Mask: 0xff) */

/* -------------------------------  IR_IR_CTRL_REG  ------------------------------- */
#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Pos (0UL)                     /*!< IR IR_CTRL_REG: IR_CODE_FIFO_RESET (Bit 0)                  */
#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Msk (0x1UL)                   /*!< IR IR_CTRL_REG: IR_CODE_FIFO_RESET (Bitfield-Mask: 0x01)    */
#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Pos  (1UL)                     /*!< IR IR_CTRL_REG: IR_REP_FIFO_RESET (Bit 1)                   */
#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Msk  (0x2UL)                   /*!< IR IR_CTRL_REG: IR_REP_FIFO_RESET (Bitfield-Mask: 0x01)     */
#define IR_IR_CTRL_REG_IR_ENABLE_Pos          (2UL)                     /*!< IR IR_CTRL_REG: IR_ENABLE (Bit 2)                           */
#define IR_IR_CTRL_REG_IR_ENABLE_Msk          (0x4UL)                   /*!< IR IR_CTRL_REG: IR_ENABLE (Bitfield-Mask: 0x01)             */
#define IR_IR_CTRL_REG_IR_TX_START_Pos        (3UL)                     /*!< IR IR_CTRL_REG: IR_TX_START (Bit 3)                         */
#define IR_IR_CTRL_REG_IR_TX_START_Msk        (0x8UL)                   /*!< IR IR_CTRL_REG: IR_TX_START (Bitfield-Mask: 0x01)           */
#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Pos     (4UL)                     /*!< IR IR_CTRL_REG: IR_REPEAT_TYPE (Bit 4)                      */
#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Msk     (0x10UL)                  /*!< IR IR_CTRL_REG: IR_REPEAT_TYPE (Bitfield-Mask: 0x01)        */
#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Pos   (5UL)                     /*!< IR IR_CTRL_REG: IR_INVERT_OUTPUT (Bit 5)                    */
#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Msk   (0x20UL)                  /*!< IR IR_CTRL_REG: IR_INVERT_OUTPUT (Bitfield-Mask: 0x01)      */
#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Pos (6UL)                   /*!< IR IR_CTRL_REG: IR_LOGIC_ZERO_FORMAT (Bit 6)                */
#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Msk (0x40UL)                /*!< IR IR_CTRL_REG: IR_LOGIC_ZERO_FORMAT (Bitfield-Mask: 0x01)  */
#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Pos (7UL)                    /*!< IR IR_CTRL_REG: IR_LOGIC_ONE_FORMAT (Bit 7)                 */
#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Msk (0x80UL)                 /*!< IR IR_CTRL_REG: IR_LOGIC_ONE_FORMAT (Bitfield-Mask: 0x01)   */
#define IR_IR_CTRL_REG_IR_IRQ_EN_Pos          (8UL)                     /*!< IR IR_CTRL_REG: IR_IRQ_EN (Bit 8)                           */
#define IR_IR_CTRL_REG_IR_IRQ_EN_Msk          (0x100UL)                 /*!< IR IR_CTRL_REG: IR_IRQ_EN (Bitfield-Mask: 0x01)             */

/* ------------------------------  IR_IR_STATUS_REG  ------------------------------ */
#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Pos (0UL)                    /*!< IR IR_STATUS_REG: IR_CODE_FIFO_WRDS (Bit 0)                 */
#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Msk (0x3fUL)                 /*!< IR IR_STATUS_REG: IR_CODE_FIFO_WRDS (Bitfield-Mask: 0x3f)   */
#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Pos (6UL)                     /*!< IR IR_STATUS_REG: IR_REP_FIFO_WRDS (Bit 6)                  */
#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Msk (0x3c0UL)                 /*!< IR IR_STATUS_REG: IR_REP_FIFO_WRDS (Bitfield-Mask: 0x0f)    */
#define IR_IR_STATUS_REG_IR_BUSY_Pos          (10UL)                    /*!< IR IR_STATUS_REG: IR_BUSY (Bit 10)                          */
#define IR_IR_STATUS_REG_IR_BUSY_Msk          (0x400UL)                 /*!< IR IR_STATUS_REG: IR_BUSY (Bitfield-Mask: 0x01)             */

/* ----------------------------  IR_IR_REPEAT_TIME_REG  --------------------------- */
#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Pos (0UL)                  /*!< IR IR_REPEAT_TIME_REG: IR_REPEAT_TIME (Bit 0)               */
#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Msk (0xffffUL)             /*!< IR IR_REPEAT_TIME_REG: IR_REPEAT_TIME (Bitfield-Mask: 0xffff) */

/* -----------------------------  IR_IR_MAIN_FIFO_REG  ---------------------------- */
#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Pos (0UL)                 /*!< IR IR_MAIN_FIFO_REG: IR_CODE_FIFO_DATA (Bit 0)              */
#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Msk (0xffffUL)            /*!< IR IR_MAIN_FIFO_REG: IR_CODE_FIFO_DATA (Bitfield-Mask: 0xffff) */

/* ----------------------------  IR_IR_REPEAT_FIFO_REG  --------------------------- */
#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Pos (0UL)             /*!< IR IR_REPEAT_FIFO_REG: IR_REPEAT_FIFO_DATA (Bit 0)          */
#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Msk (0xffffUL)        /*!< IR IR_REPEAT_FIFO_REG: IR_REPEAT_FIFO_DATA (Bitfield-Mask: 0xffff) */

/* ----------------------------  IR_IR_IRQ_STATUS_REG  ---------------------------- */
#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Pos   (0UL)                     /*!< IR IR_IRQ_STATUS_REG: IR_IRQ_ACK (Bit 0)                    */
#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Msk   (0x1UL)                   /*!< IR IR_IRQ_STATUS_REG: IR_IRQ_ACK (Bitfield-Mask: 0x01)      */


/* ================================================================================ */
/* ================         struct 'KBSCAN' Position & Mask        ================ */
/* ================================================================================ */


/* ----------------------------  KBSCAN_KBSCN_CTRL_REG  --------------------------- */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Pos    (0UL)                     /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_EN (Bit 0)                     */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Msk    (0x1UL)                   /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_EN (Bitfield-Mask: 0x01)       */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Pos (1UL)          /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_MESSAGE_MASK (Bit 1)       */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Msk (0x2UL)        /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_MESSAGE_MASK (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Pos (2UL)         /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_INACTIVE_MASK (Bit 2)      */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Msk (0x4UL)       /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_INACTIVE_MASK (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Pos (3UL)             /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_FIFO_MASK (Bit 3)          */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Msk (0x8UL)           /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_FIFO_MASK (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Pos (4UL)             /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_TIME (Bit 4)          */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Msk (0x7f0UL)         /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_TIME (Bitfield-Mask: 0x7f) */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Pos (11UL)              /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_EN (Bit 11)           */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Msk (0x800UL)           /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_EN (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Pos (12UL)                   /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_CLKDIV (Bit 12)                */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Msk (0x3000UL)               /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_CLKDIV (Bitfield-Mask: 0x03)   */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Pos (14UL)               /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_RESET_FIFO (Bit 14)            */
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Msk (0x4000UL)           /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_RESET_FIFO (Bitfield-Mask: 0x01) */

/* ---------------------------  KBSCAN_KBSCN_CTRL2_REG  --------------------------- */
#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Pos (0UL)          /*!< KBSCAN KBSCN_CTRL2_REG: KBSCN_ROW_ACTIVE_TIME (Bit 0)       */
#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Msk (0xffffUL)     /*!< KBSCAN KBSCN_CTRL2_REG: KBSCN_ROW_ACTIVE_TIME (Bitfield-Mask: 0xffff) */

/* ------------------------  KBSCAN_KBSCN_MATRIX_SIZE_REG  ------------------------ */
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Pos (0UL)         /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_ROW (Bit 0)      */
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Msk (0xfUL)       /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_ROW (Bitfield-Mask: 0x0f) */
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Pos (4UL)      /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_COLUMN (Bit 4)   */
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Msk (0x1f0UL)  /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_COLUMN (Bitfield-Mask: 0x1f) */

/* --------------------------  KBSCAN_KBSCN_DEBOUNCE_REG  ------------------------- */
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Pos (0UL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_RELEASE_TIME (Bit 0) */
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Msk (0x3fUL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_RELEASE_TIME (Bitfield-Mask: 0x3f) */
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Pos (6UL)   /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_PRESS_TIME (Bit 6) */
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Msk (0xfc0UL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_PRESS_TIME (Bitfield-Mask: 0x3f) */

/* ---------------------------  KBSCAN_KBSCN_STATUS_REG  -------------------------- */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Pos (0UL)          /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_MES_IRQ_STATUS (Bit 0)       */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Msk (0x1UL)        /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_MES_IRQ_STATUS (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Pos (1UL)     /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_INACTIVE_IRQ_STATUS (Bit 1)  */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Msk (0x2UL)   /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_INACTIVE_IRQ_STATUS (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Pos (2UL)             /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_NUM_MESSAGE (Bit 2)          */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Msk (0x7cUL)          /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_NUM_MESSAGE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Pos (7UL)             /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_OVERFL (Bit 7)          */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Msk (0x80UL)          /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_OVERFL (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Pos (8UL)            /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_UNDERFL (Bit 8)         */
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Msk (0x100UL)        /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_UNDERFL (Bitfield-Mask: 0x01) */

/* ------------------------  KBSCAN_KBSCN_MESSAGE_KEY_REG  ------------------------ */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Pos (0UL)          /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_ROW (Bit 0)       */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Msk (0xfUL)        /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_ROW (Bitfield-Mask: 0x0f) */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Pos (4UL)       /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_COLUMN (Bit 4)    */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Msk (0x1f0UL)   /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_COLUMN (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Pos (9UL)          /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEY_STATE (Bit 9)       */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Msk (0x200UL)      /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEY_STATE (Bitfield-Mask: 0x01) */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Pos (10UL)        /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_LAST_ENTRY (Bit 10)     */
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Msk (0x400UL)     /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_LAST_ENTRY (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P00_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P01_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P02_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P03_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P04_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P05_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P06_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P07_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P10_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P11_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P12_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P13_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P14_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P15_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P16_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P17_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P20_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P21_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P22_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P23_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P24_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P30_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P31_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P32_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P33_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P34_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P35_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P36_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P37_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P40_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P41_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P42_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P43_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P44_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P45_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P46_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */

/* --------------------------  KBSCAN_KBSCN_P47_MODE_REG  ------------------------- */
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Pos (0UL)                  /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_MODE (Bit 0)               */
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Msk (0x1fUL)               /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Pos (5UL)                   /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_ROW (Bit 5)                */
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Msk (0x20UL)                /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)  */
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Pos (6UL)               /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_GPIO_EN (Bit 6)            */
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL)            /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================          struct 'OTPC' Position & Mask         ================ */
/* ================================================================================ */


/* -----------------------------  OTPC_OTPC_MODE_REG  ----------------------------- */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos (0UL)                     /*!< OTPC OTPC_MODE_REG: OTPC_MODE_MODE (Bit 0)                  */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk (0x7UL)                   /*!< OTPC OTPC_MODE_REG: OTPC_MODE_MODE (Bitfield-Mask: 0x07)    */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Pos (4UL)                  /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_DMA (Bit 4)               */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Msk (0x10UL)               /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_DMA (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Pos (5UL)               /*!< OTPC OTPC_MODE_REG: OTPC_MODE_FIFO_FLUSH (Bit 5)            */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Msk (0x20UL)            /*!< OTPC OTPC_MODE_REG: OTPC_MODE_FIFO_FLUSH (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Pos (6UL)             /*!< OTPC OTPC_MODE_REG: OTPC_MODE_ERR_RESP_DIS (Bit 6)          */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Msk (0x40UL)          /*!< OTPC OTPC_MODE_REG: OTPC_MODE_ERR_RESP_DIS (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Pos (8UL)              /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_SP_ROWS (Bit 8)           */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Msk (0x100UL)          /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_SP_ROWS (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Pos (9UL)               /*!< OTPC OTPC_MODE_REG: OTPC_MODE_RLD_RR_REQ (Bit 9)            */
#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Msk (0x200UL)           /*!< OTPC OTPC_MODE_REG: OTPC_MODE_RLD_RR_REQ (Bitfield-Mask: 0x01) */

/* -----------------------------  OTPC_OTPC_PCTRL_REG  ---------------------------- */
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Pos (0UL)                  /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_WADDR (Bit 0)               */
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Msk (0x1fffUL)             /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_WADDR (Bitfield-Mask: 0x1fff) */
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Pos (14UL)                /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PRETRY (Bit 14)             */
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Msk (0x4000UL)            /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PRETRY (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Pos (15UL)                /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PSTART (Bit 15)             */
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Msk (0x8000UL)            /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PSTART (Bitfield-Mask: 0x01) */

/* -----------------------------  OTPC_OTPC_STAT_REG  ----------------------------- */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos (0UL)                     /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PRDY (Bit 0)                  */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk (0x1UL)                   /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PRDY (Bitfield-Mask: 0x01)    */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Pos (1UL)                 /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_UNC (Bit 1)              */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Msk (0x2UL)               /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_UNC (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Pos (2UL)                 /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_COR (Bit 2)              */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Msk (0x4UL)               /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_COR (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Pos (3UL)                    /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PZERO (Bit 3)                 */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Msk (0x8UL)                  /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PZERO (Bitfield-Mask: 0x01)   */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Pos (4UL)                     /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TRDY (Bit 4)                  */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Msk (0x10UL)                  /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TRDY (Bitfield-Mask: 0x01)    */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Pos (5UL)                   /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TERROR (Bit 5)                */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Msk (0x20UL)                /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TERROR (Bitfield-Mask: 0x01)  */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Pos (6UL)                     /*!< OTPC OTPC_STAT_REG: OTPC_STAT_ARDY (Bit 6)                  */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Msk (0x40UL)                  /*!< OTPC OTPC_STAT_REG: OTPC_STAT_ARDY (Bitfield-Mask: 0x01)    */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Pos (7UL)                   /*!< OTPC OTPC_STAT_REG: OTPC_STAT_RERROR (Bit 7)                */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Msk (0x80UL)                /*!< OTPC OTPC_STAT_REG: OTPC_STAT_RERROR (Bitfield-Mask: 0x01)  */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Pos (8UL)                   /*!< OTPC OTPC_STAT_REG: OTPC_STAT_FWORDS (Bit 8)                */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Msk (0xf00UL)               /*!< OTPC OTPC_STAT_REG: OTPC_STAT_FWORDS (Bitfield-Mask: 0x0f)  */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Pos (16UL)                  /*!< OTPC OTPC_STAT_REG: OTPC_STAT_NWORDS (Bit 16)               */
#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Msk (0x3fff0000UL)          /*!< OTPC OTPC_STAT_REG: OTPC_STAT_NWORDS (Bitfield-Mask: 0x3fff) */

/* ----------------------------  OTPC_OTPC_AHBADR_REG  ---------------------------- */
#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Pos  (2UL)                     /*!< OTPC OTPC_AHBADR_REG: OTPC_AHBADR (Bit 2)                   */
#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Msk  (0xfffffffcUL)            /*!< OTPC OTPC_AHBADR_REG: OTPC_AHBADR (Bitfield-Mask: 0x3fffffff) */

/* ----------------------------  OTPC_OTPC_CELADR_REG  ---------------------------- */
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Pos  (0UL)                     /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR (Bit 0)                   */
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Msk  (0x3fffUL)                /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR (Bitfield-Mask: 0x3fff)   */
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Pos (16UL)                  /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bit 16)               */
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Msk (0x3fff0000UL)          /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bitfield-Mask: 0x3fff) */

/* ----------------------------  OTPC_OTPC_NWORDS_REG  ---------------------------- */
#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Pos  (0UL)                     /*!< OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bit 0)                   */
#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Msk  (0x3fffUL)                /*!< OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bitfield-Mask: 0x3fff)   */

/* -----------------------------  OTPC_OTPC_FFPRT_REG  ---------------------------- */
#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Pos    (0UL)                     /*!< OTPC OTPC_FFPRT_REG: OTPC_FFPRT (Bit 0)                     */
#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Msk    (0xffffffffUL)            /*!< OTPC OTPC_FFPRT_REG: OTPC_FFPRT (Bitfield-Mask: 0xffffffff) */

/* -----------------------------  OTPC_OTPC_FFRD_REG  ----------------------------- */
#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Pos      (0UL)                     /*!< OTPC OTPC_FFRD_REG: OTPC_FFRD (Bit 0)                       */
#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Msk      (0xffffffffUL)            /*!< OTPC OTPC_FFRD_REG: OTPC_FFRD (Bitfield-Mask: 0xffffffff)   */

/* ----------------------------  OTPC_OTPC_PWORDL_REG  ---------------------------- */
#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Pos  (0UL)                     /*!< OTPC OTPC_PWORDL_REG: OTPC_PWORDL (Bit 0)                   */
#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Msk  (0xffffffffUL)            /*!< OTPC OTPC_PWORDL_REG: OTPC_PWORDL (Bitfield-Mask: 0xffffffff) */

/* ----------------------------  OTPC_OTPC_PWORDH_REG  ---------------------------- */
#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Pos  (0UL)                     /*!< OTPC OTPC_PWORDH_REG: OTPC_PWORDH (Bit 0)                   */
#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Msk  (0xffffffffUL)            /*!< OTPC OTPC_PWORDH_REG: OTPC_PWORDH (Bitfield-Mask: 0xffffffff) */

/* -----------------------------  OTPC_OTPC_TIM1_REG  ----------------------------- */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos (0UL)                /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_CADX (Bit 0)             */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Msk (0xffUL)             /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_CADX (Bitfield-Mask: 0xff) */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos (8UL)                  /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_PW (Bit 8)               */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Msk (0xff00UL)             /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_PW (Bitfield-Mask: 0xff) */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos (16UL)                /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_1US (Bit 16)             */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk (0x3f0000UL)          /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0x3f) */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos (22UL)              /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_500NS (Bit 22)           */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Msk (0x7c00000UL)       /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_500NS (Bitfield-Mask: 0x1f) */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos (27UL)              /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_200NS (Bit 27)           */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Msk (0x78000000UL)      /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_200NS (Bitfield-Mask: 0x0f) */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos (31UL)               /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_25NS (Bit 31)            */
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Msk (0x80000000UL)       /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_25NS (Bitfield-Mask: 0x01) */

/* -----------------------------  OTPC_OTPC_TIM2_REG  ----------------------------- */
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Pos (0UL)              /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_STBY_THR (Bit 0)           */
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Msk (0x3ffUL)          /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_STBY_THR (Bitfield-Mask: 0x3ff) */
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Pos (16UL)               /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_T_BCHK (Bit 16)            */
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Msk (0x7f0000UL)         /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_T_BCHK (Bitfield-Mask: 0x7f) */
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Pos (23UL)              /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bit 23)           */
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Msk (0x800000UL)        /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bitfield-Mask: 0x01) */

/* -----------------------------  OTPC_OTPC_TEST_REG  ----------------------------- */
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Pos (0UL)                /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bit 0)             */
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Msk (0x1UL)              /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bitfield-Mask: 0x01) */
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Pos (16UL)               /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bit 16)            */
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Msk (0xff0000UL)         /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bitfield-Mask: 0xff) */
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Pos (24UL)                  /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bit 24)               */
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Msk (0x3000000UL)           /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bitfield-Mask: 0x03)  */
#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Pos   (26UL)                    /*!< OTPC OTPC_TEST_REG: OTPC_USED_RR (Bit 26)                   */
#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Msk   (0x4000000UL)             /*!< OTPC OTPC_TEST_REG: OTPC_USED_RR (Bitfield-Mask: 0x01)      */


/* ================================================================================ */
/* ================         struct 'PATCH' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------  PATCH_PATCH_VALID_REG  --------------------------- */
#define PATCH_PATCH_VALID_REG_PATCH_VALID_Pos (0UL)                     /*!< PATCH PATCH_VALID_REG: PATCH_VALID (Bit 0)                  */
#define PATCH_PATCH_VALID_REG_PATCH_VALID_Msk (0xfffffffUL)             /*!< PATCH PATCH_VALID_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff) */

/* --------------------------  PATCH_PATCH_VALID_SET_REG  ------------------------- */
#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Pos (0UL)                 /*!< PATCH PATCH_VALID_SET_REG: PATCH_VALID (Bit 0)              */
#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Msk (0xfffffffUL)         /*!< PATCH PATCH_VALID_SET_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff) */

/* -------------------------  PATCH_PATCH_VALID_RESET_REG  ------------------------ */
#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Pos (0UL)               /*!< PATCH PATCH_VALID_RESET_REG: PATCH_VALID (Bit 0)            */
#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Msk (0xfffffffUL)       /*!< PATCH PATCH_VALID_RESET_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff) */

/* ----------------------------  PATCH_PATCH_ADDR0_REG  --------------------------- */
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR1_REG  --------------------------- */
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR2_REG  --------------------------- */
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR3_REG  --------------------------- */
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR4_REG  --------------------------- */
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR5_REG  --------------------------- */
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR6_REG  --------------------------- */
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR7_REG  --------------------------- */
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR8_REG  --------------------------- */
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ----------------------------  PATCH_PATCH_ADDR9_REG  --------------------------- */
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Pos (1UL)                    /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_C (Bit 1)                 */
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Msk (0x1fffeUL)              /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Pos (19UL)                  /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_19 (Bit 19)               */
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Msk (0x80000UL)             /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)  */

/* ---------------------------  PATCH_PATCH_ADDR10_REG  --------------------------- */
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR11_REG  --------------------------- */
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR12_REG  --------------------------- */
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR13_REG  --------------------------- */
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR14_REG  --------------------------- */
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR15_REG  --------------------------- */
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR16_REG  --------------------------- */
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR17_REG  --------------------------- */
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR18_REG  --------------------------- */
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR19_REG  --------------------------- */
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Pos (1UL)                   /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_C (Bit 1)                */
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Msk (0x1fffeUL)             /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_ADDR20_REG  --------------------------- */
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA20_REG  --------------------------- */
#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA20_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA20_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR21_REG  --------------------------- */
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA21_REG  --------------------------- */
#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA21_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA21_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR22_REG  --------------------------- */
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA22_REG  --------------------------- */
#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA22_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA22_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR23_REG  --------------------------- */
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA23_REG  --------------------------- */
#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA23_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA23_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR24_REG  --------------------------- */
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA24_REG  --------------------------- */
#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA24_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA24_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR25_REG  --------------------------- */
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA25_REG  --------------------------- */
#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA25_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA25_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR26_REG  --------------------------- */
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA26_REG  --------------------------- */
#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA26_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA26_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */

/* ---------------------------  PATCH_PATCH_ADDR27_REG  --------------------------- */
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Pos (2UL)                   /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_D (Bit 2)                */
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Msk (0x1fffcUL)             /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Pos (19UL)                 /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_19 (Bit 19)              */
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Msk (0x80000UL)            /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */

/* ---------------------------  PATCH_PATCH_DATA27_REG  --------------------------- */
#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Pos (0UL)                     /*!< PATCH PATCH_DATA27_REG: PATCH_DATA (Bit 0)                  */
#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Msk (0xffffffffUL)            /*!< PATCH PATCH_DATA27_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */


/* ================================================================================ */
/* ================         struct 'PLLDIG' Position & Mask        ================ */
/* ================================================================================ */


/* ------------------------  PLLDIG_RF_SYNTH_CTRL1_BLE_REG  ----------------------- */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Pos (0UL)            /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CHANNEL_ZERO (Bit 0)         */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Msk (0xfffUL)        /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CHANNEL_ZERO (Bitfield-Mask: 0xfff) */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Pos (12UL)                    /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: SGN (Bit 12)                 */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Msk (0x1000UL)                /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: SGN (Bitfield-Mask: 0x01)    */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Pos  (13UL)                    /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CS (Bit 13)                  */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Msk  (0x2000UL)                /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CS (Bitfield-Mask: 0x01)     */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Pos (14UL)            /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: PLL_HSI_POL (Bit 14)         */
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Msk (0x4000UL)        /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: PLL_HSI_POL (Bitfield-Mask: 0x01) */

/* -----------------------  PLLDIG_RF_SYNTH_CTRL1_FTDF_REG  ----------------------- */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Pos (0UL)           /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CHANNEL_ZERO (Bit 0)        */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Msk (0xfffUL)       /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CHANNEL_ZERO (Bitfield-Mask: 0xfff) */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Pos (12UL)                   /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: SGN (Bit 12)                */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Msk (0x1000UL)               /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: SGN (Bitfield-Mask: 0x01)   */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Pos (13UL)                    /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CS (Bit 13)                 */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Msk (0x2000UL)                /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CS (Bitfield-Mask: 0x01)    */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Pos (14UL)           /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: PLL_HSI_POL (Bit 14)        */
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Msk (0x4000UL)       /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: PLL_HSI_POL (Bitfield-Mask: 0x01) */

/* ------------------------  PLLDIG_RF_SYNTH_CTRL2_BLE_REG  ----------------------- */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Pos (0UL)             /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_RX (Bit 0)          */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Msk (0x3UL)           /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_RX (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Pos (2UL)             /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bit 2)          */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Msk (0xcUL)           /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Pos (4UL)                /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bit 4)             */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Msk (0x30UL)             /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Pos (6UL)             /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bit 6)          */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Msk (0xc0UL)          /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Pos (8UL)               /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bit 8)            */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Msk (0x100UL)           /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Pos (9UL)                /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bit 9)             */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Msk (0x200UL)            /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Pos (10UL)             /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: TXDATA_INV (Bit 10)          */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Msk (0x400UL)          /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: TXDATA_INV (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Pos (11UL)          /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bit 11)       */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Msk (0x800UL)       /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Pos (12UL)                 /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bit 12)              */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Msk (0x1000UL)             /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Pos (13UL)            /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bit 13)         */
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Msk (0x2000UL)        /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bitfield-Mask: 0x01) */

/* -----------------------  PLLDIG_RF_SYNTH_CTRL2_FTDF_REG  ----------------------- */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Pos (0UL)            /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bit 0)         */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Msk (0x3UL)          /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Pos (2UL)            /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bit 2)         */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Msk (0xcUL)          /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Pos (4UL)               /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bit 4)            */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Msk (0x30UL)            /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Pos (6UL)            /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bit 6)         */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Msk (0x40UL)         /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Pos (8UL)              /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bit 8)           */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Msk (0x100UL)          /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Pos (10UL)            /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bit 10)         */
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Msk (0x400UL)         /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bitfield-Mask: 0x01) */

/* --------------------------  PLLDIG_RF_SYNTH_CTRL3_REG  ------------------------- */
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Pos (0UL)                   /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bit 0)                */
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Msk (0x3fffUL)              /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bitfield-Mask: 0x3fff) */
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Pos (14UL)                 /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_SEL (Bit 14)              */
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Msk (0x4000UL)             /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Pos (15UL)                /*!< PLLDIG RF_SYNTH_CTRL3_REG: ZIF_MODE_EN (Bit 15)             */
#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Msk (0x8000UL)            /*!< PLLDIG RF_SYNTH_CTRL3_REG: ZIF_MODE_EN (Bitfield-Mask: 0x01) */

/* --------------------------  PLLDIG_RF_VCOCAL_CTRL_REG  ------------------------- */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Pos (0UL)             /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_WR (Bit 0)          */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Msk (0xfUL)           /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_WR (Bitfield-Mask: 0x0f) */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Pos (4UL)            /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bit 4)         */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Msk (0x30UL)         /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Pos (6UL)               /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bit 6)            */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Msk (0xc0UL)            /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Pos (8UL)     /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bit 8)  */
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Msk (0x100UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bitfield-Mask: 0x01) */

/* ------------------------  PLLDIG_RF_MGAIN_CTRL_BLE_REG  ------------------------ */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Pos (0UL)            /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bit 0)         */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Msk (0xffUL)         /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bitfield-Mask: 0xff) */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Pos (8UL)           /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_SEL (Bit 8)        */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Msk (0x100UL)       /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Pos (9UL)          /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: BLE_TESTPAT_GEN (Bit 9)       */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Msk (0x200UL)      /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: BLE_TESTPAT_GEN (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Pos (10UL)           /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_CMP_INV (Bit 10)        */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Msk (0x400UL)        /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_CMP_INV (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Pos (11UL)              /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_AVER (Bit 11)           */
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Msk (0x1800UL)          /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_AVER (Bitfield-Mask: 0x03) */

/* ------------------------  PLLDIG_RF_MGAIN_CTRL_FTDF_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Pos (0UL)             /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bit 0)          */
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk (0x7fUL)          /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bitfield-Mask: 0x7f) */
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos (7UL)            /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bit 7)         */
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk (0x80UL)         /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Pos (8UL)         /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bit 8)      */
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk (0xff00UL)    /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bitfield-Mask: 0xff) */

/* --------------------------  PLLDIG_RF_MGAIN_CTRL2_REG  ------------------------- */
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Pos (0UL)       /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bit 0)    */
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Msk (0x7fUL)    /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bitfield-Mask: 0x7f) */
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Pos (7UL)              /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bit 7)           */
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Msk (0x80UL)           /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Pos (8UL)            /*!< PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bit 8)         */
#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Msk (0x100UL)        /*!< PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bitfield-Mask: 0x01) */

/* -----------------------  PLLDIG_RF_VCO_CALCAP_BIT14_REG  ----------------------- */
#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Pos (0UL)       /*!< PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bit 0)    */
#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Msk (0xffffUL)  /*!< PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bitfield-Mask: 0xffff) */

/* -----------------------  PLLDIG_RF_VCO_CALCAP_BIT15_REG  ----------------------- */
#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Pos (0UL)       /*!< PLLDIG RF_VCO_CALCAP_BIT15_REG: VCO_CALCAP_BIT15 (Bit 0)    */
#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Msk (0xffffUL)  /*!< PLLDIG RF_VCO_CALCAP_BIT15_REG: VCO_CALCAP_BIT15 (Bitfield-Mask: 0xffff) */

/* -----------------------------  PLLDIG_RF_BMCW_REG  ----------------------------- */
#define PLLDIG_RF_BMCW_REG_CN_WR_Pos          (0UL)                     /*!< PLLDIG RF_BMCW_REG: CN_WR (Bit 0)                           */
#define PLLDIG_RF_BMCW_REG_CN_WR_Msk          (0x3fUL)                  /*!< PLLDIG RF_BMCW_REG: CN_WR (Bitfield-Mask: 0x3f)             */
#define PLLDIG_RF_BMCW_REG_HSI_WR_Pos         (6UL)                     /*!< PLLDIG RF_BMCW_REG: HSI_WR (Bit 6)                          */
#define PLLDIG_RF_BMCW_REG_HSI_WR_Msk         (0x40UL)                  /*!< PLLDIG RF_BMCW_REG: HSI_WR (Bitfield-Mask: 0x01)            */
#define PLLDIG_RF_BMCW_REG_CN_SEL_Pos         (7UL)                     /*!< PLLDIG RF_BMCW_REG: CN_SEL (Bit 7)                          */
#define PLLDIG_RF_BMCW_REG_CN_SEL_Msk         (0x80UL)                  /*!< PLLDIG RF_BMCW_REG: CN_SEL (Bitfield-Mask: 0x01)            */
#define PLLDIG_RF_BMCW_REG_HSI_SEL_Pos        (8UL)                     /*!< PLLDIG RF_BMCW_REG: HSI_SEL (Bit 8)                         */
#define PLLDIG_RF_BMCW_REG_HSI_SEL_Msk        (0x100UL)                 /*!< PLLDIG RF_BMCW_REG: HSI_SEL (Bitfield-Mask: 0x01)           */

/* ------------------------  PLLDIG_RF_KMOD_ALPHA_BLE_REG  ------------------------ */
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Pos (0UL)      /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bit 0)   */
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Msk (0x3fUL)   /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bitfield-Mask: 0x3f) */
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Pos (6UL)         /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bit 6)      */
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Msk (0xfc0UL)     /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bitfield-Mask: 0x3f) */

/* ------------------------  PLLDIG_RF_KMOD_ALPHA_FTDF_REG  ----------------------- */
#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Pos (0UL)         /*!< PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bit 0)      */
#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Msk (0x3fUL)      /*!< PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bitfield-Mask: 0x3f) */

/* -----------------------  PLLDIG_RF_SYNTH_RESULT_BLE_REG  ----------------------- */
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Pos (0UL)      /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bit 0)   */
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Msk (0xffUL)   /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bitfield-Mask: 0xff) */
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Pos (8UL)        /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: VCO_FREQTRIM_RD (Bit 8)     */
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Msk (0xf00UL)    /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: VCO_FREQTRIM_RD (Bitfield-Mask: 0x0f) */

/* -----------------------  PLLDIG_RF_SYNTH_RESULT_FTDF_REG  ---------------------- */
#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Pos (0UL)       /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bit 0)    */
#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk (0x7fUL)    /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bitfield-Mask: 0x7f) */

/* -----------------------  PLLDIG_RF_SYNTH_RESULT2_BLE_REG  ---------------------- */
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Pos (0UL)         /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bit 0)      */
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Msk (0xffUL)      /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bitfield-Mask: 0xff) */
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Pos (8UL)             /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bit 8)          */
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Msk (0x3f00UL)        /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bitfield-Mask: 0x3f) */

/* ----------------------  PLLDIG_RF_SYNTH_RESULT2_FTDF_REG  ---------------------- */
#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Pos (0UL)          /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bit 0)       */
#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Msk (0xffUL)       /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bitfield-Mask: 0xff) */

/* ----------------------  PLLDIG_RF_SYNTH_RESULT3_FTDF_REG  ---------------------- */
#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Pos (0UL)       /*!< PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bit 0)    */
#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Msk (0x3fUL)    /*!< PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bitfield-Mask: 0x3f) */

/* ----------------------------  PLLDIG_RF_CALCAP1_REG  --------------------------- */
#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Pos (0UL)                  /*!< PLLDIG RF_CALCAP1_REG: VCO_CALCAP_LOW (Bit 0)               */
#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Msk (0xffffUL)             /*!< PLLDIG RF_CALCAP1_REG: VCO_CALCAP_LOW (Bitfield-Mask: 0xffff) */

/* ----------------------------  PLLDIG_RF_CALCAP2_REG  --------------------------- */
#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Pos (0UL)                 /*!< PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bit 0)              */
#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Msk (0x3UL)               /*!< PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bitfield-Mask: 0x03) */

/* --------------------------  PLLDIG_RF_NMD_OFFSET_REG  -------------------------- */
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Pos (0UL)           /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bit 0)        */
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Msk (0xffUL)        /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bitfield-Mask: 0xff) */
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Pos (8UL)            /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bit 8)         */
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Msk (0xff00UL)       /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bitfield-Mask: 0xff) */

/* -------------------------  PLLDIG_RF_FTDF_PHYATTR_REG  ------------------------- */
#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Pos (0UL)               /*!< PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bit 0)            */
#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Msk (0xffffUL)          /*!< PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bitfield-Mask: 0xffff) */

/* -------------------------  PLLDIG_RF_CALTRIM_STEP1_REG  ------------------------ */
#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Pos (0UL)                /*!< PLLDIG RF_CALTRIM_STEP1_REG: MDSTATE_RD (Bit 0)             */
#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Msk (0xffffUL)           /*!< PLLDIG RF_CALTRIM_STEP1_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */

/* -------------------------  PLLDIG_RF_CALTRIM_STEP2_REG  ------------------------ */
#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Pos (0UL)                /*!< PLLDIG RF_CALTRIM_STEP2_REG: MDSTATE_RD (Bit 0)             */
#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Msk (0xffffUL)           /*!< PLLDIG RF_CALTRIM_STEP2_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */

/* -------------------------  PLLDIG_RF_CALTRIM_STEP3_REG  ------------------------ */
#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Pos (0UL)                /*!< PLLDIG RF_CALTRIM_STEP3_REG: MDSTATE_RD (Bit 0)             */
#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Msk (0xffffUL)           /*!< PLLDIG RF_CALTRIM_STEP3_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */

/* -------------------------  PLLDIG_RF_CALTRIM_STEP4_REG  ------------------------ */
#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Pos (0UL)                /*!< PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bit 0)             */
#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Msk (0xffffUL)           /*!< PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */

/* --------------------------  PLLDIG_RF_MGAIN_CTRL3_REG  ------------------------- */
#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Pos (0UL)            /*!< PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bit 0)         */
#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Msk (0xffUL)         /*!< PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bitfield-Mask: 0xff) */

/* -------------------------  PLLDIG_RF_VCO_FREQ_EST_REG  ------------------------- */
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Pos (0UL)            /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bit 0)         */
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Msk (0x1UL)          /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Pos (1UL)           /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bit 1)        */
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Msk (0xfeUL)        /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bitfield-Mask: 0x7f) */
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Pos (8UL)      /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bit 8)   */
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Msk (0x700UL)  /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bitfield-Mask: 0x07) */

/* --------------------------  PLLDIG_RF_SYNTH_SPARE_REG  ------------------------- */
#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Pos   (0UL)                     /*!< PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bit 0)                    */
#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Msk   (0xffUL)                  /*!< PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bitfield-Mask: 0xff)      */

/* -------------------------  PLLDIG_RF_MSKMOD_CTRL1_REG  ------------------------- */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Pos (0UL)                    /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bit 0)                 */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Msk (0xfUL)                  /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bitfield-Mask: 0x0f)   */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Pos (4UL)                   /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bit 4)                */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Msk (0x10UL)                /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bitfield-Mask: 0x01)  */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Pos (5UL)                 /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bit 5)              */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Msk (0x20UL)              /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Pos (6UL)                 /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bit 6)              */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Msk (0x40UL)              /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos (7UL)           /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bit 7)        */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk (0x80UL)        /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos (8UL)           /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bit 8)        */
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk (0x100UL)       /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bitfield-Mask: 0x01) */

/* -------------------------  PLLDIG_RF_MSKMOD_CHIPL_REG  ------------------------- */
#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Pos (0UL)                  /*!< PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bit 0)               */
#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Msk (0xffffUL)             /*!< PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bitfield-Mask: 0xffff) */

/* -------------------------  PLLDIG_RF_MSKMOD_CHIPH_REG  ------------------------- */
#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Pos (0UL)                  /*!< PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bit 0)               */
#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Msk (0xffffUL)             /*!< PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bitfield-Mask: 0xffff) */

/* --------------------------  PLLDIG_RF_TXDAC_TEST_REG  -------------------------- */
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Pos (0UL)             /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bit 0)          */
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Msk (0xffUL)          /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bitfield-Mask: 0xff) */
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Pos (8UL)            /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bit 8)         */
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Msk (0x100UL)        /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bitfield-Mask: 0x01) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL0_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL1_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL1_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL1_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL2_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL2_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL2_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL3_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL3_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL3_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL4_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL4_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL4_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL5_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL5_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL5_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL6_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* ------------------------  PLLDIG_RF_MGAIN_COMP_VAL7_REG  ----------------------- */
#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Pos (0UL)          /*!< PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bit 0)       */
#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Msk (0x1fUL)       /*!< PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_0_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_1_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_2_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_3_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_4_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_5_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_6_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_TBL_7_REG  ------------------------- */
#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Pos (0UL)              /*!< PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bit 0)           */
#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Msk (0x7ffUL)          /*!< PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */

/* --------------------------  PLLDIG_RF_PULSE_CTRL_REG  -------------------------- */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Pos (0UL)               /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bit 0)            */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Msk (0x1UL)             /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Pos (1UL)              /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bit 1)           */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Msk (0x6UL)            /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bitfield-Mask: 0x03) */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Pos (3UL)              /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bit 3)           */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Msk (0x8UL)            /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bitfield-Mask: 0x01) */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Pos (4UL)              /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bit 4)           */
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Msk (0xf0UL)           /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bitfield-Mask: 0x0f) */


/* ================================================================================ */
/* ================         struct 'QSPIC' Position & Mask         ================ */
/* ================================================================================ */


/* ---------------------------  QSPIC_QSPIC_CTRLBUS_REG  -------------------------- */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL)              /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_SINGLE (Bit 0)           */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL)            /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL)                /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_DUAL (Bit 1)             */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL)              /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL)                /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_QUAD (Bit 2)             */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL)              /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL)                   /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_EN_CS (Bit 3)                */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL)                 /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_EN_CS (Bitfield-Mask: 0x01)  */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL)                  /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_DIS_CS (Bit 4)               */
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL)               /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_DIS_CS (Bitfield-Mask: 0x01) */

/* --------------------------  QSPIC_QSPIC_CTRLMODE_REG  -------------------------- */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_AUTO_MD (Bit 0)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL)              /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL)                 /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_CLK_MD (Bit 1)              */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL)               /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_CLK_MD (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_OEN (Bit 2)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL)              /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_OEN (Bit 3)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL)              /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_DAT (Bit 4)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL)             /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_DAT (Bit 5)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL)             /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_HRDY_MD (Bit 6)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL)             /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RXD_NEG (Bit 7)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL)             /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL)               /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RPIPE_EN (Bit 8)            */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL)           /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL)                /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_PCLK_MD (Bit 9)             */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL)            /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL)          /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_FORCENSEQ_EN (Bit 12)       */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL)      /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL)              /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_USE_32BA (Bit 13)           */
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL)          /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_USE_32BA (Bitfield-Mask: 0x01) */

/* --------------------------  QSPIC_QSPIC_RECVDATA_REG  -------------------------- */
#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL)               /*!< QSPIC QSPIC_RECVDATA_REG: QSPIC_RECVDATA (Bit 0)            */
#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL)      /*!< QSPIC QSPIC_RECVDATA_REG: QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */

/* --------------------------  QSPIC_QSPIC_BURSTCMDA_REG  ------------------------- */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL)                  /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST (Bit 0)               */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL)               /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL)               /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_WB (Bit 8)            */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL)          /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_WB (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL)             /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_BYTE (Bit 16)          */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL)       /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL)           /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_TX_MD (Bit 24)        */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL)    /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL)            /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_ADR_TX_MD (Bit 26)         */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL)     /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL)            /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_TX_MD (Bit 28)         */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL)    /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL)            /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_DMY_TX_MD (Bit 30)         */
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL)    /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */

/* --------------------------  QSPIC_QSPIC_BURSTCMDB_REG  ------------------------- */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL)             /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DAT_RX_MD (Bit 0)          */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL)           /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL)           /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_BYTE_EN (Bit 2)        */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL)         /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL)             /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_HF_DS (Bit 3)          */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL)           /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL)               /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_NUM (Bit 4)            */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL)            /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL)               /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_INST_MD (Bit 6)            */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL)            /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_INST_MD (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL)               /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_MD (Bit 7)            */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL)            /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL)              /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_LEN (Bit 8)           */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL)          /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL)            /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_SIZE (Bit 10)         */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL)         /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL)          /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_CS_HIGH_MIN (Bit 12)       */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL)      /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL)            /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_FORCE (Bit 15)         */
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL)        /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */

/* ---------------------------  QSPIC_QSPIC_STATUS_REG  --------------------------- */
#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL)                     /*!< QSPIC QSPIC_STATUS_REG: QSPIC_BUSY (Bit 0)                  */
#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL)                   /*!< QSPIC QSPIC_STATUS_REG: QSPIC_BUSY (Bitfield-Mask: 0x01)    */

/* --------------------------  QSPIC_QSPIC_WRITEDATA_REG  ------------------------- */
#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL)             /*!< QSPIC QSPIC_WRITEDATA_REG: QSPIC_WRITEDATA (Bit 0)          */
#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL)    /*!< QSPIC QSPIC_WRITEDATA_REG: QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */

/* --------------------------  QSPIC_QSPIC_READDATA_REG  -------------------------- */
#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL)               /*!< QSPIC QSPIC_READDATA_REG: QSPIC_READDATA (Bit 0)            */
#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL)      /*!< QSPIC QSPIC_READDATA_REG: QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */

/* --------------------------  QSPIC_QSPIC_DUMMYDATA_REG  ------------------------- */
#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL)             /*!< QSPIC QSPIC_DUMMYDATA_REG: QSPIC_DUMMYDATA (Bit 0)          */
#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL)    /*!< QSPIC QSPIC_DUMMYDATA_REG: QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */

/* --------------------------  QSPIC_QSPIC_ERASECTRL_REG  ------------------------- */
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL)              /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_ADDR (Bit 4)           */
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL)       /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL)             /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERASE_EN (Bit 24)          */
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL)      /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL)            /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_STATE (Bit 25)         */
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL)     /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */

/* --------------------------  QSPIC_QSPIC_ERASECMDA_REG  ------------------------- */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL)              /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_ERS_INST (Bit 0)           */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL)           /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_ERS_INST (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL)              /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_WEN_INST (Bit 8)           */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL)         /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_WEN_INST (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL)             /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_SUS_INST (Bit 16)          */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL)       /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_SUS_INST (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL)             /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_RES_INST (Bit 24)          */
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL)     /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_RES_INST (Bitfield-Mask: 0xff) */

/* --------------------------  QSPIC_QSPIC_ERASECMDB_REG  ------------------------- */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL)             /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_TX_MD (Bit 0)          */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL)           /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL)             /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_WEN_TX_MD (Bit 2)          */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL)           /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL)             /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_SUS_TX_MD (Bit 4)          */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL)          /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL)             /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RES_TX_MD (Bit 6)          */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL)          /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL)             /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_EAD_TX_MD (Bit 8)          */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL)         /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL)            /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_CS_HI (Bit 10)         */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL)        /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL)           /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERSRES_HLD (Bit 16)        */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL)      /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL)           /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RESSUS_DLY (Bit 24)        */
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL)   /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */

/* --------------------------  QSPIC_QSPIC_BURSTBRK_REG  -------------------------- */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL)                /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_WRD (Bit 0)             */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL)           /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL)                /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_EN (Bit 16)             */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL)           /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_EN (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL)                /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_SZ (Bit 17)             */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL)           /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL)             /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_TX_MD (Bit 18)          */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL)        /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL)             /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_SEC_HF_DS (Bit 20)          */
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL)       /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */

/* --------------------------  QSPIC_QSPIC_STATUSCMD_REG  ------------------------- */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL)            /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_INST (Bit 0)         */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL)         /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL)           /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_TX_MD (Bit 8)        */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL)       /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL)          /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_RX_MD (Bit 10)       */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL)       /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL)             /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_POS (Bit 12)          */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL)         /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL)             /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_VAL (Bit 15)          */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL)         /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL)           /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RESSTS_DLY (Bit 16)        */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL)     /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL)           /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_STSDLY_SEL (Bit 22)        */
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL)     /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */

/* --------------------------  QSPIC_QSPIC_CHCKERASE_REG  ------------------------- */
#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL)             /*!< QSPIC QSPIC_CHCKERASE_REG: QSPIC_CHCKERASE (Bit 0)          */
#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL)    /*!< QSPIC QSPIC_CHCKERASE_REG: QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */

/* -----------------------------  QSPIC_QSPIC_GP_REG  ----------------------------- */
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL)                     /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_DRV (Bit 1)                  */
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL)                   /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_DRV (Bitfield-Mask: 0x03)    */
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL)                    /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_SLEW (Bit 3)                 */
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL)                 /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_SLEW (Bitfield-Mask: 0x03)   */

/* ---------------------------  QSPIC_QSPIC_UCODE_START  -------------------------- */
#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos (0UL)                 /*!< QSPIC QSPIC_UCODE_START: QSPIC_UCODE_X (Bit 0)              */
#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk (0xffffffffUL)        /*!< QSPIC QSPIC_UCODE_START: QSPIC_UCODE_X (Bitfield-Mask: 0xffffffff) */


/* ================================================================================ */
/* ================          struct 'QUAD' Position & Mask         ================ */
/* ================================================================================ */


/* -----------------------------  QUAD_QDEC_CTRL_REG  ----------------------------- */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Pos    (0UL)                     /*!< QUAD QDEC_CTRL_REG: QD_IRQ_MASK (Bit 0)                     */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Msk    (0x1UL)                   /*!< QUAD QDEC_CTRL_REG: QD_IRQ_MASK (Bitfield-Mask: 0x01)       */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Pos     (1UL)                     /*!< QUAD QDEC_CTRL_REG: QD_IRQ_CLR (Bit 1)                      */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Msk     (0x2UL)                   /*!< QUAD QDEC_CTRL_REG: QD_IRQ_CLR (Bitfield-Mask: 0x01)        */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Pos  (2UL)                     /*!< QUAD QDEC_CTRL_REG: QD_IRQ_STATUS (Bit 2)                   */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Msk  (0x4UL)                   /*!< QUAD QDEC_CTRL_REG: QD_IRQ_STATUS (Bitfield-Mask: 0x01)     */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Pos   (3UL)                     /*!< QUAD QDEC_CTRL_REG: QD_IRQ_THRES (Bit 3)                    */
#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Msk   (0x3f8UL)                 /*!< QUAD QDEC_CTRL_REG: QD_IRQ_THRES (Bitfield-Mask: 0x7f)      */
#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Pos    (10UL)                    /*!< QUAD QDEC_CTRL_REG: CHX_PORT_EN (Bit 10)                    */
#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Msk    (0x400UL)                 /*!< QUAD QDEC_CTRL_REG: CHX_PORT_EN (Bitfield-Mask: 0x01)       */
#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Pos    (11UL)                    /*!< QUAD QDEC_CTRL_REG: CHY_PORT_EN (Bit 11)                    */
#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Msk    (0x800UL)                 /*!< QUAD QDEC_CTRL_REG: CHY_PORT_EN (Bitfield-Mask: 0x01)       */
#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Pos    (12UL)                    /*!< QUAD QDEC_CTRL_REG: CHZ_PORT_EN (Bit 12)                    */
#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Msk    (0x1000UL)                /*!< QUAD QDEC_CTRL_REG: CHZ_PORT_EN (Bitfield-Mask: 0x01)       */

/* -----------------------------  QUAD_QDEC_XCNT_REG  ----------------------------- */
#define QUAD_QDEC_XCNT_REG_X_counter_Pos      (0UL)                     /*!< QUAD QDEC_XCNT_REG: X_counter (Bit 0)                       */
#define QUAD_QDEC_XCNT_REG_X_counter_Msk      (0xffffUL)                /*!< QUAD QDEC_XCNT_REG: X_counter (Bitfield-Mask: 0xffff)       */

/* -----------------------------  QUAD_QDEC_YCNT_REG  ----------------------------- */
#define QUAD_QDEC_YCNT_REG_Y_counter_Pos      (0UL)                     /*!< QUAD QDEC_YCNT_REG: Y_counter (Bit 0)                       */
#define QUAD_QDEC_YCNT_REG_Y_counter_Msk      (0xffffUL)                /*!< QUAD QDEC_YCNT_REG: Y_counter (Bitfield-Mask: 0xffff)       */

/* -----------------------------  QUAD_QDEC_ZCNT_REG  ----------------------------- */
#define QUAD_QDEC_ZCNT_REG_Z_counter_Pos      (0UL)                     /*!< QUAD QDEC_ZCNT_REG: Z_counter (Bit 0)                       */
#define QUAD_QDEC_ZCNT_REG_Z_counter_Msk      (0xffffUL)                /*!< QUAD QDEC_ZCNT_REG: Z_counter (Bitfield-Mask: 0xffff)       */

/* ---------------------------  QUAD_QDEC_CLOCKDIV_REG  --------------------------- */
#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Pos (0UL)                  /*!< QUAD QDEC_CLOCKDIV_REG: clock_divider (Bit 0)               */
#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Msk (0x3ffUL)              /*!< QUAD QDEC_CLOCKDIV_REG: clock_divider (Bitfield-Mask: 0x3ff) */


/* ================================================================================ */
/* ================          struct 'RFCU' Position & Mask         ================ */
/* ================================================================================ */


/* ----------------------------  RFCU_RF_OVERRULE_REG  ---------------------------- */
#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Pos    (0UL)                     /*!< RFCU RF_OVERRULE_REG: TX_EN_OVR (Bit 0)                     */
#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Msk    (0x3UL)                   /*!< RFCU RF_OVERRULE_REG: TX_EN_OVR (Bitfield-Mask: 0x03)       */
#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Pos    (2UL)                     /*!< RFCU RF_OVERRULE_REG: RX_EN_OVR (Bit 2)                     */
#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Msk    (0xcUL)                   /*!< RFCU RF_OVERRULE_REG: RX_EN_OVR (Bitfield-Mask: 0x03)       */
#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Pos  (4UL)                     /*!< RFCU RF_OVERRULE_REG: RF_MODE_OVR (Bit 4)                   */
#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Msk  (0x30UL)                  /*!< RFCU RF_OVERRULE_REG: RF_MODE_OVR (Bitfield-Mask: 0x03)     */
#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Pos (6UL)                     /*!< RFCU RF_OVERRULE_REG: IFF_FTDF_OVR (Bit 6)                  */
#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Msk (0xc0UL)                  /*!< RFCU RF_OVERRULE_REG: IFF_FTDF_OVR (Bitfield-Mask: 0x03)    */
#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Pos (8UL)                     /*!< RFCU RF_OVERRULE_REG: MIX_FTDF_OVR (Bit 8)                  */
#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Msk (0x300UL)                 /*!< RFCU RF_OVERRULE_REG: MIX_FTDF_OVR (Bitfield-Mask: 0x03)    */
#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Pos    (10UL)                    /*!< RFCU RF_OVERRULE_REG: TXDAC_SEL (Bit 10)                    */
#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Msk    (0xc00UL)                 /*!< RFCU RF_OVERRULE_REG: TXDAC_SEL (Bitfield-Mask: 0x03)       */
#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Pos (12UL)                   /*!< RFCU RF_OVERRULE_REG: GAUSS_DAC_SEL (Bit 12)                */
#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Msk (0x3000UL)               /*!< RFCU RF_OVERRULE_REG: GAUSS_DAC_SEL (Bitfield-Mask: 0x03)   */
#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Pos (14UL)                  /*!< RFCU RF_OVERRULE_REG: CN_FTDF_TIMES2 (Bit 14)               */
#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Msk (0x4000UL)              /*!< RFCU RF_OVERRULE_REG: CN_FTDF_TIMES2 (Bitfield-Mask: 0x01)  */

/* ----------------------------  RFCU_RF_DIAGIRQ01_REG  --------------------------- */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Pos (0UL)                  /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_0 (Bit 0)               */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Msk (0x1UL)                /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_0 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Pos (1UL)                  /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_0 (Bit 1)               */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Msk (0x6UL)                /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_0 (Bitfield-Mask: 0x03) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Pos (3UL)                  /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_0 (Bit 3)               */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Msk (0x38UL)               /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_0 (Bitfield-Mask: 0x07) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Pos (6UL)                  /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_0 (Bit 6)               */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Msk (0x40UL)               /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_0 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Pos (8UL)                  /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_1 (Bit 8)               */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Msk (0x100UL)              /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_1 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Pos (9UL)                  /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_1 (Bit 9)               */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Msk (0x600UL)              /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_1 (Bitfield-Mask: 0x03) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Pos (11UL)                 /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_1 (Bit 11)              */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Msk (0x3800UL)             /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_1 (Bitfield-Mask: 0x07) */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Pos (14UL)                 /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_1 (Bit 14)              */
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Msk (0x4000UL)             /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_1 (Bitfield-Mask: 0x01) */

/* ----------------------------  RFCU_RF_DIAGIRQ23_REG  --------------------------- */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Pos (0UL)                  /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_2 (Bit 0)               */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Msk (0x1UL)                /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_2 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Pos (1UL)                  /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_2 (Bit 1)               */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Msk (0x6UL)                /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_2 (Bitfield-Mask: 0x03) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Pos (3UL)                  /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_2 (Bit 3)               */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Msk (0x38UL)               /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_2 (Bitfield-Mask: 0x07) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Pos (6UL)                  /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_2 (Bit 6)               */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Msk (0x40UL)               /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_2 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Pos (8UL)                  /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_3 (Bit 8)               */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Msk (0x100UL)              /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_3 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Pos (9UL)                  /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_3 (Bit 9)               */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Msk (0x600UL)              /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_3 (Bitfield-Mask: 0x03) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Pos (11UL)                 /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_3 (Bit 11)              */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Msk (0x3800UL)             /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_3 (Bitfield-Mask: 0x07) */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Pos (14UL)                 /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_3 (Bit 14)              */
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Msk (0x4000UL)             /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_3 (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_DIAGIRQ_STAT_REG  -------------------------- */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Pos (0UL)               /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_0 (Bit 0)            */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Msk (0x1UL)             /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_0 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Pos (1UL)               /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_1 (Bit 1)            */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Msk (0x2UL)             /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_1 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Pos (2UL)               /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_2 (Bit 2)            */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Msk (0x4UL)             /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_2 (Bitfield-Mask: 0x01) */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Pos (3UL)               /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bit 3)            */
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Msk (0x8UL)             /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_AGC_EXT1_LUT_REG  -------------------------- */
#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Pos (0UL)                  /*!< RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bit 0)               */
#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Msk (0x3ffUL)              /*!< RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bitfield-Mask: 0x3ff) */

/* ----------------------------  RFCU_RF_CALSTATE_REG  ---------------------------- */
#define RFCU_RF_CALSTATE_REG_CALSTATE_Pos     (0UL)                     /*!< RFCU RF_CALSTATE_REG: CALSTATE (Bit 0)                      */
#define RFCU_RF_CALSTATE_REG_CALSTATE_Msk     (0xfUL)                   /*!< RFCU RF_CALSTATE_REG: CALSTATE (Bitfield-Mask: 0x0f)        */

/* --------------------------  RFCU_RF_SCAN_FEEDBACK_REG  ------------------------- */
#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Pos  (0UL)                     /*!< RFCU RF_SCAN_FEEDBACK_REG: LF_RES (Bit 0)                   */
#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Msk  (0xfUL)                   /*!< RFCU RF_SCAN_FEEDBACK_REG: LF_RES (Bitfield-Mask: 0x0f)     */
#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Pos  (4UL)                     /*!< RFCU RF_SCAN_FEEDBACK_REG: CP_CUR (Bit 4)                   */
#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Msk  (0xf0UL)                  /*!< RFCU RF_SCAN_FEEDBACK_REG: CP_CUR (Bitfield-Mask: 0x0f)     */

/* ---------------------------  RFCU_RF_REF_OSC_BLE_REG  -------------------------- */
#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Pos    (0UL)                     /*!< RFCU RF_REF_OSC_BLE_REG: CNT_RO (Bit 0)                     */
#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Msk    (0x3fUL)                  /*!< RFCU RF_REF_OSC_BLE_REG: CNT_RO (Bitfield-Mask: 0x3f)       */
#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Pos   (6UL)                     /*!< RFCU RF_REF_OSC_BLE_REG: CNT_CLK (Bit 6)                    */
#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Msk   (0x7fc0UL)                /*!< RFCU RF_REF_OSC_BLE_REG: CNT_CLK (Bitfield-Mask: 0x1ff)     */

/* --------------------------  RFCU_RF_REF_OSC_FTDF_REG  -------------------------- */
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Pos   (0UL)                     /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_RO (Bit 0)                    */
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Msk   (0x3fUL)                  /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_RO (Bitfield-Mask: 0x3f)      */
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Pos  (6UL)                     /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_CLK (Bit 6)                   */
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Msk  (0x7fc0UL)                /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_CLK (Bitfield-Mask: 0x1ff)    */

/* ----------------------------  RFCU_RF_CAL_CTRL_REG  ---------------------------- */
#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Pos       (0UL)                     /*!< RFCU RF_CAL_CTRL_REG: SO_CAL (Bit 0)                        */
#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Msk       (0x1UL)                   /*!< RFCU RF_CAL_CTRL_REG: SO_CAL (Bitfield-Mask: 0x01)          */
#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Pos       (1UL)                     /*!< RFCU RF_CAL_CTRL_REG: EO_CAL (Bit 1)                        */
#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Msk       (0x2UL)                   /*!< RFCU RF_CAL_CTRL_REG: EO_CAL (Bitfield-Mask: 0x01)          */
#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Pos (2UL)                    /*!< RFCU RF_CAL_CTRL_REG: MGAIN_CAL_DIS (Bit 2)                 */
#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Msk (0x4UL)                  /*!< RFCU RF_CAL_CTRL_REG: MGAIN_CAL_DIS (Bitfield-Mask: 0x01)   */
#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Pos  (3UL)                     /*!< RFCU RF_CAL_CTRL_REG: IFF_CAL_DIS (Bit 3)                   */
#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Msk  (0x8UL)                   /*!< RFCU RF_CAL_CTRL_REG: IFF_CAL_DIS (Bitfield-Mask: 0x01)     */
#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Pos (4UL)                /*!< RFCU RF_CAL_CTRL_REG: DC_OFFSET_CAL_DIS (Bit 4)             */
#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Msk (0x10UL)             /*!< RFCU RF_CAL_CTRL_REG: DC_OFFSET_CAL_DIS (Bitfield-Mask: 0x01) */
#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Pos  (5UL)                     /*!< RFCU RF_CAL_CTRL_REG: VCO_CAL_DIS (Bit 5)                   */
#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Msk  (0x20UL)                  /*!< RFCU RF_CAL_CTRL_REG: VCO_CAL_DIS (Bitfield-Mask: 0x01)     */

/* ----------------------------  RFCU_RF_IRQ_CTRL_REG  ---------------------------- */
#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Pos (0UL)                     /*!< RFCU RF_IRQ_CTRL_REG: EO_CAL_CLEAR (Bit 0)                  */
#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Msk (0x1UL)                   /*!< RFCU RF_IRQ_CTRL_REG: EO_CAL_CLEAR (Bitfield-Mask: 0x01)    */

/* -------------------------  RFCU_RF_ADCI_DC_OFFSET_REG  ------------------------- */
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Pos (0UL)              /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFP_I_RD (Bit 0)           */
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Msk (0xffUL)           /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFP_I_RD (Bitfield-Mask: 0xff) */
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Pos (8UL)              /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFN_I_RD (Bit 8)           */
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Msk (0xff00UL)         /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFN_I_RD (Bitfield-Mask: 0xff) */

/* -------------------------  RFCU_RF_ADCQ_DC_OFFSET_REG  ------------------------- */
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Pos (0UL)              /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFP_Q_RD (Bit 0)           */
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Msk (0xffUL)           /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFP_Q_RD (Bitfield-Mask: 0xff) */
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Pos (8UL)              /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFN_Q_RD (Bit 8)           */
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Msk (0xff00UL)         /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFN_Q_RD (Bitfield-Mask: 0xff) */

/* ---------------------------  RFCU_RF_SPARE1_BLE_REG  --------------------------- */
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Pos (0UL)             /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_RFCLK_TEST (Bit 0)          */
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Msk (0x1UL)           /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_RFCLK_TEST (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos (1UL)       /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bit 1)    */
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk (0x2UL)     /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos (2UL)        /*!< RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2)     */
#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk (0x4UL)      /*!< RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Pos (3UL)           /*!< RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bit 3)        */
#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Msk (0x8UL)         /*!< RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Pos (4UL)                /*!< RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bit 4)             */
#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Msk (0x30UL)             /*!< RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03) */
#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Pos (6UL)                   /*!< RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bit 6)                */
#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Msk (0xffc0UL)              /*!< RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff) */

/* ---------------------------  RFCU_RF_SPARE1_FTDF_REG  -------------------------- */
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Pos (0UL)            /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bit 0)         */
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Msk (0x1UL)          /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos (1UL)      /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bit 1)   */
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk (0x2UL)    /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos (2UL)       /*!< RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2)    */
#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk (0x4UL)     /*!< RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Pos (3UL)          /*!< RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bit 3)       */
#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Msk (0x8UL)        /*!< RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01) */
#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Pos (4UL)               /*!< RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bit 4)            */
#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Msk (0x30UL)            /*!< RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03) */
#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Pos (6UL)                  /*!< RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bit 6)               */
#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Msk (0xffc0UL)             /*!< RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff) */

/* -------------------------  RFCU_RF_BIAS_CTRL1_BLE_REG  ------------------------- */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Pos (0UL)           /*!< RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bit 0)        */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Msk (0xfUL)         /*!< RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Pos (4UL)            /*!< RFCU RF_BIAS_CTRL1_BLE_REG: CP_BIAS_BLE_SET (Bit 4)         */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Msk (0xf0UL)         /*!< RFCU RF_BIAS_CTRL1_BLE_REG: CP_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Pos (8UL)           /*!< RFCU RF_BIAS_CTRL1_BLE_REG: VCO_BIAS_BLE_SET (Bit 8)        */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Msk (0xf00UL)       /*!< RFCU RF_BIAS_CTRL1_BLE_REG: VCO_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Pos (12UL)          /*!< RFCU RF_BIAS_CTRL1_BLE_REG: IFF_BIAS_BLE_SET (Bit 12)       */
#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Msk (0xf000UL)      /*!< RFCU RF_BIAS_CTRL1_BLE_REG: IFF_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */

/* -------------------------  RFCU_RF_BIAS_CTRL1_FTDF_REG  ------------------------ */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Pos (0UL)         /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: MIX_BIAS_FTDF_SET (Bit 0)      */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Msk (0xfUL)       /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: MIX_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Pos (4UL)          /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: CP_BIAS_FTDF_SET (Bit 4)       */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Msk (0xf0UL)       /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: CP_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Pos (8UL)         /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: VCO_BIAS_FTDF_SET (Bit 8)      */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Msk (0xf00UL)     /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: VCO_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Pos (12UL)        /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: IFF_BIAS_FTDF_SET (Bit 12)     */
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Msk (0xf000UL)    /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: IFF_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */

/* ----------------------------  RFCU_RF_IFF_CTRL1_REG  --------------------------- */
#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Pos  (0UL)                     /*!< RFCU RF_IFF_CTRL1_REG: IF_CAL_CAP (Bit 0)                   */
#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Msk  (0x1fUL)                  /*!< RFCU RF_IFF_CTRL1_REG: IF_CAL_CAP (Bitfield-Mask: 0x1f)     */
#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Pos     (5UL)                     /*!< RFCU RF_IFF_CTRL1_REG: IF_MUTE (Bit 5)                      */
#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Msk     (0x20UL)                  /*!< RFCU RF_IFF_CTRL1_REG: IF_MUTE (Bitfield-Mask: 0x01)        */
#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Pos (6UL)                /*!< RFCU RF_IFF_CTRL1_REG: IFF_DCOC_DAC_DIS (Bit 6)             */
#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Msk (0x40UL)             /*!< RFCU RF_IFF_CTRL1_REG: IFF_DCOC_DAC_DIS (Bitfield-Mask: 0x01) */
#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Pos  (7UL)                     /*!< RFCU RF_IFF_CTRL1_REG: RO_TO_PINS (Bit 7)                   */
#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Msk  (0x80UL)                  /*!< RFCU RF_IFF_CTRL1_REG: RO_TO_PINS (Bitfield-Mask: 0x01)     */
#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Pos (8UL)                  /*!< RFCU RF_IFF_CTRL1_REG: IF_SEL_SET2_GT (Bit 8)               */
#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Msk (0xf00UL)              /*!< RFCU RF_IFF_CTRL1_REG: IF_SEL_SET2_GT (Bitfield-Mask: 0x0f) */
#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Pos (12UL)                  /*!< RFCU RF_IFF_CTRL1_REG: IF_SELECT_FSM (Bit 12)               */
#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Msk (0x1000UL)              /*!< RFCU RF_IFF_CTRL1_REG: IF_SELECT_FSM (Bitfield-Mask: 0x01)  */
#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Pos (13UL)                /*!< RFCU RF_IFF_CTRL1_REG: IFF_COMPLEX_DIS (Bit 13)             */
#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Msk (0x2000UL)            /*!< RFCU RF_IFF_CTRL1_REG: IFF_COMPLEX_DIS (Bitfield-Mask: 0x01) */

/* ----------------------------  RFCU_RF_ADC_CTRL1_REG  --------------------------- */
#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Pos (0UL)               /*!< RFCU RF_ADC_CTRL1_REG: ADC_DC_OFFSET_SEL (Bit 0)            */
#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Msk (0x1UL)             /*!< RFCU RF_ADC_CTRL1_REG: ADC_DC_OFFSET_SEL (Bitfield-Mask: 0x01) */
#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Pos    (13UL)                    /*!< RFCU RF_ADC_CTRL1_REG: ADC_MUTE (Bit 13)                    */
#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Msk    (0x2000UL)                /*!< RFCU RF_ADC_CTRL1_REG: ADC_MUTE (Bitfield-Mask: 0x01)       */
#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Pos    (14UL)                    /*!< RFCU RF_ADC_CTRL1_REG: ADC_SIGN (Bit 14)                    */
#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Msk    (0x4000UL)                /*!< RFCU RF_ADC_CTRL1_REG: ADC_SIGN (Bitfield-Mask: 0x01)       */

/* ----------------------------  RFCU_RF_ADC_CTRL2_REG  --------------------------- */
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Pos (0UL)                   /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFP_I_WR (Bit 0)                */
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Msk (0xffUL)                /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFP_I_WR (Bitfield-Mask: 0xff)  */
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Pos (8UL)                   /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFN_I_WR (Bit 8)                */
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Msk (0xff00UL)              /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFN_I_WR (Bitfield-Mask: 0xff)  */

/* ----------------------------  RFCU_RF_ADC_CTRL3_REG  --------------------------- */
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Pos (0UL)                   /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFP_Q_WR (Bit 0)                */
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Msk (0xffUL)                /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFP_Q_WR (Bitfield-Mask: 0xff)  */
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Pos (8UL)                   /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bit 8)                */
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Msk (0xff00UL)              /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bitfield-Mask: 0xff)  */

/* -----------------------------  RFCU_RF_PA_CTRL_REG  ---------------------------- */
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Pos (5UL)                 /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bit 5)              */
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Msk (0x60UL)              /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bitfield-Mask: 0x03) */
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Pos (7UL)                   /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bit 7)                */
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Msk (0x180UL)               /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bitfield-Mask: 0x03)  */
#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Pos (9UL)              /*!< RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bit 9)           */
#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Msk (0x200UL)          /*!< RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bitfield-Mask: 0x01) */
#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Pos (11UL)                   /*!< RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bit 11)                */
#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Msk (0x7800UL)               /*!< RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bitfield-Mask: 0x0f)   */

/* ----------------------------  RFCU_RF_MGC_CTRL_REG  ---------------------------- */
#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Pos (0UL)                     /*!< RFCU RF_MGC_CTRL_REG: MGC_GAIN_SET (Bit 0)                  */
#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Msk (0x1UL)                   /*!< RFCU RF_MGC_CTRL_REG: MGC_GAIN_SET (Bitfield-Mask: 0x01)    */
#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Pos  (1UL)                     /*!< RFCU RF_MGC_CTRL_REG: MGC_POLE_SW (Bit 1)                   */
#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Msk  (0x2UL)                   /*!< RFCU RF_MGC_CTRL_REG: MGC_POLE_SW (Bitfield-Mask: 0x01)     */
#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Pos (2UL)                   /*!< RFCU RF_MGC_CTRL_REG: GAUSS_DAC_CTRL (Bit 2)                */
#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Msk (0xcUL)                 /*!< RFCU RF_MGC_CTRL_REG: GAUSS_DAC_CTRL (Bitfield-Mask: 0x03)  */

/* ---------------------------  RFCU_RF_VCOVAR_CTRL_REG  -------------------------- */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Pos (0UL)                   /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V0 (Bit 0)                */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Msk (0x7UL)                 /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V0 (Bitfield-Mask: 0x07)  */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Pos (3UL)                   /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V1 (Bit 3)                */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Msk (0x38UL)                /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V1 (Bitfield-Mask: 0x07)  */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Pos (6UL)                   /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V2 (Bit 6)                */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Msk (0x1c0UL)               /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V2 (Bitfield-Mask: 0x07)  */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Pos (9UL)                   /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V3 (Bit 9)                */
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Msk (0xe00UL)               /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V3 (Bitfield-Mask: 0x07)  */
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Pos (12UL)                   /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V0 (Bit 12)                */
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Msk (0x3000UL)               /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V0 (Bitfield-Mask: 0x03)   */
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Pos (14UL)                   /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V1 (Bit 14)                */
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Msk (0xc000UL)               /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V1 (Bitfield-Mask: 0x03)   */

/* ----------------------------  RFCU_RF_PFD_CTRL_REG  ---------------------------- */
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Pos (0UL)                    /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_SET (Bit 0)                 */
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Msk (0x3UL)                  /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_SET (Bitfield-Mask: 0x03)   */
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Pos (2UL)                     /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_EN (Bit 2)                  */
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Msk (0x4UL)                   /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_EN (Bitfield-Mask: 0x01)    */
#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Pos (3UL)                     /*!< RFCU RF_PFD_CTRL_REG: PFD_POLARITY (Bit 3)                  */
#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Msk (0x8UL)                   /*!< RFCU RF_PFD_CTRL_REG: PFD_POLARITY (Bitfield-Mask: 0x01)    */

/* ---------------------------  RFCU_RF_CP_CTRL_BLE_REG  -------------------------- */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Pos (0UL)             /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_RX (Bit 0)          */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Msk (0xfUL)           /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Pos (4UL)             /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_TX (Bit 4)          */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Msk (0xf0UL)          /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_TX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Pos (8UL)                 /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_RX (Bit 8)              */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Msk (0xf00UL)             /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Pos (12UL)                /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_TX (Bit 12)             */
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Msk (0xf000UL)            /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_TX (Bitfield-Mask: 0x0f) */

/* --------------------------  RFCU_RF_CP_CTRL_FTDF_REG  -------------------------- */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Pos (0UL)           /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_RX (Bit 0)        */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Msk (0xfUL)         /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Pos (4UL)           /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_TX (Bit 4)        */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Msk (0xf0UL)        /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_TX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Pos (8UL)               /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_RX (Bit 8)            */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Msk (0xf00UL)           /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Pos (12UL)              /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_TX (Bit 12)           */
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Msk (0xf000UL)          /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_TX (Bitfield-Mask: 0x0f) */

/* -------------------------  RFCU_RF_LF_RES_CTRL_BLE_REG  ------------------------ */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Pos (0UL)         /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_RX (Bit 0)      */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Msk (0xfUL)       /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Pos (4UL)         /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_TX (Bit 4)      */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Msk (0xf0UL)      /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_TX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Pos (8UL)             /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_RX (Bit 8)          */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Msk (0xf00UL)         /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Pos (12UL)            /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_TX (Bit 12)         */
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Msk (0xf000UL)        /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_TX (Bitfield-Mask: 0x0f) */

/* ------------------------  RFCU_RF_LF_RES_CTRL_FTDF_REG  ------------------------ */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Pos (0UL)       /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_RX (Bit 0)    */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Msk (0xfUL)     /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Pos (4UL)       /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_TX (Bit 4)    */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Msk (0xf0UL)    /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_TX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Pos (8UL)           /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_RX (Bit 8)        */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Msk (0xf00UL)       /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Pos (12UL)          /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_TX (Bit 12)       */
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Msk (0xf000UL)      /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_TX (Bitfield-Mask: 0x0f) */

/* -------------------------  RFCU_RF_MIXER_CTRL1_BLE_REG  ------------------------ */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Pos (0UL)       /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_GMBIAS_BLE (Bit 0)    */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Msk (0xfUL)     /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_GMBIAS_BLE (Bitfield-Mask: 0x0f) */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Pos (4UL)        /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_IBIAS_BLE (Bit 4)     */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Msk (0xf0UL)     /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_IBIAS_BLE (Bitfield-Mask: 0x0f) */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Pos (8UL)          /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_VCM_BLE (Bit 8)       */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Msk (0xf00UL)      /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_VCM_BLE (Bitfield-Mask: 0x0f) */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Pos (12UL)            /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_SPARE_BLE (Bit 12)         */
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Msk (0xf000UL)        /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_SPARE_BLE (Bitfield-Mask: 0x0f) */

/* ------------------------  RFCU_RF_MIXER_CTRL1_FTDF_REG  ------------------------ */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Pos (0UL)     /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_GMBIAS_FTDF (Bit 0)  */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Msk (0xfUL)   /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_GMBIAS_FTDF (Bitfield-Mask: 0x0f) */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Pos (4UL)      /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_IBIAS_FTDF (Bit 4)   */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Msk (0xf0UL)   /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_IBIAS_FTDF (Bitfield-Mask: 0x0f) */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Pos (8UL)        /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_VCM_FTDF (Bit 8)     */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Msk (0xf00UL)    /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_VCM_FTDF (Bitfield-Mask: 0x0f) */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Pos (12UL)               /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bit 12)            */
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Msk (0xf000UL)           /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bitfield-Mask: 0x0f) */

/* ---------------------------  RFCU_RF_MIXER_CTRL2_REG  -------------------------- */
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Pos (0UL)            /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bit 0)         */
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Msk (0x1fUL)         /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Pos (5UL)                /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bit 5)             */
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Msk (0x20UL)             /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bitfield-Mask: 0x01) */
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Pos (6UL)           /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bit 6)        */
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Msk (0x7c0UL)       /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */

/* -----------------------------  RFCU_RF_LF_CTRL_REG  ---------------------------- */
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Pos (0UL)                 /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bit 0)              */
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Msk (0x1fUL)              /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Pos (5UL)                    /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bit 5)                 */
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Msk (0x20UL)                 /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bitfield-Mask: 0x01)   */
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Pos (6UL)                   /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bit 6)                */
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Msk (0x40UL)                /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bitfield-Mask: 0x01)  */
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Pos (7UL)                  /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bit 7)               */
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Msk (0x80UL)               /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bitfield-Mask: 0x01) */
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Pos (8UL)                /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bit 8)             */
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Msk (0x1f00UL)           /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */

/* ----------------------------  RFCU_RF_TDC_CTRL_REG  ---------------------------- */
#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Pos    (0UL)                     /*!< RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bit 0)                     */
#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Msk    (0xfUL)                   /*!< RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bitfield-Mask: 0x0f)       */
#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Pos    (4UL)                     /*!< RFCU RF_TDC_CTRL_REG: CTRL_SLOW (Bit 4)                     */
#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Msk    (0xf0UL)                  /*!< RFCU RF_TDC_CTRL_REG: CTRL_SLOW (Bitfield-Mask: 0x0f)       */
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Pos     (8UL)                     /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_1 (Bit 8)                      */
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Msk     (0x100UL)                 /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_1 (Bitfield-Mask: 0x01)        */
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Pos     (9UL)                     /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_2 (Bit 9)                      */
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Msk     (0x200UL)                 /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_2 (Bitfield-Mask: 0x01)        */
#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Pos     (10UL)                    /*!< RFCU RF_TDC_CTRL_REG: REF_CTRL (Bit 10)                     */
#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Msk     (0xc00UL)                 /*!< RFCU RF_TDC_CTRL_REG: REF_CTRL (Bitfield-Mask: 0x03)        */
#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Pos  (12UL)                    /*!< RFCU RF_TDC_CTRL_REG: TDC_CONNECT (Bit 12)                  */
#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Msk  (0x1000UL)                /*!< RFCU RF_TDC_CTRL_REG: TDC_CONNECT (Bitfield-Mask: 0x01)     */

/* ----------------------------  RFCU_RF_IO_CTRL1_REG  ---------------------------- */
#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Pos (0UL)                   /*!< RFCU RF_IO_CTRL1_REG: RFIO_TRIM1_CAP (Bit 0)                */
#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Msk (0xffUL)                /*!< RFCU RF_IO_CTRL1_REG: RFIO_TRIM1_CAP (Bitfield-Mask: 0xff)  */

/* ----------------------------  RFCU_RF_LNA_CTRL1_REG  --------------------------- */
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Pos (0UL)                  /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_LF (Bit 0)               */
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Msk (0x3fUL)               /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_LF (Bitfield-Mask: 0x3f) */
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Pos (6UL)                  /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_HF (Bit 6)               */
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Msk (0xfc0UL)              /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_HF (Bitfield-Mask: 0x3f) */

/* ----------------------------  RFCU_RF_LNA_CTRL2_REG  --------------------------- */
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Pos (0UL)                  /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_HI (Bit 0)               */
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Msk (0x3fUL)               /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_HI (Bitfield-Mask: 0x3f) */
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Pos (6UL)                  /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_LO (Bit 6)               */
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Msk (0xfc0UL)              /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_LO (Bitfield-Mask: 0x3f) */

/* ----------------------------  RFCU_RF_LNA_CTRL3_REG  --------------------------- */
#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Pos (0UL)                    /*!< RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bit 0)                 */
#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Msk (0x1fUL)                 /*!< RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bitfield-Mask: 0x1f)   */

/* --------------------------  RFCU_RF_VCO_AMP_CTRL1_REG  ------------------------- */
#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Pos (0UL)               /*!< RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bit 0)            */
#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Msk (0x7fUL)            /*!< RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bitfield-Mask: 0x7f) */

/* --------------------------  RFCU_RF_VCO_AMP_CTRL2_REG  ------------------------- */
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Pos (0UL)             /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bit 0)          */
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Msk (0xffUL)          /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bitfield-Mask: 0xff) */
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Pos (8UL)             /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bit 8)          */
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Msk (0xff00UL)        /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bitfield-Mask: 0xff) */

/* ---------------------------  RFCU_RF_TX_PWR_BLE_REG  --------------------------- */
#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Pos (0UL)                   /*!< RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bit 0)                */
#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Msk (0x7UL)                 /*!< RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bitfield-Mask: 0x07)  */

/* --------------------------  RFCU_RF_TX_PWR_LUT_1_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_2_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_3_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_4_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_5_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_6_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_7_REG  -------------------------- */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL)       /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)    */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL)     /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL)        /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)     */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL)     /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL)      /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)   */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL)  /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL)    /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */

/* ---------------------------  RFCU_RF_TX_PWR_FTDF_REG  -------------------------- */
#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Pos (0UL)                  /*!< RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bit 0)               */
#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Msk (0x7UL)                /*!< RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bitfield-Mask: 0x07) */

/* --------------------------  RFCU_RF_TX_PWR_LUT_RD_REG  ------------------------- */
#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Pos (0UL)            /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bit 0)         */
#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk (0xfffUL)        /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bitfield-Mask: 0xfff) */

/* ----------------------------  RFCU_RF_DIV_IQ_RX_REG  --------------------------- */
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Pos (0UL)               /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bit 0)            */
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Msk (0xfUL)             /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Pos (4UL)               /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFP_TRIM_RX (Bit 4)            */
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Msk (0xf0UL)            /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFP_TRIM_RX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Pos (8UL)           /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_IQ_TRIM_RX_SPARE (Bit 8)        */
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Msk (0x100UL)       /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_IQ_TRIM_RX_SPARE (Bitfield-Mask: 0x01) */

/* ----------------------------  RFCU_RF_DIV_IQ_TX_REG  --------------------------- */
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Pos (0UL)               /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFN_TRIM_TX (Bit 0)            */
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Msk (0xfUL)             /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFN_TRIM_TX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Pos (4UL)               /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFP_TRIM_TX (Bit 4)            */
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Msk (0xf0UL)            /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFP_TRIM_TX (Bitfield-Mask: 0x0f) */
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Pos (8UL)           /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_IQ_TRIM_TX_SPARE (Bit 8)        */
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Msk (0x100UL)       /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_IQ_TRIM_TX_SPARE (Bitfield-Mask: 0x01) */

/* ---------------------------  RFCU_RF_LO_IQ_TRIM_REG  --------------------------- */
#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Pos (0UL)                  /*!< RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bit 0)               */
#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Msk (0xffffUL)             /*!< RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bitfield-Mask: 0xffff) */

/* ---------------------------  RFCU_RF_TXDAC_CTRL_REG  --------------------------- */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Pos (0UL)           /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bit 0)        */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Msk (0x1fUL)        /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Pos (5UL)              /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bit 5)           */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Msk (0x20UL)           /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bitfield-Mask: 0x01) */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Pos (6UL)             /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bit 6)          */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Msk (0x40UL)          /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bitfield-Mask: 0x01) */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Pos (7UL)          /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bit 7)       */
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Msk (0xf80UL)      /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */

/* -----------------------  RFCU_RF_TXDAC_CAL_CAP_STAT_REG  ----------------------- */
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Pos (0UL)       /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bit 0)    */
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Msk (0x1fUL)    /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bitfield-Mask: 0x1f) */
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Pos (5UL)  /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bit 5) */
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Msk (0x20UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bitfield-Mask: 0x01) */

/* ---------------------------  RFCU_RF_IFF_RESULT_REG  --------------------------- */
#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Pos (0UL)                  /*!< RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bit 0)               */
#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Msk (0x1fUL)               /*!< RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bitfield-Mask: 0x1f) */

/* -------------------------  RFCU_RF_IFF_CC_BLE_SET1_REG  ------------------------ */
#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Pos (0UL)             /*!< RFCU RF_IFF_CC_BLE_SET1_REG: IF_CAL_CAP_WR (Bit 0)          */
#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Msk (0x1fUL)          /*!< RFCU RF_IFF_CC_BLE_SET1_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */

/* -------------------------  RFCU_RF_IFF_CC_BLE_SET2_REG  ------------------------ */
#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Pos (0UL)             /*!< RFCU RF_IFF_CC_BLE_SET2_REG: IF_CAL_CAP_WR (Bit 0)          */
#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Msk (0x1fUL)          /*!< RFCU RF_IFF_CC_BLE_SET2_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */

/* ------------------------  RFCU_RF_IFF_CC_FTDF_SET1_REG  ------------------------ */
#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Pos (0UL)            /*!< RFCU RF_IFF_CC_FTDF_SET1_REG: IF_CAL_CAP_WR (Bit 0)         */
#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Msk (0x1fUL)         /*!< RFCU RF_IFF_CC_FTDF_SET1_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */

/* ------------------------  RFCU_RF_IFF_CC_FTDF_SET2_REG  ------------------------ */
#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Pos (0UL)            /*!< RFCU RF_IFF_CC_FTDF_SET2_REG: IF_CAL_CAP_WR (Bit 0)         */
#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Msk (0x1fUL)         /*!< RFCU RF_IFF_CC_FTDF_SET2_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */

/* ------------------------  RFCU_RF_IFF_CAL_CAP_STAT_REG  ------------------------ */
#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Pos (0UL)            /*!< RFCU RF_IFF_CAL_CAP_STAT_REG: IF_CAL_CAP_RD (Bit 0)         */
#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Msk (0x1fUL)         /*!< RFCU RF_IFF_CAL_CAP_STAT_REG: IF_CAL_CAP_RD (Bitfield-Mask: 0x1f) */

/* ------------------------  RFCU_RF_MIX_CAL_CAP_STAT_REG  ------------------------ */
#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Pos (0UL)           /*!< RFCU RF_MIX_CAL_CAP_STAT_REG: MIX_CAL_CAP_RD (Bit 0)        */
#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Msk (0x1fUL)        /*!< RFCU RF_MIX_CAL_CAP_STAT_REG: MIX_CAL_CAP_RD (Bitfield-Mask: 0x1f) */

/* -------------------------  RFCU_RF_LF_CAL_CAP_STAT_REG  ------------------------ */
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Pos (0UL)             /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_CAL_CAP_RD (Bit 0)          */
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Msk (0x1fUL)          /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_CAL_CAP_RD (Bitfield-Mask: 0x1f) */
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Pos (5UL)            /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_SHORT_R4_RD (Bit 5)         */
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Msk (0x20UL)         /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_SHORT_R4_RD (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================       struct 'RFCU_POWER' Position & Mask      ================ */
/* ================================================================================ */


/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG0_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Pos (0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Pos (5UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG1_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Pos (0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Pos (5UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG2_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Pos (0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Pos (5UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG3_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Pos (0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Pos (5UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG4_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Pos (0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Pos (5UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG5_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG6_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Pos (0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Pos (5UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG7_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Pos (0UL)     /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bit 0)  */
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Msk (0x1fUL)  /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Pos (5UL)     /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bit 5)  */
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG8_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Pos (0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Pos (5UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG9_REG  ---------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Pos (0UL)     /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bit 0)  */
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Msk (0x1fUL)  /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Pos (5UL)     /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bit 5)  */
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG10_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG11_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Pos (0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Pos (5UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG12_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Pos (0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Pos (5UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG13_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG14_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Pos (0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Pos (5UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG15_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Pos (0UL)        /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bit 0)     */
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Msk (0x1fUL)     /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Pos (5UL)        /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bit 5)     */
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Msk (0x3e0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG16_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Pos (0UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bit 0)    */
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Msk (0x1fUL)    /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Pos (5UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bit 5)    */
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Msk (0x3e0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG17_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Pos (0UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bit 0)    */
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Msk (0x1fUL)    /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Pos (5UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bit 5)    */
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Msk (0x3e0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG18_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Pos (0UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bit 0)    */
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Msk (0x1fUL)    /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Pos (5UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bit 5)    */
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Msk (0x3e0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG19_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Pos (0UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bit 0)    */
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Msk (0x1fUL)    /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Pos (5UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bit 5)    */
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Msk (0x3e0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG20_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Pos (0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Pos (5UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG21_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Pos (0UL)        /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bit 0)     */
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Msk (0x1fUL)     /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Pos (5UL)        /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bit 5)     */
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Msk (0x3e0UL)    /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG22_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Pos (0UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bit 0)    */
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Msk (0x1fUL)    /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Pos (5UL)       /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bit 5)    */
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Msk (0x3e0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG25_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Pos (0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Pos (5UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG26_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG27_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Pos (0UL)      /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bit 0)   */
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Msk (0x1fUL)   /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Pos (5UL)      /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bit 5)   */
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Msk (0x3e0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG28_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG29_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG30_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG32_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Pos (0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Pos (5UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG33_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Pos (0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Pos (5UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG34_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG36_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Pos (0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Pos (5UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG39_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Pos (0UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Pos (5UL)  /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG40_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG41_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG42_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* ----------------------  RFCU_POWER_RF_ENABLE_CONFIG43_REG  --------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Pos (0UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Pos (5UL)   /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* --------------------  RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -------------------  RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG  ------------------- */
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_rx (Bit 0) */
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_tx (Bit 5) */
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_1_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_2_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_3_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_4_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_5_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_6_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_7_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_8_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* -----------------------  RFCU_POWER_RF_CNTRL_TIMER_9_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Pos (0UL)            /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: SET_OFFSET (Bit 0)         */
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Msk (0xffUL)         /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Pos (8UL)          /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: RESET_OFFSET (Bit 8)       */
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Msk (0xff00UL)     /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_10_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_11_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_12_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_13_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_14_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_15_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_16_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_17_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_18_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_19_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_20_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_21_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_22_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_23_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_24_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_25_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_26_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_27_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_28_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_29_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_30_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ----------------------  RFCU_POWER_RF_CNTRL_TIMER_31_REG  ---------------------- */
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Pos (0UL)           /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: SET_OFFSET (Bit 0)        */
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Msk (0xffUL)        /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: SET_OFFSET (Bitfield-Mask: 0xff) */
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Pos (8UL)         /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: RESET_OFFSET (Bit 8)      */
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Msk (0xff00UL)    /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */

/* ------------------------  RFCU_POWER_RF_ALWAYS_EN1_REG  ------------------------ */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Pos (0UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_EN (Bit 0)     */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Msk (0x1UL)      /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Pos (1UL)       /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CORE_EN (Bit 1)    */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Msk (0x2UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CORE_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Pos (2UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CGM_EN (Bit 2)     */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Msk (0x4UL)      /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CGM_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Pos (3UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MIX_LDO_EN (Bit 3)     */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Msk (0x8UL)      /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MIX_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Pos (4UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFF_LDO_EN (Bit 4)     */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Msk (0x10UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFF_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Pos (5UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFFADC_LDO_EN (Bit 5)  */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Msk (0x20UL)  /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFFADC_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Pos (6UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_LDO_EN (Bit 6)     */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Msk (0x40UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Pos (7UL)         /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MD_LDO_EN (Bit 7)      */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Msk (0x80UL)      /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MD_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Pos (8UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PFD_LDO_EN (Bit 8)     */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Msk (0x100UL)    /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PFD_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Pos (9UL)         /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_LDO_EN (Bit 9)      */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Msk (0x200UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_LDO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Pos (10UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_SWITCH_EN (Bit 10)  */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Msk (0x400UL)  /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_SWITCH_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Pos (11UL)      /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_BIAS_EN (Bit 11)   */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Msk (0x800UL)   /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_BIAS_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Pos (12UL)       /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_BIAS_EN (Bit 12)    */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Msk (0x1000UL)   /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_BIAS_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Pos (13UL)     /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_ZERO (Bit 13)  */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Msk (0x2000UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_ZERO (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Pos (14UL)       /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_RAMP_EN (Bit 14)    */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Msk (0x4000UL)   /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_RAMP_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Pos (15UL)            /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_EN (Bit 15)         */
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Msk (0x8000UL)        /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_EN (Bitfield-Mask: 0x01) */

/* ------------------------  RFCU_POWER_RF_ALWAYS_EN2_REG  ------------------------ */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Pos (0UL)            /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_MIX_EN (Bit 0)         */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Msk (0x1UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_MIX_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Pos (1UL)            /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFF_EN (Bit 1)         */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Msk (0x2UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFF_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Pos (2UL)            /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_ADC_EN (Bit 2)         */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Msk (0x4UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_ADC_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Pos (3UL)            /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_EN (Bit 3)         */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Msk (0x8UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Pos (4UL)       /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_MD_EN (Bit 4)    */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Msk (0x10UL)    /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_MD_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Pos (5UL)             /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_EN (Bit 5)          */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Msk (0x20UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Pos (6UL)            /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_PDF_EN (Bit 6)         */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Msk (0x40UL)         /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_PDF_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Pos (7UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_EN (Bit 7)       */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Msk (0x80UL)       /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Pos (8UL)         /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RFIO_TXRX (Bit 8)      */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Msk (0x100UL)     /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RFIO_TXRX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Pos (9UL)       /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_PA_EN (Bit 9)    */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Msk (0x200UL)   /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_PA_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Pos (10UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RXIQ_EN (Bit 10)       */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Msk (0x400UL)       /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RXIQ_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Pos (11UL)          /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_DIV2_EN (Bit 11)       */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Msk (0x800UL)       /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_DIV2_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Pos (12UL)  /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_BIAS_SH_OPEN (Bit 12) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Msk (0x1000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_BIAS_SH_OPEN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Pos (13UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_BIAS_SH_OPEN (Bit 13) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Msk (0x2000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_BIAS_SH_OPEN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Pos (14UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFFMIX_BIAS_SH_OPEN (Bit 14) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Msk (0x4000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFFMIX_BIAS_SH_OPEN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Pos (15UL)    /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_BIAS_SH (Bit 15) */
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Msk (0x8000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_BIAS_SH (Bitfield-Mask: 0x01) */

/* ------------------------  RFCU_POWER_RF_ALWAYS_EN3_REG  ------------------------ */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Pos (0UL)       /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_MIX_BIAS_SH (Bit 0)    */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Msk (0x1UL)     /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_MIX_BIAS_SH (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Pos (1UL)        /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLL_DIG_EN (Bit 1)     */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Msk (0x2UL)      /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLL_DIG_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Pos (2UL)      /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLLCLOSED_EN (Bit 2)   */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Msk (0x4UL)    /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLLCLOSED_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Pos (3UL)            /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_DEM_EN (Bit 3)         */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Msk (0x8UL)          /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_DEM_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Pos (4UL)       /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_ZERO_EN (Bit 4)    */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Msk (0x10UL)    /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_ZERO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Pos (5UL)            /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_CAL_EN (Bit 5)         */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Msk (0x20UL)         /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_CAL_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Pos (6UL)            /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TDC_EN (Bit 6)         */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Msk (0x40UL)         /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TDC_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Pos (7UL)       /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RFIO_EN (Bit 7)    */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Msk (0x80UL)    /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RFIO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Pos (8UL)      /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_EN (Bit 8)   */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Msk (0x100UL)  /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Pos (9UL)      /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_SH (Bit 9)   */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Msk (0x200UL)  /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_SH (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Pos (10UL)     /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RADIO_EN (Bit 10)  */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Msk (0x400UL)  /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RADIO_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Pos (11UL)       /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_ADC_CLK_EN (Bit 11)    */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Msk (0x800UL)    /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_ADC_CLK_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Pos (12UL)   /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TR_PWRM_OFF_EN (Bit 12) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Msk (0x1000UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TR_PWRM_OFF_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Pos (13UL)         /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TXDAC_EN (Bit 13)      */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Msk (0x2000UL)     /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TXDAC_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Pos (14UL)        /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE2_EN (Bit 14)     */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Msk (0x4000UL)    /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE2_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Pos (15UL)        /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE3_EN (Bit 15)     */
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Msk (0x8000UL)    /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE3_EN (Bitfield-Mask: 0x01) */

/* ------------------------  RFCU_POWER_RF_ALWAYS_EN4_REG  ------------------------ */
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Pos (0UL)         /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_SPARE4_EN (Bit 0)      */
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Msk (0x1UL)       /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_SPARE4_EN (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Pos (1UL)       /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bit 1)    */
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Msk (0x2UL)     /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bitfield-Mask: 0x01) */

/* ------------------------  RFCU_POWER_RF_PORT_EN_BLE_REG  ----------------------- */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Pos (0UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bit 0)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Msk (0x1UL)           /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Pos (1UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bit 1)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Msk (0x2UL)           /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Pos (2UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bit 2)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Msk (0x4UL)           /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Pos (3UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bit 3)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Msk (0x8UL)           /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Pos (4UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bit 4)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Msk (0x10UL)          /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Pos (5UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bit 5)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Msk (0x20UL)          /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Pos (6UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bit 6)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk (0x40UL)          /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Pos (7UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bit 7)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk (0x80UL)          /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Pos (8UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bit 8)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Msk (0x100UL)         /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Pos (9UL)             /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bit 9)          */
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Msk (0x200UL)         /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */

/* -----------------------  RFCU_POWER_RF_PORT_EN_FTDF_REG  ----------------------- */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Pos (0UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bit 0)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Msk (0x1UL)          /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Pos (1UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bit 1)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Msk (0x2UL)          /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Pos (2UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bit 2)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Msk (0x4UL)          /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Pos (3UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bit 3)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Msk (0x8UL)          /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Pos (4UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bit 4)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Msk (0x10UL)         /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Pos (5UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bit 5)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Msk (0x20UL)         /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Pos (6UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bit 6)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk (0x40UL)         /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Pos (7UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bit 7)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk (0x80UL)         /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Pos (8UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bit 8)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Msk (0x100UL)        /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Pos (9UL)            /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bit 9)         */
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Msk (0x200UL)        /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */

/* -------------------------  RFCU_POWER_RF_PORT_POL_REG  ------------------------- */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Pos (0UL)               /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bit 0)            */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Msk (0x1UL)             /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Pos (1UL)               /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT1_POL (Bit 1)            */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Msk (0x2UL)             /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT1_POL (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Pos (2UL)               /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT2_POL (Bit 2)            */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Msk (0x4UL)             /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT2_POL (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Pos (3UL)               /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT3_POL (Bit 3)            */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Msk (0x8UL)             /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT3_POL (Bitfield-Mask: 0x01) */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Pos (4UL)               /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT4_POL (Bit 4)            */
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Msk (0x10UL)            /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT4_POL (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================          struct 'RFPT' Position & Mask         ================ */
/* ================================================================================ */


/* -----------------------------  RFPT_RFPT_CTRL_REG  ----------------------------- */
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Pos   (0UL)                     /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_EN (Bit 0)                    */
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Msk   (0x1UL)                   /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_EN (Bitfield-Mask: 0x01)      */
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Pos  (1UL)                     /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_SEL (Bit 1)                   */
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Msk  (0x6UL)                   /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_SEL (Bitfield-Mask: 0x03)     */
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Pos (3UL)                 /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_ADC_TYPE (Bit 3)              */
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Msk (0x8UL)               /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_ADC_TYPE (Bitfield-Mask: 0x01) */
#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Pos   (4UL)                     /*!< RFPT RFPT_CTRL_REG: RFPT_CIRC_EN (Bit 4)                    */
#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Msk   (0x10UL)                  /*!< RFPT RFPT_CTRL_REG: RFPT_CIRC_EN (Bitfield-Mask: 0x01)      */
#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Pos (5UL)                    /*!< RFPT RFPT_CTRL_REG: RFPT_BREQ_FORCE (Bit 5)                 */
#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Msk (0x20UL)                 /*!< RFPT RFPT_CTRL_REG: RFPT_BREQ_FORCE (Bitfield-Mask: 0x01)   */

/* -----------------------------  RFPT_RFPT_ADDRL_REG  ---------------------------- */
#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Pos    (2UL)                     /*!< RFPT RFPT_ADDRL_REG: RFPT_ADDRL (Bit 2)                     */
#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Msk    (0xfffcUL)                /*!< RFPT RFPT_ADDRL_REG: RFPT_ADDRL (Bitfield-Mask: 0x3fff)     */

/* -----------------------------  RFPT_RFPT_ADDRH_REG  ---------------------------- */
#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Pos    (0UL)                     /*!< RFPT RFPT_ADDRH_REG: RFPT_ADDRH (Bit 0)                     */
#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Msk    (0x3UL)                   /*!< RFPT RFPT_ADDRH_REG: RFPT_ADDRH (Bitfield-Mask: 0x03)       */

/* ------------------------------  RFPT_RFPT_LEN_REG  ----------------------------- */
#define RFPT_RFPT_LEN_REG_RFPT_LEN_Pos        (0UL)                     /*!< RFPT RFPT_LEN_REG: RFPT_LEN (Bit 0)                         */
#define RFPT_RFPT_LEN_REG_RFPT_LEN_Msk        (0x7fffUL)                /*!< RFPT RFPT_LEN_REG: RFPT_LEN (Bitfield-Mask: 0x7fff)         */

/* -----------------------------  RFPT_RFPT_STAT_REG  ----------------------------- */
#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Pos    (0UL)                     /*!< RFPT RFPT_STAT_REG: RFPT_ACTIVE (Bit 0)                     */
#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Msk    (0x1UL)                   /*!< RFPT RFPT_STAT_REG: RFPT_ACTIVE (Bitfield-Mask: 0x01)       */
#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Pos (1UL)                     /*!< RFPT RFPT_STAT_REG: RFPT_OFLOW_STK (Bit 1)                  */
#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Msk (0x2UL)                   /*!< RFPT RFPT_STAT_REG: RFPT_OFLOW_STK (Bitfield-Mask: 0x01)    */

/* ---------------------------  RFPT_RFPT_CRV_ADDRL_REG  -------------------------- */
#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Pos (2UL)                /*!< RFPT RFPT_CRV_ADDRL_REG: RFPT_CRV_ADDRL (Bit 2)             */
#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Msk (0xfffcUL)           /*!< RFPT RFPT_CRV_ADDRL_REG: RFPT_CRV_ADDRL (Bitfield-Mask: 0x3fff) */

/* ---------------------------  RFPT_RFPT_CRV_ADDRH_REG  -------------------------- */
#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Pos (0UL)                /*!< RFPT RFPT_CRV_ADDRH_REG: RFPT_CRV_ADDRH (Bit 0)             */
#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Msk (0x3UL)              /*!< RFPT RFPT_CRV_ADDRH_REG: RFPT_CRV_ADDRH (Bitfield-Mask: 0x03) */

/* ----------------------------  RFPT_RFPT_CRV_LEN_REG  --------------------------- */
#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Pos (0UL)                    /*!< RFPT RFPT_CRV_LEN_REG: RFPT_CRV_LEN (Bit 0)                 */
#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Msk (0x7fffUL)               /*!< RFPT RFPT_CRV_LEN_REG: RFPT_CRV_LEN (Bitfield-Mask: 0x7fff) */


/* ================================================================================ */
/* ================          struct 'SPI' Position & Mask          ================ */
/* ================================================================================ */


/* ------------------------------  SPI_SPI_CTRL_REG  ------------------------------ */
#define SPI_SPI_CTRL_REG_SPI_ON_Pos           (0UL)                     /*!< SPI SPI_CTRL_REG: SPI_ON (Bit 0)                            */
#define SPI_SPI_CTRL_REG_SPI_ON_Msk           (0x1UL)                   /*!< SPI SPI_CTRL_REG: SPI_ON (Bitfield-Mask: 0x01)              */
#define SPI_SPI_CTRL_REG_SPI_PHA_Pos          (1UL)                     /*!< SPI SPI_CTRL_REG: SPI_PHA (Bit 1)                           */
#define SPI_SPI_CTRL_REG_SPI_PHA_Msk          (0x2UL)                   /*!< SPI SPI_CTRL_REG: SPI_PHA (Bitfield-Mask: 0x01)             */
#define SPI_SPI_CTRL_REG_SPI_POL_Pos          (2UL)                     /*!< SPI SPI_CTRL_REG: SPI_POL (Bit 2)                           */
#define SPI_SPI_CTRL_REG_SPI_POL_Msk          (0x4UL)                   /*!< SPI SPI_CTRL_REG: SPI_POL (Bitfield-Mask: 0x01)             */
#define SPI_SPI_CTRL_REG_SPI_CLK_Pos          (3UL)                     /*!< SPI SPI_CTRL_REG: SPI_CLK (Bit 3)                           */
#define SPI_SPI_CTRL_REG_SPI_CLK_Msk          (0x18UL)                  /*!< SPI SPI_CTRL_REG: SPI_CLK (Bitfield-Mask: 0x03)             */
#define SPI_SPI_CTRL_REG_SPI_DO_Pos           (5UL)                     /*!< SPI SPI_CTRL_REG: SPI_DO (Bit 5)                            */
#define SPI_SPI_CTRL_REG_SPI_DO_Msk           (0x20UL)                  /*!< SPI SPI_CTRL_REG: SPI_DO (Bitfield-Mask: 0x01)              */
#define SPI_SPI_CTRL_REG_SPI_SMN_Pos          (6UL)                     /*!< SPI SPI_CTRL_REG: SPI_SMN (Bit 6)                           */
#define SPI_SPI_CTRL_REG_SPI_SMN_Msk          (0x40UL)                  /*!< SPI SPI_CTRL_REG: SPI_SMN (Bitfield-Mask: 0x01)             */
#define SPI_SPI_CTRL_REG_SPI_WORD_Pos         (7UL)                     /*!< SPI SPI_CTRL_REG: SPI_WORD (Bit 7)                          */
#define SPI_SPI_CTRL_REG_SPI_WORD_Msk         (0x180UL)                 /*!< SPI SPI_CTRL_REG: SPI_WORD (Bitfield-Mask: 0x03)            */
#define SPI_SPI_CTRL_REG_SPI_RST_Pos          (9UL)                     /*!< SPI SPI_CTRL_REG: SPI_RST (Bit 9)                           */
#define SPI_SPI_CTRL_REG_SPI_RST_Msk          (0x200UL)                 /*!< SPI SPI_CTRL_REG: SPI_RST (Bitfield-Mask: 0x01)             */
#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos     (10UL)                    /*!< SPI SPI_CTRL_REG: SPI_FORCE_DO (Bit 10)                     */
#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk     (0x400UL)                 /*!< SPI SPI_CTRL_REG: SPI_FORCE_DO (Bitfield-Mask: 0x01)        */
#define SPI_SPI_CTRL_REG_SPI_TXH_Pos          (11UL)                    /*!< SPI SPI_CTRL_REG: SPI_TXH (Bit 11)                          */
#define SPI_SPI_CTRL_REG_SPI_TXH_Msk          (0x800UL)                 /*!< SPI SPI_CTRL_REG: SPI_TXH (Bitfield-Mask: 0x01)             */
#define SPI_SPI_CTRL_REG_SPI_DI_Pos           (12UL)                    /*!< SPI SPI_CTRL_REG: SPI_DI (Bit 12)                           */
#define SPI_SPI_CTRL_REG_SPI_DI_Msk           (0x1000UL)                /*!< SPI SPI_CTRL_REG: SPI_DI (Bitfield-Mask: 0x01)              */
#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos      (13UL)                    /*!< SPI SPI_CTRL_REG: SPI_INT_BIT (Bit 13)                      */
#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk      (0x2000UL)                /*!< SPI SPI_CTRL_REG: SPI_INT_BIT (Bitfield-Mask: 0x01)         */
#define SPI_SPI_CTRL_REG_SPI_MINT_Pos         (14UL)                    /*!< SPI SPI_CTRL_REG: SPI_MINT (Bit 14)                         */
#define SPI_SPI_CTRL_REG_SPI_MINT_Msk         (0x4000UL)                /*!< SPI SPI_CTRL_REG: SPI_MINT (Bitfield-Mask: 0x01)            */
#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos      (15UL)                    /*!< SPI SPI_CTRL_REG: SPI_EN_CTRL (Bit 15)                      */
#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk      (0x8000UL)                /*!< SPI SPI_CTRL_REG: SPI_EN_CTRL (Bitfield-Mask: 0x01)         */

/* -----------------------------  SPI_SPI_RX_TX_REG0  ----------------------------- */
#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Pos      (0UL)                     /*!< SPI SPI_RX_TX_REG0: SPI_DATA0 (Bit 0)                       */
#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Msk      (0xffffUL)                /*!< SPI SPI_RX_TX_REG0: SPI_DATA0 (Bitfield-Mask: 0xffff)       */

/* -----------------------------  SPI_SPI_RX_TX_REG1  ----------------------------- */
#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Pos      (0UL)                     /*!< SPI SPI_RX_TX_REG1: SPI_DATA1 (Bit 0)                       */
#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Msk      (0xffffUL)                /*!< SPI SPI_RX_TX_REG1: SPI_DATA1 (Bitfield-Mask: 0xffff)       */

/* ----------------------------  SPI_SPI_CLEAR_INT_REG  --------------------------- */
#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL)                   /*!< SPI SPI_CLEAR_INT_REG: SPI_CLEAR_INT (Bit 0)                */
#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffUL)              /*!< SPI SPI_CLEAR_INT_REG: SPI_CLEAR_INT (Bitfield-Mask: 0xffff) */

/* ------------------------------  SPI_SPI_CTRL_REG1  ----------------------------- */
#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Pos   (0UL)                     /*!< SPI SPI_CTRL_REG1: SPI_FIFO_MODE (Bit 0)                    */
#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Msk   (0x3UL)                   /*!< SPI SPI_CTRL_REG1: SPI_FIFO_MODE (Bitfield-Mask: 0x03)      */
#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Pos    (2UL)                     /*!< SPI SPI_CTRL_REG1: SPI_PRIORITY (Bit 2)                     */
#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Msk    (0x4UL)                   /*!< SPI SPI_CTRL_REG1: SPI_PRIORITY (Bitfield-Mask: 0x01)       */
#define SPI_SPI_CTRL_REG1_SPI_BUSY_Pos        (3UL)                     /*!< SPI SPI_CTRL_REG1: SPI_BUSY (Bit 3)                         */
#define SPI_SPI_CTRL_REG1_SPI_BUSY_Msk        (0x8UL)                   /*!< SPI SPI_CTRL_REG1: SPI_BUSY (Bitfield-Mask: 0x01)           */
#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Pos    (4UL)                     /*!< SPI SPI_CTRL_REG1: SPI_9BIT_VAL (Bit 4)                     */
#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Msk    (0x10UL)                  /*!< SPI SPI_CTRL_REG1: SPI_9BIT_VAL (Bitfield-Mask: 0x01)       */


/* ================================================================================ */
/* ================          struct 'SPI2' Position & Mask         ================ */
/* ================================================================================ */


/* -----------------------------  SPI2_SPI2_CTRL_REG  ----------------------------- */
#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos         (0UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_ON (Bit 0)                          */
#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk         (0x1UL)                   /*!< SPI2 SPI2_CTRL_REG: SPI_ON (Bitfield-Mask: 0x01)            */
#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos        (1UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_PHA (Bit 1)                         */
#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk        (0x2UL)                   /*!< SPI2 SPI2_CTRL_REG: SPI_PHA (Bitfield-Mask: 0x01)           */
#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos        (2UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_POL (Bit 2)                         */
#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk        (0x4UL)                   /*!< SPI2 SPI2_CTRL_REG: SPI_POL (Bitfield-Mask: 0x01)           */
#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos        (3UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_CLK (Bit 3)                         */
#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk        (0x18UL)                  /*!< SPI2 SPI2_CTRL_REG: SPI_CLK (Bitfield-Mask: 0x03)           */
#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos         (5UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_DO (Bit 5)                          */
#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk         (0x20UL)                  /*!< SPI2 SPI2_CTRL_REG: SPI_DO (Bitfield-Mask: 0x01)            */
#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos        (6UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_SMN (Bit 6)                         */
#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk        (0x40UL)                  /*!< SPI2 SPI2_CTRL_REG: SPI_SMN (Bitfield-Mask: 0x01)           */
#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos       (7UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_WORD (Bit 7)                        */
#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk       (0x180UL)                 /*!< SPI2 SPI2_CTRL_REG: SPI_WORD (Bitfield-Mask: 0x03)          */
#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos        (9UL)                     /*!< SPI2 SPI2_CTRL_REG: SPI_RST (Bit 9)                         */
#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk        (0x200UL)                 /*!< SPI2 SPI2_CTRL_REG: SPI_RST (Bitfield-Mask: 0x01)           */
#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos   (10UL)                    /*!< SPI2 SPI2_CTRL_REG: SPI_FORCE_DO (Bit 10)                   */
#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk   (0x400UL)                 /*!< SPI2 SPI2_CTRL_REG: SPI_FORCE_DO (Bitfield-Mask: 0x01)      */
#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos        (11UL)                    /*!< SPI2 SPI2_CTRL_REG: SPI_TXH (Bit 11)                        */
#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk        (0x800UL)                 /*!< SPI2 SPI2_CTRL_REG: SPI_TXH (Bitfield-Mask: 0x01)           */
#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos         (12UL)                    /*!< SPI2 SPI2_CTRL_REG: SPI_DI (Bit 12)                         */
#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk         (0x1000UL)                /*!< SPI2 SPI2_CTRL_REG: SPI_DI (Bitfield-Mask: 0x01)            */
#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos    (13UL)                    /*!< SPI2 SPI2_CTRL_REG: SPI_INT_BIT (Bit 13)                    */
#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk    (0x2000UL)                /*!< SPI2 SPI2_CTRL_REG: SPI_INT_BIT (Bitfield-Mask: 0x01)       */
#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos       (14UL)                    /*!< SPI2 SPI2_CTRL_REG: SPI_MINT (Bit 14)                       */
#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk       (0x4000UL)                /*!< SPI2 SPI2_CTRL_REG: SPI_MINT (Bitfield-Mask: 0x01)          */
#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos    (15UL)                    /*!< SPI2 SPI2_CTRL_REG: SPI_EN_CTRL (Bit 15)                    */
#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk    (0x8000UL)                /*!< SPI2 SPI2_CTRL_REG: SPI_EN_CTRL (Bitfield-Mask: 0x01)       */

/* ----------------------------  SPI2_SPI2_RX_TX_REG0  ---------------------------- */
#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Pos    (0UL)                     /*!< SPI2 SPI2_RX_TX_REG0: SPI_DATA0 (Bit 0)                     */
#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Msk    (0xffffUL)                /*!< SPI2 SPI2_RX_TX_REG0: SPI_DATA0 (Bitfield-Mask: 0xffff)     */

/* ----------------------------  SPI2_SPI2_RX_TX_REG1  ---------------------------- */
#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Pos    (0UL)                     /*!< SPI2 SPI2_RX_TX_REG1: SPI_DATA1 (Bit 0)                     */
#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Msk    (0xffffUL)                /*!< SPI2 SPI2_RX_TX_REG1: SPI_DATA1 (Bitfield-Mask: 0xffff)     */

/* ---------------------------  SPI2_SPI2_CLEAR_INT_REG  -------------------------- */
#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL)                 /*!< SPI2 SPI2_CLEAR_INT_REG: SPI_CLEAR_INT (Bit 0)              */
#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffUL)            /*!< SPI2 SPI2_CLEAR_INT_REG: SPI_CLEAR_INT (Bitfield-Mask: 0xffff) */

/* -----------------------------  SPI2_SPI2_CTRL_REG1  ---------------------------- */
#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Pos (0UL)                     /*!< SPI2 SPI2_CTRL_REG1: SPI_FIFO_MODE (Bit 0)                  */
#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Msk (0x3UL)                   /*!< SPI2 SPI2_CTRL_REG1: SPI_FIFO_MODE (Bitfield-Mask: 0x03)    */
#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Pos  (2UL)                     /*!< SPI2 SPI2_CTRL_REG1: SPI_PRIORITY (Bit 2)                   */
#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Msk  (0x4UL)                   /*!< SPI2 SPI2_CTRL_REG1: SPI_PRIORITY (Bitfield-Mask: 0x01)     */
#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Pos      (3UL)                     /*!< SPI2 SPI2_CTRL_REG1: SPI_BUSY (Bit 3)                       */
#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Msk      (0x8UL)                   /*!< SPI2 SPI2_CTRL_REG1: SPI_BUSY (Bitfield-Mask: 0x01)         */
#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Pos  (4UL)                     /*!< SPI2 SPI2_CTRL_REG1: SPI_9BIT_VAL (Bit 4)                   */
#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Msk  (0x10UL)                  /*!< SPI2 SPI2_CTRL_REG1: SPI_9BIT_VAL (Bitfield-Mask: 0x01)     */


/* ================================================================================ */
/* ================         struct 'TIMER1' Position & Mask        ================ */
/* ================================================================================ */


/* ---------------------------  TIMER1_CAPTIM_CTRL_REG  --------------------------- */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Pos  (0UL)                     /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_EN (Bit 0)                   */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Msk  (0x1UL)                   /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_EN (Bitfield-Mask: 0x01)     */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Pos (1UL)         /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_ONESHOT_MODE_EN (Bit 1)      */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Msk (0x2UL)       /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Pos (2UL)           /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_COUNT_DOWN_EN (Bit 2)        */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Msk (0x4UL)         /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Pos (3UL)       /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN1_EVENT_FALL_EN (Bit 3)    */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Msk (0x8UL)     /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Pos (4UL)       /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN2_EVENT_FALL_EN (Bit 4)    */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Msk (0x10UL)    /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Pos (5UL)                  /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IRQ_EN (Bit 5)               */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk (0x20UL)               /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IRQ_EN (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Pos (6UL)        /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_FREE_RUN_MODE_EN (Bit 6)     */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Msk (0x40UL)     /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Pos (7UL)              /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_SYS_CLK_EN (Bit 7)           */
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Msk (0x80UL)           /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */

/* -------------------------  TIMER1_CAPTIM_TIMER_VAL_REG  ------------------------ */
#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Pos (0UL)        /*!< TIMER1 CAPTIM_TIMER_VAL_REG: CAPTIM_TIMER_VALUE (Bit 0)     */
#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Msk (0xffffUL)   /*!< TIMER1 CAPTIM_TIMER_VAL_REG: CAPTIM_TIMER_VALUE (Bitfield-Mask: 0xffff) */

/* --------------------------  TIMER1_CAPTIM_STATUS_REG  -------------------------- */
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Pos (0UL)             /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN1_STATE (Bit 0)          */
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Msk (0x1UL)           /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN1_STATE (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Pos (1UL)             /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN2_STATE (Bit 1)          */
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Msk (0x2UL)           /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN2_STATE (Bitfield-Mask: 0x01) */
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Pos (2UL)         /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_ONESHOT_PHASE (Bit 2)      */
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Msk (0xcUL)       /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */

/* ------------------------  TIMER1_CAPTIM_GPIO1_CONF_REG  ------------------------ */
#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Pos (0UL)        /*!< TIMER1 CAPTIM_GPIO1_CONF_REG: CAPTIM_GPIO1_CONF (Bit 0)     */
#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Msk (0x3fUL)     /*!< TIMER1 CAPTIM_GPIO1_CONF_REG: CAPTIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */

/* ------------------------  TIMER1_CAPTIM_GPIO2_CONF_REG  ------------------------ */
#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Pos (0UL)        /*!< TIMER1 CAPTIM_GPIO2_CONF_REG: CAPTIM_GPIO2_CONF (Bit 0)     */
#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Msk (0x3fUL)     /*!< TIMER1 CAPTIM_GPIO2_CONF_REG: CAPTIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */

/* --------------------------  TIMER1_CAPTIM_RELOAD_REG  -------------------------- */
#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Pos (0UL)                /*!< TIMER1 CAPTIM_RELOAD_REG: CAPTIM_RELOAD (Bit 0)             */
#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Msk (0xffffUL)           /*!< TIMER1 CAPTIM_RELOAD_REG: CAPTIM_RELOAD (Bitfield-Mask: 0xffff) */

/* -------------------------  TIMER1_CAPTIM_SHOTWIDTH_REG  ------------------------ */
#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Pos (0UL)          /*!< TIMER1 CAPTIM_SHOTWIDTH_REG: CAPTIM_SHOTWIDTH (Bit 0)       */
#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Msk (0xffffUL)     /*!< TIMER1 CAPTIM_SHOTWIDTH_REG: CAPTIM_SHOTWIDTH (Bitfield-Mask: 0xffff) */

/* -------------------------  TIMER1_CAPTIM_PRESCALER_REG  ------------------------ */
#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Pos (0UL)          /*!< TIMER1 CAPTIM_PRESCALER_REG: CAPTIM_PRESCALER (Bit 0)       */
#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Msk (0xffffUL)     /*!< TIMER1 CAPTIM_PRESCALER_REG: CAPTIM_PRESCALER (Bitfield-Mask: 0xffff) */

/* -----------------------  TIMER1_CAPTIM_CAPTURE_GPIO1_REG  ---------------------- */
#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Pos (0UL)  /*!< TIMER1 CAPTIM_CAPTURE_GPIO1_REG: CAPTIM_CAPTURE_GPIO1 (Bit 0) */
#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_GPIO1_REG: CAPTIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffff) */

/* -----------------------  TIMER1_CAPTIM_CAPTURE_GPIO2_REG  ---------------------- */
#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Pos (0UL)  /*!< TIMER1 CAPTIM_CAPTURE_GPIO2_REG: CAPTIM_CAPTURE_GPIO2 (Bit 0) */
#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_GPIO2_REG: CAPTIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffff) */

/* -----------------------  TIMER1_CAPTIM_PRESCALER_VAL_REG  ---------------------- */
#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Pos (0UL)  /*!< TIMER1 CAPTIM_PRESCALER_VAL_REG: CAPTIM_PRESCALER_VAL (Bit 0) */
#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Msk (0xffffUL) /*!< TIMER1 CAPTIM_PRESCALER_VAL_REG: CAPTIM_PRESCALER_VAL (Bitfield-Mask: 0xffff) */

/* -------------------------  TIMER1_CAPTIM_PWM_FREQ_REG  ------------------------- */
#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Pos (0UL)            /*!< TIMER1 CAPTIM_PWM_FREQ_REG: CAPTIM_PWM_FREQ (Bit 0)         */
#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Msk (0xffffUL)       /*!< TIMER1 CAPTIM_PWM_FREQ_REG: CAPTIM_PWM_FREQ (Bitfield-Mask: 0xffff) */

/* --------------------------  TIMER1_CAPTIM_PWM_DC_REG  -------------------------- */
#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Pos (0UL)                /*!< TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bit 0)             */
#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Msk (0xffffUL)           /*!< TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bitfield-Mask: 0xffff) */

/* ------------------------  TIMER1_CAPTIM_TIMER_HVAL_REG  ------------------------ */
#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Pos (0UL)      /*!< TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bit 0)   */
#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Msk (0xffffUL) /*!< TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bitfield-Mask: 0xffff) */

/* ------------------------  TIMER1_CAPTIM_RELOAD_HIGH_REG  ----------------------- */
#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Pos (0UL)      /*!< TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bit 0)   */
#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bitfield-Mask: 0xffff) */

/* --------------------  TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG  -------------------- */
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bit 0) */
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bitfield-Mask: 0xffff) */

/* --------------------  TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG  -------------------- */
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bit 0) */
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bitfield-Mask: 0xffff) */

/* ----------------------  TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG  ---------------------- */
#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Pos (0UL) /*!< TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bit 0) */
#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bitfield-Mask: 0xffff) */


/* ================================================================================ */
/* ================          struct 'TRNG' Position & Mask         ================ */
/* ================================================================================ */


/* -----------------------------  TRNG_TRNG_CTRL_REG  ----------------------------- */
#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos    (0UL)                     /*!< TRNG TRNG_CTRL_REG: TRNG_ENABLE (Bit 0)                     */
#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk    (0x1UL)                   /*!< TRNG TRNG_CTRL_REG: TRNG_ENABLE (Bitfield-Mask: 0x01)       */
#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Pos      (1UL)                     /*!< TRNG TRNG_CTRL_REG: TRNG_MODE (Bit 1)                       */
#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Msk      (0x2UL)                   /*!< TRNG TRNG_CTRL_REG: TRNG_MODE (Bitfield-Mask: 0x01)         */

/* ----------------------------  TRNG_TRNG_FIFOLVL_REG  --------------------------- */
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos (0UL)                    /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOLVL (Bit 0)                 */
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk (0x1fUL)                 /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOLVL (Bitfield-Mask: 0x1f)   */
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos (5UL)                   /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOFULL (Bit 5)                */
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk (0x20UL)                /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOFULL (Bitfield-Mask: 0x01)  */

/* ------------------------------  TRNG_TRNG_VER_REG  ----------------------------- */
#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos        (0UL)                     /*!< TRNG TRNG_VER_REG: TRNG_SVN (Bit 0)                         */
#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk        (0xffffUL)                /*!< TRNG TRNG_VER_REG: TRNG_SVN (Bitfield-Mask: 0xffff)         */
#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos        (16UL)                    /*!< TRNG TRNG_VER_REG: TRNG_MIN (Bit 16)                        */
#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk        (0xff0000UL)              /*!< TRNG TRNG_VER_REG: TRNG_MIN (Bitfield-Mask: 0xff)           */
#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos        (24UL)                    /*!< TRNG TRNG_VER_REG: TRNG_MAJ (Bit 24)                        */
#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk        (0xff000000UL)            /*!< TRNG TRNG_VER_REG: TRNG_MAJ (Bitfield-Mask: 0xff)           */


/* ================================================================================ */
/* ================          struct 'UART' Position & Mask         ================ */
/* ================================================================================ */


/* --------------------------  UART_UART_RBR_THR_DLL_REG  ------------------------- */
#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)                 /*!< UART UART_RBR_THR_DLL_REG: RBR_THR_DLL (Bit 0)              */
#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)              /*!< UART UART_RBR_THR_DLL_REG: RBR_THR_DLL (Bitfield-Mask: 0xff) */

/* ----------------------------  UART_UART_IER_DLH_REG  --------------------------- */
#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Pos  (0UL)                     /*!< UART UART_IER_DLH_REG: ERBFI_dlh0 (Bit 0)                   */
#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Msk  (0x1UL)                   /*!< UART UART_IER_DLH_REG: ERBFI_dlh0 (Bitfield-Mask: 0x01)     */
#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos  (1UL)                     /*!< UART UART_IER_DLH_REG: ETBEI_dlh1 (Bit 1)                   */
#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk  (0x2UL)                   /*!< UART UART_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01)     */
#define UART_UART_IER_DLH_REG_ELSI_dhl2_Pos   (2UL)                     /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bit 2)                    */
#define UART_UART_IER_DLH_REG_ELSI_dhl2_Msk   (0x4UL)                   /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01)      */
#define UART_UART_IER_DLH_REG_PTIME_dlh7_Pos  (7UL)                     /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bit 7)                   */
#define UART_UART_IER_DLH_REG_PTIME_dlh7_Msk  (0x80UL)                  /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01)     */

/* ----------------------------  UART_UART_IIR_FCR_REG  --------------------------- */
#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos     (0UL)                     /*!< UART UART_IIR_FCR_REG: IIR_FCR (Bit 0)                      */
#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk     (0xffffUL)                /*!< UART UART_IIR_FCR_REG: IIR_FCR (Bitfield-Mask: 0xffff)      */

/* ------------------------------  UART_UART_LCR_REG  ----------------------------- */
#define UART_UART_LCR_REG_UART_DLS_Pos        (0UL)                     /*!< UART UART_LCR_REG: UART_DLS (Bit 0)                         */
#define UART_UART_LCR_REG_UART_DLS_Msk        (0x3UL)                   /*!< UART UART_LCR_REG: UART_DLS (Bitfield-Mask: 0x03)           */
#define UART_UART_LCR_REG_UART_STOP_Pos       (2UL)                     /*!< UART UART_LCR_REG: UART_STOP (Bit 2)                        */
#define UART_UART_LCR_REG_UART_STOP_Msk       (0x4UL)                   /*!< UART UART_LCR_REG: UART_STOP (Bitfield-Mask: 0x01)          */
#define UART_UART_LCR_REG_UART_PEN_Pos        (3UL)                     /*!< UART UART_LCR_REG: UART_PEN (Bit 3)                         */
#define UART_UART_LCR_REG_UART_PEN_Msk        (0x8UL)                   /*!< UART UART_LCR_REG: UART_PEN (Bitfield-Mask: 0x01)           */
#define UART_UART_LCR_REG_UART_EPS_Pos        (4UL)                     /*!< UART UART_LCR_REG: UART_EPS (Bit 4)                         */
#define UART_UART_LCR_REG_UART_EPS_Msk        (0x10UL)                  /*!< UART UART_LCR_REG: UART_EPS (Bitfield-Mask: 0x01)           */
#define UART_UART_LCR_REG_UART_BC_Pos         (6UL)                     /*!< UART UART_LCR_REG: UART_BC (Bit 6)                          */
#define UART_UART_LCR_REG_UART_BC_Msk         (0x40UL)                  /*!< UART UART_LCR_REG: UART_BC (Bitfield-Mask: 0x01)            */
#define UART_UART_LCR_REG_UART_DLAB_Pos       (7UL)                     /*!< UART UART_LCR_REG: UART_DLAB (Bit 7)                        */
#define UART_UART_LCR_REG_UART_DLAB_Msk       (0x80UL)                  /*!< UART UART_LCR_REG: UART_DLAB (Bitfield-Mask: 0x01)          */

/* ------------------------------  UART_UART_MCR_REG  ----------------------------- */
#define UART_UART_MCR_REG_UART_OUT1_Pos       (2UL)                     /*!< UART UART_MCR_REG: UART_OUT1 (Bit 2)                        */
#define UART_UART_MCR_REG_UART_OUT1_Msk       (0x4UL)                   /*!< UART UART_MCR_REG: UART_OUT1 (Bitfield-Mask: 0x01)          */
#define UART_UART_MCR_REG_UART_OUT2_Pos       (3UL)                     /*!< UART UART_MCR_REG: UART_OUT2 (Bit 3)                        */
#define UART_UART_MCR_REG_UART_OUT2_Msk       (0x8UL)                   /*!< UART UART_MCR_REG: UART_OUT2 (Bitfield-Mask: 0x01)          */
#define UART_UART_MCR_REG_UART_LB_Pos         (4UL)                     /*!< UART UART_MCR_REG: UART_LB (Bit 4)                          */
#define UART_UART_MCR_REG_UART_LB_Msk         (0x10UL)                  /*!< UART UART_MCR_REG: UART_LB (Bitfield-Mask: 0x01)            */
#define UART_UART_MCR_REG_UART_SIRE_Pos       (6UL)                     /*!< UART UART_MCR_REG: UART_SIRE (Bit 6)                        */
#define UART_UART_MCR_REG_UART_SIRE_Msk       (0x40UL)                  /*!< UART UART_MCR_REG: UART_SIRE (Bitfield-Mask: 0x01)          */

/* ------------------------------  UART_UART_LSR_REG  ----------------------------- */
#define UART_UART_LSR_REG_UART_DR_Pos         (0UL)                     /*!< UART UART_LSR_REG: UART_DR (Bit 0)                          */
#define UART_UART_LSR_REG_UART_DR_Msk         (0x1UL)                   /*!< UART UART_LSR_REG: UART_DR (Bitfield-Mask: 0x01)            */
#define UART_UART_LSR_REG_UART_OE_Pos         (1UL)                     /*!< UART UART_LSR_REG: UART_OE (Bit 1)                          */
#define UART_UART_LSR_REG_UART_OE_Msk         (0x2UL)                   /*!< UART UART_LSR_REG: UART_OE (Bitfield-Mask: 0x01)            */
#define UART_UART_LSR_REG_UART_PE_Pos         (2UL)                     /*!< UART UART_LSR_REG: UART_PE (Bit 2)                          */
#define UART_UART_LSR_REG_UART_PE_Msk         (0x4UL)                   /*!< UART UART_LSR_REG: UART_PE (Bitfield-Mask: 0x01)            */
#define UART_UART_LSR_REG_UART_FE_Pos         (3UL)                     /*!< UART UART_LSR_REG: UART_FE (Bit 3)                          */
#define UART_UART_LSR_REG_UART_FE_Msk         (0x8UL)                   /*!< UART UART_LSR_REG: UART_FE (Bitfield-Mask: 0x01)            */
#define UART_UART_LSR_REG_UART_BI_Pos         (4UL)                     /*!< UART UART_LSR_REG: UART_BI (Bit 4)                          */
#define UART_UART_LSR_REG_UART_BI_Msk         (0x10UL)                  /*!< UART UART_LSR_REG: UART_BI (Bitfield-Mask: 0x01)            */
#define UART_UART_LSR_REG_UART_THRE_Pos       (5UL)                     /*!< UART UART_LSR_REG: UART_THRE (Bit 5)                        */
#define UART_UART_LSR_REG_UART_THRE_Msk       (0x20UL)                  /*!< UART UART_LSR_REG: UART_THRE (Bitfield-Mask: 0x01)          */
#define UART_UART_LSR_REG_UART_TEMT_Pos       (6UL)                     /*!< UART UART_LSR_REG: UART_TEMT (Bit 6)                        */
#define UART_UART_LSR_REG_UART_TEMT_Msk       (0x40UL)                  /*!< UART UART_LSR_REG: UART_TEMT (Bitfield-Mask: 0x01)          */

/* ------------------------------  UART_UART_SCR_REG  ----------------------------- */
#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)                    /*!< UART UART_SCR_REG: UART_SCRATCH_PAD (Bit 0)                 */
#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)                 /*!< UART UART_SCR_REG: UART_SCRATCH_PAD (Bitfield-Mask: 0xff)   */

/* ------------------------------  UART_UART_USR_REG  ----------------------------- */
#define UART_UART_USR_REG_UART_BUSY_Pos       (0UL)                     /*!< UART UART_USR_REG: UART_BUSY (Bit 0)                        */
#define UART_UART_USR_REG_UART_BUSY_Msk       (0x1UL)                   /*!< UART UART_USR_REG: UART_BUSY (Bitfield-Mask: 0x01)          */

/* ------------------------------  UART_UART_SRR_REG  ----------------------------- */
#define UART_UART_SRR_REG_UART_UR_Pos         (0UL)                     /*!< UART UART_SRR_REG: UART_UR (Bit 0)                          */
#define UART_UART_SRR_REG_UART_UR_Msk         (0x1UL)                   /*!< UART UART_SRR_REG: UART_UR (Bitfield-Mask: 0x01)            */

/* -----------------------------  UART_UART_SBCR_REG  ----------------------------- */
#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)          /*!< UART UART_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bit 0)       */
#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)        /*!< UART UART_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */

/* -----------------------------  UART_UART_DMASA_REG  ---------------------------- */
#define UART_UART_DMASA_REG_DMASA_Pos         (0UL)                     /*!< UART UART_DMASA_REG: DMASA (Bit 0)                          */
#define UART_UART_DMASA_REG_DMASA_Msk         (0x1UL)                   /*!< UART UART_DMASA_REG: DMASA (Bitfield-Mask: 0x01)            */

/* ------------------------------  UART_UART_DLF_REG  ----------------------------- */
#define UART_UART_DLF_REG_UART_DLF_Pos        (0UL)                     /*!< UART UART_DLF_REG: UART_DLF (Bit 0)                         */
#define UART_UART_DLF_REG_UART_DLF_Msk        (0xfUL)                   /*!< UART UART_DLF_REG: UART_DLF (Bitfield-Mask: 0x0f)           */

/* ------------------------------  UART_UART_CPR_REG  ----------------------------- */
#define UART_UART_CPR_REG_CPR_Pos             (0UL)                     /*!< UART UART_CPR_REG: CPR (Bit 0)                              */
#define UART_UART_CPR_REG_CPR_Msk             (0xffffUL)                /*!< UART UART_CPR_REG: CPR (Bitfield-Mask: 0xffff)              */

/* ------------------------------  UART_UART_UCV_REG  ----------------------------- */
#define UART_UART_UCV_REG_UCV_Pos             (0UL)                     /*!< UART UART_UCV_REG: UCV (Bit 0)                              */
#define UART_UART_UCV_REG_UCV_Msk             (0xffffUL)                /*!< UART UART_UCV_REG: UCV (Bitfield-Mask: 0xffff)              */

/* ------------------------------  UART_UART_CTR_REG  ----------------------------- */
#define UART_UART_CTR_REG_CTR_Pos             (0UL)                     /*!< UART UART_CTR_REG: CTR (Bit 0)                              */
#define UART_UART_CTR_REG_CTR_Msk             (0xffffUL)                /*!< UART UART_CTR_REG: CTR (Bitfield-Mask: 0xffff)              */


/* ================================================================================ */
/* ================         struct 'UART2' Position & Mask         ================ */
/* ================================================================================ */


/* -------------------------  UART2_UART2_RBR_THR_DLL_REG  ------------------------ */
#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)               /*!< UART2 UART2_RBR_THR_DLL_REG: RBR_THR_DLL (Bit 0)            */
#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)            /*!< UART2 UART2_RBR_THR_DLL_REG: RBR_THR_DLL (Bitfield-Mask: 0xff) */

/* ---------------------------  UART2_UART2_IER_DLH_REG  -------------------------- */
#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Pos (0UL)                    /*!< UART2 UART2_IER_DLH_REG: ERBFI_dlh0 (Bit 0)                 */
#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Msk (0x1UL)                  /*!< UART2 UART2_IER_DLH_REG: ERBFI_dlh0 (Bitfield-Mask: 0x01)   */
#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Pos (1UL)                    /*!< UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bit 1)                 */
#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL)                  /*!< UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01)   */
#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos (2UL)                     /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bit 2)                  */
#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL)                   /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01)    */
#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos (7UL)                    /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bit 7)                 */
#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL)                 /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01)   */

/* ---------------------------  UART2_UART2_IIR_FCR_REG  -------------------------- */
#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos   (0UL)                     /*!< UART2 UART2_IIR_FCR_REG: IIR_FCR (Bit 0)                    */
#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk   (0xffffUL)                /*!< UART2 UART2_IIR_FCR_REG: IIR_FCR (Bitfield-Mask: 0xffff)    */

/* -----------------------------  UART2_UART2_LCR_REG  ---------------------------- */
#define UART2_UART2_LCR_REG_UART_DLS_Pos      (0UL)                     /*!< UART2 UART2_LCR_REG: UART_DLS (Bit 0)                       */
#define UART2_UART2_LCR_REG_UART_DLS_Msk      (0x3UL)                   /*!< UART2 UART2_LCR_REG: UART_DLS (Bitfield-Mask: 0x03)         */
#define UART2_UART2_LCR_REG_UART_STOP_Pos     (2UL)                     /*!< UART2 UART2_LCR_REG: UART_STOP (Bit 2)                      */
#define UART2_UART2_LCR_REG_UART_STOP_Msk     (0x4UL)                   /*!< UART2 UART2_LCR_REG: UART_STOP (Bitfield-Mask: 0x01)        */
#define UART2_UART2_LCR_REG_UART_PEN_Pos      (3UL)                     /*!< UART2 UART2_LCR_REG: UART_PEN (Bit 3)                       */
#define UART2_UART2_LCR_REG_UART_PEN_Msk      (0x8UL)                   /*!< UART2 UART2_LCR_REG: UART_PEN (Bitfield-Mask: 0x01)         */
#define UART2_UART2_LCR_REG_UART_EPS_Pos      (4UL)                     /*!< UART2 UART2_LCR_REG: UART_EPS (Bit 4)                       */
#define UART2_UART2_LCR_REG_UART_EPS_Msk      (0x10UL)                  /*!< UART2 UART2_LCR_REG: UART_EPS (Bitfield-Mask: 0x01)         */
#define UART2_UART2_LCR_REG_UART_BC_Pos       (6UL)                     /*!< UART2 UART2_LCR_REG: UART_BC (Bit 6)                        */
#define UART2_UART2_LCR_REG_UART_BC_Msk       (0x40UL)                  /*!< UART2 UART2_LCR_REG: UART_BC (Bitfield-Mask: 0x01)          */
#define UART2_UART2_LCR_REG_UART_DLAB_Pos     (7UL)                     /*!< UART2 UART2_LCR_REG: UART_DLAB (Bit 7)                      */
#define UART2_UART2_LCR_REG_UART_DLAB_Msk     (0x80UL)                  /*!< UART2 UART2_LCR_REG: UART_DLAB (Bitfield-Mask: 0x01)        */

/* -----------------------------  UART2_UART2_MCR_REG  ---------------------------- */
#define UART2_UART2_MCR_REG_UART_RTS_Pos      (1UL)                     /*!< UART2 UART2_MCR_REG: UART_RTS (Bit 1)                       */
#define UART2_UART2_MCR_REG_UART_RTS_Msk      (0x2UL)                   /*!< UART2 UART2_MCR_REG: UART_RTS (Bitfield-Mask: 0x01)         */
#define UART2_UART2_MCR_REG_UART_OUT1_Pos     (2UL)                     /*!< UART2 UART2_MCR_REG: UART_OUT1 (Bit 2)                      */
#define UART2_UART2_MCR_REG_UART_OUT1_Msk     (0x4UL)                   /*!< UART2 UART2_MCR_REG: UART_OUT1 (Bitfield-Mask: 0x01)        */
#define UART2_UART2_MCR_REG_UART_OUT2_Pos     (3UL)                     /*!< UART2 UART2_MCR_REG: UART_OUT2 (Bit 3)                      */
#define UART2_UART2_MCR_REG_UART_OUT2_Msk     (0x8UL)                   /*!< UART2 UART2_MCR_REG: UART_OUT2 (Bitfield-Mask: 0x01)        */
#define UART2_UART2_MCR_REG_UART_LB_Pos       (4UL)                     /*!< UART2 UART2_MCR_REG: UART_LB (Bit 4)                        */
#define UART2_UART2_MCR_REG_UART_LB_Msk       (0x10UL)                  /*!< UART2 UART2_MCR_REG: UART_LB (Bitfield-Mask: 0x01)          */
#define UART2_UART2_MCR_REG_UART_AFCE_Pos     (5UL)                     /*!< UART2 UART2_MCR_REG: UART_AFCE (Bit 5)                      */
#define UART2_UART2_MCR_REG_UART_AFCE_Msk     (0x20UL)                  /*!< UART2 UART2_MCR_REG: UART_AFCE (Bitfield-Mask: 0x01)        */
#define UART2_UART2_MCR_REG_UART_SIRE_Pos     (6UL)                     /*!< UART2 UART2_MCR_REG: UART_SIRE (Bit 6)                      */
#define UART2_UART2_MCR_REG_UART_SIRE_Msk     (0x40UL)                  /*!< UART2 UART2_MCR_REG: UART_SIRE (Bitfield-Mask: 0x01)        */

/* -----------------------------  UART2_UART2_LSR_REG  ---------------------------- */
#define UART2_UART2_LSR_REG_UART_DR_Pos       (0UL)                     /*!< UART2 UART2_LSR_REG: UART_DR (Bit 0)                        */
#define UART2_UART2_LSR_REG_UART_DR_Msk       (0x1UL)                   /*!< UART2 UART2_LSR_REG: UART_DR (Bitfield-Mask: 0x01)          */
#define UART2_UART2_LSR_REG_UART_OE_Pos       (1UL)                     /*!< UART2 UART2_LSR_REG: UART_OE (Bit 1)                        */
#define UART2_UART2_LSR_REG_UART_OE_Msk       (0x2UL)                   /*!< UART2 UART2_LSR_REG: UART_OE (Bitfield-Mask: 0x01)          */
#define UART2_UART2_LSR_REG_UART_PE_Pos       (2UL)                     /*!< UART2 UART2_LSR_REG: UART_PE (Bit 2)                        */
#define UART2_UART2_LSR_REG_UART_PE_Msk       (0x4UL)                   /*!< UART2 UART2_LSR_REG: UART_PE (Bitfield-Mask: 0x01)          */
#define UART2_UART2_LSR_REG_UART_FE_Pos       (3UL)                     /*!< UART2 UART2_LSR_REG: UART_FE (Bit 3)                        */
#define UART2_UART2_LSR_REG_UART_FE_Msk       (0x8UL)                   /*!< UART2 UART2_LSR_REG: UART_FE (Bitfield-Mask: 0x01)          */
#define UART2_UART2_LSR_REG_UART_BI_Pos       (4UL)                     /*!< UART2 UART2_LSR_REG: UART_BI (Bit 4)                        */
#define UART2_UART2_LSR_REG_UART_BI_Msk       (0x10UL)                  /*!< UART2 UART2_LSR_REG: UART_BI (Bitfield-Mask: 0x01)          */
#define UART2_UART2_LSR_REG_UART_THRE_Pos     (5UL)                     /*!< UART2 UART2_LSR_REG: UART_THRE (Bit 5)                      */
#define UART2_UART2_LSR_REG_UART_THRE_Msk     (0x20UL)                  /*!< UART2 UART2_LSR_REG: UART_THRE (Bitfield-Mask: 0x01)        */
#define UART2_UART2_LSR_REG_UART_TEMT_Pos     (6UL)                     /*!< UART2 UART2_LSR_REG: UART_TEMT (Bit 6)                      */
#define UART2_UART2_LSR_REG_UART_TEMT_Msk     (0x40UL)                  /*!< UART2 UART2_LSR_REG: UART_TEMT (Bitfield-Mask: 0x01)        */
#define UART2_UART2_LSR_REG_UART_RFE_Pos      (7UL)                     /*!< UART2 UART2_LSR_REG: UART_RFE (Bit 7)                       */
#define UART2_UART2_LSR_REG_UART_RFE_Msk      (0x80UL)                  /*!< UART2 UART2_LSR_REG: UART_RFE (Bitfield-Mask: 0x01)         */

/* -----------------------------  UART2_UART2_MSR_REG  ---------------------------- */
#define UART2_UART2_MSR_REG_UART_DCTS_Pos     (0UL)                     /*!< UART2 UART2_MSR_REG: UART_DCTS (Bit 0)                      */
#define UART2_UART2_MSR_REG_UART_DCTS_Msk     (0x1UL)                   /*!< UART2 UART2_MSR_REG: UART_DCTS (Bitfield-Mask: 0x01)        */
#define UART2_UART2_MSR_REG_UART_CTS_Pos      (4UL)                     /*!< UART2 UART2_MSR_REG: UART_CTS (Bit 4)                       */
#define UART2_UART2_MSR_REG_UART_CTS_Msk      (0x10UL)                  /*!< UART2 UART2_MSR_REG: UART_CTS (Bitfield-Mask: 0x01)         */

/* -----------------------------  UART2_UART2_SCR_REG  ---------------------------- */
#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)                  /*!< UART2 UART2_SCR_REG: UART_SCRATCH_PAD (Bit 0)               */
#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)               /*!< UART2 UART2_SCR_REG: UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR0_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR0_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR0_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR1_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR1_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR1_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR2_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR2_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR2_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR3_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR3_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR3_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR4_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR4_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR4_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR5_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR5_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR5_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR6_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR6_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR6_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR7_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR7_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR7_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR8_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR8_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR8_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR9_REG  ------------------------- */
#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)                 /*!< UART2 UART2_SRBR_STHR9_REG: SRBR_STHRx (Bit 0)              */
#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)              /*!< UART2 UART2_SRBR_STHR9_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR10_REG  ------------------------ */
#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)                /*!< UART2 UART2_SRBR_STHR10_REG: SRBR_STHRx (Bit 0)             */
#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)             /*!< UART2 UART2_SRBR_STHR10_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR11_REG  ------------------------ */
#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)                /*!< UART2 UART2_SRBR_STHR11_REG: SRBR_STHRx (Bit 0)             */
#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)             /*!< UART2 UART2_SRBR_STHR11_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR12_REG  ------------------------ */
#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)                /*!< UART2 UART2_SRBR_STHR12_REG: SRBR_STHRx (Bit 0)             */
#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)             /*!< UART2 UART2_SRBR_STHR12_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR13_REG  ------------------------ */
#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)                /*!< UART2 UART2_SRBR_STHR13_REG: SRBR_STHRx (Bit 0)             */
#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)             /*!< UART2 UART2_SRBR_STHR13_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR14_REG  ------------------------ */
#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)                /*!< UART2 UART2_SRBR_STHR14_REG: SRBR_STHRx (Bit 0)             */
#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)             /*!< UART2 UART2_SRBR_STHR14_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -------------------------  UART2_UART2_SRBR_STHR15_REG  ------------------------ */
#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)                /*!< UART2 UART2_SRBR_STHR15_REG: SRBR_STHRx (Bit 0)             */
#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)             /*!< UART2 UART2_SRBR_STHR15_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */

/* -----------------------------  UART2_UART2_FAR_REG  ---------------------------- */
#define UART2_UART2_FAR_REG_UART_FAR_Pos      (0UL)                     /*!< UART2 UART2_FAR_REG: UART_FAR (Bit 0)                       */
#define UART2_UART2_FAR_REG_UART_FAR_Msk      (0x1UL)                   /*!< UART2 UART2_FAR_REG: UART_FAR (Bitfield-Mask: 0x01)         */

/* -----------------------------  UART2_UART2_USR_REG  ---------------------------- */
#define UART2_UART2_USR_REG_UART_BUSY_Pos     (0UL)                     /*!< UART2 UART2_USR_REG: UART_BUSY (Bit 0)                      */
#define UART2_UART2_USR_REG_UART_BUSY_Msk     (0x1UL)                   /*!< UART2 UART2_USR_REG: UART_BUSY (Bitfield-Mask: 0x01)        */
#define UART2_UART2_USR_REG_UART_TFNF_Pos     (1UL)                     /*!< UART2 UART2_USR_REG: UART_TFNF (Bit 1)                      */
#define UART2_UART2_USR_REG_UART_TFNF_Msk     (0x2UL)                   /*!< UART2 UART2_USR_REG: UART_TFNF (Bitfield-Mask: 0x01)        */
#define UART2_UART2_USR_REG_UART_TFE_Pos      (2UL)                     /*!< UART2 UART2_USR_REG: UART_TFE (Bit 2)                       */
#define UART2_UART2_USR_REG_UART_TFE_Msk      (0x4UL)                   /*!< UART2 UART2_USR_REG: UART_TFE (Bitfield-Mask: 0x01)         */
#define UART2_UART2_USR_REG_UART_RFNE_Pos     (3UL)                     /*!< UART2 UART2_USR_REG: UART_RFNE (Bit 3)                      */
#define UART2_UART2_USR_REG_UART_RFNE_Msk     (0x8UL)                   /*!< UART2 UART2_USR_REG: UART_RFNE (Bitfield-Mask: 0x01)        */
#define UART2_UART2_USR_REG_UART_RFF_Pos      (4UL)                     /*!< UART2 UART2_USR_REG: UART_RFF (Bit 4)                       */
#define UART2_UART2_USR_REG_UART_RFF_Msk      (0x10UL)                  /*!< UART2 UART2_USR_REG: UART_RFF (Bitfield-Mask: 0x01)         */

/* -----------------------------  UART2_UART2_TFL_REG  ---------------------------- */
#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)          /*!< UART2 UART2_TFL_REG: UART_TRANSMIT_FIFO_LEVEL (Bit 0)       */
#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0xffffUL)     /*!< UART2 UART2_TFL_REG: UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0xffff) */

/* -----------------------------  UART2_UART2_RFL_REG  ---------------------------- */
#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)           /*!< UART2 UART2_RFL_REG: UART_RECEIVE_FIFO_LEVEL (Bit 0)        */
#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0xffffUL)      /*!< UART2 UART2_RFL_REG: UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0xffff) */

/* -----------------------------  UART2_UART2_SRR_REG  ---------------------------- */
#define UART2_UART2_SRR_REG_UART_UR_Pos       (0UL)                     /*!< UART2 UART2_SRR_REG: UART_UR (Bit 0)                        */
#define UART2_UART2_SRR_REG_UART_UR_Msk       (0x1UL)                   /*!< UART2 UART2_SRR_REG: UART_UR (Bitfield-Mask: 0x01)          */
#define UART2_UART2_SRR_REG_UART_RFR_Pos      (1UL)                     /*!< UART2 UART2_SRR_REG: UART_RFR (Bit 1)                       */
#define UART2_UART2_SRR_REG_UART_RFR_Msk      (0x2UL)                   /*!< UART2 UART2_SRR_REG: UART_RFR (Bitfield-Mask: 0x01)         */
#define UART2_UART2_SRR_REG_UART_XFR_Pos      (2UL)                     /*!< UART2 UART2_SRR_REG: UART_XFR (Bit 2)                       */
#define UART2_UART2_SRR_REG_UART_XFR_Msk      (0x4UL)                   /*!< UART2 UART2_SRR_REG: UART_XFR (Bitfield-Mask: 0x01)         */

/* ----------------------------  UART2_UART2_SRTS_REG  ---------------------------- */
#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL)      /*!< UART2 UART2_SRTS_REG: UART_SHADOW_REQUEST_TO_SEND (Bit 0)   */
#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL)    /*!< UART2 UART2_SRTS_REG: UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01) */

/* ----------------------------  UART2_UART2_SBCR_REG  ---------------------------- */
#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)        /*!< UART2 UART2_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bit 0)     */
#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)      /*!< UART2 UART2_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */

/* ----------------------------  UART2_UART2_SDMAM_REG  --------------------------- */
#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)            /*!< UART2 UART2_SDMAM_REG: UART_SHADOW_DMA_MODE (Bit 0)         */
#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)          /*!< UART2 UART2_SDMAM_REG: UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */

/* -----------------------------  UART2_UART2_SFE_REG  ---------------------------- */
#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)           /*!< UART2 UART2_SFE_REG: UART_SHADOW_FIFO_ENABLE (Bit 0)        */
#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)         /*!< UART2 UART2_SFE_REG: UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */

/* -----------------------------  UART2_UART2_SRT_REG  ---------------------------- */
#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)          /*!< UART2 UART2_SRT_REG: UART_SHADOW_RCVR_TRIGGER (Bit 0)       */
#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)        /*!< UART2 UART2_SRT_REG: UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */

/* ----------------------------  UART2_UART2_STET_REG  ---------------------------- */
#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)     /*!< UART2 UART2_STET_REG: UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)  */
#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)   /*!< UART2 UART2_STET_REG: UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */

/* -----------------------------  UART2_UART2_HTX_REG  ---------------------------- */
#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos  (0UL)                     /*!< UART2 UART2_HTX_REG: UART_HALT_TX (Bit 0)                   */
#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk  (0x1UL)                   /*!< UART2 UART2_HTX_REG: UART_HALT_TX (Bitfield-Mask: 0x01)     */

/* ----------------------------  UART2_UART2_DMASA_REG  --------------------------- */
#define UART2_UART2_DMASA_REG_DMASA_Pos       (0UL)                     /*!< UART2 UART2_DMASA_REG: DMASA (Bit 0)                        */
#define UART2_UART2_DMASA_REG_DMASA_Msk       (0x1UL)                   /*!< UART2 UART2_DMASA_REG: DMASA (Bitfield-Mask: 0x01)          */

/* -----------------------------  UART2_UART2_DLF_REG  ---------------------------- */
#define UART2_UART2_DLF_REG_UART_DLF_Pos      (0UL)                     /*!< UART2 UART2_DLF_REG: UART_DLF (Bit 0)                       */
#define UART2_UART2_DLF_REG_UART_DLF_Msk      (0xfUL)                   /*!< UART2 UART2_DLF_REG: UART_DLF (Bitfield-Mask: 0x0f)         */

/* -----------------------------  UART2_UART2_CPR_REG  ---------------------------- */
#define UART2_UART2_CPR_REG_CPR_Pos           (0UL)                     /*!< UART2 UART2_CPR_REG: CPR (Bit 0)                            */
#define UART2_UART2_CPR_REG_CPR_Msk           (0xffffUL)                /*!< UART2 UART2_CPR_REG: CPR (Bitfield-Mask: 0xffff)            */

/* -----------------------------  UART2_UART2_UCV_REG  ---------------------------- */
#define UART2_UART2_UCV_REG_UCV_Pos           (0UL)                     /*!< UART2 UART2_UCV_REG: UCV (Bit 0)                            */
#define UART2_UART2_UCV_REG_UCV_Msk           (0xffffUL)                /*!< UART2 UART2_UCV_REG: UCV (Bitfield-Mask: 0xffff)            */

/* -----------------------------  UART2_UART2_CTR_REG  ---------------------------- */
#define UART2_UART2_CTR_REG_CTR_Pos           (0UL)                     /*!< UART2 UART2_CTR_REG: CTR (Bit 0)                            */
#define UART2_UART2_CTR_REG_CTR_Msk           (0xffffUL)                /*!< UART2 UART2_CTR_REG: CTR (Bitfield-Mask: 0xffff)            */


/* ================================================================================ */
/* ================          struct 'USB' Position & Mask          ================ */
/* ================================================================================ */


/* ------------------------------  USB_USB_MCTRL_REG  ----------------------------- */
#define USB_USB_MCTRL_REG_USBEN_Pos           (0UL)                     /*!< USB USB_MCTRL_REG: USBEN (Bit 0)                            */
#define USB_USB_MCTRL_REG_USBEN_Msk           (0x1UL)                   /*!< USB USB_MCTRL_REG: USBEN (Bitfield-Mask: 0x01)              */
#define USB_USB_MCTRL_REG_USB_DBG_Pos         (1UL)                     /*!< USB USB_MCTRL_REG: USB_DBG (Bit 1)                          */
#define USB_USB_MCTRL_REG_USB_DBG_Msk         (0x2UL)                   /*!< USB USB_MCTRL_REG: USB_DBG (Bitfield-Mask: 0x01)            */
#define USB_USB_MCTRL_REG_USB_NAT_Pos         (3UL)                     /*!< USB USB_MCTRL_REG: USB_NAT (Bit 3)                          */
#define USB_USB_MCTRL_REG_USB_NAT_Msk         (0x8UL)                   /*!< USB USB_MCTRL_REG: USB_NAT (Bitfield-Mask: 0x01)            */
#define USB_USB_MCTRL_REG_LSMODE_Pos          (4UL)                     /*!< USB USB_MCTRL_REG: LSMODE (Bit 4)                           */
#define USB_USB_MCTRL_REG_LSMODE_Msk          (0x10UL)                  /*!< USB USB_MCTRL_REG: LSMODE (Bitfield-Mask: 0x01)             */

/* -----------------------------  USB_USB_XCVDIAG_REG  ---------------------------- */
#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos  (0UL)                     /*!< USB USB_XCVDIAG_REG: USB_XCV_TEST (Bit 0)                   */
#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk  (0x1UL)                   /*!< USB USB_XCVDIAG_REG: USB_XCV_TEST (Bitfield-Mask: 0x01)     */
#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos   (1UL)                     /*!< USB USB_XCVDIAG_REG: USB_XCV_TXp (Bit 1)                    */
#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk   (0x2UL)                   /*!< USB USB_XCVDIAG_REG: USB_XCV_TXp (Bitfield-Mask: 0x01)      */
#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos   (2UL)                     /*!< USB USB_XCVDIAG_REG: USB_XCV_TXn (Bit 2)                    */
#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk   (0x4UL)                   /*!< USB USB_XCVDIAG_REG: USB_XCV_TXn (Bitfield-Mask: 0x01)      */
#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos  (3UL)                     /*!< USB USB_XCVDIAG_REG: USB_XCV_TXEN (Bit 3)                   */
#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk  (0x8UL)                   /*!< USB USB_XCVDIAG_REG: USB_XCV_TXEN (Bitfield-Mask: 0x01)     */
#define USB_USB_XCVDIAG_REG_USB_RCV_Pos       (5UL)                     /*!< USB USB_XCVDIAG_REG: USB_RCV (Bit 5)                        */
#define USB_USB_XCVDIAG_REG_USB_RCV_Msk       (0x20UL)                  /*!< USB USB_XCVDIAG_REG: USB_RCV (Bitfield-Mask: 0x01)          */
#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos      (6UL)                     /*!< USB USB_XCVDIAG_REG: USB_VMIN (Bit 6)                       */
#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk      (0x40UL)                  /*!< USB USB_XCVDIAG_REG: USB_VMIN (Bitfield-Mask: 0x01)         */
#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos      (7UL)                     /*!< USB USB_XCVDIAG_REG: USB_VPIN (Bit 7)                       */
#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk      (0x80UL)                  /*!< USB USB_XCVDIAG_REG: USB_VPIN (Bitfield-Mask: 0x01)         */

/* -------------------------------  USB_USB_TCR_REG  ------------------------------ */
#define USB_USB_TCR_REG_USB_CADJ_Pos          (0UL)                     /*!< USB USB_TCR_REG: USB_CADJ (Bit 0)                           */
#define USB_USB_TCR_REG_USB_CADJ_Msk          (0x1fUL)                  /*!< USB USB_TCR_REG: USB_CADJ (Bitfield-Mask: 0x1f)             */
#define USB_USB_TCR_REG_USB_VADJ_Pos          (5UL)                     /*!< USB USB_TCR_REG: USB_VADJ (Bit 5)                           */
#define USB_USB_TCR_REG_USB_VADJ_Msk          (0xe0UL)                  /*!< USB USB_TCR_REG: USB_VADJ (Bitfield-Mask: 0x07)             */

/* -------------------------------  USB_USB_UTR_REG  ------------------------------ */
#define USB_USB_UTR_REG_USB_UTR_RES_Pos       (0UL)                     /*!< USB USB_UTR_REG: USB_UTR_RES (Bit 0)                        */
#define USB_USB_UTR_REG_USB_UTR_RES_Msk       (0x1fUL)                  /*!< USB USB_UTR_REG: USB_UTR_RES (Bitfield-Mask: 0x1f)          */
#define USB_USB_UTR_REG_USB_SF_Pos            (5UL)                     /*!< USB USB_UTR_REG: USB_SF (Bit 5)                             */
#define USB_USB_UTR_REG_USB_SF_Msk            (0x20UL)                  /*!< USB USB_UTR_REG: USB_SF (Bitfield-Mask: 0x01)               */
#define USB_USB_UTR_REG_USB_NCRC_Pos          (6UL)                     /*!< USB USB_UTR_REG: USB_NCRC (Bit 6)                           */
#define USB_USB_UTR_REG_USB_NCRC_Msk          (0x40UL)                  /*!< USB USB_UTR_REG: USB_NCRC (Bitfield-Mask: 0x01)             */
#define USB_USB_UTR_REG_USB_DIAG_Pos          (7UL)                     /*!< USB USB_UTR_REG: USB_DIAG (Bit 7)                           */
#define USB_USB_UTR_REG_USB_DIAG_Msk          (0x80UL)                  /*!< USB USB_UTR_REG: USB_DIAG (Bitfield-Mask: 0x01)             */

/* -------------------------------  USB_USB_FAR_REG  ------------------------------ */
#define USB_USB_FAR_REG_USB_AD_Pos            (0UL)                     /*!< USB USB_FAR_REG: USB_AD (Bit 0)                             */
#define USB_USB_FAR_REG_USB_AD_Msk            (0x7fUL)                  /*!< USB USB_FAR_REG: USB_AD (Bitfield-Mask: 0x7f)               */
#define USB_USB_FAR_REG_USB_AD_EN_Pos         (7UL)                     /*!< USB USB_FAR_REG: USB_AD_EN (Bit 7)                          */
#define USB_USB_FAR_REG_USB_AD_EN_Msk         (0x80UL)                  /*!< USB USB_FAR_REG: USB_AD_EN (Bitfield-Mask: 0x01)            */

/* ------------------------------  USB_USB_NFSR_REG  ------------------------------ */
#define USB_USB_NFSR_REG_USB_NFS_Pos          (0UL)                     /*!< USB USB_NFSR_REG: USB_NFS (Bit 0)                           */
#define USB_USB_NFSR_REG_USB_NFS_Msk          (0x3UL)                   /*!< USB USB_NFSR_REG: USB_NFS (Bitfield-Mask: 0x03)             */

/* ------------------------------  USB_USB_MAEV_REG  ------------------------------ */
#define USB_USB_MAEV_REG_USB_WARN_Pos         (0UL)                     /*!< USB USB_MAEV_REG: USB_WARN (Bit 0)                          */
#define USB_USB_MAEV_REG_USB_WARN_Msk         (0x1UL)                   /*!< USB USB_MAEV_REG: USB_WARN (Bitfield-Mask: 0x01)            */
#define USB_USB_MAEV_REG_USB_ALT_Pos          (1UL)                     /*!< USB USB_MAEV_REG: USB_ALT (Bit 1)                           */
#define USB_USB_MAEV_REG_USB_ALT_Msk          (0x2UL)                   /*!< USB USB_MAEV_REG: USB_ALT (Bitfield-Mask: 0x01)             */
#define USB_USB_MAEV_REG_USB_TX_EV_Pos        (2UL)                     /*!< USB USB_MAEV_REG: USB_TX_EV (Bit 2)                         */
#define USB_USB_MAEV_REG_USB_TX_EV_Msk        (0x4UL)                   /*!< USB USB_MAEV_REG: USB_TX_EV (Bitfield-Mask: 0x01)           */
#define USB_USB_MAEV_REG_USB_FRAME_Pos        (3UL)                     /*!< USB USB_MAEV_REG: USB_FRAME (Bit 3)                         */
#define USB_USB_MAEV_REG_USB_FRAME_Msk        (0x8UL)                   /*!< USB USB_MAEV_REG: USB_FRAME (Bitfield-Mask: 0x01)           */
#define USB_USB_MAEV_REG_USB_NAK_Pos          (4UL)                     /*!< USB USB_MAEV_REG: USB_NAK (Bit 4)                           */
#define USB_USB_MAEV_REG_USB_NAK_Msk          (0x10UL)                  /*!< USB USB_MAEV_REG: USB_NAK (Bitfield-Mask: 0x01)             */
#define USB_USB_MAEV_REG_USB_ULD_Pos          (5UL)                     /*!< USB USB_MAEV_REG: USB_ULD (Bit 5)                           */
#define USB_USB_MAEV_REG_USB_ULD_Msk          (0x20UL)                  /*!< USB USB_MAEV_REG: USB_ULD (Bitfield-Mask: 0x01)             */
#define USB_USB_MAEV_REG_USB_RX_EV_Pos        (6UL)                     /*!< USB USB_MAEV_REG: USB_RX_EV (Bit 6)                         */
#define USB_USB_MAEV_REG_USB_RX_EV_Msk        (0x40UL)                  /*!< USB USB_MAEV_REG: USB_RX_EV (Bitfield-Mask: 0x01)           */
#define USB_USB_MAEV_REG_USB_INTR_Pos         (7UL)                     /*!< USB USB_MAEV_REG: USB_INTR (Bit 7)                          */
#define USB_USB_MAEV_REG_USB_INTR_Msk         (0x80UL)                  /*!< USB USB_MAEV_REG: USB_INTR (Bitfield-Mask: 0x01)            */
#define USB_USB_MAEV_REG_USB_EP0_TX_Pos       (8UL)                     /*!< USB USB_MAEV_REG: USB_EP0_TX (Bit 8)                        */
#define USB_USB_MAEV_REG_USB_EP0_TX_Msk       (0x100UL)                 /*!< USB USB_MAEV_REG: USB_EP0_TX (Bitfield-Mask: 0x01)          */
#define USB_USB_MAEV_REG_USB_EP0_RX_Pos       (9UL)                     /*!< USB USB_MAEV_REG: USB_EP0_RX (Bit 9)                        */
#define USB_USB_MAEV_REG_USB_EP0_RX_Msk       (0x200UL)                 /*!< USB USB_MAEV_REG: USB_EP0_RX (Bitfield-Mask: 0x01)          */
#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos      (10UL)                    /*!< USB USB_MAEV_REG: USB_EP0_NAK (Bit 10)                      */
#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk      (0x400UL)                 /*!< USB USB_MAEV_REG: USB_EP0_NAK (Bitfield-Mask: 0x01)         */
#define USB_USB_MAEV_REG_USB_CH_EV_Pos        (11UL)                    /*!< USB USB_MAEV_REG: USB_CH_EV (Bit 11)                        */
#define USB_USB_MAEV_REG_USB_CH_EV_Msk        (0x800UL)                 /*!< USB USB_MAEV_REG: USB_CH_EV (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_MAMSK_REG  ----------------------------- */
#define USB_USB_MAMSK_REG_USB_M_WARN_Pos      (0UL)                     /*!< USB USB_MAMSK_REG: USB_M_WARN (Bit 0)                       */
#define USB_USB_MAMSK_REG_USB_M_WARN_Msk      (0x1UL)                   /*!< USB USB_MAMSK_REG: USB_M_WARN (Bitfield-Mask: 0x01)         */
#define USB_USB_MAMSK_REG_USB_M_ALT_Pos       (1UL)                     /*!< USB USB_MAMSK_REG: USB_M_ALT (Bit 1)                        */
#define USB_USB_MAMSK_REG_USB_M_ALT_Msk       (0x2UL)                   /*!< USB USB_MAMSK_REG: USB_M_ALT (Bitfield-Mask: 0x01)          */
#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos     (2UL)                     /*!< USB USB_MAMSK_REG: USB_M_TX_EV (Bit 2)                      */
#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk     (0x4UL)                   /*!< USB USB_MAMSK_REG: USB_M_TX_EV (Bitfield-Mask: 0x01)        */
#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos     (3UL)                     /*!< USB USB_MAMSK_REG: USB_M_FRAME (Bit 3)                      */
#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk     (0x8UL)                   /*!< USB USB_MAMSK_REG: USB_M_FRAME (Bitfield-Mask: 0x01)        */
#define USB_USB_MAMSK_REG_USB_M_NAK_Pos       (4UL)                     /*!< USB USB_MAMSK_REG: USB_M_NAK (Bit 4)                        */
#define USB_USB_MAMSK_REG_USB_M_NAK_Msk       (0x10UL)                  /*!< USB USB_MAMSK_REG: USB_M_NAK (Bitfield-Mask: 0x01)          */
#define USB_USB_MAMSK_REG_USB_M_ULD_Pos       (5UL)                     /*!< USB USB_MAMSK_REG: USB_M_ULD (Bit 5)                        */
#define USB_USB_MAMSK_REG_USB_M_ULD_Msk       (0x20UL)                  /*!< USB USB_MAMSK_REG: USB_M_ULD (Bitfield-Mask: 0x01)          */
#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos     (6UL)                     /*!< USB USB_MAMSK_REG: USB_M_RX_EV (Bit 6)                      */
#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk     (0x40UL)                  /*!< USB USB_MAMSK_REG: USB_M_RX_EV (Bitfield-Mask: 0x01)        */
#define USB_USB_MAMSK_REG_USB_M_INTR_Pos      (7UL)                     /*!< USB USB_MAMSK_REG: USB_M_INTR (Bit 7)                       */
#define USB_USB_MAMSK_REG_USB_M_INTR_Msk      (0x80UL)                  /*!< USB USB_MAMSK_REG: USB_M_INTR (Bitfield-Mask: 0x01)         */
#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos    (8UL)                     /*!< USB USB_MAMSK_REG: USB_M_EP0_TX (Bit 8)                     */
#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk    (0x100UL)                 /*!< USB USB_MAMSK_REG: USB_M_EP0_TX (Bitfield-Mask: 0x01)       */
#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos    (9UL)                     /*!< USB USB_MAMSK_REG: USB_M_EP0_RX (Bit 9)                     */
#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk    (0x200UL)                 /*!< USB USB_MAMSK_REG: USB_M_EP0_RX (Bitfield-Mask: 0x01)       */
#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos   (10UL)                    /*!< USB USB_MAMSK_REG: USB_M_EP0_NAK (Bit 10)                   */
#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk   (0x400UL)                 /*!< USB USB_MAMSK_REG: USB_M_EP0_NAK (Bitfield-Mask: 0x01)      */
#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos     (11UL)                    /*!< USB USB_MAMSK_REG: USB_M_CH_EV (Bit 11)                     */
#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk     (0x800UL)                 /*!< USB USB_MAMSK_REG: USB_M_CH_EV (Bitfield-Mask: 0x01)        */

/* ------------------------------  USB_USB_ALTEV_REG  ----------------------------- */
#define USB_USB_ALTEV_REG_USB_EOP_Pos         (3UL)                     /*!< USB USB_ALTEV_REG: USB_EOP (Bit 3)                          */
#define USB_USB_ALTEV_REG_USB_EOP_Msk         (0x8UL)                   /*!< USB USB_ALTEV_REG: USB_EOP (Bitfield-Mask: 0x01)            */
#define USB_USB_ALTEV_REG_USB_SD3_Pos         (4UL)                     /*!< USB USB_ALTEV_REG: USB_SD3 (Bit 4)                          */
#define USB_USB_ALTEV_REG_USB_SD3_Msk         (0x10UL)                  /*!< USB USB_ALTEV_REG: USB_SD3 (Bitfield-Mask: 0x01)            */
#define USB_USB_ALTEV_REG_USB_SD5_Pos         (5UL)                     /*!< USB USB_ALTEV_REG: USB_SD5 (Bit 5)                          */
#define USB_USB_ALTEV_REG_USB_SD5_Msk         (0x20UL)                  /*!< USB USB_ALTEV_REG: USB_SD5 (Bitfield-Mask: 0x01)            */
#define USB_USB_ALTEV_REG_USB_RESET_Pos       (6UL)                     /*!< USB USB_ALTEV_REG: USB_RESET (Bit 6)                        */
#define USB_USB_ALTEV_REG_USB_RESET_Msk       (0x40UL)                  /*!< USB USB_ALTEV_REG: USB_RESET (Bitfield-Mask: 0x01)          */
#define USB_USB_ALTEV_REG_USB_RESUME_Pos      (7UL)                     /*!< USB USB_ALTEV_REG: USB_RESUME (Bit 7)                       */
#define USB_USB_ALTEV_REG_USB_RESUME_Msk      (0x80UL)                  /*!< USB USB_ALTEV_REG: USB_RESUME (Bitfield-Mask: 0x01)         */

/* -----------------------------  USB_USB_ALTMSK_REG  ----------------------------- */
#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos      (3UL)                     /*!< USB USB_ALTMSK_REG: USB_M_EOP (Bit 3)                       */
#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk      (0x8UL)                   /*!< USB USB_ALTMSK_REG: USB_M_EOP (Bitfield-Mask: 0x01)         */
#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos      (4UL)                     /*!< USB USB_ALTMSK_REG: USB_M_SD3 (Bit 4)                       */
#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk      (0x10UL)                  /*!< USB USB_ALTMSK_REG: USB_M_SD3 (Bitfield-Mask: 0x01)         */
#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos      (5UL)                     /*!< USB USB_ALTMSK_REG: USB_M_SD5 (Bit 5)                       */
#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk      (0x20UL)                  /*!< USB USB_ALTMSK_REG: USB_M_SD5 (Bitfield-Mask: 0x01)         */
#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos    (6UL)                     /*!< USB USB_ALTMSK_REG: USB_M_RESET (Bit 6)                     */
#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk    (0x40UL)                  /*!< USB USB_ALTMSK_REG: USB_M_RESET (Bitfield-Mask: 0x01)       */
#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos   (7UL)                     /*!< USB USB_ALTMSK_REG: USB_M_RESUME (Bit 7)                    */
#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk   (0x80UL)                  /*!< USB USB_ALTMSK_REG: USB_M_RESUME (Bitfield-Mask: 0x01)      */

/* ------------------------------  USB_USB_TXEV_REG  ------------------------------ */
#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos     (0UL)                     /*!< USB USB_TXEV_REG: USB_TXFIFO31 (Bit 0)                      */
#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk     (0x7UL)                   /*!< USB USB_TXEV_REG: USB_TXFIFO31 (Bitfield-Mask: 0x07)        */
#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos    (4UL)                     /*!< USB USB_TXEV_REG: USB_TXUDRRN31 (Bit 4)                     */
#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk    (0x70UL)                  /*!< USB USB_TXEV_REG: USB_TXUDRRN31 (Bitfield-Mask: 0x07)       */

/* ------------------------------  USB_USB_TXMSK_REG  ----------------------------- */
#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos  (0UL)                     /*!< USB USB_TXMSK_REG: USB_M_TXFIFO31 (Bit 0)                   */
#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk  (0x7UL)                   /*!< USB USB_TXMSK_REG: USB_M_TXFIFO31 (Bitfield-Mask: 0x07)     */
#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos (4UL)                     /*!< USB USB_TXMSK_REG: USB_M_TXUDRRN31 (Bit 4)                  */
#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk (0x70UL)                  /*!< USB USB_TXMSK_REG: USB_M_TXUDRRN31 (Bitfield-Mask: 0x07)    */

/* ------------------------------  USB_USB_RXEV_REG  ------------------------------ */
#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos     (0UL)                     /*!< USB USB_RXEV_REG: USB_RXFIFO31 (Bit 0)                      */
#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk     (0x7UL)                   /*!< USB USB_RXEV_REG: USB_RXFIFO31 (Bitfield-Mask: 0x07)        */
#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos    (4UL)                     /*!< USB USB_RXEV_REG: USB_RXOVRRN31 (Bit 4)                     */
#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk    (0x70UL)                  /*!< USB USB_RXEV_REG: USB_RXOVRRN31 (Bitfield-Mask: 0x07)       */

/* ------------------------------  USB_USB_RXMSK_REG  ----------------------------- */
#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos  (0UL)                     /*!< USB USB_RXMSK_REG: USB_M_RXFIFO31 (Bit 0)                   */
#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk  (0x7UL)                   /*!< USB USB_RXMSK_REG: USB_M_RXFIFO31 (Bitfield-Mask: 0x07)     */
#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos (4UL)                     /*!< USB USB_RXMSK_REG: USB_M_RXOVRRN31 (Bit 4)                  */
#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk (0x70UL)                  /*!< USB USB_RXMSK_REG: USB_M_RXOVRRN31 (Bitfield-Mask: 0x07)    */

/* ------------------------------  USB_USB_NAKEV_REG  ----------------------------- */
#define USB_USB_NAKEV_REG_USB_IN31_Pos        (0UL)                     /*!< USB USB_NAKEV_REG: USB_IN31 (Bit 0)                         */
#define USB_USB_NAKEV_REG_USB_IN31_Msk        (0x7UL)                   /*!< USB USB_NAKEV_REG: USB_IN31 (Bitfield-Mask: 0x07)           */
#define USB_USB_NAKEV_REG_USB_OUT31_Pos       (4UL)                     /*!< USB USB_NAKEV_REG: USB_OUT31 (Bit 4)                        */
#define USB_USB_NAKEV_REG_USB_OUT31_Msk       (0x70UL)                  /*!< USB USB_NAKEV_REG: USB_OUT31 (Bitfield-Mask: 0x07)          */

/* -----------------------------  USB_USB_NAKMSK_REG  ----------------------------- */
#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos     (0UL)                     /*!< USB USB_NAKMSK_REG: USB_M_IN31 (Bit 0)                      */
#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk     (0x7UL)                   /*!< USB USB_NAKMSK_REG: USB_M_IN31 (Bitfield-Mask: 0x07)        */
#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos    (4UL)                     /*!< USB USB_NAKMSK_REG: USB_M_OUT31 (Bit 4)                     */
#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk    (0x70UL)                  /*!< USB USB_NAKMSK_REG: USB_M_OUT31 (Bitfield-Mask: 0x07)       */

/* ------------------------------  USB_USB_FWEV_REG  ------------------------------ */
#define USB_USB_FWEV_REG_USB_TXWARN31_Pos     (0UL)                     /*!< USB USB_FWEV_REG: USB_TXWARN31 (Bit 0)                      */
#define USB_USB_FWEV_REG_USB_TXWARN31_Msk     (0x7UL)                   /*!< USB USB_FWEV_REG: USB_TXWARN31 (Bitfield-Mask: 0x07)        */
#define USB_USB_FWEV_REG_USB_RXWARN31_Pos     (4UL)                     /*!< USB USB_FWEV_REG: USB_RXWARN31 (Bit 4)                      */
#define USB_USB_FWEV_REG_USB_RXWARN31_Msk     (0x70UL)                  /*!< USB USB_FWEV_REG: USB_RXWARN31 (Bitfield-Mask: 0x07)        */

/* ------------------------------  USB_USB_FWMSK_REG  ----------------------------- */
#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos  (0UL)                     /*!< USB USB_FWMSK_REG: USB_M_TXWARN31 (Bit 0)                   */
#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk  (0x7UL)                   /*!< USB USB_FWMSK_REG: USB_M_TXWARN31 (Bitfield-Mask: 0x07)     */
#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos  (4UL)                     /*!< USB USB_FWMSK_REG: USB_M_RXWARN31 (Bit 4)                   */
#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk  (0x70UL)                  /*!< USB USB_FWMSK_REG: USB_M_RXWARN31 (Bitfield-Mask: 0x07)     */

/* -------------------------------  USB_USB_FNH_REG  ------------------------------ */
#define USB_USB_FNH_REG_USB_FN_10_8_Pos       (0UL)                     /*!< USB USB_FNH_REG: USB_FN_10_8 (Bit 0)                        */
#define USB_USB_FNH_REG_USB_FN_10_8_Msk       (0x7UL)                   /*!< USB USB_FNH_REG: USB_FN_10_8 (Bitfield-Mask: 0x07)          */
#define USB_USB_FNH_REG_USB_RFC_Pos           (5UL)                     /*!< USB USB_FNH_REG: USB_RFC (Bit 5)                            */
#define USB_USB_FNH_REG_USB_RFC_Msk           (0x20UL)                  /*!< USB USB_FNH_REG: USB_RFC (Bitfield-Mask: 0x01)              */
#define USB_USB_FNH_REG_USB_UL_Pos            (6UL)                     /*!< USB USB_FNH_REG: USB_UL (Bit 6)                             */
#define USB_USB_FNH_REG_USB_UL_Msk            (0x40UL)                  /*!< USB USB_FNH_REG: USB_UL (Bitfield-Mask: 0x01)               */
#define USB_USB_FNH_REG_USB_MF_Pos            (7UL)                     /*!< USB USB_FNH_REG: USB_MF (Bit 7)                             */
#define USB_USB_FNH_REG_USB_MF_Msk            (0x80UL)                  /*!< USB USB_FNH_REG: USB_MF (Bitfield-Mask: 0x01)               */

/* -------------------------------  USB_USB_FNL_REG  ------------------------------ */
#define USB_USB_FNL_REG_USB_FN_Pos            (0UL)                     /*!< USB USB_FNL_REG: USB_FN (Bit 0)                             */
#define USB_USB_FNL_REG_USB_FN_Msk            (0xffUL)                  /*!< USB USB_FNL_REG: USB_FN (Bitfield-Mask: 0xff)               */

/* -----------------------------  USB_USB_UX20CDR_REG  ---------------------------- */
#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos  (0UL)                     /*!< USB USB_UX20CDR_REG: RPU_SSPROTEN (Bit 0)                   */
#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk  (0x1UL)                   /*!< USB USB_UX20CDR_REG: RPU_SSPROTEN (Bitfield-Mask: 0x01)     */
#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos   (1UL)                     /*!< USB USB_UX20CDR_REG: RPU_RCDELAY (Bit 1)                    */
#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk   (0x2UL)                   /*!< USB USB_UX20CDR_REG: RPU_RCDELAY (Bitfield-Mask: 0x01)      */
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos (2UL)                    /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1DM (Bit 2)                 */
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk (0x4UL)                  /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1DM (Bitfield-Mask: 0x01)   */
#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos   (4UL)                     /*!< USB USB_UX20CDR_REG: RPU_TEST_EN (Bit 4)                    */
#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk   (0x10UL)                  /*!< USB USB_UX20CDR_REG: RPU_TEST_EN (Bitfield-Mask: 0x01)      */
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos  (5UL)                     /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1 (Bit 5)                   */
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk  (0x20UL)                  /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1 (Bitfield-Mask: 0x01)     */
#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos  (6UL)                     /*!< USB USB_UX20CDR_REG: RPU_TEST_SW2 (Bit 6)                   */
#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk  (0x40UL)                  /*!< USB USB_UX20CDR_REG: RPU_TEST_SW2 (Bitfield-Mask: 0x01)     */
#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos     (7UL)                     /*!< USB USB_UX20CDR_REG: RPU_TEST7 (Bit 7)                      */
#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk     (0x80UL)                  /*!< USB USB_UX20CDR_REG: RPU_TEST7 (Bitfield-Mask: 0x01)        */

/* ------------------------------  USB_USB_EPC0_REG  ------------------------------ */
#define USB_USB_EPC0_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC0_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC0_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC0_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC0_REG_USB_DEF_Pos          (6UL)                     /*!< USB USB_EPC0_REG: USB_DEF (Bit 6)                           */
#define USB_USB_EPC0_REG_USB_DEF_Msk          (0x40UL)                  /*!< USB USB_EPC0_REG: USB_DEF (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC0_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC0_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC0_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC0_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_TXD0_REG  ------------------------------ */
#define USB_USB_TXD0_REG_USB_TXFD_Pos         (0UL)                     /*!< USB USB_TXD0_REG: USB_TXFD (Bit 0)                          */
#define USB_USB_TXD0_REG_USB_TXFD_Msk         (0xffUL)                  /*!< USB USB_TXD0_REG: USB_TXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_TXS0_REG  ------------------------------ */
#define USB_USB_TXS0_REG_USB_TCOUNT_Pos       (0UL)                     /*!< USB USB_TXS0_REG: USB_TCOUNT (Bit 0)                        */
#define USB_USB_TXS0_REG_USB_TCOUNT_Msk       (0x1fUL)                  /*!< USB USB_TXS0_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)          */
#define USB_USB_TXS0_REG_USB_TX_DONE_Pos      (5UL)                     /*!< USB USB_TXS0_REG: USB_TX_DONE (Bit 5)                       */
#define USB_USB_TXS0_REG_USB_TX_DONE_Msk      (0x20UL)                  /*!< USB USB_TXS0_REG: USB_TX_DONE (Bitfield-Mask: 0x01)         */
#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos     (6UL)                     /*!< USB USB_TXS0_REG: USB_ACK_STAT (Bit 6)                      */
#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk     (0x40UL)                  /*!< USB USB_TXS0_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)        */

/* ------------------------------  USB_USB_TXC0_REG  ------------------------------ */
#define USB_USB_TXC0_REG_USB_TX_EN_Pos        (0UL)                     /*!< USB USB_TXC0_REG: USB_TX_EN (Bit 0)                         */
#define USB_USB_TXC0_REG_USB_TX_EN_Msk        (0x1UL)                   /*!< USB USB_TXC0_REG: USB_TX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos   (2UL)                     /*!< USB USB_TXC0_REG: USB_TOGGLE_TX0 (Bit 2)                    */
#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk   (0x4UL)                   /*!< USB USB_TXC0_REG: USB_TOGGLE_TX0 (Bitfield-Mask: 0x01)      */
#define USB_USB_TXC0_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_TXC0_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_TXC0_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_TXC0_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC0_REG_USB_IGN_IN_Pos       (4UL)                     /*!< USB USB_TXC0_REG: USB_IGN_IN (Bit 4)                        */
#define USB_USB_TXC0_REG_USB_IGN_IN_Msk       (0x10UL)                  /*!< USB USB_TXC0_REG: USB_IGN_IN (Bitfield-Mask: 0x01)          */

/* -----------------------------  USB_USB_EP0_NAK_REG  ---------------------------- */
#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos (0UL)                     /*!< USB USB_EP0_NAK_REG: USB_EP0_INNAK (Bit 0)                  */
#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk (0x1UL)                   /*!< USB USB_EP0_NAK_REG: USB_EP0_INNAK (Bitfield-Mask: 0x01)    */
#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos (1UL)                    /*!< USB USB_EP0_NAK_REG: USB_EP0_OUTNAK (Bit 1)                 */
#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk (0x2UL)                  /*!< USB USB_EP0_NAK_REG: USB_EP0_OUTNAK (Bitfield-Mask: 0x01)   */

/* ------------------------------  USB_USB_RXD0_REG  ------------------------------ */
#define USB_USB_RXD0_REG_USB_RXFD_Pos         (0UL)                     /*!< USB USB_RXD0_REG: USB_RXFD (Bit 0)                          */
#define USB_USB_RXD0_REG_USB_RXFD_Msk         (0xffUL)                  /*!< USB USB_RXD0_REG: USB_RXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_RXS0_REG  ------------------------------ */
#define USB_USB_RXS0_REG_USB_RCOUNT_Pos       (0UL)                     /*!< USB USB_RXS0_REG: USB_RCOUNT (Bit 0)                        */
#define USB_USB_RXS0_REG_USB_RCOUNT_Msk       (0xfUL)                   /*!< USB USB_RXS0_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)          */
#define USB_USB_RXS0_REG_USB_RX_LAST_Pos      (4UL)                     /*!< USB USB_RXS0_REG: USB_RX_LAST (Bit 4)                       */
#define USB_USB_RXS0_REG_USB_RX_LAST_Msk      (0x10UL)                  /*!< USB USB_RXS0_REG: USB_RX_LAST (Bitfield-Mask: 0x01)         */
#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos   (5UL)                     /*!< USB USB_RXS0_REG: USB_TOGGLE_RX0 (Bit 5)                    */
#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk   (0x20UL)                  /*!< USB USB_RXS0_REG: USB_TOGGLE_RX0 (Bitfield-Mask: 0x01)      */
#define USB_USB_RXS0_REG_USB_SETUP_Pos        (6UL)                     /*!< USB USB_RXS0_REG: USB_SETUP (Bit 6)                         */
#define USB_USB_RXS0_REG_USB_SETUP_Msk        (0x40UL)                  /*!< USB USB_RXS0_REG: USB_SETUP (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_RXC0_REG  ------------------------------ */
#define USB_USB_RXC0_REG_USB_RX_EN_Pos        (0UL)                     /*!< USB USB_RXC0_REG: USB_RX_EN (Bit 0)                         */
#define USB_USB_RXC0_REG_USB_RX_EN_Msk        (0x1UL)                   /*!< USB USB_RXC0_REG: USB_RX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos      (1UL)                     /*!< USB USB_RXC0_REG: USB_IGN_OUT (Bit 1)                       */
#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk      (0x2UL)                   /*!< USB USB_RXC0_REG: USB_IGN_OUT (Bitfield-Mask: 0x01)         */
#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos    (2UL)                     /*!< USB USB_RXC0_REG: USB_IGN_SETUP (Bit 2)                     */
#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk    (0x4UL)                   /*!< USB USB_RXC0_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)       */
#define USB_USB_RXC0_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_RXC0_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_RXC0_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_RXC0_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_EPC1_REG  ------------------------------ */
#define USB_USB_EPC1_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC1_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC1_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC1_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC1_REG_USB_EP_EN_Pos        (4UL)                     /*!< USB USB_EPC1_REG: USB_EP_EN (Bit 4)                         */
#define USB_USB_EPC1_REG_USB_EP_EN_Msk        (0x10UL)                  /*!< USB USB_EPC1_REG: USB_EP_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_EPC1_REG_USB_ISO_Pos          (5UL)                     /*!< USB USB_EPC1_REG: USB_ISO (Bit 5)                           */
#define USB_USB_EPC1_REG_USB_ISO_Msk          (0x20UL)                  /*!< USB USB_EPC1_REG: USB_ISO (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC1_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC1_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC1_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC1_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_TXD1_REG  ------------------------------ */
#define USB_USB_TXD1_REG_USB_TXFD_Pos         (0UL)                     /*!< USB USB_TXD1_REG: USB_TXFD (Bit 0)                          */
#define USB_USB_TXD1_REG_USB_TXFD_Msk         (0xffUL)                  /*!< USB USB_TXD1_REG: USB_TXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_TXS1_REG  ------------------------------ */
#define USB_USB_TXS1_REG_USB_TCOUNT_Pos       (0UL)                     /*!< USB USB_TXS1_REG: USB_TCOUNT (Bit 0)                        */
#define USB_USB_TXS1_REG_USB_TCOUNT_Msk       (0x1fUL)                  /*!< USB USB_TXS1_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)          */
#define USB_USB_TXS1_REG_USB_TX_DONE_Pos      (5UL)                     /*!< USB USB_TXS1_REG: USB_TX_DONE (Bit 5)                       */
#define USB_USB_TXS1_REG_USB_TX_DONE_Msk      (0x20UL)                  /*!< USB USB_TXS1_REG: USB_TX_DONE (Bitfield-Mask: 0x01)         */
#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos     (6UL)                     /*!< USB USB_TXS1_REG: USB_ACK_STAT (Bit 6)                      */
#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk     (0x40UL)                  /*!< USB USB_TXS1_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)        */
#define USB_USB_TXS1_REG_USB_TX_URUN_Pos      (7UL)                     /*!< USB USB_TXS1_REG: USB_TX_URUN (Bit 7)                       */
#define USB_USB_TXS1_REG_USB_TX_URUN_Msk      (0x80UL)                  /*!< USB USB_TXS1_REG: USB_TX_URUN (Bitfield-Mask: 0x01)         */

/* ------------------------------  USB_USB_TXC1_REG  ------------------------------ */
#define USB_USB_TXC1_REG_USB_TX_EN_Pos        (0UL)                     /*!< USB USB_TXC1_REG: USB_TX_EN (Bit 0)                         */
#define USB_USB_TXC1_REG_USB_TX_EN_Msk        (0x1UL)                   /*!< USB USB_TXC1_REG: USB_TX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC1_REG_USB_LAST_Pos         (1UL)                     /*!< USB USB_TXC1_REG: USB_LAST (Bit 1)                          */
#define USB_USB_TXC1_REG_USB_LAST_Msk         (0x2UL)                   /*!< USB USB_TXC1_REG: USB_LAST (Bitfield-Mask: 0x01)            */
#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos    (2UL)                     /*!< USB USB_TXC1_REG: USB_TOGGLE_TX (Bit 2)                     */
#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk    (0x4UL)                   /*!< USB USB_TXC1_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01)       */
#define USB_USB_TXC1_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_TXC1_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_TXC1_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_TXC1_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC1_REG_USB_RFF_Pos          (4UL)                     /*!< USB USB_TXC1_REG: USB_RFF (Bit 4)                           */
#define USB_USB_TXC1_REG_USB_RFF_Msk          (0x10UL)                  /*!< USB USB_TXC1_REG: USB_RFF (Bitfield-Mask: 0x01)             */
#define USB_USB_TXC1_REG_USB_TFWL_Pos         (5UL)                     /*!< USB USB_TXC1_REG: USB_TFWL (Bit 5)                          */
#define USB_USB_TXC1_REG_USB_TFWL_Msk         (0x60UL)                  /*!< USB USB_TXC1_REG: USB_TFWL (Bitfield-Mask: 0x03)            */
#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos   (7UL)                     /*!< USB USB_TXC1_REG: USB_IGN_ISOMSK (Bit 7)                    */
#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk   (0x80UL)                  /*!< USB USB_TXC1_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01)      */

/* ------------------------------  USB_USB_EPC2_REG  ------------------------------ */
#define USB_USB_EPC2_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC2_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC2_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC2_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC2_REG_USB_EP_EN_Pos        (4UL)                     /*!< USB USB_EPC2_REG: USB_EP_EN (Bit 4)                         */
#define USB_USB_EPC2_REG_USB_EP_EN_Msk        (0x10UL)                  /*!< USB USB_EPC2_REG: USB_EP_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_EPC2_REG_USB_ISO_Pos          (5UL)                     /*!< USB USB_EPC2_REG: USB_ISO (Bit 5)                           */
#define USB_USB_EPC2_REG_USB_ISO_Msk          (0x20UL)                  /*!< USB USB_EPC2_REG: USB_ISO (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC2_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC2_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC2_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC2_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_RXD1_REG  ------------------------------ */
#define USB_USB_RXD1_REG_USB_RXFD_Pos         (0UL)                     /*!< USB USB_RXD1_REG: USB_RXFD (Bit 0)                          */
#define USB_USB_RXD1_REG_USB_RXFD_Msk         (0xffUL)                  /*!< USB USB_RXD1_REG: USB_RXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_RXS1_REG  ------------------------------ */
#define USB_USB_RXS1_REG_USB_RCOUNT_Pos       (0UL)                     /*!< USB USB_RXS1_REG: USB_RCOUNT (Bit 0)                        */
#define USB_USB_RXS1_REG_USB_RCOUNT_Msk       (0xfUL)                   /*!< USB USB_RXS1_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)          */
#define USB_USB_RXS1_REG_USB_RX_LAST_Pos      (4UL)                     /*!< USB USB_RXS1_REG: USB_RX_LAST (Bit 4)                       */
#define USB_USB_RXS1_REG_USB_RX_LAST_Msk      (0x10UL)                  /*!< USB USB_RXS1_REG: USB_RX_LAST (Bitfield-Mask: 0x01)         */
#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos    (5UL)                     /*!< USB USB_RXS1_REG: USB_TOGGLE_RX (Bit 5)                     */
#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk    (0x20UL)                  /*!< USB USB_RXS1_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01)       */
#define USB_USB_RXS1_REG_USB_SETUP_Pos        (6UL)                     /*!< USB USB_RXS1_REG: USB_SETUP (Bit 6)                         */
#define USB_USB_RXS1_REG_USB_SETUP_Msk        (0x40UL)                  /*!< USB USB_RXS1_REG: USB_SETUP (Bitfield-Mask: 0x01)           */
#define USB_USB_RXS1_REG_USB_RX_ERR_Pos       (7UL)                     /*!< USB USB_RXS1_REG: USB_RX_ERR (Bit 7)                        */
#define USB_USB_RXS1_REG_USB_RX_ERR_Msk       (0x80UL)                  /*!< USB USB_RXS1_REG: USB_RX_ERR (Bitfield-Mask: 0x01)          */

/* ------------------------------  USB_USB_RXC1_REG  ------------------------------ */
#define USB_USB_RXC1_REG_USB_RX_EN_Pos        (0UL)                     /*!< USB USB_RXC1_REG: USB_RX_EN (Bit 0)                         */
#define USB_USB_RXC1_REG_USB_RX_EN_Msk        (0x1UL)                   /*!< USB USB_RXC1_REG: USB_RX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos    (2UL)                     /*!< USB USB_RXC1_REG: USB_IGN_SETUP (Bit 2)                     */
#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk    (0x4UL)                   /*!< USB USB_RXC1_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)       */
#define USB_USB_RXC1_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_RXC1_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_RXC1_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_RXC1_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC1_REG_USB_RFWL_Pos         (5UL)                     /*!< USB USB_RXC1_REG: USB_RFWL (Bit 5)                          */
#define USB_USB_RXC1_REG_USB_RFWL_Msk         (0x60UL)                  /*!< USB USB_RXC1_REG: USB_RFWL (Bitfield-Mask: 0x03)            */

/* ------------------------------  USB_USB_EPC3_REG  ------------------------------ */
#define USB_USB_EPC3_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC3_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC3_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC3_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC3_REG_USB_EP_EN_Pos        (4UL)                     /*!< USB USB_EPC3_REG: USB_EP_EN (Bit 4)                         */
#define USB_USB_EPC3_REG_USB_EP_EN_Msk        (0x10UL)                  /*!< USB USB_EPC3_REG: USB_EP_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_EPC3_REG_USB_ISO_Pos          (5UL)                     /*!< USB USB_EPC3_REG: USB_ISO (Bit 5)                           */
#define USB_USB_EPC3_REG_USB_ISO_Msk          (0x20UL)                  /*!< USB USB_EPC3_REG: USB_ISO (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC3_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC3_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC3_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC3_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_TXD2_REG  ------------------------------ */
#define USB_USB_TXD2_REG_USB_TXFD_Pos         (0UL)                     /*!< USB USB_TXD2_REG: USB_TXFD (Bit 0)                          */
#define USB_USB_TXD2_REG_USB_TXFD_Msk         (0xffUL)                  /*!< USB USB_TXD2_REG: USB_TXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_TXS2_REG  ------------------------------ */
#define USB_USB_TXS2_REG_USB_TCOUNT_Pos       (0UL)                     /*!< USB USB_TXS2_REG: USB_TCOUNT (Bit 0)                        */
#define USB_USB_TXS2_REG_USB_TCOUNT_Msk       (0x1fUL)                  /*!< USB USB_TXS2_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)          */
#define USB_USB_TXS2_REG_USB_TX_DONE_Pos      (5UL)                     /*!< USB USB_TXS2_REG: USB_TX_DONE (Bit 5)                       */
#define USB_USB_TXS2_REG_USB_TX_DONE_Msk      (0x20UL)                  /*!< USB USB_TXS2_REG: USB_TX_DONE (Bitfield-Mask: 0x01)         */
#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos     (6UL)                     /*!< USB USB_TXS2_REG: USB_ACK_STAT (Bit 6)                      */
#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk     (0x40UL)                  /*!< USB USB_TXS2_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)        */
#define USB_USB_TXS2_REG_USB_TX_URUN_Pos      (7UL)                     /*!< USB USB_TXS2_REG: USB_TX_URUN (Bit 7)                       */
#define USB_USB_TXS2_REG_USB_TX_URUN_Msk      (0x80UL)                  /*!< USB USB_TXS2_REG: USB_TX_URUN (Bitfield-Mask: 0x01)         */

/* ------------------------------  USB_USB_TXC2_REG  ------------------------------ */
#define USB_USB_TXC2_REG_USB_TX_EN_Pos        (0UL)                     /*!< USB USB_TXC2_REG: USB_TX_EN (Bit 0)                         */
#define USB_USB_TXC2_REG_USB_TX_EN_Msk        (0x1UL)                   /*!< USB USB_TXC2_REG: USB_TX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC2_REG_USB_LAST_Pos         (1UL)                     /*!< USB USB_TXC2_REG: USB_LAST (Bit 1)                          */
#define USB_USB_TXC2_REG_USB_LAST_Msk         (0x2UL)                   /*!< USB USB_TXC2_REG: USB_LAST (Bitfield-Mask: 0x01)            */
#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos    (2UL)                     /*!< USB USB_TXC2_REG: USB_TOGGLE_TX (Bit 2)                     */
#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk    (0x4UL)                   /*!< USB USB_TXC2_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01)       */
#define USB_USB_TXC2_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_TXC2_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_TXC2_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_TXC2_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC2_REG_USB_RFF_Pos          (4UL)                     /*!< USB USB_TXC2_REG: USB_RFF (Bit 4)                           */
#define USB_USB_TXC2_REG_USB_RFF_Msk          (0x10UL)                  /*!< USB USB_TXC2_REG: USB_RFF (Bitfield-Mask: 0x01)             */
#define USB_USB_TXC2_REG_USB_TFWL_Pos         (5UL)                     /*!< USB USB_TXC2_REG: USB_TFWL (Bit 5)                          */
#define USB_USB_TXC2_REG_USB_TFWL_Msk         (0x60UL)                  /*!< USB USB_TXC2_REG: USB_TFWL (Bitfield-Mask: 0x03)            */
#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos   (7UL)                     /*!< USB USB_TXC2_REG: USB_IGN_ISOMSK (Bit 7)                    */
#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk   (0x80UL)                  /*!< USB USB_TXC2_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01)      */

/* ------------------------------  USB_USB_EPC4_REG  ------------------------------ */
#define USB_USB_EPC4_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC4_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC4_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC4_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC4_REG_USB_EP_EN_Pos        (4UL)                     /*!< USB USB_EPC4_REG: USB_EP_EN (Bit 4)                         */
#define USB_USB_EPC4_REG_USB_EP_EN_Msk        (0x10UL)                  /*!< USB USB_EPC4_REG: USB_EP_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_EPC4_REG_USB_ISO_Pos          (5UL)                     /*!< USB USB_EPC4_REG: USB_ISO (Bit 5)                           */
#define USB_USB_EPC4_REG_USB_ISO_Msk          (0x20UL)                  /*!< USB USB_EPC4_REG: USB_ISO (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC4_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC4_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC4_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC4_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_RXD2_REG  ------------------------------ */
#define USB_USB_RXD2_REG_USB_RXFD_Pos         (0UL)                     /*!< USB USB_RXD2_REG: USB_RXFD (Bit 0)                          */
#define USB_USB_RXD2_REG_USB_RXFD_Msk         (0xffUL)                  /*!< USB USB_RXD2_REG: USB_RXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_RXS2_REG  ------------------------------ */
#define USB_USB_RXS2_REG_USB_RCOUNT_Pos       (0UL)                     /*!< USB USB_RXS2_REG: USB_RCOUNT (Bit 0)                        */
#define USB_USB_RXS2_REG_USB_RCOUNT_Msk       (0xfUL)                   /*!< USB USB_RXS2_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)          */
#define USB_USB_RXS2_REG_USB_RX_LAST_Pos      (4UL)                     /*!< USB USB_RXS2_REG: USB_RX_LAST (Bit 4)                       */
#define USB_USB_RXS2_REG_USB_RX_LAST_Msk      (0x10UL)                  /*!< USB USB_RXS2_REG: USB_RX_LAST (Bitfield-Mask: 0x01)         */
#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos    (5UL)                     /*!< USB USB_RXS2_REG: USB_TOGGLE_RX (Bit 5)                     */
#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk    (0x20UL)                  /*!< USB USB_RXS2_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01)       */
#define USB_USB_RXS2_REG_USB_SETUP_Pos        (6UL)                     /*!< USB USB_RXS2_REG: USB_SETUP (Bit 6)                         */
#define USB_USB_RXS2_REG_USB_SETUP_Msk        (0x40UL)                  /*!< USB USB_RXS2_REG: USB_SETUP (Bitfield-Mask: 0x01)           */
#define USB_USB_RXS2_REG_USB_RX_ERR_Pos       (7UL)                     /*!< USB USB_RXS2_REG: USB_RX_ERR (Bit 7)                        */
#define USB_USB_RXS2_REG_USB_RX_ERR_Msk       (0x80UL)                  /*!< USB USB_RXS2_REG: USB_RX_ERR (Bitfield-Mask: 0x01)          */

/* ------------------------------  USB_USB_RXC2_REG  ------------------------------ */
#define USB_USB_RXC2_REG_USB_RX_EN_Pos        (0UL)                     /*!< USB USB_RXC2_REG: USB_RX_EN (Bit 0)                         */
#define USB_USB_RXC2_REG_USB_RX_EN_Msk        (0x1UL)                   /*!< USB USB_RXC2_REG: USB_RX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos    (2UL)                     /*!< USB USB_RXC2_REG: USB_IGN_SETUP (Bit 2)                     */
#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk    (0x4UL)                   /*!< USB USB_RXC2_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)       */
#define USB_USB_RXC2_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_RXC2_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_RXC2_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_RXC2_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC2_REG_USB_RFWL_Pos         (5UL)                     /*!< USB USB_RXC2_REG: USB_RFWL (Bit 5)                          */
#define USB_USB_RXC2_REG_USB_RFWL_Msk         (0x60UL)                  /*!< USB USB_RXC2_REG: USB_RFWL (Bitfield-Mask: 0x03)            */

/* ------------------------------  USB_USB_EPC5_REG  ------------------------------ */
#define USB_USB_EPC5_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC5_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC5_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC5_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC5_REG_USB_EP_EN_Pos        (4UL)                     /*!< USB USB_EPC5_REG: USB_EP_EN (Bit 4)                         */
#define USB_USB_EPC5_REG_USB_EP_EN_Msk        (0x10UL)                  /*!< USB USB_EPC5_REG: USB_EP_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_EPC5_REG_USB_ISO_Pos          (5UL)                     /*!< USB USB_EPC5_REG: USB_ISO (Bit 5)                           */
#define USB_USB_EPC5_REG_USB_ISO_Msk          (0x20UL)                  /*!< USB USB_EPC5_REG: USB_ISO (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC5_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC5_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC5_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC5_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_TXD3_REG  ------------------------------ */
#define USB_USB_TXD3_REG_USB_TXFD_Pos         (0UL)                     /*!< USB USB_TXD3_REG: USB_TXFD (Bit 0)                          */
#define USB_USB_TXD3_REG_USB_TXFD_Msk         (0xffUL)                  /*!< USB USB_TXD3_REG: USB_TXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_TXS3_REG  ------------------------------ */
#define USB_USB_TXS3_REG_USB_TCOUNT_Pos       (0UL)                     /*!< USB USB_TXS3_REG: USB_TCOUNT (Bit 0)                        */
#define USB_USB_TXS3_REG_USB_TCOUNT_Msk       (0x1fUL)                  /*!< USB USB_TXS3_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)          */
#define USB_USB_TXS3_REG_USB_TX_DONE_Pos      (5UL)                     /*!< USB USB_TXS3_REG: USB_TX_DONE (Bit 5)                       */
#define USB_USB_TXS3_REG_USB_TX_DONE_Msk      (0x20UL)                  /*!< USB USB_TXS3_REG: USB_TX_DONE (Bitfield-Mask: 0x01)         */
#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos     (6UL)                     /*!< USB USB_TXS3_REG: USB_ACK_STAT (Bit 6)                      */
#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk     (0x40UL)                  /*!< USB USB_TXS3_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)        */
#define USB_USB_TXS3_REG_USB_TX_URUN_Pos      (7UL)                     /*!< USB USB_TXS3_REG: USB_TX_URUN (Bit 7)                       */
#define USB_USB_TXS3_REG_USB_TX_URUN_Msk      (0x80UL)                  /*!< USB USB_TXS3_REG: USB_TX_URUN (Bitfield-Mask: 0x01)         */

/* ------------------------------  USB_USB_TXC3_REG  ------------------------------ */
#define USB_USB_TXC3_REG_USB_TX_EN_Pos        (0UL)                     /*!< USB USB_TXC3_REG: USB_TX_EN (Bit 0)                         */
#define USB_USB_TXC3_REG_USB_TX_EN_Msk        (0x1UL)                   /*!< USB USB_TXC3_REG: USB_TX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC3_REG_USB_LAST_Pos         (1UL)                     /*!< USB USB_TXC3_REG: USB_LAST (Bit 1)                          */
#define USB_USB_TXC3_REG_USB_LAST_Msk         (0x2UL)                   /*!< USB USB_TXC3_REG: USB_LAST (Bitfield-Mask: 0x01)            */
#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos    (2UL)                     /*!< USB USB_TXC3_REG: USB_TOGGLE_TX (Bit 2)                     */
#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk    (0x4UL)                   /*!< USB USB_TXC3_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01)       */
#define USB_USB_TXC3_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_TXC3_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_TXC3_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_TXC3_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_TXC3_REG_USB_RFF_Pos          (4UL)                     /*!< USB USB_TXC3_REG: USB_RFF (Bit 4)                           */
#define USB_USB_TXC3_REG_USB_RFF_Msk          (0x10UL)                  /*!< USB USB_TXC3_REG: USB_RFF (Bitfield-Mask: 0x01)             */
#define USB_USB_TXC3_REG_USB_TFWL_Pos         (5UL)                     /*!< USB USB_TXC3_REG: USB_TFWL (Bit 5)                          */
#define USB_USB_TXC3_REG_USB_TFWL_Msk         (0x60UL)                  /*!< USB USB_TXC3_REG: USB_TFWL (Bitfield-Mask: 0x03)            */
#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos   (7UL)                     /*!< USB USB_TXC3_REG: USB_IGN_ISOMSK (Bit 7)                    */
#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk   (0x80UL)                  /*!< USB USB_TXC3_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01)      */

/* ------------------------------  USB_USB_EPC6_REG  ------------------------------ */
#define USB_USB_EPC6_REG_USB_EP_Pos           (0UL)                     /*!< USB USB_EPC6_REG: USB_EP (Bit 0)                            */
#define USB_USB_EPC6_REG_USB_EP_Msk           (0xfUL)                   /*!< USB USB_EPC6_REG: USB_EP (Bitfield-Mask: 0x0f)              */
#define USB_USB_EPC6_REG_USB_EP_EN_Pos        (4UL)                     /*!< USB USB_EPC6_REG: USB_EP_EN (Bit 4)                         */
#define USB_USB_EPC6_REG_USB_EP_EN_Msk        (0x10UL)                  /*!< USB USB_EPC6_REG: USB_EP_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_EPC6_REG_USB_ISO_Pos          (5UL)                     /*!< USB USB_EPC6_REG: USB_ISO (Bit 5)                           */
#define USB_USB_EPC6_REG_USB_ISO_Msk          (0x20UL)                  /*!< USB USB_EPC6_REG: USB_ISO (Bitfield-Mask: 0x01)             */
#define USB_USB_EPC6_REG_USB_STALL_Pos        (7UL)                     /*!< USB USB_EPC6_REG: USB_STALL (Bit 7)                         */
#define USB_USB_EPC6_REG_USB_STALL_Msk        (0x80UL)                  /*!< USB USB_EPC6_REG: USB_STALL (Bitfield-Mask: 0x01)           */

/* ------------------------------  USB_USB_RXD3_REG  ------------------------------ */
#define USB_USB_RXD3_REG_USB_RXFD_Pos         (0UL)                     /*!< USB USB_RXD3_REG: USB_RXFD (Bit 0)                          */
#define USB_USB_RXD3_REG_USB_RXFD_Msk         (0xffUL)                  /*!< USB USB_RXD3_REG: USB_RXFD (Bitfield-Mask: 0xff)            */

/* ------------------------------  USB_USB_RXS3_REG  ------------------------------ */
#define USB_USB_RXS3_REG_USB_RCOUNT_Pos       (0UL)                     /*!< USB USB_RXS3_REG: USB_RCOUNT (Bit 0)                        */
#define USB_USB_RXS3_REG_USB_RCOUNT_Msk       (0xfUL)                   /*!< USB USB_RXS3_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)          */
#define USB_USB_RXS3_REG_USB_RX_LAST_Pos      (4UL)                     /*!< USB USB_RXS3_REG: USB_RX_LAST (Bit 4)                       */
#define USB_USB_RXS3_REG_USB_RX_LAST_Msk      (0x10UL)                  /*!< USB USB_RXS3_REG: USB_RX_LAST (Bitfield-Mask: 0x01)         */
#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos    (5UL)                     /*!< USB USB_RXS3_REG: USB_TOGGLE_RX (Bit 5)                     */
#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk    (0x20UL)                  /*!< USB USB_RXS3_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01)       */
#define USB_USB_RXS3_REG_USB_SETUP_Pos        (6UL)                     /*!< USB USB_RXS3_REG: USB_SETUP (Bit 6)                         */
#define USB_USB_RXS3_REG_USB_SETUP_Msk        (0x40UL)                  /*!< USB USB_RXS3_REG: USB_SETUP (Bitfield-Mask: 0x01)           */
#define USB_USB_RXS3_REG_USB_RX_ERR_Pos       (7UL)                     /*!< USB USB_RXS3_REG: USB_RX_ERR (Bit 7)                        */
#define USB_USB_RXS3_REG_USB_RX_ERR_Msk       (0x80UL)                  /*!< USB USB_RXS3_REG: USB_RX_ERR (Bitfield-Mask: 0x01)          */

/* ------------------------------  USB_USB_RXC3_REG  ------------------------------ */
#define USB_USB_RXC3_REG_USB_RX_EN_Pos        (0UL)                     /*!< USB USB_RXC3_REG: USB_RX_EN (Bit 0)                         */
#define USB_USB_RXC3_REG_USB_RX_EN_Msk        (0x1UL)                   /*!< USB USB_RXC3_REG: USB_RX_EN (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos    (2UL)                     /*!< USB USB_RXC3_REG: USB_IGN_SETUP (Bit 2)                     */
#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk    (0x4UL)                   /*!< USB USB_RXC3_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)       */
#define USB_USB_RXC3_REG_USB_FLUSH_Pos        (3UL)                     /*!< USB USB_RXC3_REG: USB_FLUSH (Bit 3)                         */
#define USB_USB_RXC3_REG_USB_FLUSH_Msk        (0x8UL)                   /*!< USB USB_RXC3_REG: USB_FLUSH (Bitfield-Mask: 0x01)           */
#define USB_USB_RXC3_REG_USB_RFWL_Pos         (5UL)                     /*!< USB USB_RXC3_REG: USB_RFWL (Bit 5)                          */
#define USB_USB_RXC3_REG_USB_RFWL_Msk         (0x60UL)                  /*!< USB USB_RXC3_REG: USB_RFWL (Bitfield-Mask: 0x03)            */

/* ----------------------------  USB_USB_DMA_CTRL_REG  ---------------------------- */
#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos   (0UL)                     /*!< USB USB_DMA_CTRL_REG: USB_DMA_RX (Bit 0)                    */
#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk   (0x7UL)                   /*!< USB USB_DMA_CTRL_REG: USB_DMA_RX (Bitfield-Mask: 0x07)      */
#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos   (3UL)                     /*!< USB USB_DMA_CTRL_REG: USB_DMA_TX (Bit 3)                    */
#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk   (0x38UL)                  /*!< USB USB_DMA_CTRL_REG: USB_DMA_TX (Bitfield-Mask: 0x07)      */
#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos   (6UL)                     /*!< USB USB_DMA_CTRL_REG: USB_DMA_EN (Bit 6)                    */
#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk   (0x40UL)                  /*!< USB USB_DMA_CTRL_REG: USB_DMA_EN (Bitfield-Mask: 0x01)      */

/* --------------------------  USB_USB_CHARGER_CTRL_REG  -------------------------- */
#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos (0UL)                /*!< USB USB_CHARGER_CTRL_REG: USB_CHARGE_ON (Bit 0)             */
#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk (0x1UL)              /*!< USB USB_CHARGER_CTRL_REG: USB_CHARGE_ON (Bitfield-Mask: 0x01) */
#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos (1UL)                   /*!< USB USB_CHARGER_CTRL_REG: IDP_SRC_ON (Bit 1)                */
#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk (0x2UL)                 /*!< USB USB_CHARGER_CTRL_REG: IDP_SRC_ON (Bitfield-Mask: 0x01)  */
#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos (2UL)                   /*!< USB USB_CHARGER_CTRL_REG: VDP_SRC_ON (Bit 2)                */
#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk (0x4UL)                 /*!< USB USB_CHARGER_CTRL_REG: VDP_SRC_ON (Bitfield-Mask: 0x01)  */
#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos (3UL)                   /*!< USB USB_CHARGER_CTRL_REG: VDM_SRC_ON (Bit 3)                */
#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk (0x8UL)                 /*!< USB USB_CHARGER_CTRL_REG: VDM_SRC_ON (Bitfield-Mask: 0x01)  */
#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos (4UL)                  /*!< USB USB_CHARGER_CTRL_REG: IDP_SINK_ON (Bit 4)               */
#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk (0x10UL)               /*!< USB USB_CHARGER_CTRL_REG: IDP_SINK_ON (Bitfield-Mask: 0x01) */
#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos (5UL)                  /*!< USB USB_CHARGER_CTRL_REG: IDM_SINK_ON (Bit 5)               */
#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk (0x20UL)               /*!< USB USB_CHARGER_CTRL_REG: IDM_SINK_ON (Bitfield-Mask: 0x01) */

/* --------------------------  USB_USB_CHARGER_STAT_REG  -------------------------- */
#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos (0UL)                  /*!< USB USB_CHARGER_STAT_REG: USB_DCP_DET (Bit 0)               */
#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk (0x1UL)                /*!< USB USB_CHARGER_STAT_REG: USB_DCP_DET (Bitfield-Mask: 0x01) */
#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos (1UL)                  /*!< USB USB_CHARGER_STAT_REG: USB_CHG_DET (Bit 1)               */
#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk (0x2UL)                /*!< USB USB_CHARGER_STAT_REG: USB_CHG_DET (Bitfield-Mask: 0x01) */
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos (2UL)                   /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL (Bit 2)                */
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk (0x4UL)                 /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL (Bitfield-Mask: 0x01)  */
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos (3UL)                   /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL (Bit 3)                */
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk (0x8UL)                 /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL (Bitfield-Mask: 0x01)  */
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos (4UL)                  /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL2 (Bit 4)               */
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk (0x10UL)               /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL2 (Bitfield-Mask: 0x01) */
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos (5UL)                  /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL2 (Bit 5)               */
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk (0x20UL)               /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL2 (Bitfield-Mask: 0x01) */


/* ================================================================================ */
/* ================         struct 'WAKEUP' Position & Mask        ================ */
/* ================================================================================ */


/* ----------------------------  WAKEUP_WKUP_CTRL_REG  ---------------------------- */
#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL)                   /*!< WAKEUP WKUP_CTRL_REG: WKUP_DEB_VALUE (Bit 0)                */
#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL)                /*!< WAKEUP WKUP_CTRL_REG: WKUP_DEB_VALUE (Bitfield-Mask: 0x3f)  */
#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL)                  /*!< WAKEUP WKUP_CTRL_REG: WKUP_SFT_KEYHIT (Bit 6)               */
#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL)               /*!< WAKEUP WKUP_CTRL_REG: WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01) */
#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL)                  /*!< WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bit 7)               */
#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL)               /*!< WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01) */

/* --------------------------  WAKEUP_WKUP_RESET_IRQ_REG  ------------------------- */
#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL)                /*!< WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bit 0)             */
#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL)           /*!< WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bitfield-Mask: 0xffff) */

/* --------------------------  WAKEUP_WKUP_SELECT_P0_REG  ------------------------- */
#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL)              /*!< WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bit 0)           */
#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffUL)           /*!< WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bitfield-Mask: 0xff) */

/* --------------------------  WAKEUP_WKUP_SELECT_P1_REG  ------------------------- */
#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL)              /*!< WAKEUP WKUP_SELECT_P1_REG: WKUP_SELECT_P1 (Bit 0)           */
#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0xffUL)           /*!< WAKEUP WKUP_SELECT_P1_REG: WKUP_SELECT_P1 (Bitfield-Mask: 0xff) */

/* --------------------------  WAKEUP_WKUP_SELECT_P2_REG  ------------------------- */
#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Pos (0UL)              /*!< WAKEUP WKUP_SELECT_P2_REG: WKUP_SELECT_P2 (Bit 0)           */
#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Msk (0x1fUL)           /*!< WAKEUP WKUP_SELECT_P2_REG: WKUP_SELECT_P2 (Bitfield-Mask: 0x1f) */

/* --------------------------  WAKEUP_WKUP_SELECT_P3_REG  ------------------------- */
#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Pos (0UL)              /*!< WAKEUP WKUP_SELECT_P3_REG: WKUP_SELECT_P3 (Bit 0)           */
#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Msk (0xffUL)           /*!< WAKEUP WKUP_SELECT_P3_REG: WKUP_SELECT_P3 (Bitfield-Mask: 0xff) */

/* --------------------------  WAKEUP_WKUP_SELECT_P4_REG  ------------------------- */
#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Pos (0UL)              /*!< WAKEUP WKUP_SELECT_P4_REG: WKUP_SELECT_P4 (Bit 0)           */
#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Msk (0xffUL)           /*!< WAKEUP WKUP_SELECT_P4_REG: WKUP_SELECT_P4 (Bitfield-Mask: 0xff) */

/* ---------------------------  WAKEUP_WKUP_POL_P0_REG  --------------------------- */
#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL)                    /*!< WAKEUP WKUP_POL_P0_REG: WKUP_POL_P0 (Bit 0)                 */
#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffUL)                 /*!< WAKEUP WKUP_POL_P0_REG: WKUP_POL_P0 (Bitfield-Mask: 0xff)   */

/* ---------------------------  WAKEUP_WKUP_POL_P1_REG  --------------------------- */
#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL)                    /*!< WAKEUP WKUP_POL_P1_REG: WKUP_POL_P1 (Bit 0)                 */
#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0xffUL)                 /*!< WAKEUP WKUP_POL_P1_REG: WKUP_POL_P1 (Bitfield-Mask: 0xff)   */

/* ---------------------------  WAKEUP_WKUP_POL_P2_REG  --------------------------- */
#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Pos (0UL)                    /*!< WAKEUP WKUP_POL_P2_REG: WKUP_POL_P2 (Bit 0)                 */
#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Msk (0x1fUL)                 /*!< WAKEUP WKUP_POL_P2_REG: WKUP_POL_P2 (Bitfield-Mask: 0x1f)   */

/* ---------------------------  WAKEUP_WKUP_POL_P3_REG  --------------------------- */
#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Pos (0UL)                    /*!< WAKEUP WKUP_POL_P3_REG: WKUP_POL_P3 (Bit 0)                 */
#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Msk (0xffUL)                 /*!< WAKEUP WKUP_POL_P3_REG: WKUP_POL_P3 (Bitfield-Mask: 0xff)   */

/* ---------------------------  WAKEUP_WKUP_POL_P4_REG  --------------------------- */
#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Pos (0UL)                    /*!< WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bit 0)                 */
#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Msk (0xffUL)                 /*!< WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bitfield-Mask: 0xff)   */

/* --------------------------  WAKEUP_WKUP_STATUS_0_REG  -------------------------- */
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Pos (0UL)                 /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bit 0)              */
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Msk (0xffUL)              /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bitfield-Mask: 0xff) */
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Pos (8UL)                 /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bit 8)              */
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Msk (0xff00UL)            /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bitfield-Mask: 0xff) */

/* --------------------------  WAKEUP_WKUP_STATUS_1_REG  -------------------------- */
#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Pos (0UL)                 /*!< WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bit 0)              */
#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Msk (0x1fUL)              /*!< WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bitfield-Mask: 0x1f) */

/* --------------------------  WAKEUP_WKUP_STATUS_2_REG  -------------------------- */
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Pos (0UL)                 /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bit 0)              */
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Msk (0xffUL)              /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bitfield-Mask: 0xff) */
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Pos (8UL)                 /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bit 8)              */
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Msk (0xff00UL)            /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bitfield-Mask: 0xff) */

/* ---------------------------  WAKEUP_WKUP_CLEAR_0_REG  -------------------------- */
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Pos (0UL)                 /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bit 0)              */
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Msk (0xffUL)              /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bitfield-Mask: 0xff) */
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Pos (8UL)                 /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bit 8)              */
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Msk (0xff00UL)            /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bitfield-Mask: 0xff) */

/* ---------------------------  WAKEUP_WKUP_CLEAR_1_REG  -------------------------- */
#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Pos (0UL)                 /*!< WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bit 0)              */
#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Msk (0x1fUL)              /*!< WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bitfield-Mask: 0x1f) */

/* ---------------------------  WAKEUP_WKUP_CLEAR_2_REG  -------------------------- */
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Pos (0UL)                 /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bit 0)              */
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Msk (0xffUL)              /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bitfield-Mask: 0xff) */
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Pos (8UL)                 /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bit 8)              */
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Msk (0xff00UL)            /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bitfield-Mask: 0xff) */

/* -------------------------  WAKEUP_WKUP_SEL_GPIO_P0_REG  ------------------------ */
#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL)          /*!< WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bit 0)       */
#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffUL)       /*!< WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xff) */

/* -------------------------  WAKEUP_WKUP_SEL_GPIO_P1_REG  ------------------------ */
#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL)          /*!< WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bit 0)       */
#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0xffUL)       /*!< WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0xff) */

/* -------------------------  WAKEUP_WKUP_SEL_GPIO_P2_REG  ------------------------ */
#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Pos (0UL)          /*!< WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bit 0)       */
#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Msk (0x1fUL)       /*!< WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bitfield-Mask: 0x1f) */

/* -------------------------  WAKEUP_WKUP_SEL_GPIO_P3_REG  ------------------------ */
#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Pos (0UL)          /*!< WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bit 0)       */
#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Msk (0xffUL)       /*!< WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bitfield-Mask: 0xff) */

/* -------------------------  WAKEUP_WKUP_SEL_GPIO_P4_REG  ------------------------ */
#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Pos (0UL)          /*!< WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bit 0)       */
#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Msk (0xffUL)       /*!< WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bitfield-Mask: 0xff) */


/* ================================================================================ */
/* ================          struct 'WDOG' Position & Mask         ================ */
/* ================================================================================ */


/* ------------------------------  WDOG_WATCHDOG_REG  ----------------------------- */
#define WDOG_WATCHDOG_REG_WDOG_VAL_Pos        (0UL)                     /*!< WDOG WATCHDOG_REG: WDOG_VAL (Bit 0)                         */
#define WDOG_WATCHDOG_REG_WDOG_VAL_Msk        (0xffUL)                  /*!< WDOG WATCHDOG_REG: WDOG_VAL (Bitfield-Mask: 0xff)           */
#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos    (8UL)                     /*!< WDOG WATCHDOG_REG: WDOG_VAL_NEG (Bit 8)                     */
#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk    (0x100UL)                 /*!< WDOG WATCHDOG_REG: WDOG_VAL_NEG (Bitfield-Mask: 0x01)       */
#define WDOG_WATCHDOG_REG_WDOG_WEN_Pos        (9UL)                     /*!< WDOG WATCHDOG_REG: WDOG_WEN (Bit 9)                         */
#define WDOG_WATCHDOG_REG_WDOG_WEN_Msk        (0xfe00UL)                /*!< WDOG WATCHDOG_REG: WDOG_WEN (Bitfield-Mask: 0x7f)           */

/* ---------------------------  WDOG_WATCHDOG_CTRL_REG  --------------------------- */
#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos    (0UL)                     /*!< WDOG WATCHDOG_CTRL_REG: NMI_RST (Bit 0)                     */
#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk    (0x1UL)                   /*!< WDOG WATCHDOG_CTRL_REG: NMI_RST (Bitfield-Mask: 0x01)       */


/* ================================================================================ */
/* ================              Peripheral memory map             ================ */
/* ================================================================================ */

#define AES_HASH_BASE                   0x40020000UL
#define ANAMISC_BASE                    0x50001B00UL
#define APU_BASE                        0x50004000UL
#define BLE_BASE                        0x40000000UL
#define CACHE_BASE                      0x400C3000UL
#define CHIP_VERSION_BASE               0x50003200UL
#define COEX_BASE                       0x50002F00UL
#define CRG_PER_BASE                    0x50001C00UL
#define CRG_TOP_BASE                    0x50000000UL
#define DCDC_BASE                       0x50000080UL
#define DEM_BASE                        0x50002E00UL
#define DMA_BASE                        0x50003500UL
#define ECC_BASE                        0x50006000UL
#define FTDF_BASE                       0x40080000UL
#define GP_TIMERS_BASE                  0x50003400UL
#define GPADC_BASE                      0x50001900UL
#define GPIO_BASE                       0x50003000UL
#define GPREG_BASE                      0x50003300UL
#define I2C_BASE                        0x50001400UL
#define I2C2_BASE                       0x50001500UL
#define IR_BASE                         0x50001700UL
#define KBSCAN_BASE                     0x50001600UL
#define OTPC_BASE                       0x07F40000UL
#define PATCH_BASE                      0x40050000UL
#define PLLDIG_BASE                     0x50002D00UL
#define QSPIC_BASE                      0x0C000000UL
#define QUAD_BASE                       0x50001A00UL
#define RFCU_BASE                       0x50002000UL
#define RFCU_POWER_BASE                 0x50002200UL
#define RFPT_BASE                       0x50003600UL
#define SPI_BASE                        0x50001200UL
#define SPI2_BASE                       0x50001300UL
#define TIMER1_BASE                     0x50000200UL
#define TRNG_BASE                       0x50005000UL
#define UART_BASE                       0x50001000UL
#define UART2_BASE                      0x50001100UL
#define USB_BASE                        0x50001800UL
#define WAKEUP_BASE                     0x50000100UL
#define WDOG_BASE                       0x50003100UL


/* ================================================================================ */
/* ================             Peripheral declaration             ================ */
/* ================================================================================ */

#define AES_HASH                        ((AES_HASH_Type           *) AES_HASH_BASE)
#define ANAMISC                         ((ANAMISC_Type            *) ANAMISC_BASE)
#define APU                             ((APU_Type                *) APU_BASE)
#define BLE                             ((BLE_Type                *) BLE_BASE)
#define CACHE                           ((CACHE_Type              *) CACHE_BASE)
#define CHIP_VERSION                    ((CHIP_VERSION_Type       *) CHIP_VERSION_BASE)
#define COEX                            ((COEX_Type               *) COEX_BASE)
#define CRG_PER                         ((CRG_PER_Type            *) CRG_PER_BASE)
#define CRG_TOP                         ((CRG_TOP_Type            *) CRG_TOP_BASE)
#define DCDC                            ((DCDC_Type               *) DCDC_BASE)
#define DEM                             ((DEM_Type                *) DEM_BASE)
#define DMA                             ((DMA_Type                *) DMA_BASE)
#define ECC                             ((ECC_Type                *) ECC_BASE)
#define FTDF                            ((FTDF_Type               *) FTDF_BASE)
#define GP_TIMERS                       ((GP_TIMERS_Type          *) GP_TIMERS_BASE)
#define GPADC                           ((GPADC_Type              *) GPADC_BASE)
#define GPIO                            ((GPIO_Type               *) GPIO_BASE)
#define GPREG                           ((GPREG_Type              *) GPREG_BASE)
#define I2C                             ((I2C_Type                *) I2C_BASE)
#define I2C2                            ((I2C2_Type               *) I2C2_BASE)
#define IR                              ((IR_Type                 *) IR_BASE)
#define KBSCAN                          ((KBSCAN_Type             *) KBSCAN_BASE)
#define OTPC                            ((OTPC_Type               *) OTPC_BASE)
#define PATCH                           ((PATCH_Type              *) PATCH_BASE)
#define PLLDIG                          ((PLLDIG_Type             *) PLLDIG_BASE)
#define QSPIC                           ((QSPIC_Type              *) QSPIC_BASE)
#define QUAD                            ((QUAD_Type               *) QUAD_BASE)
#define RFCU                            ((RFCU_Type               *) RFCU_BASE)
#define RFCU_POWER                      ((RFCU_POWER_Type         *) RFCU_POWER_BASE)
#define RFPT                            ((RFPT_Type               *) RFPT_BASE)
#define SPI                             ((SPI_Type                *) SPI_BASE)
#define SPI2                            ((SPI2_Type               *) SPI2_BASE)
#define TIMER1                          ((TIMER1_Type             *) TIMER1_BASE)
#define TRNG                            ((TRNG_Type               *) TRNG_BASE)
#define UART                            ((UART_Type               *) UART_BASE)
#define UART2                           ((UART2_Type              *) UART2_BASE)
#define USB                             ((USB_Type                *) USB_BASE)
#define WAKEUP                          ((WAKEUP_Type             *) WAKEUP_BASE)
#define WDOG                            ((WDOG_Type               *) WDOG_BASE)


/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group DA14680BA */
/** @} */ /* End of group Dialog */

#ifdef __cplusplus
}
#endif


#endif  /* DA14680BA_H */