/*
 * B4420 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of
 * this software, even if advised of the possibility of such damage.
 */

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,ifc", "simple-bus";
	interrupts = <25 2 0 0>;
};

/* controller at 0x200000 */
&pci0 {
	compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	interrupts = <20 2 0 0>;
	fsl,iommu-parent = <&pamu0>;
	pcie@0 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		reg = <0 0 0 0 0>;
		interrupts = <20 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 40 1 0 0
			0000 0 0 2 &mpic 1 1 0 0
			0000 0 0 3 &mpic 2 1 0 0
			0000 0 0 4 &mpic 3 1 0 0
			>;
	};
};

&dcsr {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,dcsr", "simple-bus";

	dcsr-epu@0 {
		compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
		interrupts = <52 2 0 0
			      84 2 0 0
			      85 2 0 0
			      94 2 0 0
			      95 2 0 0>;
		reg = <0x0 0x1000>;
	};
	dcsr-npc {
		compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
		reg = <0x1000 0x1000 0x1002000 0x10000>;
	};
	dcsr-nxc@2000 {
		compatible = "fsl,dcsr-nxc";
		reg = <0x2000 0x1000>;
	};
	dcsr-corenet {
		compatible = "fsl,dcsr-corenet";
		reg = <0x8000 0x1000 0x1A000 0x1000>;
	};
	dcsr-dpaa@9000 {
		compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
		reg = <0x9000 0x1000>;
	};
	dcsr-ocn@11000 {
		compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
		reg = <0x11000 0x1000>;
	};
	dcsr-ddr@12000 {
		compatible = "fsl,dcsr-ddr";
		dev-handle = <&ddr1>;
		reg = <0x12000 0x1000>;
	};
	dcsr-nal@18000 {
		compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
		reg = <0x18000 0x1000>;
	};
	dcsr-rcpm@22000 {
		compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
		reg = <0x22000 0x1000>;
	};
	dcsr-snpc@30000 {
		compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
		reg = <0x30000 0x1000 0x1022000 0x10000>;
	};
	dcsr-snpc@31000 {
		compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
		reg = <0x31000 0x1000 0x1042000 0x10000>;
	};
	dcsr-cpu-sb-proxy@100000 {
		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		cpu-handle = <&cpu0>;
		reg = <0x100000 0x1000 0x101000 0x1000>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "simple-bus";

	soc-sram-error {
		compatible = "fsl,soc-sram-error";
		interrupts = <16 2 1 2>;
	};

	corenet-law@0 {
		compatible = "fsl,corenet-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <32>;
	};

	ddr1: memory-controller@8000 {
		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
		reg = <0x8000 0x1000>;
		interrupts = <16 2 1 8>;
	};

	cpc: l3-cache-controller@10000 {
		compatible = "fsl,b4-l3-cache-controller", "cache";
		reg = <0x10000 0x1000>;
		interrupts = <16 2 1 4>;
	};

	corenet-cf@18000 {
		compatible = "fsl,b4-corenet-cf";
		reg = <0x18000 0x1000>;
		interrupts = <16 2 1 0>;
		fsl,ccf-num-csdids = <32>;
		fsl,ccf-num-snoopids = <32>;
	};

	iommu@20000 {
		compatible =  "fsl,pamu-v1.0", "fsl,pamu";
		reg = <0x20000 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <
			24 2 0 0
			16 2 1 1>;


		/* PCIe, DMA, SRIO */
		pamu0: pamu@0 {
			reg = <0 0x1000>;
			fsl,primary-cache-geometry = <8 1>;
			fsl,secondary-cache-geometry = <32 2>;
		};

		/* AXI2, Maple */
		pamu1: pamu@1000 {
			reg = <0x1000 0x1000>;
			fsl,primary-cache-geometry = <32 1>;
			fsl,secondary-cache-geometry = <32 2>;
		};

		/* Q/BMan */
		pamu2: pamu@2000 {
			reg = <0x2000 0x1000>;
			fsl,primary-cache-geometry = <32 1>;
			fsl,secondary-cache-geometry = <32 2>;
		};

		/* AXI1, FMAN */
		pamu3: pamu@3000 {
			reg = <0x3000 0x1000>;
			fsl,primary-cache-geometry = <32 1>;
			fsl,secondary-cache-geometry = <32 2>;
		};
	};

/include/ "qoriq-mpic.dtsi"

	guts: global-utilities@e0000 {
		compatible = "fsl,b4-device-config";
		reg = <0xe0000 0xe00>;
		fsl,has-rstcr;
		fsl,liodn-bits = <12>;
	};

	clockgen: global-utilities@e1000 {
		compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
		reg = <0xe1000 0x1000>;
	};

	rcpm: global-utilities@e2000 {
		compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
		reg = <0xe2000 0x1000>;
	};

/include/ "qoriq-dma-0.dtsi"
	dma@100300 {
		fsl,iommu-parent = <&pamu0>;
		fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
	};

/include/ "qoriq-dma-1.dtsi"
	dma@101300 {
		fsl,iommu-parent = <&pamu0>;
		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
	};

/include/ "qonverge-usb2-dr-0.dtsi"
	usb0: usb@210000 {
		compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
		fsl,iommu-parent = <&pamu1>;
		fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
	};

/include/ "qoriq-espi-0.dtsi"
	spi@110000 {
		fsl,espi-num-chipselects = <4>;
	};

/include/ "qoriq-esdhc-0.dtsi"
	sdhc@114000 {
		sdhci,auto-cmd12;
		fsl,iommu-parent = <&pamu1>;
		fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
	};

/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-sec5.3-0.dtsi"

	L2: l2-cache-controller@c20000 {
		compatible = "fsl,b4-l2-cache-controller";
		reg = <0xc20000 0x1000>;
		next-level-cache = <&cpc>;
	};
};