/*
 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2011-2012 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&lbc {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
	interrupts = <19 2 0 0>;
};

/* controller at 0x9000 */
&pci0 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <16 2 0 0>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
			>;
	};
};

/* controller at 0xa000 */
&pci1 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <16 2 0 0>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
			>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "fsl,p1021-immr", "simple-bus";
	bus-frequency = <0>;		// Filled out by uboot.

	ecm-law@0 {
		compatible = "fsl,ecm-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <12>;
	};

	ecm@1000 {
		compatible = "fsl,p1021-ecm", "fsl,ecm";
		reg = <0x1000 0x1000>;
		interrupts = <16 2 0 0>;
	};

	memory-controller@2000 {
		compatible = "fsl,p1021-memory-controller";
		reg = <0x2000 0x1000>;
		interrupts = <16 2 0 0>;
	};

/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"

/include/ "pq3-espi-0.dtsi"
	spi@7000 {
		fsl,espi-num-chipselects = <4>;
	};

/include/ "pq3-gpio-0.dtsi"

	L2: l2-cache-controller@20000 {
		compatible = "fsl,p1021-l2-cache-controller";
		reg = <0x20000 0x1000>;
		cache-line-size = <32>;	// 32 bytes
		cache-size = <0x40000>; // L2,256K
		interrupts = <16 2 0 0>;
	};

/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
	usb@22000 {
		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
	};

/include/ "pq3-esdhc-0.dtsi"
	sdhc@2e000 {
		sdhci,auto-cmd12;
	};

/include/ "pq3-sec3.3-0.dtsi"

/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"

/include/ "pq3-etsec2-0.dtsi"
	enet0: enet0_grp2: ethernet@b0000 {
	};

/include/ "pq3-etsec2-1.dtsi"
	enet1: enet1_grp2: ethernet@b1000 {
	};

/include/ "pq3-etsec2-2.dtsi"
	enet2: enet2_grp2: ethernet@b2000 {
	};

	global-utilities@e0000 {
		compatible = "fsl,p1021-guts";
		reg = <0xe0000 0x1000>;
		fsl,has-rstcr;
	};
};

&qe {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "qe";
	compatible = "fsl,qe";
	fsl,qe-num-riscs = <1>;
	fsl,qe-num-snums = <28>;

	qeic: interrupt-controller@80 {
		interrupt-controller;
		compatible = "fsl,qe-ic";
		#address-cells = <0>;
		#interrupt-cells = <1>;
		reg = <0x80 0x80>;
		interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
	};

	ucc@2000 {
		cell-index = <1>;
		reg = <0x2000 0x200>;
		interrupts = <32>;
		interrupt-parent = <&qeic>;
	};

	mdio@2120 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x2120 0x18>;
		compatible = "fsl,ucc-mdio";
	};

	ucc@2400 {
		cell-index = <5>;
		reg = <0x2400 0x200>;
		interrupts = <40>;
		interrupt-parent = <&qeic>;
	};

	ucc@2600 {
		cell-index = <7>;
		reg = <0x2600 0x200>;
		interrupts = <42>;
		interrupt-parent = <&qeic>;
	};

	ucc@2200 {
		cell-index = <3>;
		reg = <0x2200 0x200>;
		interrupts = <34>;
		interrupt-parent = <&qeic>;
	};

	muram@10000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,qe-muram", "fsl,cpm-muram";
		ranges = <0x0 0x10000 0x6000>;

		data-only@0 {
			compatible = "fsl,qe-muram-data",
			"fsl,cpm-muram-data";
			reg = <0x0 0x6000>;
		};
	};
};

/include/ "pq3-etsec2-grp2-0.dtsi"
/include/ "pq3-etsec2-grp2-1.dtsi"
/include/ "pq3-etsec2-grp2-2.dtsi"