* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX

Required properties:
- compatible : Should be "fsl,<chip>-sdma"
- reg : Should contain SDMA registers location and length
- interrupts : Should contain SDMA interrupt
- #dma-cells : Must be <3>.
  The first cell specifies the DMA request/event ID.  See details below
  about the second and third cell.
- gpr : The phandle to general purpose register node.
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
  <reg shift val>.
    reg is the gpr register offset.
    shift is the bit offset of event remap.
    val is the value of the bit to be set.
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
  scripts firmware

The second cell of dma phandle specifies the peripheral type of DMA transfer.
The full ID of peripheral types can be found below.

	ID	transfer type
	---------------------
	0	MCU domain SSI
	1	Shared SSI
	2	MMC
	3	SDHC
	4	MCU domain UART
	5	Shared UART
	6	FIRI
	7	MCU domain CSPI
	8	Shared CSPI
	9	SIM
	10	ATA
	11	CCM
	12	External peripheral
	13	Memory Stick Host Controller
	14	Shared Memory Stick Host Controller
	15	DSP
	16	Memory
	17	FIFO type Memory
	18	SPDIF
	19	IPU Memory
	20	ASRC
	21	ESAI
	22	HDMI Audio
	23	SAI

The third cell specifies the transfer priority as below.

	ID	transfer priority
	-------------------------
	0	High
	1	Medium
	2	Low

Examples:

sdma@83fb0000 {
	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	reg = <0x83fb0000 0x4000>;
	interrupts = <6>;
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "sdma-imx51.bin";
};

DMA clients connected to the i.MX SDMA controller must use the format
described in the dma.txt file.

Examples:

ssi2: ssi@70014000 {
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x70014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks 49>;
	dmas = <&sdma 24 1 0>,
	       <&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
};