/*
 * Copyright (C) 2014 Nest labs, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License or (at your option) any later version.
 *
 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

#define __ASSEMBLY__
#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
 * Boot Device : one of
 * spi/sd/nand/onenand, qspi/nor
 */

#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM	qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM	nor
#else
BOOT_FROM	sd
#endif

#ifdef CONFIG_USE_PLUGIN
/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
PLUGIN	board/freescale/mx6sxsabresd/plugin.bin 0x00907000
#else

#ifdef CONFIG_SECURE_BOOT
CSF 0x2000
#endif

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */


// Enable all clocks (they are disabled by ROM code)
DATA 4	0x020C4068 	0xFFFFFFFF
DATA 4	0x020C406C 	0xFFFFFFFF
DATA 4	0x020C4070 	0xFFFFFFFF
DATA 4	0x020C4074 	0xFFFFFFFF
DATA 4	0x020C4078 	0xFFFFFFFF
DATA 4	0x020C407C 	0xFFFFFFFF
DATA 4	0x020C4080 	0xFFFFFFFF
DATA 4	0x020C4084 	0xFFFFFFFF

#ifndef CONFIG_NEST_DIAGNOSTICS
// Run DDR at 198Mhz except diags
DATA 4	0x020C4014 	0x00018908	//DDR clk to 198MHz
#endif

// IOMUX
//DDR IO TYPE:
DATA 4	0x020E0618 	0x00080000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4	0x020E05FC 	0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE

//CLOCK:
DATA 4	0x020E032C 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P

//ADDRESS:
DATA 4	0x020E0300 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DATA 4	0x020E02FC 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DATA 4	0x020E05F4 	0x00000028	// IOMUXC_SW_PAD_CTL_GRP_ADDDS

//Control:
DATA 4	0x020E0340 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4	0x020E0320 	0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4	0x020E0310 	0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
DATA 4	0x020E0314 	0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
DATA 4	0x020E0614 	0x00000028	// IOMUXC_SW_PAD_CTL_GRP_CTLDS

//Data Strobes:
DATA 4	0x020E05F8 	0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4	0x020E0330 	0x00003028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
DATA 4	0x020E0334 	0x00003028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
DATA 4	0x020E0338 	0x00003028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P
DATA 4	0x020E033C 	0x00003028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P

//Data:
DATA 4	0x020E0608 	0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4	0x020E060C 	0x00000028	// IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4	0x020E0610 	0x00000028	// IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4	0x020E061C 	0x00000028	// IOMUXC_SW_PAD_CTL_GRP_B2DS
DATA 4	0x020E0620 	0x00000028	// IOMUXC_SW_PAD_CTL_GRP_B3DS

DATA 4	0x020E02EC 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4	0x020E02F0 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DATA 4	0x020E02F4 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DATA 4	0x020E02F8 	0x00000028	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3


// DDR Controller Registers
// Manufacturer:	NANYA
// Device Part Number:	NT6TL128M32AQ
// Clock Freq.:	400MHz
// Density per CS in Gb:	4
// Chip Selects used:	1
// Total DRAM density (Gb)	4
// Number of Banks:	8
// Row address:	14
// Column address:	10
// Data bus width	32


DATA 4	0x021B001C 	0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up

DATA 4	0x021B085C 	0x1B4700C7	// MMDC0_MPZQLP2CTL, LPDDR2 ZQ params

DATA 4	0x021B08C0 	0x2492244A	// MMDC0_MPDCCR, Duty Cycle Control - Added per JEDEC testing.

DATA 4	0x021B0800 	0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

DATA 4	0x021B0890 	0x00470000	// MMDC0_MPPDCMPR2, CA bus absolute delay - Update to mid-point of valid window

DATA 4	0x021B08B8 	0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

//######################################################
//calibration values based on calibration compare of 0x00ffff00:
//Note, these calibration values are based on Freescale's board
//May need to run calibration on target board to fine tune these
//######################################################

//DATA TRACE READ DELAYS:
DATA 4	0x021B081C 	0x33333333	// DDR_PHY_P0_MPREDQBY0DL3
DATA 4	0x021B0820 	0x33333333	// DDR_PHY_P0_MPRDQBY1DL3
DATA 4	0x021B0824 	0x33333333	// DDR_PHY_P0_MPRDQBY2DL3
DATA 4	0x021B0828 	0x33333333	// DDR_PHY_P0_MPRDQBY3DL3

//DATA TRACE WRITE DELAYS:
DATA 4	0x021B082C 	0xF3333333	// DDR_PHY_P0_MPWRQBY0DL3
DATA 4	0x021B0830 	0xF3333333	// DDR_PHY_P0_MPWRQBY1DL3
DATA 4	0x021B0834 	0xF3333333	// DDR_PHY_P0_MPWRQBY2DL3
DATA 4	0x021B0838 	0xF3333333	// DDR_PHY_P0_MPWRQBY3DL3

// READ DQS DELAY:
DATA 4	0x021B0848 	0x3E3E4244	// MPRDDLCTL PHY0

// WRITE DQS DELAY:
DATA 4	0x021B0850 	0x36323632	// MPWRDLCTL PHY0

// DQS GATE DELAY:
DATA 4	0x021B083C 	0x20000000	// MPDGCTRL0 PHY0, gate delay not used in LPDDR2, disable
DATA 4	0x021B0840 	0x00000000	// MPDGCTRL1 PHY0

// Complete calibration by forced measurement:
DATA 4	0x021B08B8 	0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

DATA 4	0x021B000C 	0x33374135	// MMDC0_MDCFG0 - Update tCL to 8 cycles per Samsung Datasheet
DATA 4	0x021B0004 	0x00020036	// MMDC0_MDPDC
DATA 4	0x021B0010 	0xB6B00A83	// MMDC0_MDCFG1 - Change DDR3 fields to default values. Update tCWL to 4 cycles per Samsung Datasheet
DATA 4	0x021B0014 	0x00000093	// MMDC0_MDCFG2
DATA 4	0x021B0018 	0x00001748	// MMDC0_MDMISC
DATA 4	0x021B002C 	0x0F9F26D2	// MMDC0_MDRWD; recommend to maintain the default values
DATA 4	0x021B0030 	0x009F0E10	// MMDC0_MDOR - Change DDR3 fields to default values
DATA 4	0x021B0038 	0x001A0889	// MMDC0_MDCFG3LP - Add 1 cycle to tRCD_LP per spreadsheet
DATA 4	0x021B0008 	0x12272000	// MMDC0_MDOTC - Change DDR3 fields to default values
DATA 4	0x021B0040 	0x0000004F	// CS0_END
DATA 4	0x021B0000 	0x83110000	// MMDC0_MDCTL


// Mode register writes
DATA 4	0x021B001C 	0x003F8030	// MMDC0_MDSCR, MR63 write, CS0
DATA 4	0x021B001C 	0xFF0A8030	// MMDC0_MDSCR, MR10 write, CS0
DATA 4	0x021B001C 	0x82018030	// MMDC0_MDSCR, MR1 write, CS0
DATA 4	0x021B001C 	0x06028030	// MMDC0_MDSCR, MR2 write, CS0 - Update RL and WL to 8/4 to match Samsung Datasheet
DATA 4	0x021B001C 	0x01038030	// MMDC0_MDSCR, MR3 write, CS0 - Using slightly higher DQS, DQ drive strength

// Skip CS1 configuration since elpida and samsung parts do not have CS1
// DATA 4	0x021B001C 	0x003F8038	// MMDC0_MDSCR, MR63 write, CS1
// DATA 4	0x021B001C 	0xFF0A8038	// MMDC0_MDSCR, MR10 write, CS1
// DATA 4	0x021B001C 	0x82018038	// MMDC0_MDSCR, MR1 write, CS1
// DATA 4	0x021B001C 	0x06028038	// MMDC0_MDSCR, MR2 write, CS1
// DATA 4	0x021B001C 	0x01038038	// MMDC0_MDSCR, MR3 write, CS1

//FINAL SETTINGS:
DATA 4	0x021B0020 	0x00001800	// MMDC0_MDREF
DATA 4	0x021B0818 	0x00000000	// DDR_PHY_P0_MPODTCTRL

DATA 4	0x021B0800 	0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable automatic HW ZQ calibration.
DATA 4	0x021B0004 	0x00025536	// MMDC0_MDPDC now SDCTL power down enabled - Change to match 0x021b0004 above
DATA 4	0x021B0404 	0x00011006	//MMDC0_MAPSR ADOPT power down enabled

DATA 4	0x021B001C 	0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)


#endif