Project import
diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..2c76a3e --- /dev/null +++ b/Makefile
@@ -0,0 +1,108 @@ +# +# Copyright (c) 2010-2011 Nest, Inc. +# All rights reserved. +# +# This document is the property of Nest. It is considered +# confidential and proprietary information. +# +# This document may not be reproduced or transmitted in any form, +# in whole or in part, without the express written permission of +# Nest. +# +# Description: +# This file is the make file for ethtool, a utility that may be +# used to query and change settings such as MAC address, speed, +# auto-negotiation and checksum offload on many network devices, +# especially Ethernet devices. +# + +BuildConfigSpecialized := No +BuildProductSpecialized := No + +include pre.mak + +PackageName := ethtool + +PackageExtension := tar.gz +PackageSeparator := - + +PackagePatchArgs := -p1 + +PackageArchive := $(PackageName).$(PackageExtension) +PackageSourceDir := $(PackageName)$(PackageSeparator)$(PackageVersion) + +PackageBuildMakefile = $(call GenerateBuildPaths,Makefile) + +LicenseSourceFile := $(PackageSourceDir)/COPYING + +CleanPaths += $(PackageLicenseFile) + +all: $(PackageDefaultGoal) + +# Generate the package license contents. + +$(LicenseSourceFile): source + +$(PackageLicenseFile): $(LicenseSourceFile) + $(copy-result) + +# Extract the source from the archive and apply patches, if any. + +$(PackageSourceDir): $(PackageArchive) $(PackagePatchPaths) + $(expand-and-patch-package) + +# Prepare the sources. + +.PHONY: source +source: | $(PackageSourceDir) + +# Patch the sources, if necessary. + +.PHONY: patch +patch: source + +# Generate the package build makefile. + +$(PackageBuildMakefile): | $(PackageSourceDir) $(BuildDirectory) $(ResultDirectory) + $(Verbose)cd $(BuildDirectory) && \ + $(CURDIR)/$(PackageSourceDir)/configure \ + CC="$(CC)" CXX="$(CXX)" AR=$(AR) NM=$(NM) RANLIB=$(RANLIB) STRIP=$(STRIP) \ + INSTALL="$(INSTALL) $(INSTALLFLAGS)" \ + --build=$(HostTuple) \ + --host=$(TargetTuple) \ + --prefix=/usr \ + --sysconfdir=/etc \ + --localstatedir=/var + +# Configure the source for building. + +.PHONY: configure +configure: source $(PackageBuildMakefile) + +# Build the source. +# +# We have to unset MAKEFLAGS since they confuse the package build otherwise. + +.PHONY: build +build: configure + $(Verbose)unset MAKEFLAGS && \ + $(MAKE) $(JOBSFLAG) -C $(BuildDirectory) \ + all + +# Stage the build to a temporary installation area. +# +# We have to unset MAKEFLAGS since they confuse the package build otherwise. + +.PHONY: stage +stage: build | $(ResultDirectory) + $(Verbose)unset MAKEFLAGS && \ + $(MAKE) $(JOBSFLAG) -C $(BuildDirectory) \ + DESTDIR=$(ResultDirectory) \ + install + +clean: + $(Verbose)$(RM) $(RMFLAGS) -r $(PackageSourceDir) + $(Verbose)$(RM) $(RMFLAGS) -r $(BuildDirectory) + $(Verbose)$(RM) $(RMFLAGS) -r $(ResultDirectory) + +include post.mak
diff --git a/ethtool-2.6.35/AUTHORS b/ethtool-2.6.35/AUTHORS new file mode 100644 index 0000000..77500ce --- /dev/null +++ b/ethtool-2.6.35/AUTHORS
@@ -0,0 +1,8 @@ +David Miller <davem@redhat.com> +Jakub Jelinek <jj@ultra.linux.cz> +Jeff Garzik <jgarzik@pobox.com> +Tim Hockin <thockin@sun.com> +Eli Kupermann <eli.kupermann@intel.com> +Chris Leech <christopher.leech@intel.com> +Scott Feldman <scott.feldman@intel.com> +Andi Kleen
diff --git a/ethtool-2.6.35/COPYING b/ethtool-2.6.35/COPYING new file mode 100644 index 0000000..d60c31a --- /dev/null +++ b/ethtool-2.6.35/COPYING
@@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License.
diff --git a/ethtool-2.6.35/ChangeLog b/ethtool-2.6.35/ChangeLog new file mode 100644 index 0000000..379c0bb --- /dev/null +++ b/ethtool-2.6.35/ChangeLog
@@ -0,0 +1,351 @@ + + +NOTE: For further changelog entries, see BitKeeper repository. + + +Tue Aug 17 2004 Jeff Garzik <jgarzik@pobox.com> + + * NEWS, configure.ac: Release version 2 + +Fri Jul 2 2004 Jeff Garzik <jgarzik@pobox.com> + + Merged + * fec_8xx.c, ethtool-util.h, Makefile.am: Add fec_8xx register dump. + Contributed by Pantelis Antoniou <panto@intracom.gr> + + * Update ethtool.c to iterate through a list of drivers + * Fixed fec_8xx.c warnings on 64-bit + +Fri Jul 2 2004 Jim Lewis <jim@jklewis.com> + + * pcnet32.c, ethtool-util.h, Makefile.am: Add pcnet32 register dump. + +Fri Apr 9 2004 Jason Lunz <lunz@reflexsecurity.com> + + * ethtool.c: Remove incorrect restriction on ethernet interface + names. + +Fri Apr 9 2004 OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> + + * ethtool.c: This fixes the bogus tail backslash that I did. + +Fri Apr 9 2004 Jim Lewis <jim@jklewis.com> + + * ethtool.c: Return results of self-test back to OS, + via exit(2). + +Fri Apr 9 2004 Jeb Cramer <cramerj@intel.com> + + * e1000.c: Update device id list and add printout of phy type in + register dump. Set default mac_type to 82543 since register offsets + haven't changed. + +Fri Apr 9 2004 Jeff Garzik <jgarzik@pobox.com> + + * configure.ac, Makefile.am, ethtool.c, etc.: + convert to more recent autoconf. + +Sat Aug 30 2003 OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> + + * ethtool.8, ethtool.c: ethtool register dump raw mode + +Sat Jul 19 2003 Scott Feldman <scott.feldman@intel.com> + + * ethtool.8, ethtool.c, ethtool-copy.h: + Add support for TSO get/set. Corresponds to NETIF_F_TSO. + Extended -k|K option to included tso, and changed meaning from + just "checksum/sg" to more general "offload". Now covers Rx/Tx + csum, SG, and TSO. + +Thu May 28 2003 Ganesh Venkatesan <ganesh.venkatesan@intel.com> + + * ethtool-copy.h: new definitions for 10GbE + +Thu May 28 2003 Scott Feldman <scott.feldman@intel.com> + + * ethtool.c: Add ethtool -E to write EEPROM byte. + * e100.c: Added MDI/MDI-X status to register dump. + +Thu May 28 2003 Reeja John <reeja.john@amd.com> + + * amd8111e.c: new file, support for AMD-8111e NICs + * ethtool.c: properly set ecmd.advertising + +Sat Mar 29 2003 OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> + + * realtek.c: clean up chip enumeration, support additional chips + +Fri Mar 28 2003 Jeb Cramer <cramerj@intel.com> + + * e1000.c: Update supported devices (82541 & 82547). Add bus type, + speed and width to register dump printout. + * ethtool.c (show_usage): Add -S to printout of supported commands. + +Tue Jan 22 2003 Jeff Garzik <jgarzik@pobox.com> + + * natsemi.c (PRINT_INTR, __print_intr): Decompose PRINT_INTR + macro into macro abuse and function call portions. Move the + actual function body to new static functoin __print_intr. + + This eliminates the annoying build warning :) + +Thu Jan 16 2003 Jeb Cramer <jeb.j.cramer@intel.com> + + * ethtool.c (do_regs, dump_eeprom): Fix memory leaks on failed + operations. Add error handling of dump_regs(). Modify printout of + eeprom dump to accomodate larger eeproms. + * e1000.c: Update supported devices. Add error conditions for + unsupported devices. + +Mon Oct 21 2002 Ben Collins <bcollins@debian.org> + + * ethtool.c: Add new parameters to -e, for raw EEPROM output, and + offset and length options. + * natsemi.c (natsemi_dump_eeprom): Show correct offset using new + offset feature above. + * tg3.c: New file, implements tg3_dump_eeprom. + * Makefile.am: Add it to the build sources. + * ethtool-util.h: Prototype tg3_dump_eeprom. + * ethtool.8: Document new -e options. + +Thu Oct 17 2002 Tim Hockin <thockin@sun.com> + + * ethtool.c: make calls to strtol() use base 0 + +Wed Sep 18 2002 Scott Feldman <scott.feldman@intel.com> + + * ethtool.c (dump_regs): call e100_dump_regs if e100 + * e100.c: new file + * ethtool-util.h: prototype e100_dump_regs + +Thu Jun 20 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool.8: document new -S stats dump argument + * configure.in, NEWS: release version 1.6 + +Fri Jun 14 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * realtek.c (realtek_dump_regs): dump legacy 8139 registers + * ethtool.c (do_gstats, doit, parse_cmdline): + support dumping of NIC-specific statistics + +Fri Jun 14 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * realtek.c (realtek_dump_regs): dump RTL8139C+ registers + +Fri Jun 14 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * realtek.c: new file, dumps RealTek RTL8169 PCI NIC's registers + * Makefile.am, ethtool.c, ethtool-util.h: use it + +Tue Jun 11 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * NEWS: list new commands added recently + * ethtool.c (do_gcoalesce, do_scoalesce, dump_coalesce): new + (parse_cmdline, doit): handle get/set coalesce parameters (-c,-C) + (do_[gs]*): convert to use table-driven cmd line parsing + * ethtool.8: document -c and -C + +Tue Jun 11 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool.c (do_gring, do_sring, dump_ring, + parse_ring_cmdline): new functions + (parse_cmdline, doit): handle get/set ring parameters (-g,-G) + (do_spause): fix off-by-one bugs + * ethtool.8: document -g and -G + +Tue Jun 11 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool.c (do_gpause, do_spause, dump_pause, + parse_pause_cmdline): new functions + (parse_cmdline, doit): handle get/set pause parameters (-a,-A) + * ethtool.8: document -a, -A, -e, and -p + +Wed May 22 2002 Chris Leech <christopher.leech@intel.com> + Scott Feldman <scott.feldman@intel.com> + + * ethtool-copy.h: add support for ETHTOOL_PHYS_ID function. + * ethtool.c: add support for ETHTOOL_PHYS_ID function, add + support for e1000 reg dump. + * Makefile.am: add e1000.c + * e1000.c: reg dump support for Intel(R) PRO/1000 adapters. + * ethtool-util.h: add e1000 reg dump support. + +Sat May 11 2002 Eli Kupermann <eli.kupermann@intel.com> + + * ethtool.c (do_test): add support for online/offline test modes + Elsewhere: document "-t" arg usage, and handle usage + +Sat May 11 2002 Jes Sorensen <jes@wildopensource.com> + + * ethtool.c (dump_ecmd): If unknown value is + encountered in speed, duplex, or port ETHTOOL_GSET + return data, print the numeric value returned. + +Wed May 1 2002 Eli Kupermann <eli.kupermann@intel.com> + + * ethtool.8: document new -t test option + +Wed May 1 2002 Christoph Hellwig <hch@lst.de> + + * Makefile.am (dist-hook): Use $(top-srcdir) for refering to sources. + +Mon Apr 29 2002 Christoph Hellwig <hch@lst.de> + + * Makefile.am (SUBDIRS): Remove. + (RPMSRCS): Likewise. + (TMPDIR): Likewise. + (rpm): Likewise. + (EXTRA_DIST): Add ethtool.spec.in. + (dist-hook): New rule. Create rpm specfile. + * configure.in (AC_OUTPUT): Add ethtool.spec. + * ethtool.spec.in: New file. Rpm specfile template. + * redhat/ethtool.spec.in: Removed. + * redhat/Makefile.am: Removed. + +Wed Mar 20 2002 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool-copy.h: Merge coalescing param, ring + param, and pause param ioctl structs from kernel 2.5.7. + Merge ethtool_test changes fromkernel 2.5.7. + * ethtool: Update for ethtool_test cleanups. + +Wed Mar 20 2002 Eli Kupermann <eli.kupermann@intel.com> + + * ethtool.c: (do_test): new function + Elsewhere: add support for 'perform test' function, + via a new "-t" arg, by calling do_test. + +Sun Mar 3 2002 Brad Hards <bhards@bigpond.net.au> + + * ethtool.c (parse_cmdline): Support "usb" + as well as "eth" network interfaces. USB networking + uses a different prefix. + +Fri Feb 8 2002 "Noam, Amir" <amir.noam@intel.com>, + "Kupermann, Eli" <eli.kupermann@intel.com> + + * ethtool.c (dump_advertised): new function. + (dump_ecmd): Call it. + Elsewhere: reformat code. + +Wed Nov 28 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * configure.in, Makefile.am, redhat/Makefile.am: + make sure redhat spec is included in dist tarball. + +Tue Nov 27 2001 Tim Hockin <thockin@sun.com> + + * natsemi.c: strings changes + * ethtool.c: print messagelevel as hex (netif_msg_* shows better :) + +Sun Nov 18 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * NEWS: update with recent changes + * ethtool.8: phy address can be used if implemented in the + driver, so remove "Not used yet" remark. + +Sun Nov 18 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * Makefile.am, de2104x.c, ethtool-util.h, ethtool.c: + Support register dumps for de2104x driver. + +Tue Nov 13 2001 Tim Hockin <thockin@sun.com> + + * natsemi.c, ethtool.c: use u8 data for ethtool_regs + * ethtool-copy.h: latest from kernel + * natsemi.c, ethtool.c: support ETHTOOL_GEEPROM via -e param + +Mon Nov 12 2001 Tim Hockin <thockin@sun.com> + + * natsemi.c: check version, conditionally print RFCR-indexed data + +Wed Nov 07 2001 Tim Hockin <thockin@sun.com> + + * ethtool.c: print less errors for unsupported ioctl()s + * ethtool.c: warn if all ioctl()s are unsupported or failed + * ethtool.c: change autoneg-restart mechanism to -r (as per jgarzik) + * ethtool.c: check for "eth" in devicename (per jg) + * ethtool.c: remove 'extraneous' braces + +Wed Nov 07 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool.c, ethtool.8: support bnc port/media + +Tue Nov 06 2001 Tim Hockin <thockin@sun.com> + + * ethtool.c: clean up output for unhandled register dumps + * natsemi.c: finish pretty-printing register dumps + * ethtool.8: document -d option + * various: add copyright info, where applicable + * ethtool.c: be nicer about unsupported ioctl()s where possible + and be more verbose where nice is not an option. + +Mon Nov 05 2001 Tim Hockin <thockin@sun.com> + + * natsemi.c: first cut at 'pretty-printing' register dumps + +Fri Nov 02 2001 Tim Hockin <thockin@sun.com> + + * ethtool.c: add support for ETHTOOL_GREGS via -d (dump) flag + * ethtool.c: add support for device-specific dumps for known devices + * ethtool.c: make mode-specific handling allocate ifr_data + * Makefile.am: import ChangeLog to rpm specfile + * natsemi.c: added + * ethtool-util.h: added + +Thu Nov 01 2001 Tim Hockin <thockin@sun.com> + + * ethtool.c: add support for ETHTOOL_GLINK in output + * ethtool.c: add support for ETHTOOL_NWAY_RST via 'autoneg restart' + * ethtool.c: add support for ETHTOOL_[GS]MSGLVL via 'msglvl' param + * ethtool.8: add documentation for above + * ethtool-copy.h: updated to sync with kernel + +Fri Oct 26 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool.8: Update contributors list, home page URL. + * ethtool.8: Much cleanup, no content change. + Contributed by Andre Majorel. + * ethtool.c: Clean up '-h' usage message. + Contributed by Andre Majorel. + +Fri Oct 26 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * Configure.in: bump version to 1.4cvs + * Makefile.am: include ethtool-copy.h in list of sources + * ethtool-copy.h: + Import ethtool.h from kernel 2.4.13. + * ethtool.c: + Define SIOCETHTOOL if it is missing, + trim trailing whitespace. + * NEWS: update for these changes + +Wed Sep 19 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * ethtool.c, ethtool-copy.h: + Import copy of kernel 2.4.10-pre12's ethtool.h. + +Wed Sep 19 2001 Tim Hockin <thockin@sun.com> + + * Makefile.am, redhat/ethtool.spec.in: + Basic "make rpm" support. + +Wed Sep 19 2001 Tim Hockin <thockin@sun.com> + + * AUTHORS, NEWS, ethtool.8, ethtool.c: + Wake-on-LAN support. + +Thu May 17 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * configure.in, NEWS, README: Version 1.2 release + + * ethtool.c: Support ETHTOOL_GDRVINFO. + * ethtool.8: Document it. + +Fri Mar 20 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + + * Makefile.am, configure.in, autogen.sh, NEWS, + ChangeLog, AUTHORS, README: + Add autoconf/automake support. +
diff --git a/ethtool-2.6.35/INSTALL b/ethtool-2.6.35/INSTALL new file mode 100644 index 0000000..d3c5b40 --- /dev/null +++ b/ethtool-2.6.35/INSTALL
@@ -0,0 +1,237 @@ +Installation Instructions +************************* + +Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005, +2006, 2007 Free Software Foundation, Inc. + +This file is free documentation; the Free Software Foundation gives +unlimited permission to copy, distribute and modify it. + +Basic Installation +================== + +Briefly, the shell commands `./configure; make; make install' should +configure, build, and install this package. The following +more-detailed instructions are generic; see the `README' file for +instructions specific to this package. + + The `configure' shell script attempts to guess correct values for +various system-dependent variables used during compilation. It uses +those values to create a `Makefile' in each directory of the package. +It may also create one or more `.h' files containing system-dependent +definitions. Finally, it creates a shell script `config.status' that +you can run in the future to recreate the current configuration, and a +file `config.log' containing compiler output (useful mainly for +debugging `configure'). + + It can also use an optional file (typically called `config.cache' +and enabled with `--cache-file=config.cache' or simply `-C') that saves +the results of its tests to speed up reconfiguring. Caching is +disabled by default to prevent problems with accidental use of stale +cache files. + + If you need to do unusual things to compile the package, please try +to figure out how `configure' could check whether to do them, and mail +diffs or instructions to the address given in the `README' so they can +be considered for the next release. If you are using the cache, and at +some point `config.cache' contains results you don't want to keep, you +may remove or edit it. + + The file `configure.ac' (or `configure.in') is used to create +`configure' by a program called `autoconf'. You need `configure.ac' if +you want to change it or regenerate `configure' using a newer version +of `autoconf'. + +The simplest way to compile this package is: + + 1. `cd' to the directory containing the package's source code and type + `./configure' to configure the package for your system. + + Running `configure' might take a while. While running, it prints + some messages telling which features it is checking for. + + 2. Type `make' to compile the package. + + 3. Optionally, type `make check' to run any self-tests that come with + the package. + + 4. Type `make install' to install the programs and any data files and + documentation. + + 5. You can remove the program binaries and object files from the + source code directory by typing `make clean'. To also remove the + files that `configure' created (so you can compile the package for + a different kind of computer), type `make distclean'. There is + also a `make maintainer-clean' target, but that is intended mainly + for the package's developers. If you use it, you may have to get + all sorts of other programs in order to regenerate files that came + with the distribution. + + 6. Often, you can also type `make uninstall' to remove the installed + files again. + +Compilers and Options +===================== + +Some systems require unusual options for compilation or linking that the +`configure' script does not know about. Run `./configure --help' for +details on some of the pertinent environment variables. + + You can give `configure' initial values for configuration parameters +by setting variables in the command line or in the environment. Here +is an example: + + ./configure CC=c99 CFLAGS=-g LIBS=-lposix + + *Note Defining Variables::, for more details. + +Compiling For Multiple Architectures +==================================== + +You can compile the package for more than one kind of computer at the +same time, by placing the object files for each architecture in their +own directory. To do this, you can use GNU `make'. `cd' to the +directory where you want the object files and executables to go and run +the `configure' script. `configure' automatically checks for the +source code in the directory that `configure' is in and in `..'. + + With a non-GNU `make', it is safer to compile the package for one +architecture at a time in the source code directory. After you have +installed the package for one architecture, use `make distclean' before +reconfiguring for another architecture. + +Installation Names +================== + +By default, `make install' installs the package's commands under +`/usr/local/bin', include files under `/usr/local/include', etc. You +can specify an installation prefix other than `/usr/local' by giving +`configure' the option `--prefix=PREFIX'. + + You can specify separate installation prefixes for +architecture-specific files and architecture-independent files. If you +pass the option `--exec-prefix=PREFIX' to `configure', the package uses +PREFIX as the prefix for installing programs and libraries. +Documentation and other data files still use the regular prefix. + + In addition, if you use an unusual directory layout you can give +options like `--bindir=DIR' to specify different values for particular +kinds of files. Run `configure --help' for a list of the directories +you can set and what kinds of files go in them. + + If the package supports it, you can cause programs to be installed +with an extra prefix or suffix on their names by giving `configure' the +option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. + +Optional Features +================= + +Some packages pay attention to `--enable-FEATURE' options to +`configure', where FEATURE indicates an optional part of the package. +They may also pay attention to `--with-PACKAGE' options, where PACKAGE +is something like `gnu-as' or `x' (for the X Window System). The +`README' should mention any `--enable-' and `--with-' options that the +package recognizes. + + For packages that use the X Window System, `configure' can usually +find the X include and library files automatically, but if it doesn't, +you can use the `configure' options `--x-includes=DIR' and +`--x-libraries=DIR' to specify their locations. + +Specifying the System Type +========================== + +There may be some features `configure' cannot figure out automatically, +but needs to determine by the type of machine the package will run on. +Usually, assuming the package is built to be run on the _same_ +architectures, `configure' can figure that out, but if it prints a +message saying it cannot guess the machine type, give it the +`--build=TYPE' option. TYPE can either be a short name for the system +type, such as `sun4', or a canonical name which has the form: + + CPU-COMPANY-SYSTEM + +where SYSTEM can have one of these forms: + + OS KERNEL-OS + + See the file `config.sub' for the possible values of each field. If +`config.sub' isn't included in this package, then this package doesn't +need to know the machine type. + + If you are _building_ compiler tools for cross-compiling, you should +use the option `--target=TYPE' to select the type of system they will +produce code for. + + If you want to _use_ a cross compiler, that generates code for a +platform different from the build platform, you should specify the +"host" platform (i.e., that on which the generated programs will +eventually be run) with `--host=TYPE'. + +Sharing Defaults +================ + +If you want to set default values for `configure' scripts to share, you +can create a site shell script called `config.site' that gives default +values for variables like `CC', `cache_file', and `prefix'. +`configure' looks for `PREFIX/share/config.site' if it exists, then +`PREFIX/etc/config.site' if it exists. Or, you can set the +`CONFIG_SITE' environment variable to the location of the site script. +A warning: not all `configure' scripts look for a site script. + +Defining Variables +================== + +Variables not defined in a site shell script can be set in the +environment passed to `configure'. However, some packages may run +configure again during the build, and the customized values of these +variables may be lost. In order to avoid this problem, you should set +them in the `configure' command line, using `VAR=value'. For example: + + ./configure CC=/usr/local2/bin/gcc + +causes the specified `gcc' to be used as the C compiler (unless it is +overridden in the site shell script). + +Unfortunately, this technique does not work for `CONFIG_SHELL' due to +an Autoconf bug. Until the bug is fixed you can use this workaround: + + CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash + +`configure' Invocation +====================== + +`configure' recognizes the following options to control how it operates. + +`--help' +`-h' + Print a summary of the options to `configure', and exit. + +`--version' +`-V' + Print the version of Autoconf used to generate the `configure' + script, and exit. + +`--cache-file=FILE' + Enable the cache: use and save the results of the tests in FILE, + traditionally `config.cache'. FILE defaults to `/dev/null' to + disable caching. + +`--config-cache' +`-C' + Alias for `--cache-file=config.cache'. + +`--quiet' +`--silent' +`-q' + Do not print messages saying which checks are being made. To + suppress all normal output, redirect it to `/dev/null' (any error + messages will still be shown). + +`--srcdir=DIR' + Look for the package's source code in directory DIR. Usually + `configure' can determine that directory automatically. + +`configure' also accepts some other, not widely useful, options. Run +`configure --help' for more details. +
diff --git a/ethtool-2.6.35/LICENSE b/ethtool-2.6.35/LICENSE new file mode 100644 index 0000000..d68dccb --- /dev/null +++ b/ethtool-2.6.35/LICENSE
@@ -0,0 +1,3 @@ +ethtool is available under the terms of the GNU Public License version 2. + +See COPYING for details.
diff --git a/ethtool-2.6.35/Makefile.am b/ethtool-2.6.35/Makefile.am new file mode 100644 index 0000000..632f054 --- /dev/null +++ b/ethtool-2.6.35/Makefile.am
@@ -0,0 +1,15 @@ +AM_CFLAGS = -Wall + +man_MANS = ethtool.8 +EXTRA_DIST = LICENSE ethtool.8 ethtool.spec.in aclocal.m4 ChangeLog autogen.sh + +sbin_PROGRAMS = ethtool +ethtool_SOURCES = ethtool.c ethtool-copy.h ethtool-util.h \ + amd8111e.c de2104x.c e100.c e1000.c igb.c \ + fec_8xx.c ibm_emac.c ixgb.c ixgbe.c natsemi.c \ + pcnet32.c realtek.c tg3.c marvell.c vioc.c \ + smsc911x.c at76c50x-usb.c sfc.c + +dist-hook: + cp $(top_srcdir)/ethtool.spec $(distdir) +
diff --git a/ethtool-2.6.35/Makefile.in b/ethtool-2.6.35/Makefile.in new file mode 100644 index 0000000..a8fe297 --- /dev/null +++ b/ethtool-2.6.35/Makefile.in
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diff --git a/ethtool-2.6.35/NEWS b/ethtool-2.6.35/NEWS new file mode 100644 index 0000000..1f3dc86 --- /dev/null +++ b/ethtool-2.6.35/NEWS
@@ -0,0 +1,147 @@ + +Version 2.6.35 - August 10, 2010 + + * Feature: sfc register dump support + * Feature: improve cmd line parsing of ints, IPv4 addresses + * Feature: support ethtool named flags, messaging types + * Feature: minor man page fixes + * Feature: control RX flow hash indirection + +Version 2.6.34 - May 26, 2010 + + * Feature: Support n-tuple filter programming + * Feature: Support rx hashing, v2 (targetted for 2.6.35) + * Feature: Add names of newer Marvell chips + +Version 2.6.33 - February 24, 2010 + + This version introduces a new release numbering scheme, based + on the latest upstream kernel interface supported. + + * Fix: several man page corrections + * Feature: rx flow hash configuration + * Feature: report 10000baseT support, where available + * Feature: report MDI-X status, pause auto-neg, link partner adverts + * Feature: support additional port types + * Feature: support arbitrary speeds, faster than 65535 Mb + * Feature: large and generic receive offload (LRO, GRO) support + * Feature: option to flash firmware image from specified file + * Feature: support for block writing of EEPROMs + * Feature: marvell register dump update + * Feature: at76c50x-usb, e1000e, igb, ixgbe, r8169 register dump support + * Cleanup: remove support for RX hashing by port (was removed in + kernel by 59089d8d162ddcb5c434672e915331964d38a754) + * Doc: Explicitly ship GPLv2 license, rather than relying + on autotools to supply it for us (autotools started auto-installing + GPLv3 recently) + +Version 6 - July 26, 2007 + + * Fix/security: Fix handling of statistics where the label + is exactly 32 bytes (ETH_GSTRING_LEN). + * Feature: Add ability to change the advertised speed/duplex + to a different range of values, rather than all-or-one. + * Feature: ixgb register dump support + * Feature: sky2 register dump support + * Feature: Fabric7 VIOC register dump support + * Feature: Decode raw register dump stored in a file + * Feature: Add ability to force hex register dump, if desired + * Feature: update e1000 register dump + * Feature: Additional 10Gbps support + * Feature: Add 2.5G support + * Feature: Update r8169 register dump + * Feature: SMSC LAN911x/LAN921x register dump support + * Cleanup: Update internal ethtool.h copy to match upstream + kernel 2.6.23-rc1 version of ethtool.h. + +Version 5 - September 1, 2006 + + * Security: Avoid potential buffer overflow + * Feature: GSO support + * Feature: skge register dump + +Version 4 - July 18, 2006 + + * Feature: UFO support + * Feature: support long options + * Features: e1000, pcnet32, tg3 updates + * Feature: added PPC4xx EMAC support + * Feature: Use hexdump instead of single values for register dump + +Version 3 - January 27, 2005 + + * Feature: r8159 register dump support + * Feature / bug fix: Support advertising gigabit ethernet + * Bug fix: make sure to advertise 10baseT-HD + * Other minor bug fixes. + +Version 2 - August 17, 2004 + + * Feature: ethtool register dump raw mode + * Feature: return results of self-test back to OS via exit(2) + * Feature: add verbose register dump for pcnet32, fec_8xx + * Maintenance: update to more recent autoconf + * Maintenance: minor updates to e1000-specific module + * Bug fix: Remove silly restriction on ethernet interface naming + +Version 1.8 - July 19, 2003 + + * Feature: Support amd8111e register dumps + * Feature: Support TSO enable/disable + * Feature: Support 10 gigabit ethernet + * Feature: Support writing EEPROM data + * Feature: Output e100 MDI/MDI-x status in register dump + * Feature: Clean up RealTek (RTL) chip output, support new chips. + * Feature: More supported e1000 devices. + * Bug fix: Properly set ecmd.advertising + * Bug fix: Fix leaks, handle some error conditions better. + +Version 1.7 - October 21, 2002 + + * Feature: Support e100 register dumps + * Feature: Support tg3 eeprom dumps + * Feature: Support partial eeprom dumps (with non-zero offsets) + * Feature: Support decimal/octal/hex numbers transparently, + at the user's discretion. + +Version 1.6 - June 20, 2002 + + * Feature: Support e1000 register dumps + * Feature: Support RealTek RTL-8139C+ and RTL-8169 register dumps + * Feature: Support coalescing config (ETHTOOL_[GS]COALESCE) + * Feature: Support ring param config (ETHTOOL_[GS]RINGPARAM) + * Feature: Support pause param config (ETHTOOL_[GS]PAUSEPARAM) + * Feature: Support physical NIC identification (ETHTOOL_PHYS_ID) + * Feature: Support NIC self-testing (ETHTOOL_TEST) + * Feature: Support NIC checksum/scatter-gather configuration + (ETHTOOL_[GS]RXCSUM, ETHTOOL_[GS]TXCSUM, ETHTOOL_[GS]SG) + +Version 1.5 - Mar 4, 2002 + + * Fix: support usb network interfaces + * Fix: include redhat spec file in autoconf build system + * Fix: minor fixes to natsemi register dump + * Feature: report advertised as well as supported media, + when printing device settings. + +Version 1.4 - Nov 19, 2001 + + * Support builds on configurations missing SIOCETHTOOL constant. + * Import ethtool.h from kernel 2.4.15-pre6. + * Support retrieval/setting of per-driver debug levels + (ETHTOOL G/SMSGLVL) + * Support pretty-printing register dumps on natsemi, de2104x + (ETHTOOL GREGS) + * Support restarting autonegotiation (ETHTOOL NWAY_RST) + * Support obtaining link status (ETHTOOL GLINK) + +Version 1.3 - Aug 02, 2001 + + * Support Wake-on-LAN (ETHTOOL GWOL and ETHTOOL SWOL ioctl). + +Version 1.2 - May 17, 2001 + + * Support ETHTOOL_GDRVINFO ioctl, which obtains + information from the ethernet driver associated + with the specified interface. +
diff --git a/ethtool-2.6.35/README b/ethtool-2.6.35/README new file mode 100644 index 0000000..9e03205 --- /dev/null +++ b/ethtool-2.6.35/README
@@ -0,0 +1,2 @@ +ethtool is a small utility for examining and tuning your ethernet-based +network interface. See the man page for more details.
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However `strip' might not be the right +# tool to use in cross-compilation environments, therefore Automake +# will honor the `STRIP' environment variable to overrule this program. +dnl Don't test for $cross_compiling = yes, because it might be `maybe'. +if test "$cross_compiling" != no; then + AC_CHECK_TOOL([STRIP], [strip], :) +fi +INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" +AC_SUBST([INSTALL_STRIP_PROGRAM])]) + +# Copyright (C) 2006, 2008 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# serial 2 + +# _AM_SUBST_NOTMAKE(VARIABLE) +# --------------------------- +# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in. +# This macro is traced by Automake. +AC_DEFUN([_AM_SUBST_NOTMAKE]) + +# AM_SUBST_NOTMAKE(VARIABLE) +# --------------------------- +# Public sister of _AM_SUBST_NOTMAKE. +AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) + +# Check how to create a tarball. -*- Autoconf -*- + +# Copyright (C) 2004, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# serial 2 + +# _AM_PROG_TAR(FORMAT) +# -------------------- +# Check how to create a tarball in format FORMAT. +# FORMAT should be one of `v7', `ustar', or `pax'. +# +# Substitute a variable $(am__tar) that is a command +# writing to stdout a FORMAT-tarball containing the directory +# $tardir. +# tardir=directory && $(am__tar) > result.tar +# +# Substitute a variable $(am__untar) that extract such +# a tarball read from stdin. +# $(am__untar) < result.tar +AC_DEFUN([_AM_PROG_TAR], +[# Always define AMTAR for backward compatibility. +AM_MISSING_PROG([AMTAR], [tar]) +m4_if([$1], [v7], + [am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -'], + [m4_case([$1], [ustar],, [pax],, + [m4_fatal([Unknown tar format])]) +AC_MSG_CHECKING([how to create a $1 tar archive]) +# Loop over all known methods to create a tar archive until one works. +_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' +_am_tools=${am_cv_prog_tar_$1-$_am_tools} +# Do not fold the above two line into one, because Tru64 sh and +# Solaris sh will not grok spaces in the rhs of `-'. +for _am_tool in $_am_tools +do + case $_am_tool in + gnutar) + for _am_tar in tar gnutar gtar; + do + AM_RUN_LOG([$_am_tar --version]) && break + done + am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' + am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' + am__untar="$_am_tar -xf -" + ;; + plaintar) + # Must skip GNU tar: if it does not support --format= it doesn't create + # ustar tarball either. + (tar --version) >/dev/null 2>&1 && continue + am__tar='tar chf - "$$tardir"' + am__tar_='tar chf - "$tardir"' + am__untar='tar xf -' + ;; + pax) + am__tar='pax -L -x $1 -w "$$tardir"' + am__tar_='pax -L -x $1 -w "$tardir"' + am__untar='pax -r' + ;; + cpio) + am__tar='find "$$tardir" -print | cpio -o -H $1 -L' + am__tar_='find "$tardir" -print | cpio -o -H $1 -L' + am__untar='cpio -i -H $1 -d' + ;; + none) + am__tar=false + am__tar_=false + am__untar=false + ;; + esac + + # If the value was cached, stop now. We just wanted to have am__tar + # and am__untar set. + test -n "${am_cv_prog_tar_$1}" && break + + # tar/untar a dummy directory, and stop if the command works + rm -rf conftest.dir + mkdir conftest.dir + echo GrepMe > conftest.dir/file + AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) + rm -rf conftest.dir + if test -s conftest.tar; then + AM_RUN_LOG([$am__untar <conftest.tar]) + grep GrepMe conftest.dir/file >/dev/null 2>&1 && break + fi +done +rm -rf conftest.dir + +AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) +AC_MSG_RESULT([$am_cv_prog_tar_$1])]) +AC_SUBST([am__tar]) +AC_SUBST([am__untar]) +]) # _AM_PROG_TAR +
diff --git a/ethtool-2.6.35/amd8111e.c b/ethtool-2.6.35/amd8111e.c new file mode 100644 index 0000000..b4cd65d --- /dev/null +++ b/ethtool-2.6.35/amd8111e.c
@@ -0,0 +1,305 @@ + +/* Copyright (C) 2003 Advanced Micro Devices Inc. */ +#include <stdio.h> +#include "ethtool-util.h" + +typedef enum { + /* VAL2 */ + RDMD0 = (1 << 16), + /* VAL1 */ + TDMD3 = (1 << 11), + TDMD2 = (1 << 10), + TDMD1 = (1 << 9), + TDMD0 = (1 << 8), + /* VAL0 */ + UINTCMD = (1 << 6), + RX_FAST_SPND = (1 << 5), + TX_FAST_SPND = (1 << 4), + RX_SPND = (1 << 3), + TX_SPND = (1 << 2), + INTREN = (1 << 1), + RUN = (1 << 0), + + CMD0_CLEAR = 0x000F0F7F, /* Command style register */ + +}CMD0_BITS; +typedef enum { + + /* VAL3 */ + CONDUIT_MODE = (1 << 29), + /* VAL2 */ + RPA = (1 << 19), + DRCVPA = (1 << 18), + DRCVBC = (1 << 17), + PROM = (1 << 16), + /* VAL1 */ + ASTRP_RCV = (1 << 13), + RCV_DROP0 = (1 << 12), + EMBA = (1 << 11), + DXMT2PD = (1 << 10), + LTINTEN = (1 << 9), + DXMTFCS = (1 << 8), + /* VAL0 */ + APAD_XMT = (1 << 6), + DRTY = (1 << 5), + INLOOP = (1 << 4), + EXLOOP = (1 << 3), + REX_RTRY = (1 << 2), + REX_UFLO = (1 << 1), + REX_LCOL = (1 << 0), + + CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */ + +}CMD2_BITS; +typedef enum { + + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), + +}CMD3_BITS; +typedef enum { + + INTR = (1 << 31), + PCSINT = (1 << 28), + LCINT = (1 << 27), + APINT5 = (1 << 26), + APINT4 = (1 << 25), + APINT3 = (1 << 24), + TINT_SUM = (1 << 23), + APINT2 = (1 << 22), + APINT1 = (1 << 21), + APINT0 = (1 << 20), + MIIPDTINT = (1 << 19), + MCCINT = (1 << 17), + MREINT = (1 << 16), + RINT_SUM = (1 << 15), + SPNDINT = (1 << 14), + MPINT = (1 << 13), + SINT = (1 << 12), + TINT3 = (1 << 11), + TINT2 = (1 << 10), + TINT1 = (1 << 9), + TINT0 = (1 << 8), + UINT = (1 << 7), + STINT = (1 << 4), + RINT0 = (1 << 0), + +}INT0_BITS; +typedef enum { + + /* VAL3 */ + LCINTEN = (1 << 27), + APINT5EN = (1 << 26), + APINT4EN = (1 << 25), + APINT3EN = (1 << 24), + /* VAL2 */ + APINT2EN = (1 << 22), + APINT1EN = (1 << 21), + APINT0EN = (1 << 20), + MIIPDTINTEN = (1 << 19), + MCCIINTEN = (1 << 18), + MCCINTEN = (1 << 17), + MREINTEN = (1 << 16), + /* VAL1 */ + SPNDINTEN = (1 << 14), + MPINTEN = (1 << 13), + TINTEN3 = (1 << 11), + SINTEN = (1 << 12), + TINTEN2 = (1 << 10), + TINTEN1 = (1 << 9), + TINTEN0 = (1 << 8), + /* VAL0 */ + STINTEN = (1 << 4), + RINTEN0 = (1 << 0), + + INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */ + +}INTEN0_BITS; + +typedef enum { + + PMAT_DET = (1 << 12), + MP_DET = (1 << 11), + LC_DET = (1 << 10), + SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7), + FULL_DPLX = (1 << 6), + LINK_STATS = (1 << 5), + AUTONEG_COMPLETE = (1 << 4), + MIIPD = (1 << 3), + RX_SUSPENDED = (1 << 2), + TX_SUSPENDED = (1 << 1), + RUNNING = (1 << 0), + +}STAT0_BITS; + +#define PHY_SPEED_10 0x2 +#define PHY_SPEED_100 0x3 + + +int amd8111e_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + + u32 *reg_buff = (u32 *)regs->data; + u32 reg; + + fprintf(stdout, "Descriptor Registers\n"); + fprintf(stdout, "---------------------\n"); + + /* Transmit descriptor base address register */ + reg = reg_buff[0]; + fprintf(stdout, + "0x00100: Transmit descriptor base address register %08X\n",reg); + + /* Transmit descriptor length register */ + reg = reg_buff[1]; + fprintf(stdout, + "0x00140: Transmit descriptor length register 0x%08X\n",reg); + + /* Receive descriptor base address register */ + reg = reg_buff[2]; + fprintf(stdout, + "0x00120: Receive descriptor base address register %08X\n",reg); + + /* Receive descriptor length register */ + reg = reg_buff[3]; + fprintf(stdout, + "0x00150: Receive descriptor length register 0x%08X\n",reg); + + fprintf(stdout, "\n"); + + + fprintf(stdout, "Command Registers\n"); + fprintf(stdout, "-------------------\n"); + + /* Command 0 Register */ + reg = reg_buff[4]; + fprintf(stdout, + "0x00048: Command 0 register 0x%08X\n" + " Interrupts: %s\n" + " Device: %s\n", + reg, + reg & INTREN ? "Enabled" : "Disabled", + reg & RUN ? "Running" : "Stopped"); + + /* Command 2 Register */ + reg = reg_buff[5]; + fprintf(stdout, + "0x00050: Command 2 register 0x%08X\n" + " Promiscuous mode: %s\n" + " Retransmit on underflow: %s\n", + reg, + reg & PROM ? "Enabled" : "Disabled", + reg & REX_UFLO ? "Enabled" : "Disabled"); + /* Command 3 Register */ + reg = reg_buff[6]; + fprintf(stdout, + "0x00054: Command 3 register 0x%08X\n" + " Jumbo frame: %s\n" + " Admit only VLAN frame: %s\n" + " Delete VLAN tag: %s\n", + reg, + reg & JUMBO ? "Enabled" : "Disabled", + reg & VLONLY ? "Yes" : "No", + reg & VL_TAG_DEL ? "Yes" : "No"); + + /* Command 7 Register */ + reg = reg_buff[7]; + fprintf(stdout, + "0x00064: Command 7 register 0x%08X\n", + reg); + + fprintf(stdout, "\n"); + fprintf(stdout, "Interrupt Registers\n"); + fprintf(stdout, "-------------------\n"); + + /* Interrupt 0 Register */ + reg = reg_buff[8]; + fprintf(stdout, + "0x00038: Interrupt register 0x%08X\n" + " Any interrupt is set: %s\n" + " Link change interrupt: %s\n" + " Register 0 auto-poll interrupt: %s\n" + " Transmit interrupt: %s\n" + " Software timer interrupt: %s\n" + " Receive interrupt: %s\n", + reg, + reg & INTR ? "Yes" : "No", + reg & LCINT ? "Yes" : "No", + reg & APINT0 ? "Yes" : "No", + reg & TINT0 ? "Yes" : "No", + reg & STINT ? "Yes" : "No", + reg & RINT0 ? "Yes" : "No" + ); + /* Interrupt 0 enable Register */ + reg = reg_buff[9]; + fprintf(stdout, + "0x00040: Interrupt enable register 0x%08X\n" + " Link change interrupt: %s\n" + " Register 0 auto-poll interrupt: %s\n" + " Transmit interrupt: %s\n" + " Software timer interrupt: %s\n" + " Receive interrupt: %s\n", + reg, + reg & LCINTEN ? "Enabled" : "Disabled", + reg & APINT0EN ? "Enabled" : "Disabled", + reg & TINTEN0 ? "Enabled" : "Disabled", + reg & STINTEN ? "Enabled" : "Disabled", + reg & RINTEN0 ? "Enabled" : "Disabled" + ); + + fprintf(stdout, "\n"); + fprintf(stdout, "Logical Address Filter Register\n"); + fprintf(stdout, "-------------------\n"); + + /* Logical Address Filter Register */ + fprintf(stdout, + "0x00168: Logical address filter register 0x%08X%08X\n", + reg_buff[11],reg_buff[10]); + + fprintf(stdout, "\n"); + fprintf(stdout, "Link status Register\n"); + fprintf(stdout, "-------------------\n"); + + /* Status 0 Register */ + reg = reg_buff[12]; + if(reg & LINK_STATS){ + fprintf(stdout, + "0x00030: Link status register 0x%08X\n" + " Link status: %s\n" + " Auto negotiation complete %s\n" + " Duplex %s\n" + " Speed %s\n", + reg, + reg & LINK_STATS ? "Valid" : "Invalid", + reg & AUTONEG_COMPLETE ? "Yes" : "No", + reg & FULL_DPLX ? "Full" : "Half", + ((reg & SPEED_MASK) >> 7 == PHY_SPEED_10) ? "10Mbits/ Sec": + "100Mbits/Sec"); + + } + else{ + fprintf(stdout, + "0x00030: Link status register 0x%08X\n" + " Link status: %s\n", + reg, + reg & LINK_STATS ? "Valid" : "Invalid"); + } + return 0; + +}
diff --git a/ethtool-2.6.35/at76c50x-usb.c b/ethtool-2.6.35/at76c50x-usb.c new file mode 100644 index 0000000..4c2a1a8 --- /dev/null +++ b/ethtool-2.6.35/at76c50x-usb.c
@@ -0,0 +1,32 @@ +#include <stdio.h> +#include "ethtool-util.h" + +static char *hw_versions[] = { + "503_ISL3861", + "503_ISL3863", + " 503", + " 503_ACC", + " 505", + " 505_2958", + " 505A", + " 505AMX", +}; + +int +at76c50x_usb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u8 version = (u8)(regs->version >> 24); + u8 rev_id = (u8)(regs->version); + char *ver_string; + + if (version != 0) + return -1; + + ver_string = hw_versions[rev_id]; + fprintf(stdout, + "Hardware Version %s\n", + ver_string); + + return 0; +} +
diff --git a/ethtool-2.6.35/autogen.sh b/ethtool-2.6.35/autogen.sh new file mode 100755 index 0000000..9f98ef8 --- /dev/null +++ b/ethtool-2.6.35/autogen.sh
@@ -0,0 +1,11 @@ +#!/bin/sh + +# You need autoconf 2.5x, preferably 2.57 or later +# You need automake 1.7 or later. 1.6 might work. + +set -e + +aclocal +autoheader +automake --gnu --add-missing --copy +autoconf
diff --git a/ethtool-2.6.35/configure b/ethtool-2.6.35/configure new file mode 100755 index 0000000..42c2f77 --- /dev/null +++ b/ethtool-2.6.35/configure Binary files differ
diff --git a/ethtool-2.6.35/configure.ac b/ethtool-2.6.35/configure.ac new file mode 100644 index 0000000..4b7b757 --- /dev/null +++ b/ethtool-2.6.35/configure.ac
@@ -0,0 +1,26 @@ +dnl Process this file with autoconf to produce a configure script. +AC_INIT(ethtool, 2.6.35, [Jeff Garzik <jgarzik@pobox.com>]) +AC_PREREQ(2.52) +AC_CONFIG_SRCDIR([ethtool.c]) +AM_INIT_AUTOMAKE([gnu]) +AC_CONFIG_HEADERS([ethtool-config.h]) + +AM_MAINTAINER_MODE + +dnl Checks for programs. +AC_PROG_CC +AC_PROG_GCC_TRADITIONAL + +dnl Checks for libraries. + +dnl Checks for header files. +AC_CHECK_HEADERS(sys/ioctl.h) + +dnl Checks for typedefs, structures, and compiler characteristics. + +dnl Checks for library functions. +AC_HEADER_STDC +AC_CHECK_FUNCS(socket strtol) + +AC_CONFIG_FILES([Makefile ethtool.spec]) +AC_OUTPUT
diff --git a/ethtool-2.6.35/de2104x.c b/ethtool-2.6.35/de2104x.c new file mode 100644 index 0000000..f64e1b2 --- /dev/null +++ b/ethtool-2.6.35/de2104x.c
@@ -0,0 +1,783 @@ +/* Copyright 2001 Sun Microsystems (thockin@sun.com) */ +#include <stdio.h> +#include "ethtool-util.h" + +static const char * const csr0_tap[4] = { + "No transmit automatic polling", + "Transmit automatic polling every 200 seconds", + "Transmit automatic polling every 800 seconds", + "Transmit automatic polling every 1.6 milliseconds", +}; + +static const char * const csr0_cache_al[4] = { + "not used", + "8-longword boundary alignment", + "16-longword boundary alignment", + "32-longword boundary alignment", +}; + +static const char * const csr5_buserr[8] = { + " Bus error: parity", + " Bus error: master abort", + " Bus error: target abort", + " Bus error: (unknown code, reserved)", + " Bus error: (unknown code, reserved)", + " Bus error: (unknown code, reserved)", + " Bus error: (unknown code, reserved)", + " Bus error: (unknown code, reserved)", +}; + +static const int csr6_tx_thresh[4] = { + 72, + 96, + 128, + 160, +}; + +static const char * const csr6_om[4] = { + "normal", + "internal loopback", + "external loopback", + "unknown (not used)", +}; + +static const char * const csr5_tx_state[8] = { + "stopped", + "running: fetch desc", + "running: wait xmit end", + "running: read buf", + "unknown (reserved)", + "running: setup packet", + "suspended", + "running: close desc", +}; + +static const char * const csr5_rx_state[8] = { + "stopped", + "running: fetch desc", + "running: chk pkt end", + "running: wait for pkt", + "suspended", + "running: close", + "running: flush", + "running: queue", +}; + +static const char * const csr12_nway_state[8] = { + "Autonegotiation disable", + "Transmit disable", + "Ability detect", + "Acknowledge detect", + "Complete acknowledge", + "FLP link good, nway complete", + "Link check", + "unknown (reserved)", +}; + +static const char * const csr14_tp_comp[4] = { + "Compensation Disabled Mode", + "Compensation Disabled Mode", + "High Power Mode", + "Normal Compensation Mode", +}; + +static void +print_ring_addresses(u32 csr3, u32 csr4) +{ + fprintf(stdout, + "0x18: CSR3 (Rx Ring Base Address) 0x%08x\n" + "0x20: CSR4 (Tx Ring Base Address) 0x%08x\n" + , + csr3, + csr4); +} + +static void +print_rx_missed(u32 csr8) +{ + fprintf(stdout, + "0x40: CSR8 (Missed Frames Counter) 0x%08x\n", csr8); + if (csr8 & (1 << 16)) + fprintf(stdout, + " Counter overflow\n"); + else { + unsigned int rx_missed = csr8 & 0xffff; + if (!rx_missed) + fprintf(stdout, + " No missed frames\n"); + else + fprintf(stdout, + " %u missed frames\n", rx_missed); + } +} + +static void +de21040_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 tmp, v, *data = (u32 *)regs->data; + + fprintf(stdout, "21040 Registers\n"); + fprintf(stdout, "---------------\n"); + + /* + * CSR0 + */ + v = data[0]; + fprintf(stdout, + "0x00: CSR0 (Bus Mode) 0x%08x\n" + " %s\n" + " %s address space\n" + " Cache alignment: %s\n" + , + v, + csr0_tap[(v >> 17) & 3], + v & (1 << 16) ? "Diagnostic" : "Standard", + csr0_cache_al[(v >> 14) & 3]); + tmp = (v >> 8) & 0x3f; + if (tmp == 0) + fprintf(stdout, " Programmable burst length unlimited\n"); + else + fprintf(stdout, + " Programmable burst length %d longwords\n", + tmp); + fprintf(stdout, + " %s endian data buffers\n" + " Descriptor skip length %d longwords\n" + " %s bus arbitration scheme\n" + , + v & (1 << 7) ? "Big" : "Little", + (v >> 2) & 0x1f, + v & (1 << 1) ? "Round-robin" : "RX-has-priority"); + if (v & (1 << 0)) + fprintf(stdout, " Software reset asserted\n"); + + /* + * CSR3, 4 + */ + print_ring_addresses(data[3], data[4]); + + /* + * CSR5 + */ + v = data[5]; + fprintf(stdout, + "0x28: CSR5 (Status) 0x%08x\n" + "%s" + " Transmit process %s\n" + " Receive process %s\n" + " Link %s\n" + , + v, + v & (1 << 13) ? csr5_buserr[(v >> 23) & 0x7] : "", + csr5_tx_state[(v >> 20) & 0x7], + csr5_rx_state[(v >> 17) & 0x7], + v & (1 << 12) ? "fail" : "OK"); + if (v & (1 << 16)) + fprintf(stdout, + " Normal interrupts: %s%s%s\n" + , + v & (1 << 0) ? "TxOK " : "", + v & (1 << 2) ? "TxNoBufs " : "", + v & (1 << 6) ? "RxOK" : ""); + if (v & (1 << 15)) + fprintf(stdout, + " Abnormal intr: %s%s%s%s%s%s%s%s\n" + , + v & (1 << 1) ? "TxStop " : "", + v & (1 << 3) ? "TxJabber " : "", + v & (1 << 5) ? "TxUnder " : "", + v & (1 << 7) ? "RxNoBufs " : "", + v & (1 << 8) ? "RxStopped " : "", + v & (1 << 9) ? "RxTimeout " : "", + v & (1 << 10) ? "AUI_TP " : "", + v & (1 << 11) ? "FD_Short " : ""); + + /* + * CSR6 + */ + v = data[6]; + fprintf(stdout, + "0x30: CSR6 (Operating Mode) 0x%08x\n" + "%s" + "%s" + " Transmit threshold %d bytes\n" + " Transmit DMA %sabled\n" + "%s" + " Operating mode: %s\n" + " %s duplex\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + " Receive DMA %sabled\n" + " %s filtering mode\n" + , + v, + v & (1<<17) ? " Capture effect enabled\n" : "", + v & (1<<16) ? " Back pressure enabled\n" : "", + csr6_tx_thresh[(v >> 14) & 3], + v & (1<<13) ? "en" : "dis", + v & (1<<12) ? " Forcing collisions\n" : "", + csr6_om[(v >> 10) & 3], + v & (1<<9) ? "Full" : "Half", + v & (1<<8) ? " Flaky oscillator disable\n" : "", + v & (1<<7) ? " Pass All Multicast\n" : "", + v & (1<<6) ? " Promisc Mode\n" : "", + v & (1<<5) ? " Start/Stop Backoff Counter\n" : "", + v & (1<<4) ? " Inverse Filtering\n" : "", + v & (1<<3) ? " Pass Bad Frames\n" : "", + v & (1<<2) ? " Hash-only Filtering\n" : "", + v & (1<<1) ? "en" : "dis", + v & (1<<0) ? "Hash" : "Perfect"); + + /* + * CSR7 + */ + v = data[7]; + fprintf(stdout, + "0x38: CSR7 (Interrupt Mask) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + , + v, + v & (1<<16) ? " Normal interrupt summary\n" : "", + v & (1<<15) ? " Abnormal interrupt summary\n" : "", + v & (1<<13) ? " System error\n" : "", + v & (1<<12) ? " Link fail\n" : "", + v & (1<<11) ? " Full duplex\n" : "", + v & (1<<10) ? " AUI_TP pin\n" : "", + v & (1<<9) ? " Receive watchdog timeout\n" : "", + v & (1<<8) ? " Receive stopped\n" : "", + v & (1<<7) ? " Receive buffer unavailable\n" : "", + v & (1<<6) ? " Receive interrupt\n" : "", + v & (1<<5) ? " Transmit underflow\n" : "", + v & (1<<3) ? " Transmit jabber timeout\n" : "", + v & (1<<2) ? " Transmit buffer unavailable\n" : "", + v & (1<<1) ? " Transmit stopped\n" : "", + v & (1<<0) ? " Transmit interrupt\n" : ""); + + /* + * CSR8 + */ + print_rx_missed(data[8]); + + /* + * CSR9 + */ + v = data[9]; + fprintf(stdout, + "0x48: CSR9 (Ethernet Address ROM) 0x%08x\n", v); + + /* + * CSR11 + */ + v = data[11]; + fprintf(stdout, + "0x58: CSR11 (Full Duplex Autoconfig) 0x%08x\n", v); + + /* + * CSR12 + */ + v = data[12]; + fprintf(stdout, + "0x60: CSR12 (SIA Status) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + " AUI_TP pin: %s\n" + , + v, + v & (1<<7) ? " PLL sampler high\n" : "", + v & (1<<6) ? " PLL sampler low\n" : "", + v & (1<<5) ? " PLL self-test pass\n" : "", + v & (1<<4) ? " PLL self-test done\n" : "", + v & (1<<3) ? " Autopolarity state\n" : "", + v & (1<<2) ? " Link fail\n" : "", + v & (1<<1) ? " Network connection error\n" : "", + v & (1<<0) ? "AUI" : "TP"); + + /* + * CSR13 + */ + v = data[13]; + fprintf(stdout, + "0x68: CSR13 (SIA Connectivity) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + " External port output multiplexer select: %u%u%u%u\n" + "%s" + "%s" + "%s" + "%s" + " %s interface selected\n" + "%s" + "%s" + "%s" + , + v, + v & (1<<15) ? " Enable pins 5, 6, 7\n" : "", + v & (1<<14) ? " Enable pins 2, 4\n" : "", + v & (1<<13) ? " Enable pins 1, 3\n" : "", + v & (1<<12) ? " Input enable\n" : "", + v & (1<<11) ? 1 : 0, + v & (1<<10) ? 1 : 0, + v & (1<<9) ? 1 : 0, + v & (1<<8) ? 1 : 0, + v & (1<<7) ? " APLL start\n" : "", + v & (1<<6) ? " Serial interface input multiplexer\n" : "", + v & (1<<5) ? " Encoder input multiplexer\n" : "", + v & (1<<4) ? " SIA PLL external input enable\n" : "", + v & (1<<3) ? "AUI" : "10base-T", + v & (1<<2) ? " CSR autoconfiguration\n" : "", + v & (1<<1) ? " AUI_TP pin autoconfiguration\n" : "", + v & (1<<0) ? " SIA reset\n" : ""); + + /* + * CSR14 + */ + v = data[14]; + fprintf(stdout, + "0x70: CSR14 (SIA Transmit and Receive) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + " %s\n" + "%s" + "%s" + "%s" + "%s" + , + v, + v & (1<<14) ? " Set polarity plus\n" : "", + v & (1<<13) ? " Autopolarity enable\n" : "", + v & (1<<12) ? " Link test enable\n" : "", + v & (1<<11) ? " Heartbeat enable\n" : "", + v & (1<<10) ? " Collision detect enable\n" : "", + v & (1<<9) ? " Collision squelch enable\n" : "", + v & (1<<8) ? " Receive squelch enable\n" : "", + csr14_tp_comp[(v >> 4) & 0x3], + v & (1<<3) ? " Link pulse send enable\n" : "", + v & (1<<2) ? " Driver enable\n" : "", + v & (1<<1) ? " Loopback enable\n" : "", + v & (1<<0) ? " Encoder enable\n" : ""); + + /* + * CSR15 + */ + v = data[15]; + fprintf(stdout, + "0x78: CSR15 (SIA General) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + , + v, + v & (1<<13) ? " Force receiver low\n" : "", + v & (1<<12) ? " PLL self-test start\n" : "", + v & (1<<11) ? " Force link fail\n" : "", + v & (1<<9) ? " Force unsquelch\n" : "", + v & (1<<8) ? " Test clock\n" : "", + v & (1<<5) ? " Receive watchdog release\n" : "", + v & (1<<4) ? " Receive watchdog disable\n" : "", + v & (1<<2) ? " Jabber clock\n" : "", + v & (1<<1) ? " Host unjab\n" : "", + v & (1<<0) ? " Jabber disable\n" : ""); +} + +static void +de21041_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 tmp, v, *data = (u32 *)regs->data; + + fprintf(stdout, "21041 Registers\n"); + fprintf(stdout, "---------------\n"); + + /* + * CSR0 + */ + v = data[0]; + fprintf(stdout, + "0x00: CSR0 (Bus Mode) 0x%08x\n" + " %s endian descriptors\n" + " %s\n" + " %s address space\n" + " Cache alignment: %s\n" + , + v, + v & (1 << 20) ? "Big" : "Little", + csr0_tap[(v >> 17) & 3], + v & (1 << 16) ? "Diagnostic" : "Standard", + csr0_cache_al[(v >> 14) & 3]); + tmp = (v >> 8) & 0x3f; + if (tmp == 0) + fprintf(stdout, " Programmable burst length unlimited\n"); + else + fprintf(stdout, + " Programmable burst length %d longwords\n", + tmp); + fprintf(stdout, + " %s endian data buffers\n" + " Descriptor skip length %d longwords\n" + " %s bus arbitration scheme\n" + , + v & (1 << 7) ? "Big" : "Little", + (v >> 2) & 0x1f, + v & (1 << 1) ? "Round-robin" : "RX-has-priority"); + if (v & (1 << 0)) + fprintf(stdout, " Software reset asserted\n"); + + /* + * CSR3, 4 + */ + print_ring_addresses(data[3], data[4]); + + /* + * CSR5 + */ + v = data[5]; + fprintf(stdout, + "0x28: CSR5 (Status) 0x%08x\n" + "%s" + " Transmit process %s\n" + " Receive process %s\n" + " Link %s\n" + , + v, + v & (1 << 13) ? csr5_buserr[(v >> 23) & 0x7] : "", + csr5_tx_state[(v >> 20) & 0x7], + csr5_rx_state[(v >> 17) & 0x7], + v & (1 << 12) ? "fail" : "OK"); + if (v & (1 << 16)) + fprintf(stdout, + " Normal interrupts: %s%s%s%s%s\n" + , + v & (1 << 0) ? "TxOK " : "", + v & (1 << 2) ? "TxNoBufs " : "", + v & (1 << 6) ? "RxOK" : "", + v & (1 << 11) ? "TimerExp " : "", + v & (1 << 14) ? "EarlyRx " : ""); + if (v & (1 << 15)) + fprintf(stdout, + " Abnormal intr: %s%s%s%s%s%s%s\n" + , + v & (1 << 1) ? "TxStop " : "", + v & (1 << 3) ? "TxJabber " : "", + v & (1 << 4) ? "ANC " : "", + v & (1 << 5) ? "TxUnder " : "", + v & (1 << 7) ? "RxNoBufs " : "", + v & (1 << 8) ? "RxStopped " : "", + v & (1 << 9) ? "RxTimeout " : ""); + + /* + * CSR6 + */ + v = data[6]; + fprintf(stdout, + "0x30: CSR6 (Operating Mode) 0x%08x\n" + "%s" + "%s" + " Transmit threshold %d bytes\n" + " Transmit DMA %sabled\n" + "%s" + " Operating mode: %s\n" + " %s duplex\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + " Receive DMA %sabled\n" + " %s filtering mode\n" + , + v, + v & (1<<31) ? " Special capture effect enabled\n" : "", + v & (1<<17) ? " Capture effect enabled\n" : "", + csr6_tx_thresh[(v >> 14) & 3], + v & (1<<13) ? "en" : "dis", + v & (1<<12) ? " Forcing collisions\n" : "", + csr6_om[(v >> 10) & 3], + v & (1<<9) ? "Full" : "Half", + v & (1<<8) ? " Flaky oscillator disable\n" : "", + v & (1<<7) ? " Pass All Multicast\n" : "", + v & (1<<6) ? " Promisc Mode\n" : "", + v & (1<<5) ? " Start/Stop Backoff Counter\n" : "", + v & (1<<4) ? " Inverse Filtering\n" : "", + v & (1<<3) ? " Pass Bad Frames\n" : "", + v & (1<<2) ? " Hash-only Filtering\n" : "", + v & (1<<1) ? "en" : "dis", + v & (1<<0) ? "Hash" : "Perfect"); + + /* + * CSR7 + */ + v = data[7]; + fprintf(stdout, + "0x38: CSR7 (Interrupt Mask) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + , + v, + v & (1<<16) ? " Normal interrupt summary\n" : "", + v & (1<<15) ? " Abnormal interrupt summary\n" : "", + v & (1<<14) ? " Early receive interrupt\n" : "", + v & (1<<13) ? " System error\n" : "", + v & (1<<12) ? " Link fail\n" : "", + v & (1<<11) ? " Timer expired\n" : "", + v & (1<<9) ? " Receive watchdog timeout\n" : "", + v & (1<<8) ? " Receive stopped\n" : "", + v & (1<<7) ? " Receive buffer unavailable\n" : "", + v & (1<<6) ? " Receive interrupt\n" : "", + v & (1<<5) ? " Transmit underflow\n" : "", + v & (1<<4) ? " Link pass\n" : "", + v & (1<<3) ? " Transmit jabber timeout\n" : "", + v & (1<<2) ? " Transmit buffer unavailable\n" : "", + v & (1<<1) ? " Transmit stopped\n" : "", + v & (1<<0) ? " Transmit interrupt\n" : ""); + + /* + * CSR8 + */ + print_rx_missed(data[8]); + + /* + * CSR9 + */ + v = data[9]; + fprintf(stdout, + "0x48: CSR9 (Boot and Ethernet ROMs) 0x%08x\n" + " Select bits: %s%s%s%s%s%s\n" + " Data: %d%d%d%d%d%d%d%d\n" + , + v, + v & (1<<15) ? "Mode " : "", + v & (1<<14) ? "Read " : "", + v & (1<<13) ? "Write " : "", + v & (1<<12) ? "BootROM " : "", + v & (1<<11) ? "SROM " : "", + v & (1<<10) ? "ExtReg " : "", + v & (1<<7) ? 1 : 0, + v & (1<<6) ? 1 : 0, + v & (1<<5) ? 1 : 0, + v & (1<<4) ? 1 : 0, + v & (1<<3) ? 1 : 0, + v & (1<<2) ? 1 : 0, + v & (1<<1) ? 1 : 0, + v & (1<<0) ? 1 : 0); + + /* + * CSR10 + */ + v = data[10]; + fprintf(stdout, + "0x50: CSR10 (Boot ROM Address) 0x%08x\n", v); + + /* + * CSR11 + */ + v = data[11]; + fprintf(stdout, + "0x58: CSR11 (General Purpose Timer) 0x%08x\n" + "%s" + " Timer value: %u cycles\n" + , + v, + v & (1<<16) ? " Continuous mode\n" : "", + v & 0xffff); + + /* + * CSR12 + */ + v = data[12]; + fprintf(stdout, + "0x60: CSR12 (SIA Status) 0x%08x\n" + " Link partner code word 0x%04x\n" + "%s" + " NWay state: %s\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + , + v, + v >> 16, + v & (1<<15) ? " Link partner negotiable\n" : "", + csr12_nway_state[(v >> 12) & 0x7], + v & (1<<11) ? " Transmit remote fault\n" : "", + v & (1<<10) ? " Unstable NLP detected\n" : "", + v & (1<<9) ? " Non-selected port receive activity\n" : "", + v & (1<<8) ? " Selected port receive activity\n" : "", + v & (1<<7) ? " PLL sampler high\n" : "", + v & (1<<6) ? " PLL sampler low\n" : "", + v & (1<<5) ? " PLL self-test pass\n" : "", + v & (1<<4) ? " PLL self-test done\n" : "", + v & (1<<3) ? " Autopolarity state\n" : "", + v & (1<<2) ? " Link fail\n" : "", + v & (1<<1) ? " Network connection error\n" : ""); + + /* + * CSR13 + */ + v = data[13]; + fprintf(stdout, + "0x68: CSR13 (SIA Connectivity) 0x%08x\n" + " SIA Diagnostic Mode 0x%04x\n" + " %s\n" + "%s" + "%s" + , + v, + (v >> 4) & 0xfff, + v & (1<<3) ? "AUI/BNC port" : "10base-T port", + v & (1<<2) ? " CSR autoconfiguration enabled\n" : "", + v & (1<<0) ? " SIA register reset asserted\n" : ""); + + /* + * CSR14 + */ + v = data[14]; + fprintf(stdout, + "0x70: CSR14 (SIA Transmit and Receive) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + " %s\n" + "%s" + "%s" + "%s" + "%s" + , + v, + v & (1<<15) ? " 10base-T/AUI autosensing\n" : "", + v & (1<<14) ? " Set polarity plus\n" : "", + v & (1<<13) ? " Autopolarity enable\n" : "", + v & (1<<12) ? " Link test enable\n" : "", + v & (1<<11) ? " Heartbeat enable\n" : "", + v & (1<<10) ? " Collision detect enable\n" : "", + v & (1<<9) ? " Collision squelch enable\n" : "", + v & (1<<8) ? " Receive squelch enable\n" : "", + v & (1<<7) ? " Autonegotiation enable\n" : "", + v & (1<<6) ? " Must Be One\n" : "", + csr14_tp_comp[(v >> 4) & 0x3], + v & (1<<3) ? " Link pulse send enable\n" : "", + v & (1<<2) ? " Driver enable\n" : "", + v & (1<<1) ? " Loopback enable\n" : "", + v & (1<<0) ? " Encoder enable\n" : ""); + + /* + * CSR15 + */ + v = data[15]; + fprintf(stdout, + "0x78: CSR15 (SIA General) 0x%08x\n" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + "%s" + " %s port selected\n" + "%s" + "%s" + "%s" + , + v, + v & (1<<15) ? " GP LED2 on\n" : "", + v & (1<<14) ? " GP LED2 enable\n" : "", + v & (1<<13) ? " Force receiver low\n" : "", + v & (1<<12) ? " PLL self-test start\n" : "", + v & (1<<11) ? " LED stretch disable\n" : "", + v & (1<<10) ? " Force link fail\n" : "", + v & (1<<9) ? " Force unsquelch\n" : "", + v & (1<<8) ? " Test clock\n" : "", + v & (1<<7) ? " GP LED1 on\n" : "", + v & (1<<6) ? " GP LED1 enable\n" : "", + v & (1<<5) ? " Receive watchdog release\n" : "", + v & (1<<4) ? " Receive watchdog disable\n" : "", + v & (1<<3) ? "AUI" : "BNC", + v & (1<<2) ? " Jabber clock\n" : "", + v & (1<<1) ? " Host unjab\n" : "", + v & (1<<0) ? " Jabber disable\n" : ""); +} + +int +de2104x_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + unsigned int de21040 = regs->version & 1; + + if (de21040) + de21040_dump_regs(info, regs); + else + de21041_dump_regs(info, regs); + + return 0; +} +
diff --git a/ethtool-2.6.35/depcomp b/ethtool-2.6.35/depcomp new file mode 100755 index 0000000..e5f9736 --- /dev/null +++ b/ethtool-2.6.35/depcomp
@@ -0,0 +1,589 @@ +#! /bin/sh +# depcomp - compile a program generating dependencies as side-effects + +scriptversion=2007-03-29.01 + +# Copyright (C) 1999, 2000, 2003, 2004, 2005, 2006, 2007 Free Software +# Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# 02110-1301, USA. + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Originally written by Alexandre Oliva <oliva@dcc.unicamp.br>. + +case $1 in + '') + echo "$0: No command. Try \`$0 --help' for more information." 1>&2 + exit 1; + ;; + -h | --h*) + cat <<\EOF +Usage: depcomp [--help] [--version] PROGRAM [ARGS] + +Run PROGRAMS ARGS to compile a file, generating dependencies +as side-effects. + +Environment variables: + depmode Dependency tracking mode. + source Source file read by `PROGRAMS ARGS'. + object Object file output by `PROGRAMS ARGS'. + DEPDIR directory where to store dependencies. + depfile Dependency file to output. + tmpdepfile Temporary file to use when outputing dependencies. + libtool Whether libtool is used (yes/no). + +Report bugs to <bug-automake@gnu.org>. +EOF + exit $? + ;; + -v | --v*) + echo "depcomp $scriptversion" + exit $? + ;; +esac + +if test -z "$depmode" || test -z "$source" || test -z "$object"; then + echo "depcomp: Variables source, object and depmode must be set" 1>&2 + exit 1 +fi + +# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. +depfile=${depfile-`echo "$object" | + sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} +tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} + +rm -f "$tmpdepfile" + +# Some modes work just like other modes, but use different flags. We +# parameterize here, but still list the modes in the big case below, +# to make depend.m4 easier to write. Note that we *cannot* use a case +# here, because this file can only contain one case statement. +if test "$depmode" = hp; then + # HP compiler uses -M and no extra arg. + gccflag=-M + depmode=gcc +fi + +if test "$depmode" = dashXmstdout; then + # This is just like dashmstdout with a different argument. + dashmflag=-xM + depmode=dashmstdout +fi + +case "$depmode" in +gcc3) +## gcc 3 implements dependency tracking that does exactly what +## we want. Yay! Note: for some reason libtool 1.4 doesn't like +## it if -MD -MP comes after the -MF stuff. Hmm. +## Unfortunately, FreeBSD c89 acceptance of flags depends upon +## the command line argument order; so add the flags where they +## appear in depend2.am. Note that the slowdown incurred here +## affects only configure: in makefiles, %FASTDEP% shortcuts this. + for arg + do + case $arg in + -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; + *) set fnord "$@" "$arg" ;; + esac + shift # fnord + shift # $arg + done + "$@" + stat=$? + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile" + exit $stat + fi + mv "$tmpdepfile" "$depfile" + ;; + +gcc) +## There are various ways to get dependency output from gcc. Here's +## why we pick this rather obscure method: +## - Don't want to use -MD because we'd like the dependencies to end +## up in a subdir. Having to rename by hand is ugly. +## (We might end up doing this anyway to support other compilers.) +## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like +## -MM, not -M (despite what the docs say). +## - Using -M directly means running the compiler twice (even worse +## than renaming). + if test -z "$gccflag"; then + gccflag=-MD, + fi + "$@" -Wp,"$gccflag$tmpdepfile" + stat=$? + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + echo "$object : \\" > "$depfile" + alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz +## The second -e expression handles DOS-style file names with drive letters. + sed -e 's/^[^:]*: / /' \ + -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" +## This next piece of magic avoids the `deleted header file' problem. +## The problem is that when a header file which appears in a .P file +## is deleted, the dependency causes make to die (because there is +## typically no way to rebuild the header). We avoid this by adding +## dummy dependencies for each header file. Too bad gcc doesn't do +## this for us directly. + tr ' ' ' +' < "$tmpdepfile" | +## Some versions of gcc put a space before the `:'. On the theory +## that the space means something, we add a space to the output as +## well. +## Some versions of the HPUX 10.20 sed can't process this invocation +## correctly. Breaking it into two sed invocations is a workaround. + sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +hp) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +sgi) + if test "$libtool" = yes; then + "$@" "-Wp,-MDupdate,$tmpdepfile" + else + "$@" -MDupdate "$tmpdepfile" + fi + stat=$? + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + + if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files + echo "$object : \\" > "$depfile" + + # Clip off the initial element (the dependent). Don't try to be + # clever and replace this with sed code, as IRIX sed won't handle + # lines with more than a fixed number of characters (4096 in + # IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines; + # the IRIX cc adds comments like `#:fec' to the end of the + # dependency line. + tr ' ' ' +' < "$tmpdepfile" \ + | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' | \ + tr ' +' ' ' >> $depfile + echo >> $depfile + + # The second pass generates a dummy entry for each header file. + tr ' ' ' +' < "$tmpdepfile" \ + | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \ + >> $depfile + else + # The sourcefile does not contain any dependencies, so just + # store a dummy comment line, to avoid errors with the Makefile + # "include basename.Plo" scheme. + echo "#dummy" > "$depfile" + fi + rm -f "$tmpdepfile" + ;; + +aix) + # The C for AIX Compiler uses -M and outputs the dependencies + # in a .u file. In older versions, this file always lives in the + # current directory. Also, the AIX compiler puts `$object:' at the + # start of each line; $object doesn't have directory information. + # Version 6 uses the directory in both cases. + dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` + test "x$dir" = "x$object" && dir= + base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` + if test "$libtool" = yes; then + tmpdepfile1=$dir$base.u + tmpdepfile2=$base.u + tmpdepfile3=$dir.libs/$base.u + "$@" -Wc,-M + else + tmpdepfile1=$dir$base.u + tmpdepfile2=$dir$base.u + tmpdepfile3=$dir$base.u + "$@" -M + fi + stat=$? + + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + do + test -f "$tmpdepfile" && break + done + if test -f "$tmpdepfile"; then + # Each line is of the form `foo.o: dependent.h'. + # Do two passes, one to just change these to + # `$object: dependent.h' and one to simply `dependent.h:'. + sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile" + # That's a tab and a space in the []. + sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile" + else + # The sourcefile does not contain any dependencies, so just + # store a dummy comment line, to avoid errors with the Makefile + # "include basename.Plo" scheme. + echo "#dummy" > "$depfile" + fi + rm -f "$tmpdepfile" + ;; + +icc) + # Intel's C compiler understands `-MD -MF file'. However on + # icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c + # ICC 7.0 will fill foo.d with something like + # foo.o: sub/foo.c + # foo.o: sub/foo.h + # which is wrong. We want: + # sub/foo.o: sub/foo.c + # sub/foo.o: sub/foo.h + # sub/foo.c: + # sub/foo.h: + # ICC 7.1 will output + # foo.o: sub/foo.c sub/foo.h + # and will wrap long lines using \ : + # foo.o: sub/foo.c ... \ + # sub/foo.h ... \ + # ... + + "$@" -MD -MF "$tmpdepfile" + stat=$? + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + # Each line is of the form `foo.o: dependent.h', + # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'. + # Do two passes, one to just change these to + # `$object: dependent.h' and one to simply `dependent.h:'. + sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process this invocation + # correctly. Breaking it into two sed invocations is a workaround. + sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" | + sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +hp2) + # The "hp" stanza above does not work with aCC (C++) and HP's ia64 + # compilers, which have integrated preprocessors. The correct option + # to use with these is +Maked; it writes dependencies to a file named + # 'foo.d', which lands next to the object file, wherever that + # happens to be. + # Much of this is similar to the tru64 case; see comments there. + dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` + test "x$dir" = "x$object" && dir= + base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` + if test "$libtool" = yes; then + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir.libs/$base.d + "$@" -Wc,+Maked + else + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir$base.d + "$@" +Maked + fi + stat=$? + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile1" "$tmpdepfile2" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" + do + test -f "$tmpdepfile" && break + done + if test -f "$tmpdepfile"; then + sed -e "s,^.*\.[a-z]*:,$object:," "$tmpdepfile" > "$depfile" + # Add `dependent.h:' lines. + sed -ne '2,${; s/^ *//; s/ \\*$//; s/$/:/; p;}' "$tmpdepfile" >> "$depfile" + else + echo "#dummy" > "$depfile" + fi + rm -f "$tmpdepfile" "$tmpdepfile2" + ;; + +tru64) + # The Tru64 compiler uses -MD to generate dependencies as a side + # effect. `cc -MD -o foo.o ...' puts the dependencies into `foo.o.d'. + # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put + # dependencies in `foo.d' instead, so we check for that too. + # Subdirectories are respected. + dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` + test "x$dir" = "x$object" && dir= + base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` + + if test "$libtool" = yes; then + # With Tru64 cc, shared objects can also be used to make a + # static library. This mechanism is used in libtool 1.4 series to + # handle both shared and static libraries in a single compilation. + # With libtool 1.4, dependencies were output in $dir.libs/$base.lo.d. + # + # With libtool 1.5 this exception was removed, and libtool now + # generates 2 separate objects for the 2 libraries. These two + # compilations output dependencies in $dir.libs/$base.o.d and + # in $dir$base.o.d. We have to check for both files, because + # one of the two compilations can be disabled. We should prefer + # $dir$base.o.d over $dir.libs/$base.o.d because the latter is + # automatically cleaned when .libs/ is deleted, while ignoring + # the former would cause a distcleancheck panic. + tmpdepfile1=$dir.libs/$base.lo.d # libtool 1.4 + tmpdepfile2=$dir$base.o.d # libtool 1.5 + tmpdepfile3=$dir.libs/$base.o.d # libtool 1.5 + tmpdepfile4=$dir.libs/$base.d # Compaq CCC V6.2-504 + "$@" -Wc,-MD + else + tmpdepfile1=$dir$base.o.d + tmpdepfile2=$dir$base.d + tmpdepfile3=$dir$base.d + tmpdepfile4=$dir$base.d + "$@" -MD + fi + + stat=$? + if test $stat -eq 0; then : + else + rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4" + do + test -f "$tmpdepfile" && break + done + if test -f "$tmpdepfile"; then + sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile" + # That's a tab and a space in the []. + sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile" + else + echo "#dummy" > "$depfile" + fi + rm -f "$tmpdepfile" + ;; + +#nosideeffect) + # This comment above is used by automake to tell side-effect + # dependency tracking mechanisms from slower ones. + +dashmstdout) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout, regardless of -o. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test $1 != '--mode=compile'; do + shift + done + shift + fi + + # Remove `-o $object'. + IFS=" " + for arg + do + case $arg in + -o) + shift + ;; + $object) + shift + ;; + *) + set fnord "$@" "$arg" + shift # fnord + shift # $arg + ;; + esac + done + + test -z "$dashmflag" && dashmflag=-M + # Require at least two characters before searching for `:' + # in the target name. This is to cope with DOS-style filenames: + # a dependency such as `c:/foo/bar' could be seen as target `c' otherwise. + "$@" $dashmflag | + sed 's:^[ ]*[^: ][^:][^:]*\:[ ]*:'"$object"'\: :' > "$tmpdepfile" + rm -f "$depfile" + cat < "$tmpdepfile" > "$depfile" + tr ' ' ' +' < "$tmpdepfile" | \ +## Some versions of the HPUX 10.20 sed can't process this invocation +## correctly. Breaking it into two sed invocations is a workaround. + sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +dashXmstdout) + # This case only exists to satisfy depend.m4. It is never actually + # run, as this mode is specially recognized in the preamble. + exit 1 + ;; + +makedepend) + "$@" || exit $? + # Remove any Libtool call + if test "$libtool" = yes; then + while test $1 != '--mode=compile'; do + shift + done + shift + fi + # X makedepend + shift + cleared=no + for arg in "$@"; do + case $cleared in + no) + set ""; shift + cleared=yes ;; + esac + case "$arg" in + -D*|-I*) + set fnord "$@" "$arg"; shift ;; + # Strip any option that makedepend may not understand. Remove + # the object too, otherwise makedepend will parse it as a source file. + -*|$object) + ;; + *) + set fnord "$@" "$arg"; shift ;; + esac + done + obj_suffix="`echo $object | sed 's/^.*\././'`" + touch "$tmpdepfile" + ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@" + rm -f "$depfile" + cat < "$tmpdepfile" > "$depfile" + sed '1,2d' "$tmpdepfile" | tr ' ' ' +' | \ +## Some versions of the HPUX 10.20 sed can't process this invocation +## correctly. Breaking it into two sed invocations is a workaround. + sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" "$tmpdepfile".bak + ;; + +cpp) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test $1 != '--mode=compile'; do + shift + done + shift + fi + + # Remove `-o $object'. + IFS=" " + for arg + do + case $arg in + -o) + shift + ;; + $object) + shift + ;; + *) + set fnord "$@" "$arg" + shift # fnord + shift # $arg + ;; + esac + done + + "$@" -E | + sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ + -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' | + sed '$ s: \\$::' > "$tmpdepfile" + rm -f "$depfile" + echo "$object : \\" > "$depfile" + cat < "$tmpdepfile" >> "$depfile" + sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +msvisualcpp) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout, regardless of -o, + # because we must use -o when running libtool. + "$@" || exit $? + IFS=" " + for arg + do + case "$arg" in + "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI") + set fnord "$@" + shift + shift + ;; + *) + set fnord "$@" "$arg" + shift + shift + ;; + esac + done + "$@" -E | + sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::echo "`cygpath -u \\"\1\\"`":p' | sort | uniq > "$tmpdepfile" + rm -f "$depfile" + echo "$object : \\" > "$depfile" + . "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s:: \1 \\:p' >> "$depfile" + echo " " >> "$depfile" + . "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::\1\::p' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +none) + exec "$@" + ;; + +*) + echo "Unknown depmode $depmode" 1>&2 + exit 1 + ;; +esac + +exit 0 + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-end: "$" +# End:
diff --git a/ethtool-2.6.35/e100.c b/ethtool-2.6.35/e100.c new file mode 100644 index 0000000..4d1cef3 --- /dev/null +++ b/ethtool-2.6.35/e100.c
@@ -0,0 +1,238 @@ +/* Copyright (c) 2002 Intel Corporation */ +#include <stdio.h> +#include "ethtool-util.h" + +#define D102_REV_ID 12 + +#define MDI_MDIX_CONFIG_IS_OK 0x0010 +#define MDI_MDIX_STATUS 0x0020 + +#define SOFT_INT 0x0200 /* Generate a S/W interrupt */ + +/* Interrupt masks */ +#define ALL_INT_MASK 0x0100 /* Mask interrupts */ +#define FCP_INT_MASK 0x0400 /* Flow Control Pause */ +#define ER_INT_MASK 0x0800 /* Early Receive */ +#define RNR_INT_MASK 0x1000 /* RU Not Ready */ +#define CNA_INT_MASK 0x2000 /* CU Not Active */ +#define FR_INT_MASK 0x4000 /* Frame Received */ +#define CX_INT_MASK 0x8000 /* CU eXecution w/ I-bit done */ + +/* Interrupts pending */ +#define FCP_INT_PENDING 0x0100 /* Flow Control Pause */ +#define ER_INT_PENDING 0x0200 /* Early Receive */ +#define SWI_INT_PENDING 0x0400 /* S/W generated interrupt */ +#define MDI_INT_PENDING 0x0800 /* MDI read or write done */ +#define RNR_INT_PENDING 0x1000 /* RU Became Not Ready */ +#define CNA_INT_PENDING 0x2000 /* CU Became Inactive (IDLE) */ +#define FR_INT_PENDING 0x4000 /* RU Received A Frame */ +#define CX_INT_PENDING 0x8000 /* CU Completed Action Cmd */ + +/* Status */ +#define CU_STATUS 0x00C0 +#define RU_STATUS 0x003C + +/* Commands */ +#define CU_CMD 0x00F0 +#define RU_CMD 0x0007 + +int +e100_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *regs_buff = (u32 *)regs->data; + u8 version = (u8)(regs->version >> 24); + u8 rev_id = (u8)(regs->version); + u8 regs_len = regs->len / sizeof(u32); + u32 reg; + u16 scb_status, scb_cmd; + + if(version != 1) + return -1; + + reg = regs_buff[0]; + scb_status = reg & 0x0000ffff; + scb_cmd = reg >> 16; + fprintf(stdout, + "SCB Status Word (Lower Word) 0x%04X\n", + scb_status); + + switch ((scb_status & RU_STATUS) >> 2) { + case 0: + fprintf(stdout, + " RU Status: Idle\n"); + break; + case 1: + fprintf(stdout, + " RU Status: Suspended\n"); + break; + case 2: + fprintf(stdout, + " RU Status: No Resources\n"); + break; + case 4: + fprintf(stdout, + " RU Status: Ready\n"); + break; + case 9: + fprintf(stdout, + " RU Status: Suspended with no more RBDs\n"); + break; + case 10: + fprintf(stdout, + " RU Status: No Resources due to no more RBDs\n"); + break; + case 12: + fprintf(stdout, + " RU Status: Ready with no RBDs present\n"); + break; + default: + fprintf(stdout, + " RU Status: Unknown State\n"); + break; + } + + switch ((scb_status & CU_STATUS) >> 6) { + case 0: + fprintf(stdout, + " CU Status: Idle\n"); + break; + case 1: + fprintf(stdout, + " CU Status: Suspended\n"); + break; + case 2: + fprintf(stdout, + " CU Status: Active\n"); + break; + default: + fprintf(stdout, + " CU Status: Unknown State\n"); + break; + } + + fprintf(stdout, + " ---- Interrupts Pending ----\n" + " Flow Control Pause: %s\n" + " Early Receive: %s\n" + " Software Generated Interrupt: %s\n" + " MDI Done: %s\n" + " RU Not In Ready State: %s\n" + " CU Not in Active State: %s\n" + " RU Received Frame: %s\n" + " CU Completed Command: %s\n", + scb_status & FCP_INT_PENDING ? "yes" : "no", + scb_status & ER_INT_PENDING ? "yes" : "no", + scb_status & SWI_INT_PENDING ? "yes" : "no", + scb_status & MDI_INT_PENDING ? "yes" : "no", + scb_status & RNR_INT_PENDING ? "yes" : "no", + scb_status & CNA_INT_PENDING ? "yes" : "no", + scb_status & FR_INT_PENDING ? "yes" : "no", + scb_status & CX_INT_PENDING ? "yes" : "no"); + + fprintf(stdout, + "SCB Command Word (Upper Word) 0x%04X\n", + scb_cmd); + + switch (scb_cmd & RU_CMD) { + case 0: + fprintf(stdout, + " RU Command: No Command\n"); + break; + case 1: + fprintf(stdout, + " RU Command: RU Start\n"); + break; + case 2: + fprintf(stdout, + " RU Command: RU Resume\n"); + break; + case 4: + fprintf(stdout, + " RU Command: RU Abort\n"); + break; + case 6: + fprintf(stdout, + " RU Command: Load RU Base\n"); + break; + default: + fprintf(stdout, + " RU Command: Unknown\n"); + break; + } + + switch ((scb_cmd & CU_CMD) >> 4) { + case 0: + fprintf(stdout, + " CU Command: No Command\n"); + break; + case 1: + fprintf(stdout, + " CU Command: CU Start\n"); + break; + case 2: + fprintf(stdout, + " CU Command: CU Resume\n"); + break; + case 4: + fprintf(stdout, + " CU Command: Load Dump Counters Address\n"); + break; + case 5: + fprintf(stdout, + " CU Command: Dump Counters\n"); + break; + case 6: + fprintf(stdout, + " CU Command: Load CU Base\n"); + break; + case 7: + fprintf(stdout, + " CU Command: Dump & Reset Counters\n"); + break; + default: + fprintf(stdout, + " CU Command: Unknown\n"); + break; + } + + fprintf(stdout, + " Software Generated Interrupt: %s\n", + scb_cmd & SOFT_INT ? "yes" : "no"); + + fprintf(stdout, + " ---- Interrupts Masked ----\n" + " ALL Interrupts: %s\n" + " Flow Control Pause: %s\n" + " Early Receive: %s\n" + " RU Not In Ready State: %s\n" + " CU Not in Active State: %s\n" + " RU Received Frame: %s\n" + " CU Completed Command: %s\n", + scb_cmd & ALL_INT_MASK ? "yes" : "no", + scb_cmd & FCP_INT_MASK ? "yes" : "no", + scb_cmd & ER_INT_MASK ? "yes" : "no", + scb_cmd & RNR_INT_MASK ? "yes" : "no", + scb_cmd & CNA_INT_MASK ? "yes" : "no", + scb_cmd & FR_INT_MASK ? "yes" : "no", + scb_cmd & CX_INT_MASK ? "yes" : "no"); + + if(regs_len > 1) { + fprintf(stdout, "MDI/MDI-X Status: "); + if(rev_id < D102_REV_ID) + fprintf(stdout, "MDI\n"); + else { + u16 ctrl_reg = regs_buff[1]; + + if(ctrl_reg & MDI_MDIX_CONFIG_IS_OK) { + if(ctrl_reg & MDI_MDIX_STATUS) + fprintf(stdout, "MDI-X\n"); + else + fprintf(stdout, "MDI\n"); + } else + fprintf(stdout, "Unknown\n"); + } + } + + return 0; +} +
diff --git a/ethtool-2.6.35/e1000.c b/ethtool-2.6.35/e1000.c new file mode 100644 index 0000000..d67947a --- /dev/null +++ b/ethtool-2.6.35/e1000.c
@@ -0,0 +1,520 @@ +/* Copyright (c) 2002 Intel Corporation */ +#include <stdio.h> +#include "ethtool-util.h" + +/* Register Bit Masks */ +/* Device Control */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +/* Device Status */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ + +/* Constants used to intrepret the masked PCI-X bus speed. */ +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ + +/* Receive Control */ +#define E1000_RCTL_RST 0x00000001 /* Software reset */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define E1000_RCTL_RDMTS 0x00000300 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +#define E1000_RCTL_SZ 0x00030000 /* rx buffer size */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ + +/* Transmit Control */ +#define E1000_TCTL_RST 0x00000001 /* software reset */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ + +/* PCI Device IDs */ +#define E1000_DEV_ID_82542 0x1000 +#define E1000_DEV_ID_82543GC_FIBER 0x1001 +#define E1000_DEV_ID_82543GC_COPPER 0x1004 +#define E1000_DEV_ID_82544EI_COPPER 0x1008 +#define E1000_DEV_ID_82544EI_FIBER 0x1009 +#define E1000_DEV_ID_82544GC_COPPER 0x100C +#define E1000_DEV_ID_82544GC_LOM 0x100D +#define E1000_DEV_ID_82540EM 0x100E +#define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82540EP_LOM 0x1016 +#define E1000_DEV_ID_82540EP 0x1017 +#define E1000_DEV_ID_82540EP_LP 0x101E +#define E1000_DEV_ID_82545EM_COPPER 0x100F +#define E1000_DEV_ID_82545EM_FIBER 0x1011 +#define E1000_DEV_ID_82545GM_COPPER 0x1026 +#define E1000_DEV_ID_82545GM_FIBER 0x1027 +#define E1000_DEV_ID_82545GM_SERDES 0x1028 +#define E1000_DEV_ID_82546EB_COPPER 0x1010 +#define E1000_DEV_ID_82546EB_FIBER 0x1012 +#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D +#define E1000_DEV_ID_82546GB_COPPER 0x1079 +#define E1000_DEV_ID_82546GB_FIBER 0x107A +#define E1000_DEV_ID_82546GB_SERDES 0x107B +#define E1000_DEV_ID_82546GB_PCIE 0x108A +#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 +#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 +#define E1000_DEV_ID_82541EI 0x1013 +#define E1000_DEV_ID_82541EI_MOBILE 0x1018 +#define E1000_DEV_ID_82541ER_LOM 0x1014 +#define E1000_DEV_ID_82541ER 0x1078 +#define E1000_DEV_ID_82541GI 0x1076 +#define E1000_DEV_ID_82541GI_LF 0x107C +#define E1000_DEV_ID_82541GI_MOBILE 0x1077 +#define E1000_DEV_ID_82547EI 0x1019 +#define E1000_DEV_ID_82547EI_MOBILE 0x101A +#define E1000_DEV_ID_82547GI 0x1075 +#define E1000_DEV_ID_82571EB_COPPER 0x105E +#define E1000_DEV_ID_82571EB_FIBER 0x105F +#define E1000_DEV_ID_82571EB_SERDES 0x1060 +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC +#define E1000_DEV_ID_82572EI_COPPER 0x107D +#define E1000_DEV_ID_82572EI_FIBER 0x107E +#define E1000_DEV_ID_82572EI_SERDES 0x107F +#define E1000_DEV_ID_82572EI 0x10B9 +#define E1000_DEV_ID_82573E 0x108B +#define E1000_DEV_ID_82573E_IAMT 0x108C +#define E1000_DEV_ID_82573L 0x109A +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A +#define E1000_DEV_ID_ICH8_IGP_C 0x104B +#define E1000_DEV_ID_ICH8_IFE 0x104C +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 +#define E1000_DEV_ID_ICH8_IGP_M 0x104D + +#define E1000_82542_2_0_REV_ID 2 +#define E1000_82542_2_1_REV_ID 3 + +/* Enumerated types specific to the e1000 hardware */ +/* Media Access Controlers */ +enum e1000_mac_type { + e1000_undefined = 0, + e1000_82542, + e1000_82543, + e1000_82544, + e1000_82540, + e1000_82545, + e1000_82545_rev_3, + e1000_82546, + e1000_82546_rev_3, + e1000_82541, + e1000_82541_rev_2, + e1000_82547, + e1000_82547_rev_2, + e1000_82571, + e1000_82572, + e1000_82573, + e1000_80003es2lan, + e1000_ich8lan, + e1000_num_macs +}; + +static enum e1000_mac_type +e1000_get_mac_type(u16 device_id, u8 revision_id) +{ + enum e1000_mac_type mac_type = e1000_undefined; + + switch (device_id) { + case E1000_DEV_ID_82542: + mac_type = e1000_82542; + break; + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82543GC_COPPER: + mac_type = e1000_82543; + break; + case E1000_DEV_ID_82544EI_COPPER: + case E1000_DEV_ID_82544EI_FIBER: + case E1000_DEV_ID_82544GC_COPPER: + case E1000_DEV_ID_82544GC_LOM: + mac_type = e1000_82544; + break; + case E1000_DEV_ID_82540EM: + case E1000_DEV_ID_82540EM_LOM: + case E1000_DEV_ID_82540EP: + case E1000_DEV_ID_82540EP_LOM: + case E1000_DEV_ID_82540EP_LP: + mac_type = e1000_82540; + break; + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545EM_FIBER: + mac_type = e1000_82545; + break; + case E1000_DEV_ID_82545GM_COPPER: + case E1000_DEV_ID_82545GM_FIBER: + case E1000_DEV_ID_82545GM_SERDES: + mac_type = e1000_82545_rev_3; + break; + case E1000_DEV_ID_82546EB_COPPER: + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546EB_QUAD_COPPER: + mac_type = e1000_82546; + break; + case E1000_DEV_ID_82546GB_COPPER: + case E1000_DEV_ID_82546GB_FIBER: + case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82546GB_PCIE: + case E1000_DEV_ID_82546GB_QUAD_COPPER: + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: + mac_type = e1000_82546_rev_3; + break; + case E1000_DEV_ID_82541EI: + case E1000_DEV_ID_82541EI_MOBILE: + case E1000_DEV_ID_82541ER_LOM: + mac_type = e1000_82541; + break; + case E1000_DEV_ID_82541ER: + case E1000_DEV_ID_82541GI: + case E1000_DEV_ID_82541GI_LF: + case E1000_DEV_ID_82541GI_MOBILE: + mac_type = e1000_82541_rev_2; + break; + case E1000_DEV_ID_82547EI: + case E1000_DEV_ID_82547EI_MOBILE: + mac_type = e1000_82547; + break; + case E1000_DEV_ID_82547GI: + mac_type = e1000_82547_rev_2; + break; + case E1000_DEV_ID_82571EB_COPPER: + case E1000_DEV_ID_82571EB_FIBER: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82571EB_QUAD_COPPER: + case E1000_DEV_ID_82571EB_QUAD_FIBER: + case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: + mac_type = e1000_82571; + break; + case E1000_DEV_ID_82572EI: + case E1000_DEV_ID_82572EI_COPPER: + case E1000_DEV_ID_82572EI_FIBER: + case E1000_DEV_ID_82572EI_SERDES: + mac_type = e1000_82572; + break; + case E1000_DEV_ID_82573E: + case E1000_DEV_ID_82573E_IAMT: + case E1000_DEV_ID_82573L: + mac_type = e1000_82573; + break; + case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: + mac_type = e1000_80003es2lan; + break; + case E1000_DEV_ID_ICH8_IFE: + case E1000_DEV_ID_ICH8_IFE_GT: + case E1000_DEV_ID_ICH8_IFE_G: + case E1000_DEV_ID_ICH8_IGP_M: + case E1000_DEV_ID_ICH8_IGP_M_AMT: + case E1000_DEV_ID_ICH8_IGP_AMT: + case E1000_DEV_ID_ICH8_IGP_C: + mac_type = e1000_ich8lan; + break; + default: + /* assume old nic and attempt so user can get limited + * functionality */ + mac_type = e1000_82543; + break; + } + + return mac_type; +} + +int +e1000_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *regs_buff = (u32 *)regs->data; + u16 hw_device_id = (u16)regs->version; + u8 hw_revision_id = (u8)(regs->version >> 16); + u8 version = (u8)(regs->version >> 24); + enum e1000_mac_type mac_type; + u32 reg; + + if(version != 1) + return -1; + + mac_type = e1000_get_mac_type(hw_device_id, hw_revision_id); + + if(mac_type == e1000_undefined) + return -1; + + fprintf(stdout, "MAC Registers\n"); + fprintf(stdout, "-------------\n"); + + /* Device control register */ + reg = regs_buff[0]; + fprintf(stdout, + "0x00000: CTRL (Device control register) 0x%08X\n" + " Endian mode (buffers): %s\n" + " Link reset: %s\n" + " Set link up: %s\n" + " Invert Loss-Of-Signal: %s\n" + " Receive flow control: %s\n" + " Transmit flow control: %s\n" + " VLAN mode: %s\n", + reg, + reg & E1000_CTRL_BEM ? "big" : "little", + reg & E1000_CTRL_LRST ? "reset" : "normal", + reg & E1000_CTRL_SLU ? "1" : "0", + reg & E1000_CTRL_ILOS ? "yes" : "no", + reg & E1000_CTRL_RFCE ? "enabled" : "disabled", + reg & E1000_CTRL_TFCE ? "enabled" : "disabled", + reg & E1000_CTRL_VME ? "enabled" : "disabled"); + if(mac_type >= e1000_82543) { + fprintf(stdout, + " Auto speed detect: %s\n" + " Speed select: %s\n" + " Force speed: %s\n" + " Force duplex: %s\n", + reg & E1000_CTRL_ASDE ? "enabled" : "disabled", + (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_10 ? "10Mb/s" : + (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_100 ? "100Mb/s" : + (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_1000 ? "1000Mb/s" : + "not used", + reg & E1000_CTRL_FRCSPD ? "yes" : "no", + reg & E1000_CTRL_FRCDPX ? "yes" : "no"); + } + + /* Device status register */ + reg = regs_buff[1]; + fprintf(stdout, + "0x00008: STATUS (Device status register) 0x%08X\n" + " Duplex: %s\n" + " Link up: %s\n", + reg, + reg & E1000_STATUS_FD ? "full" : "half", + reg & E1000_STATUS_LU ? "link config" : "no link config"); + if (mac_type >= e1000_82571) { + fprintf(stdout, + " TBI mode: %s\n" + " Link speed: %s\n" + " Bus type: %s\n" + " Port number: %s\n", + reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled", + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ? + "10Mb/s" : + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ? + "100Mb/s" : + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ? + "1000Mb/s" : "not used", + "PCI Express", + (reg & E1000_STATUS_FUNC_MASK) == 0 ? "0" : "1"); + } + else if (mac_type >= e1000_82543) { + fprintf(stdout, + " TBI mode: %s\n" + " Link speed: %s\n" + " Bus type: %s\n" + " Bus speed: %s\n" + " Bus width: %s\n", + reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled", + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ? + "10Mb/s" : + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ? + "100Mb/s" : + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ? + "1000Mb/s" : "not used", + (reg & E1000_STATUS_PCIX_MODE) ? "PCI-X" : "PCI", + (reg & E1000_STATUS_PCIX_MODE) ? + ((reg & E1000_STATUS_PCIX_SPEED_133) ? "133MHz" : + (reg & E1000_STATUS_PCIX_SPEED_100) ? "100MHz" : + "66MHz") : + ((reg & E1000_STATUS_PCI66) ? "66MHz" : "33MHz"), + (reg & E1000_STATUS_BUS64) ? "64-bit" : "32-bit"); + } + + /* Receive control register */ + reg = regs_buff[2]; + fprintf(stdout, + "0x00100: RCTL (Receive control register) 0x%08X\n" + " Receiver: %s\n" + " Store bad packets: %s\n" + " Unicast promiscuous: %s\n" + " Multicast promiscuous: %s\n" + " Long packet: %s\n" + " Descriptor minimum threshold size: %s\n" + " Broadcast accept mode: %s\n" + " VLAN filter: %s\n" + " Canonical form indicator: %s\n" + " Discard pause frames: %s\n" + " Pass MAC control frames: %s\n", + reg, + reg & E1000_RCTL_EN ? "enabled" : "disabled", + reg & E1000_RCTL_SBP ? "enabled" : "disabled", + reg & E1000_RCTL_UPE ? "enabled" : "disabled", + reg & E1000_RCTL_MPE ? "enabled" : "disabled", + reg & E1000_RCTL_LPE ? "enabled" : "disabled", + (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_HALF ? "1/2" : + (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_QUAT ? "1/4" : + (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_EIGTH ? "1/8" : + "reserved", + reg & E1000_RCTL_BAM ? "accept" : "ignore", + reg & E1000_RCTL_VFE ? "enabled" : "disabled", + reg & E1000_RCTL_CFIEN ? "enabled" : "disabled", + reg & E1000_RCTL_DPF ? "ignored" : "filtered", + reg & E1000_RCTL_PMCF ? "pass" : "don't pass"); + if(mac_type >= e1000_82543) { + fprintf(stdout, + " Receive buffer size: %s\n", + reg & E1000_RCTL_BSEX ? + ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_16384 ? "16384" : + (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_8192 ? "8192" : + (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_4096 ? "4096" : + "reserved") : + ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_2048 ? "2048" : + (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_1024 ? "1024" : + (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_512 ? "512" : + "256")); + } else { + fprintf(stdout, + " Receive buffer size: %s\n", + (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_2048 ? "2048" : + (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_1024 ? "1024" : + (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_512 ? "512" : + "256"); + } + + /* Receive descriptor registers */ + fprintf(stdout, + "0x02808: RDLEN (Receive desc length) 0x%08X\n", + regs_buff[3]); + fprintf(stdout, + "0x02810: RDH (Receive desc head) 0x%08X\n", + regs_buff[4]); + fprintf(stdout, + "0x02818: RDT (Receive desc tail) 0x%08X\n", + regs_buff[5]); + fprintf(stdout, + "0x02820: RDTR (Receive delay timer) 0x%08X\n", + regs_buff[6]); + + /* Transmit control register */ + reg = regs_buff[7]; + fprintf(stdout, + "0x00400: TCTL (Transmit ctrl register) 0x%08X\n" + " Transmitter: %s\n" + " Pad short packets: %s\n" + " Software XOFF Transmission: %s\n", + reg, + reg & E1000_TCTL_EN ? "enabled" : "disabled", + reg & E1000_TCTL_PSP ? "enabled" : "disabled", + reg & E1000_TCTL_SWXOFF ? "enabled" : "disabled"); + if(mac_type >= e1000_82543) { + fprintf(stdout, + " Re-transmit on late collision: %s\n", + reg & E1000_TCTL_RTLC ? "enabled" : "disabled"); + } + + /* Transmit descriptor registers */ + fprintf(stdout, + "0x03808: TDLEN (Transmit desc length) 0x%08X\n", + regs_buff[8]); + fprintf(stdout, + "0x03810: TDH (Transmit desc head) 0x%08X\n", + regs_buff[9]); + fprintf(stdout, + "0x03818: TDT (Transmit desc tail) 0x%08X\n", + regs_buff[10]); + fprintf(stdout, + "0x03820: TIDV (Transmit delay timer) 0x%08X\n", + regs_buff[11]); + + /* PHY type */ + fprintf(stdout, + "PHY type: %s\n", + regs_buff[12] == 0 ? "M88" : + regs_buff[12] == 1 ? "IGP" : + regs_buff[12] == 2 ? "IGP2" : "unknown" ); + + return 0; +} +
diff --git a/ethtool-2.6.35/ethtool-config.h.in b/ethtool-2.6.35/ethtool-config.h.in new file mode 100644 index 0000000..4a5ffab --- /dev/null +++ b/ethtool-2.6.35/ethtool-config.h.in
@@ -0,0 +1,61 @@ +/* ethtool-config.h.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if you have the <inttypes.h> header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the <memory.h> header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `socket' function. */ +#undef HAVE_SOCKET + +/* Define to 1 if you have the <stdint.h> header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the <stdlib.h> header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the <strings.h> header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the <string.h> header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the `strtol' function. */ +#undef HAVE_STRTOL + +/* Define to 1 if you have the <sys/ioctl.h> header file. */ +#undef HAVE_SYS_IOCTL_H + +/* Define to 1 if you have the <sys/stat.h> header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the <sys/types.h> header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the <unistd.h> header file. */ +#undef HAVE_UNISTD_H + +/* Name of package */ +#undef PACKAGE + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Version number of package */ +#undef VERSION
diff --git a/ethtool-2.6.35/ethtool-copy.h b/ethtool-2.6.35/ethtool-copy.h new file mode 100644 index 0000000..894f1da --- /dev/null +++ b/ethtool-2.6.35/ethtool-copy.h
@@ -0,0 +1,664 @@ +/* + * ethtool.h: Defines for Linux ethtool. + * + * Copyright (C) 1998 David S. Miller (davem@redhat.com) + * Copyright 2001 Jeff Garzik <jgarzik@pobox.com> + * Portions Copyright 2001 Sun Microsystems (thockin@sun.com) + * Portions Copyright 2002 Intel (eli.kupermann@intel.com, + * christopher.leech@intel.com, + * scott.feldman@intel.com) + * Portions Copyright (C) Sun Microsystems 2008 + */ + +#ifndef _LINUX_ETHTOOL_H +#define _LINUX_ETHTOOL_H + +#include <linux/types.h> + +/* This should work for both 32 and 64 bit userland. */ +struct ethtool_cmd { + __u32 cmd; + __u32 supported; /* Features this interface supports */ + __u32 advertising; /* Features this interface advertises */ + __u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ + __u8 duplex; /* Duplex, half or full */ + __u8 port; /* Which connector port */ + __u8 phy_address; + __u8 transceiver; /* Which transceiver to use */ + __u8 autoneg; /* Enable or disable autonegotiation */ + __u8 mdio_support; + __u32 maxtxpkt; /* Tx pkts before generating tx int */ + __u32 maxrxpkt; /* Rx pkts before generating rx int */ + __u16 speed_hi; + __u8 eth_tp_mdix; + __u8 reserved2; + __u32 lp_advertising; /* Features the link partner advertises */ + __u32 reserved[2]; +}; + +static __inline__ void ethtool_cmd_speed_set(struct ethtool_cmd *ep, + __u32 speed) +{ + + ep->speed = (__u16)speed; + ep->speed_hi = (__u16)(speed >> 16); +} + +static __inline__ __u32 ethtool_cmd_speed(struct ethtool_cmd *ep) +{ + return (ep->speed_hi << 16) | ep->speed; +} + +#define ETHTOOL_FWVERS_LEN 32 +#define ETHTOOL_BUSINFO_LEN 32 +/* these strings are set to whatever the driver author decides... */ +struct ethtool_drvinfo { + __u32 cmd; + char driver[32]; /* driver short name, "tulip", "eepro100" */ + char version[32]; /* driver version string */ + char fw_version[ETHTOOL_FWVERS_LEN]; /* firmware version string */ + char bus_info[ETHTOOL_BUSINFO_LEN]; /* Bus info for this IF. */ + /* For PCI devices, use pci_name(pci_dev). */ + char reserved1[32]; + char reserved2[12]; + /* + * Some struct members below are filled in + * using ops->get_sset_count(). Obtaining + * this info from ethtool_drvinfo is now + * deprecated; Use ETHTOOL_GSSET_INFO + * instead. + */ + __u32 n_priv_flags; /* number of flags valid in ETHTOOL_GPFLAGS */ + __u32 n_stats; /* number of u64's from ETHTOOL_GSTATS */ + __u32 testinfo_len; + __u32 eedump_len; /* Size of data from ETHTOOL_GEEPROM (bytes) */ + __u32 regdump_len; /* Size of data from ETHTOOL_GREGS (bytes) */ +}; + +#define SOPASS_MAX 6 +/* wake-on-lan settings */ +struct ethtool_wolinfo { + __u32 cmd; + __u32 supported; + __u32 wolopts; + __u8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */ +}; + +/* for passing single values */ +struct ethtool_value { + __u32 cmd; + __u32 data; +}; + +/* for passing big chunks of data */ +struct ethtool_regs { + __u32 cmd; + __u32 version; /* driver-specific, indicates different chips/revs */ + __u32 len; /* bytes */ + __u8 data[0]; +}; + +/* for passing EEPROM chunks */ +struct ethtool_eeprom { + __u32 cmd; + __u32 magic; + __u32 offset; /* in bytes */ + __u32 len; /* in bytes */ + __u8 data[0]; +}; + +/* for configuring coalescing parameters of chip */ +struct ethtool_coalesce { + __u32 cmd; /* ETHTOOL_{G,S}COALESCE */ + + /* How many usecs to delay an RX interrupt after + * a packet arrives. If 0, only rx_max_coalesced_frames + * is used. + */ + __u32 rx_coalesce_usecs; + + /* How many packets to delay an RX interrupt after + * a packet arrives. If 0, only rx_coalesce_usecs is + * used. It is illegal to set both usecs and max frames + * to zero as this would cause RX interrupts to never be + * generated. + */ + __u32 rx_max_coalesced_frames; + + /* Same as above two parameters, except that these values + * apply while an IRQ is being serviced by the host. Not + * all cards support this feature and the values are ignored + * in that case. + */ + __u32 rx_coalesce_usecs_irq; + __u32 rx_max_coalesced_frames_irq; + + /* How many usecs to delay a TX interrupt after + * a packet is sent. If 0, only tx_max_coalesced_frames + * is used. + */ + __u32 tx_coalesce_usecs; + + /* How many packets to delay a TX interrupt after + * a packet is sent. If 0, only tx_coalesce_usecs is + * used. It is illegal to set both usecs and max frames + * to zero as this would cause TX interrupts to never be + * generated. + */ + __u32 tx_max_coalesced_frames; + + /* Same as above two parameters, except that these values + * apply while an IRQ is being serviced by the host. Not + * all cards support this feature and the values are ignored + * in that case. + */ + __u32 tx_coalesce_usecs_irq; + __u32 tx_max_coalesced_frames_irq; + + /* How many usecs to delay in-memory statistics + * block updates. Some drivers do not have an in-memory + * statistic block, and in such cases this value is ignored. + * This value must not be zero. + */ + __u32 stats_block_coalesce_usecs; + + /* Adaptive RX/TX coalescing is an algorithm implemented by + * some drivers to improve latency under low packet rates and + * improve throughput under high packet rates. Some drivers + * only implement one of RX or TX adaptive coalescing. Anything + * not implemented by the driver causes these values to be + * silently ignored. + */ + __u32 use_adaptive_rx_coalesce; + __u32 use_adaptive_tx_coalesce; + + /* When the packet rate (measured in packets per second) + * is below pkt_rate_low, the {rx,tx}_*_low parameters are + * used. + */ + __u32 pkt_rate_low; + __u32 rx_coalesce_usecs_low; + __u32 rx_max_coalesced_frames_low; + __u32 tx_coalesce_usecs_low; + __u32 tx_max_coalesced_frames_low; + + /* When the packet rate is below pkt_rate_high but above + * pkt_rate_low (both measured in packets per second) the + * normal {rx,tx}_* coalescing parameters are used. + */ + + /* When the packet rate is (measured in packets per second) + * is above pkt_rate_high, the {rx,tx}_*_high parameters are + * used. + */ + __u32 pkt_rate_high; + __u32 rx_coalesce_usecs_high; + __u32 rx_max_coalesced_frames_high; + __u32 tx_coalesce_usecs_high; + __u32 tx_max_coalesced_frames_high; + + /* How often to do adaptive coalescing packet rate sampling, + * measured in seconds. Must not be zero. + */ + __u32 rate_sample_interval; +}; + +/* for configuring RX/TX ring parameters */ +struct ethtool_ringparam { + __u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ + + /* Read only attributes. These indicate the maximum number + * of pending RX/TX ring entries the driver will allow the + * user to set. + */ + __u32 rx_max_pending; + __u32 rx_mini_max_pending; + __u32 rx_jumbo_max_pending; + __u32 tx_max_pending; + + /* Values changeable by the user. The valid values are + * in the range 1 to the "*_max_pending" counterpart above. + */ + __u32 rx_pending; + __u32 rx_mini_pending; + __u32 rx_jumbo_pending; + __u32 tx_pending; +}; + +/* for configuring link flow control parameters */ +struct ethtool_pauseparam { + __u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ + + /* If the link is being auto-negotiated (via ethtool_cmd.autoneg + * being true) the user may set 'autonet' here non-zero to have the + * pause parameters be auto-negotiated too. In such a case, the + * {rx,tx}_pause values below determine what capabilities are + * advertised. + * + * If 'autoneg' is zero or the link is not being auto-negotiated, + * then {rx,tx}_pause force the driver to use/not-use pause + * flow control. + */ + __u32 autoneg; + __u32 rx_pause; + __u32 tx_pause; +}; + +#define ETH_GSTRING_LEN 32 +enum ethtool_stringset { + ETH_SS_TEST = 0, + ETH_SS_STATS, + ETH_SS_PRIV_FLAGS, + ETH_SS_NTUPLE_FILTERS, +}; + +/* for passing string sets for data tagging */ +struct ethtool_gstrings { + __u32 cmd; /* ETHTOOL_GSTRINGS */ + __u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ + __u32 len; /* number of strings in the string set */ + __u8 data[0]; +}; + +struct ethtool_sset_info { + __u32 cmd; /* ETHTOOL_GSSET_INFO */ + __u32 reserved; + __u64 sset_mask; /* input: each bit selects an sset to query */ + /* output: each bit a returned sset */ + __u32 data[0]; /* ETH_SS_xxx count, in order, based on bits + in sset_mask. One bit implies one + __u32, two bits implies two + __u32's, etc. */ +}; + +enum ethtool_test_flags { + ETH_TEST_FL_OFFLINE = (1 << 0), /* online / offline */ + ETH_TEST_FL_FAILED = (1 << 1), /* test passed / failed */ +}; + +/* for requesting NIC test and getting results*/ +struct ethtool_test { + __u32 cmd; /* ETHTOOL_TEST */ + __u32 flags; /* ETH_TEST_FL_xxx */ + __u32 reserved; + __u32 len; /* result length, in number of u64 elements */ + __u64 data[0]; +}; + +/* for dumping NIC-specific statistics */ +struct ethtool_stats { + __u32 cmd; /* ETHTOOL_GSTATS */ + __u32 n_stats; /* number of u64's being returned */ + __u64 data[0]; +}; + +struct ethtool_perm_addr { + __u32 cmd; /* ETHTOOL_GPERMADDR */ + __u32 size; + __u8 data[0]; +}; + +/* boolean flags controlling per-interface behavior characteristics. + * When reading, the flag indicates whether or not a certain behavior + * is enabled/present. When writing, the flag indicates whether + * or not the driver should turn on (set) or off (clear) a behavior. + * + * Some behaviors may read-only (unconditionally absent or present). + * If such is the case, return EINVAL in the set-flags operation if the + * flag differs from the read-only value. + */ +enum ethtool_flags { + ETH_FLAG_LRO = (1 << 15), /* LRO is enabled */ + ETH_FLAG_NTUPLE = (1 << 27), /* N-tuple filters enabled */ + ETH_FLAG_RXHASH = (1 << 28), +}; + +/* The following structures are for supporting RX network flow + * classification configuration. Note, all multibyte fields, e.g., + * ip4src, ip4dst, psrc, pdst, spi, etc. are expected to be in network + * byte order. + */ +struct ethtool_tcpip4_spec { + __be32 ip4src; + __be32 ip4dst; + __be16 psrc; + __be16 pdst; + __u8 tos; +}; + +struct ethtool_ah_espip4_spec { + __be32 ip4src; + __be32 ip4dst; + __be32 spi; + __u8 tos; +}; + +struct ethtool_rawip4_spec { + __be32 ip4src; + __be32 ip4dst; + __u8 hdata[64]; +}; + +struct ethtool_ether_spec { + __be16 ether_type; + __u8 frame_size; + __u8 eframe[16]; +}; + +#define ETH_RX_NFC_IP4 1 +#define ETH_RX_NFC_IP6 2 + +struct ethtool_usrip4_spec { + __be32 ip4src; + __be32 ip4dst; + __be32 l4_4_bytes; + __u8 tos; + __u8 ip_ver; + __u8 proto; +}; + +struct ethtool_rx_flow_spec { + __u32 flow_type; + union { + struct ethtool_tcpip4_spec tcp_ip4_spec; + struct ethtool_tcpip4_spec udp_ip4_spec; + struct ethtool_tcpip4_spec sctp_ip4_spec; + struct ethtool_ah_espip4_spec ah_ip4_spec; + struct ethtool_ah_espip4_spec esp_ip4_spec; + struct ethtool_rawip4_spec raw_ip4_spec; + struct ethtool_ether_spec ether_spec; + struct ethtool_usrip4_spec usr_ip4_spec; + __u8 hdata[64]; + } h_u, m_u; /* entry, mask */ + __u64 ring_cookie; + __u32 location; +}; + +struct ethtool_rxnfc { + __u32 cmd; + __u32 flow_type; + /* The rx flow hash value or the rule DB size */ + __u64 data; + /* The following fields are not valid and must not be used for + * the ETHTOOL_{G,X}RXFH commands. */ + struct ethtool_rx_flow_spec fs; + __u32 rule_cnt; + __u32 rule_locs[0]; +}; + +struct ethtool_rxfh_indir { + __u32 cmd; + /* On entry, this is the array size of the user buffer. On + * return from ETHTOOL_GRXFHINDIR, this is the array size of + * the hardware indirection table. */ + __u32 size; + __u32 ring_index[0]; /* ring/queue index for each hash value */ +}; + +struct ethtool_rx_ntuple_flow_spec { + __u32 flow_type; + union { + struct ethtool_tcpip4_spec tcp_ip4_spec; + struct ethtool_tcpip4_spec udp_ip4_spec; + struct ethtool_tcpip4_spec sctp_ip4_spec; + struct ethtool_ah_espip4_spec ah_ip4_spec; + struct ethtool_ah_espip4_spec esp_ip4_spec; + struct ethtool_rawip4_spec raw_ip4_spec; + struct ethtool_ether_spec ether_spec; + struct ethtool_usrip4_spec usr_ip4_spec; + __u8 hdata[64]; + } h_u, m_u; /* entry, mask */ + + __u16 vlan_tag; + __u16 vlan_tag_mask; + __u64 data; /* user-defined flow spec data */ + __u64 data_mask; /* user-defined flow spec mask */ + + /* signed to distinguish between queue and actions (DROP) */ + __s32 action; +#define ETHTOOL_RXNTUPLE_ACTION_DROP -1 +}; + +struct ethtool_rx_ntuple { + __u32 cmd; + struct ethtool_rx_ntuple_flow_spec fs; +}; + +#define ETHTOOL_FLASH_MAX_FILENAME 128 +enum ethtool_flash_op_type { + ETHTOOL_FLASH_ALL_REGIONS = 0, +}; + +/* for passing firmware flashing related parameters */ +struct ethtool_flash { + __u32 cmd; + __u32 region; + char data[ETHTOOL_FLASH_MAX_FILENAME]; +}; + + +/* CMDs currently supported */ +#define ETHTOOL_GSET 0x00000001 /* Get settings. */ +#define ETHTOOL_SSET 0x00000002 /* Set settings. */ +#define ETHTOOL_GDRVINFO 0x00000003 /* Get driver info. */ +#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers. */ +#define ETHTOOL_GWOL 0x00000005 /* Get wake-on-lan options. */ +#define ETHTOOL_SWOL 0x00000006 /* Set wake-on-lan options. */ +#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ +#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level. */ +#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation. */ +#define ETHTOOL_GLINK 0x0000000a /* Get link status (ethtool_value) */ +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data. */ +#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ +#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters. */ +#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ +#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ +#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ +#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ +#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ +#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable + * (ethtool_value) */ +#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable + * (ethtool_value). */ +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test. */ +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ +#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ +#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ +#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ +#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ +#define ETHTOOL_GPERMADDR 0x00000020 /* Get permanent hardware address */ +#define ETHTOOL_GUFO 0x00000021 /* Get UFO enable (ethtool_value) */ +#define ETHTOOL_SUFO 0x00000022 /* Set UFO enable (ethtool_value) */ +#define ETHTOOL_GGSO 0x00000023 /* Get GSO enable (ethtool_value) */ +#define ETHTOOL_SGSO 0x00000024 /* Set GSO enable (ethtool_value) */ +#define ETHTOOL_GFLAGS 0x00000025 /* Get flags bitmap(ethtool_value) */ +#define ETHTOOL_SFLAGS 0x00000026 /* Set flags bitmap(ethtool_value) */ +#define ETHTOOL_GPFLAGS 0x00000027 /* Get driver-private flags bitmap */ +#define ETHTOOL_SPFLAGS 0x00000028 /* Set driver-private flags bitmap */ + +#define ETHTOOL_GRXFH 0x00000029 /* Get RX flow hash configuration */ +#define ETHTOOL_SRXFH 0x0000002a /* Set RX flow hash configuration */ +#define ETHTOOL_GGRO 0x0000002b /* Get GRO enable (ethtool_value) */ +#define ETHTOOL_SGRO 0x0000002c /* Set GRO enable (ethtool_value) */ +#define ETHTOOL_GRXRINGS 0x0000002d /* Get RX rings available for LB */ +#define ETHTOOL_GRXCLSRLCNT 0x0000002e /* Get RX class rule count */ +#define ETHTOOL_GRXCLSRULE 0x0000002f /* Get RX classification rule */ +#define ETHTOOL_GRXCLSRLALL 0x00000030 /* Get all RX classification rule */ +#define ETHTOOL_SRXCLSRLDEL 0x00000031 /* Delete RX classification rule */ +#define ETHTOOL_SRXCLSRLINS 0x00000032 /* Insert RX classification rule */ +#define ETHTOOL_FLASHDEV 0x00000033 /* Flash firmware to device */ +#define ETHTOOL_RESET 0x00000034 /* Reset hardware */ +#define ETHTOOL_SRXNTUPLE 0x00000035 /* Add an n-tuple filter to device */ +#define ETHTOOL_GRXNTUPLE 0x00000036 /* Get n-tuple filters from device */ +#define ETHTOOL_GSSET_INFO 0x00000037 /* Get string set info */ +#define ETHTOOL_GRXFHINDIR 0x00000038 /* Get RX flow hash indir'n table */ +#define ETHTOOL_SRXFHINDIR 0x00000039 /* Set RX flow hash indir'n table */ + +/* compatibility with older code */ +#define SPARC_ETH_GSET ETHTOOL_GSET +#define SPARC_ETH_SSET ETHTOOL_SSET + +/* Indicates what features are supported by the interface. */ +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) +#define SUPPORTED_Pause (1 << 13) +#define SUPPORTED_Asym_Pause (1 << 14) +#define SUPPORTED_2500baseX_Full (1 << 15) +#define SUPPORTED_Backplane (1 << 16) +#define SUPPORTED_1000baseKX_Full (1 << 17) +#define SUPPORTED_10000baseKX4_Full (1 << 18) +#define SUPPORTED_10000baseKR_Full (1 << 19) +#define SUPPORTED_10000baseR_FEC (1 << 20) + +/* Indicates what features are advertised by the interface. */ +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) +#define ADVERTISED_Pause (1 << 13) +#define ADVERTISED_Asym_Pause (1 << 14) +#define ADVERTISED_2500baseX_Full (1 << 15) +#define ADVERTISED_Backplane (1 << 16) +#define ADVERTISED_1000baseKX_Full (1 << 17) +#define ADVERTISED_10000baseKX4_Full (1 << 18) +#define ADVERTISED_10000baseKR_Full (1 << 19) +#define ADVERTISED_10000baseR_FEC (1 << 20) + +/* The following are all involved in forcing a particular link + * mode for the device for setting things. When getting the + * devices settings, these indicate the current mode and whether + * it was foced up into this mode or autonegotiated. + */ + +/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +/* Which connector port. */ +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 +#define PORT_DA 0x05 +#define PORT_NONE 0xef +#define PORT_OTHER 0xff + +/* Which transceiver to use. */ +#define XCVR_INTERNAL 0x00 +#define XCVR_EXTERNAL 0x01 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY3 0x04 + +/* Enable or disable autonegotiation. If this is set to enable, + * the forced link modes above are completely ignored. + */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +/* Mode MDI or MDI-X */ +#define ETH_TP_MDI_INVALID 0x00 +#define ETH_TP_MDI 0x01 +#define ETH_TP_MDI_X 0x02 + +/* Wake-On-Lan options. */ +#define WAKE_PHY (1 << 0) +#define WAKE_UCAST (1 << 1) +#define WAKE_MCAST (1 << 2) +#define WAKE_BCAST (1 << 3) +#define WAKE_ARP (1 << 4) +#define WAKE_MAGIC (1 << 5) +#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ + +/* L3-L4 network traffic flow types */ +#define TCP_V4_FLOW 0x01 +#define UDP_V4_FLOW 0x02 +#define SCTP_V4_FLOW 0x03 +#define AH_ESP_V4_FLOW 0x04 +#define TCP_V6_FLOW 0x05 +#define UDP_V6_FLOW 0x06 +#define SCTP_V6_FLOW 0x07 +#define AH_ESP_V6_FLOW 0x08 +#define AH_V4_FLOW 0x09 +#define ESP_V4_FLOW 0x0a +#define AH_V6_FLOW 0x0b +#define ESP_V6_FLOW 0x0c +#define IP_USER_FLOW 0x0d +#define IPV4_FLOW 0x10 +#define IPV6_FLOW 0x11 + +/* L3-L4 network traffic flow hash options */ +#define RXH_L2DA (1 << 1) +#define RXH_VLAN (1 << 2) +#define RXH_L3_PROTO (1 << 3) +#define RXH_IP_SRC (1 << 4) +#define RXH_IP_DST (1 << 5) +#define RXH_L4_B_0_1 (1 << 6) /* src port in case of TCP/UDP/SCTP */ +#define RXH_L4_B_2_3 (1 << 7) /* dst port in case of TCP/UDP/SCTP */ +#define RXH_DISCARD (1 << 31) + +#define RX_CLS_FLOW_DISC 0xffffffffffffffffULL + +/* Reset flags */ +/* The reset() operation must clear the flags for the components which + * were actually reset. On successful return, the flags indicate the + * components which were not reset, either because they do not exist + * in the hardware or because they cannot be reset independently. The + * driver must never reset any components that were not requested. + */ +enum ethtool_reset_flags { + /* These flags represent components dedicated to the interface + * the command is addressed to. Shift any flag left by + * ETH_RESET_SHARED_SHIFT to reset a shared component of the + * same type. + */ + ETH_RESET_MGMT = 1 << 0, /* Management processor */ + ETH_RESET_IRQ = 1 << 1, /* Interrupt requester */ + ETH_RESET_DMA = 1 << 2, /* DMA engine */ + ETH_RESET_FILTER = 1 << 3, /* Filtering/flow direction */ + ETH_RESET_OFFLOAD = 1 << 4, /* Protocol offload */ + ETH_RESET_MAC = 1 << 5, /* Media access controller */ + ETH_RESET_PHY = 1 << 6, /* Transceiver/PHY */ + ETH_RESET_RAM = 1 << 7, /* RAM shared between + * multiple components */ + + ETH_RESET_DEDICATED = 0x0000ffff, /* All components dedicated to + * this interface */ + ETH_RESET_ALL = 0xffffffff, /* All components used by this + * interface, even if shared */ +}; +#define ETH_RESET_SHARED_SHIFT 16 + +#endif /* _LINUX_ETHTOOL_H */
diff --git a/ethtool-2.6.35/ethtool-util.h b/ethtool-2.6.35/ethtool-util.h new file mode 100644 index 0000000..01b1d03 --- /dev/null +++ b/ethtool-2.6.35/ethtool-util.h
@@ -0,0 +1,96 @@ +/* Portions Copyright 2001 Sun Microsystems (thockin@sun.com) */ +/* Portions Copyright 2002 Intel (scott.feldman@intel.com) */ +#ifndef ETHTOOL_UTIL_H__ +#define ETHTOOL_UTIL_H__ + +#include <sys/types.h> +#include <endian.h> + +#include "ethtool-copy.h" + +typedef unsigned long long u64; +typedef __uint32_t u32; +typedef __uint16_t u16; +typedef __uint8_t u8; +typedef __int32_t s32; + +#if __BYTE_ORDER == __BIG_ENDIAN +static inline u16 cpu_to_be16(u16 value) +{ + return value; +} +static inline u32 cpu_to_be32(u32 value) +{ + return value; +} +#else +static inline u16 cpu_to_be16(u16 value) +{ + return (value >> 8) | (value << 8); +} +static inline u32 cpu_to_be32(u32 value) +{ + return cpu_to_be16(value >> 16) | (cpu_to_be16(value) << 16); +} +#endif + +/* National Semiconductor DP83815, DP83816 */ +int natsemi_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); +int natsemi_dump_eeprom(struct ethtool_drvinfo *info, + struct ethtool_eeprom *ee); + +/* Digital/Intel 21040 and 21041 */ +int de2104x_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Intel(R) PRO/1000 Gigabit Adapter Family */ +int e1000_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +int igb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* RealTek PCI */ +int realtek_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Intel(R) PRO/100 Fast Ethernet Adapter Family */ +int e100_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Tigon3 */ +int tg3_dump_eeprom(struct ethtool_drvinfo *info, struct ethtool_eeprom *ee); + +/* Advanced Micro Devices AMD8111 based Adapter */ +int amd8111e_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Advanced Micro Devices PCnet32 Adapter */ +int pcnet32_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Motorola 8xx FEC Ethernet controller */ +int fec_8xx_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* PowerPC 4xx on-chip Ethernet controller */ +int ibm_emac_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Intel(R) PRO/10GBe Gigabit Adapter Family */ +int ixgb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +int ixgbe_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Broadcom Tigon3 Ethernet controller */ +int tg3_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* SysKonnect Gigabit (Genesis and Yukon) */ +int skge_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* SysKonnect Gigabit (Yukon2) */ +int sky2_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Fabric7 VIOC */ +int vioc_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* SMSC LAN911x/LAN921x embedded ethernet controller */ +int smsc911x_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +int at76c50x_usb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +/* Solarflare Solarstorm controllers */ +int sfc_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +#endif
diff --git a/ethtool-2.6.35/ethtool.8 b/ethtool-2.6.35/ethtool.8 new file mode 100644 index 0000000..3ca403c --- /dev/null +++ b/ethtool-2.6.35/ethtool.8
@@ -0,0 +1,731 @@ +.\" -*- nroff -*- +.\" Copyright 1999 by David S. Miller. All Rights Reserved. +.\" Portions Copyright 2001 Sun Microsystems +.\" This file may be copied under the terms of the GNU Public License. +.\" +.\" .An - list of n alternative values as in "flav vanilla|strawberry" +.\" +.de A1 +\\fB\\$1\\fP|\\fB\\$2\\fP +.. +.de A2 +\\fB\\$1\\fP\ \\fB\\$2\\fP|\\fB\\$3\\fP +.. +.de A3 +\\fB\\$1\\fP\ \\fB\\$2\\fP|\\fB\\$3\\fP|\\fB\\$4\\fP +.. +.de A4 +\\fB\\$1\\fP\ \\fB\\$2\\fP|\\fB\\$3\\fP|\\fB\\$4\\fP|\\fB\\$5\\fP +.. +.\" +.\" .Bn - same as above but framed by square brackets +.\" +.de B1 +[\\fB\\$1\\fP|\\fB\\$2\\fP] +.. +.de B2 +[\\fB\\$1\\fP\ \\fB\\$2\\fP|\\fB\\$3\\fP] +.. +.de B3 +[\\fB\\$1\\fP\ \\fB\\$2\\fP|\\fB\\$3\\fP|\\fB\\$4\\fP] +.. +.de B4 +[\\fB\\$1\\fP\ \\fB\\$2\\fP|\\fB\\$3\\fP|\\fB\\$4\\fP|\\fB\\$5\\fP] +.. +.\" +.\" \(*MA - mac address +.\" +.ds MA \fIxx\fP\fB:\fP\fIyy\fP\fB:\fP\fIzz\fP\fB:\fP\fIaa\fP\fB:\fP\fIbb\fP\fB:\fP\fIcc\fP +.\" +.\" \(*WO - wol flags +.\" +.ds WO \fBp\fP|\fBu\fP|\fBm\fP|\fBb\fP|\fBa\fP|\fBg\fP|\fBs\fP|\fBd\fP... +.\" +.\" \(*FL - flow type values +.\" +.ds FL \fBtcp4\fP|\fBudp4\fP|\fBah4\fP|\fBsctp4\fP|\fBtcp6\fP|\fBudp6\fP|\fBah6\fP|\fBsctp6\fP +.\" +.\" \(*HO - hash options +.\" +.ds HO \fBm\fP|\fBv\fP|\fBt\fP|\fBs\fP|\fBd\fP|\fBf\fP|\fBn\fP|\fBr\fP... +.TH ETHTOOL 8 "July 2007" "Ethtool version 6" +.SH NAME +ethtool \- Display or change ethernet card settings +.SH SYNOPSIS +.B ethtool +.I ethX + +.B ethtool \-h|\-\-help + +.B ethtool \-a|\-\-show\-pause +.I ethX + +.B ethtool \-A|\-\-pause +.I ethX +.B2 autoneg on off +.B2 rx on off +.B2 tx on off + +.B ethtool \-c|\-\-show\-coalesce +.I ethX + +.B ethtool \-C|\-\-coalesce +.I ethX +.B2 adaptive-rx on off +.B2 adaptive-tx on off +.RB [ rx-usecs +.IR N ] +.RB [ rx-frames +.IR N ] +.RB [ rx-usecs-irq +.IR N ] +.RB [ rx-frames-irq +.IR N ] +.RB [ tx-usecs +.IR N ] +.RB [ tx-frames +.IR N ] +.RB [ tx-usecs-irq +.IR N ] +.RB [ tx-frames-irq +.IR N ] +.RB [ stats-block-usecs +.IR N ] +.RB [ pkt-rate-low +.IR N ] +.RB [ rx-usecs-low +.IR N ] +.RB [ rx-frames-low +.IR N ] +.RB [ tx-usecs-low +.IR N ] +.RB [ tx-frames-low +.IR N ] +.RB [ pkt-rate-high +.IR N ] +.RB [ rx-usecs-high +.IR N ] +.RB [ rx-frames-high +.IR N ] +.RB [ tx-usecs-high +.IR N ] +.RB [ tx-frames-high +.IR N ] +.RB [ sample-interval +.IR N ] + +.B ethtool \-g|\-\-show\-ring +.I ethX + +.B ethtool \-G|\-\-set\-ring +.I ethX +.RB [ rx +.IR N ] +.RB [ rx-mini +.IR N ] +.RB [ rx-jumbo +.IR N ] +.RB [ tx +.IR N ] + +.B ethtool \-i|\-\-driver +.I ethX + +.B ethtool \-d|\-\-register\-dump +.I ethX +.B2 raw on off +.B2 hex on off +.RB [ file +.IR name ] + +.B ethtool \-e|\-\-eeprom\-dump +.I ethX +.B2 raw on off +.RB [ offset +.IR N ] +.RB [ length +.IR N ] + +.B ethtool \-E|\-\-change\-eeprom +.I ethX +.RB [ magic +.IR N ] +.RB [ offset +.IR N ] +.RB [ length +.IR N ] +.RB [ value +.IR N ] + +.B ethtool \-k|\-\-show\-offload +.I ethX + +.B ethtool \-K|\-\-offload +.I ethX +.B2 rx on off +.B2 tx on off +.B2 sg on off +.B2 tso on off +.B2 ufo on off +.B2 gso on off +.B2 gro on off +.B2 lro on off +.B2 rxhash on off + +.B ethtool \-p|\-\-identify +.I ethX +.RI [ N ] + +.B ethtool \-r|\-\-negotiate +.I ethX + +.B ethtool \-S|\-\-statistics +.I ethX + +.B ethtool \-t|\-\-test +.I ethX +.B1 offline online + +.B ethtool \-s +.I ethX +.BI speed \ N +.B2 duplex half full +.B4 port tp aui bnc mii fibre +.B2 autoneg on off +.RB [ advertise +.IR N ] +.RB [ phyad +.IR N ] +.B2 xcvr internal external +.RB [ wol \ \*(WO] +.RB [ sopass \ \*(MA] +.RB [ msglvl +.IR N \ | +.BI msglvl \ type +.A1 on off +.RB ...] + +.B ethtool \-n +.I ethX +.RB [ rx-flow-hash \ \*(FL] + +.B ethtool \-N +.I ethX +.RB [ rx-flow-hash \ \*(FL +.RB \ \*(HO] + +.B ethtool \-x|\-\-show\-rxfh\-indir +.I ethX + +.B ethtool \-X|\-\-set\-rxfh\-indir +.I ethX +.RB [\ equal +.IR N \ | +.BI weight\ W0 +.IR W1 +.RB ...\ ] + +.B ethtool \-f|\-\-flash +.I ethX +.RI FILE +.RI [ N ] + +.B ethtool \-u|\-\-show\-ntuple +.I ethX + +.B ethtool \-U|\-\-config\-ntuple +.I ethX +.RB [ flow-type +.RB tcp4|udp4|sctp4 ] +.RB [ src-ip +.IR addr ] +.RB [ src-ip-mask +.IR mask ] +.RB [ dst-ip +.IR addr ] +.RB [ dst-ip-mask +.IR mask ] +.RB [ src-port +.IR port ] +.RB [ src-port-mask +.IR mask ] +.RB [ dst-port +.IR port ] +.RB [ dst-port-mask +.IR mask ] +.RB [ vlan +.IR VLAN-tag ] +.RB [ vlan-mask +.IR mask ] +.RB [ user-def +.IR data ] +.RB [ user-def-mask +.IR mask ] +.RB [ action +.IR queue\ or\ drop ] +.SH DESCRIPTION +.BI ethtool +is used for querying settings of an ethernet device and changing them. + +.I ethX +is the name of the ethernet device on which ethtool should operate. + +.SH OPTIONS +.B ethtool +with a single argument specifying the device name prints current +settings of the specified device. +.TP +.B \-h \-\-help +Shows a short help message. +.TP +.B \-a \-\-show\-pause +Queries the specified ethernet device for pause parameter information. +.TP +.B \-A \-\-pause +Changes the pause parameters of the specified ethernet device. +.TP +.A2 autoneg on off +Specifies whether pause autonegotiation should be enabled. +.TP +.A2 rx on off +Specifies whether RX pause should be enabled. +.TP +.A2 tx on off +Specifies whether TX pause should be enabled. +.TP +.B \-c \-\-show\-coalesce +Queries the specified ethernet device for coalescing information. +.TP +.B \-C \-\-coalesce +Changes the coalescing settings of the specified ethernet device. +.TP +.B \-g \-\-show\-ring +Queries the specified ethernet device for rx/tx ring parameter information. +.TP +.B \-G \-\-set\-ring +Changes the rx/tx ring parameters of the specified ethernet device. +.TP +.BI rx \ N +Changes the number of ring entries for the Rx ring. +.TP +.BI rx-mini \ N +Changes the number of ring entries for the Rx Mini ring. +.TP +.BI rx-jumbo \ N +Changes the number of ring entries for the Rx Jumbo ring. +.TP +.BI tx \ N +Changes the number of ring entries for the Tx ring. +.TP +.B \-i \-\-driver +Queries the specified ethernet device for associated driver information. +.TP +.B \-d \-\-register\-dump +Retrieves and prints a register dump for the specified ethernet device. +The register format for some devices is known and decoded others +are printed in hex. +When +.I raw +is enabled, then ethtool dumps the raw register data to stdout. +If +.I file +is specified, then use contents of previous raw register dump, rather +than reading from the device. + +.TP +.B \-e \-\-eeprom\-dump +Retrieves and prints an EEPROM dump for the specified ethernet device. +When raw is enabled, then it dumps the raw EEPROM data to stdout. The +length and offset parameters allow dumping certain portions of the EEPROM. +Default is to dump the entire EEPROM. +.TP +.B \-E \-\-change\-eeprom +If value is specified, changes EEPROM byte for the specified ethernet device. +offset and value specify which byte and it's new value. If value is not +specified, stdin is read and written to the EEPROM. The length and offset +parameters allow writing to certain portions of the EEPROM. +Because of the persistent nature of writing to the EEPROM, a device-specific +magic key must be specified to prevent the accidental writing to the EEPROM. +.TP +.B \-k \-\-show\-offload +Queries the specified ethernet device for offload information. +.TP +.B \-K \-\-offload +Changes the offload parameters of the specified ethernet device. +.TP +.A2 rx on off +Specifies whether RX checksumming should be enabled. +.TP +.A2 tx on off +Specifies whether TX checksumming should be enabled. +.TP +.A2 sg on off +Specifies whether scatter-gather should be enabled. +.TP +.A2 tso on off +Specifies whether TCP segmentation offload should be enabled. +.TP +.A2 ufo on off +Specifies whether UDP fragmentation offload should be enabled +.TP +.A2 gso on off +Specifies whether generic segmentation offload should be enabled +.TP +.A2 gro on off +Specifies whether generic receive offload should be enabled +.TP +.A2 lro on off +Specifies whether large receive offload should be enabled +.TP +.A2 rxhash on off +Specifies whether receive hashing offload should be enabled +.TP +.B \-p \-\-identify +Initiates adapter-specific action intended to enable an operator to +easily identify the adapter by sight. Typically this involves +blinking one or more LEDs on the specific ethernet port. +.TP +.B N +Length of time to perform phys-id, in seconds. +.TP +.B \-r \-\-negotiate +Restarts auto-negotiation on the specified ethernet device, if +auto-negotiation is enabled. +.TP +.B \-S \-\-statistics +Queries the specified ethernet device for NIC- and driver-specific +statistics. +.TP +.B \-t \-\-test +Executes adapter selftest on the specified ethernet device. Possible test modes are: +.TP +.A1 offline online +defines test type: +.B offline +(default) means to perform full set of tests possibly causing normal operation interruption during the tests, +.B online +means to perform limited set of tests do not interrupting normal adapter operation. +.TP +.B \-s \-\-change +Allows changing some or all settings of the specified ethernet device. +All following options only apply if +.B \-s +was specified. +.TP +.BI speed \ N +Set speed in Mb/s. +.B ethtool +with just the device name as an argument will show you the supported device speeds. +.TP +.A2 duplex half full +Sets full or half duplex mode. +.TP +.A4 port tp aui bnc mii fibre +Selects device port. +.TP +.A2 autoneg on off +Specifies whether autonegotiation should be enabled. Autonegotiation +is enabled by deafult, but in some network devices may have trouble +with it, so you can disable it if really necessary. +.TP +.BI advertise \ N +Sets the speed and duplex advertised by autonegotiation. The argument is +a hexidecimal value using one or a combination of the following values: +.RS +.PD 0 +.TP 3 +.BR "0x001" " 10 Half" +.TP 3 +.BR "0x002" " 10 Full" +.TP 3 +.BR "0x004" " 100 Half" +.TP 3 +.BR "0x008" " 100 Full" +.TP 3 +.BR "0x010" " 1000 Half" "(not supported by IEEE standards)" +.TP 3 +.BR "0x020" " 1000 Full" +.TP 3 +.BR "0x8000" " 2500 Full" "(not supported by IEEE standards)" +.TP 3 +.BR "0x1000" " 10000 Full" +.TP 3 +.BR "0x03F" " Auto" +.PD +.RE +.TP +.BI phyad \ N +PHY address. +.TP +.A2 xcvr internal external +Selects transceiver type. Currently only internal and external can be +specified, in the future further types might be added. +.TP +.BR wol \ \*(WO +Sets Wake-on-LAN options. Not all devices support this. The argument to +this option is a string of characters specifying which options to enable. +.RS +.PD 0 +.TP 3 +.B p +Wake on phy activity +.TP 3 +.B u +Wake on unicast messages +.TP 3 +.B m +Wake on multicast messages +.TP 3 +.B b +Wake on broadcast messages +.TP 3 +.B a +Wake on ARP +.TP 3 +.B g +Wake on MagicPacket(tm) +.TP 3 +.B s +Enable SecureOn(tm) password for MagicPacket(tm) +.TP 3 +.B d +Disable (wake on nothing). This option clears all previous options. +.PD +.RE +.TP +.B sopass \*(MA\c +Sets the SecureOn(tm) password. The argument to this option must be 6 +bytes in ethernet MAC hex format (\*(MA). +.PP +.BI msglvl \ N +.br +.BI msglvl \ type +.A1 on off +.RB ... +.RS +Sets the driver message type flags by name or number. \fItype\fR +names the type of message to enable or disable; \fIN\fR specifies the +new flags numerically. The defined type names and numbers are: +.PD 0 +.TP 12 +.B drv +0x0001 General driver status +.TP 12 +.B probe +0x0002 Hardware probing +.TP 12 +.B link +0x0004 Link state +.TP 12 +.B timer +0x0008 Periodic status check +.TP 12 +.B ifdown +0x0010 Interface being brought down +.TP 12 +.B ifup +0x0020 Interface being brought up +.TP 12 +.B rx_err +0x0040 Receive error +.TP 12 +.B tx_err +0x0080 Transmit error +.TP 12 +.B tx_queued +0x0100 Transmit queueing +.TP 12 +.B intr +0x0200 Interrupt handling +.TP 12 +.B tx_done +0x0400 Transmit completion +.TP 12 +.B rx_status +0x0800 Receive completion +.TP 12 +.B pktdata +0x1000 Packet contents +.TP 12 +.B hw +0x2000 Hardware status +.TP 12 +.B wol +0x4000 Wake-on-LAN status +.PP +The precise meanings of these type flags differ between drivers. +.PD +.RE +.TP +.B \-n \-\-show-nfc +Retrieves the receive network flow classification configurations. +.TP +.BR rx-flow-hash \ \*(FL +Retrieves the hash options for the specified network traffic type. +.RS +.PD 0 +.TP 3 +.BR "tcp4" " TCP over IPv4" +.TP 3 +.BR "udp4" " UDP over IPv4" +.TP 3 +.BR "ah4" " IPSEC AH/ESP over IPv4" +.TP 3 +.BR "sctp4" " SCTP over IPv4" +.TP 3 +.BR "tcp6" " TCP over IPv6" +.TP 3 +.BR "udp6" " UDP over IPv6" +.TP 3 +.BR "ah6" " IPSEC AH/ESP over IPv6" +.TP 3 +.BR "sctp6" " SCTP over IPv6" +.PD +.RE +.TP +.B \-N \-\-config-nfc +Configures the receive network flow classification. +.TP +.BR rx-flow-hash \ \*(FL \ \*(HO +Configures the hash options for the specified network traffic type. +.RS +.PD 0 +.TP 3 +.B m +Hash on the Layer 2 destination address of the rx packet. +.TP 3 +.B v +Hash on the VLAN tag of the rx packet. +.TP 3 +.B t +Hash on the Layer 3 protocol field of the rx packet. +.TP 3 +.B s +Hash on the IP source address of the rx packet. +.TP 3 +.B d +Hash on the IP destination address of the rx packet. +.TP 3 +.B f +Hash on bytes 0 and 1 of the Layer 4 header of the rx packet. +.TP 3 +.B n +Hash on bytes 2 and 3 of the Layer 4 header of the rx packet. +.TP 3 +.B r +Discard all packets of this flow type. When this option is set, all other options are ignored. +.PD +.RE +.TP +.B \-x \-\-show\-rxfh\-indir +Retrieves the receive flow hash indirection table. +.TP +.B \-X \-\-set\-rxfh\-indir +Configures the receive flow hash indirection table. +.TP +.BI equal\ N +Sets the receive flow hash indirection table to spread flows evenly +between the first \fIN\fR receive queues. +.TP +\fBweight\fR \fIW0 W1\fR ... +Sets the receive flow hash indirection table to spread flows between +receive queues according to the given weights. The sum of the weights +must be non-zero and must not exceed the size of the indirection table. +.TP +.B \-f \-\-flash \ FILE +Flash firmware image from the specified file to a region on the adapter. +By default this will flash all the regions on the adapter. +.TP +.B N +A number to identify flash region where the image should be flashed. +Default region is 0 which denotes all regions in the flash. +.PD +.RE +.TP +.B \-u \-\-show-ntuple +Get Rx ntuple filters and actions, then display them to the user. +.PD +.RE +.TP +.B \-U \-\-config-ntuple +Configure Rx ntuple filters and actions +.TP +.B flow-type tcp4|udp4|sctp4 +.RS +.PD 0 +.TP 3 +.BR "tcp4" " TCP over IPv4" +.TP 3 +.BR "udp4" " UDP over IPv4" +.TP 3 +.BR "sctp4" " SCTP over IPv4" +.PD +.RE +.TP +.BI src-ip \ addr +Includes the source IP address, specified using dotted-quad notation +or as a single 32-bit number. +.TP +.BI src-ip-mask \ mask +Specify a mask for the source IP address. +.TP +.BI dst-ip \ addr +Includes the destination IP address. +.TP +.BI dst-ip-mask \ mask +Specify a mask for the destination IP address. +.TP +.BI src-port \ port +Includes the source port. +.TP +.BI src-port-mask \ mask +Specify a mask for the source port. +.TP +.BI dst-port \ port +Includes the destination port. +.TP +.BI dst-port-mask \ mask +Specify a mask for the destination port. +.TP +.BI vlan \ VLAN-tag +Includes the VLAN tag. +.TP +.BI vlan-mask \ mask +Specify a mask for the VLAN tag. +.TP +.BI user-def \ data +Includes 64-bits of user-specific data. +.TP +.BI user-def-mask \ mask +Specify a mask for the user-specific data. +.TP +.BI action \ N +Specifies either the Rx queue to send packets to, or to drop +the matched flow. +.RS +.PD 0 +.TP 3 +.BR "-1" " Drop the matched flow" +.TP 3 +.BR "0 or higher" " Rx queue to route the flow" +.PD +.RE +.SH BUGS +Not supported (in part or whole) on all ethernet drivers. +.SH AUTHOR +.B ethtool +was written by David Miller. + +Modifications by +Jeff Garzik, +Tim Hockin, +Jakub Jelinek, +Andre Majorel, +Eli Kupermann, +Scott Feldman, +Andi Kleen. +.SH AVAILABILITY +.B ethtool +is available over the Web on the SourceForge site at +http://sourceforge.net/projects/gkernel/ +
diff --git a/ethtool-2.6.35/ethtool.c b/ethtool-2.6.35/ethtool.c new file mode 100644 index 0000000..6b2b7c8 --- /dev/null +++ b/ethtool-2.6.35/ethtool.c
@@ -0,0 +1,3033 @@ +/* + * ethtool.c: Linux ethernet device configuration tool. + * + * Copyright (C) 1998 David S. Miller (davem@dm.cobaltmicro.com) + * Portions Copyright 2001 Sun Microsystems + * Kernel 2.4 update Copyright 2001 Jeff Garzik <jgarzik@mandrakesoft.com> + * Wake-on-LAN,natsemi,misc support by Tim Hockin <thockin@sun.com> + * Portions Copyright 2002 Intel + * do_test support by Eli Kupermann <eli.kupermann@intel.com> + * ETHTOOL_PHYS_ID support by Chris Leech <christopher.leech@intel.com> + * e1000 support by Scott Feldman <scott.feldman@intel.com> + * e100 support by Wen Tao <wen-hwa.tao@intel.com> + * ixgb support by Nicholas Nunley <Nicholas.d.nunley@intel.com> + * amd8111e support by Reeja John <reeja.john@amd.com> + * long arguments by Andi Kleen. + * SMSC LAN911x support by Steve Glendinning <steve.glendinning@smsc.com> + * + * TODO: + * * no-args => summary of each device (mii-tool style) + * * better man page (steal from mii-tool?) + * * fall back on SIOCMII* ioctl()s and possibly SIOCDEVPRIVATE* + * * abstract ioctls to allow for fallback modes of data gathering + */ + +#ifdef HAVE_CONFIG_H +# include "ethtool-config.h" +#endif + +#include <sys/types.h> +#include <string.h> +#include <stdlib.h> +#include <sys/types.h> +#include <sys/ioctl.h> +#include <sys/stat.h> +#include <stdio.h> +#include <string.h> +#include <errno.h> +#include <net/if.h> +#include <sys/utsname.h> +#include <limits.h> +#include <ctype.h> + +#include <sys/socket.h> +#include <netinet/in.h> +#include <arpa/inet.h> + +#include <linux/sockios.h> +#include "ethtool-util.h" + + +#ifndef SIOCETHTOOL +#define SIOCETHTOOL 0x8946 +#endif +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +#ifndef HAVE_NETIF_MSG +enum { + NETIF_MSG_DRV = 0x0001, + NETIF_MSG_PROBE = 0x0002, + NETIF_MSG_LINK = 0x0004, + NETIF_MSG_TIMER = 0x0008, + NETIF_MSG_IFDOWN = 0x0010, + NETIF_MSG_IFUP = 0x0020, + NETIF_MSG_RX_ERR = 0x0040, + NETIF_MSG_TX_ERR = 0x0080, + NETIF_MSG_TX_QUEUED = 0x0100, + NETIF_MSG_INTR = 0x0200, + NETIF_MSG_TX_DONE = 0x0400, + NETIF_MSG_RX_STATUS = 0x0800, + NETIF_MSG_PKTDATA = 0x1000, + NETIF_MSG_HW = 0x2000, + NETIF_MSG_WOL = 0x4000, +}; +#endif + +static int parse_wolopts(char *optstr, u32 *data); +static char *unparse_wolopts(int wolopts); +static int parse_sopass(char *src, unsigned char *dest); +static int do_gdrv(int fd, struct ifreq *ifr); +static int do_gset(int fd, struct ifreq *ifr); +static int do_sset(int fd, struct ifreq *ifr); +static int do_gregs(int fd, struct ifreq *ifr); +static int do_nway_rst(int fd, struct ifreq *ifr); +static int do_geeprom(int fd, struct ifreq *ifr); +static int do_seeprom(int fd, struct ifreq *ifr); +static int do_test(int fd, struct ifreq *ifr); +static int do_phys_id(int fd, struct ifreq *ifr); +static int do_gpause(int fd, struct ifreq *ifr); +static int do_spause(int fd, struct ifreq *ifr); +static int do_gring(int fd, struct ifreq *ifr); +static int do_sring(int fd, struct ifreq *ifr); +static int do_gcoalesce(int fd, struct ifreq *ifr); +static int do_scoalesce(int fd, struct ifreq *ifr); +static int do_goffload(int fd, struct ifreq *ifr); +static int do_soffload(int fd, struct ifreq *ifr); +static int do_gstats(int fd, struct ifreq *ifr); +static int rxflow_str_to_type(const char *str); +static int parse_rxfhashopts(char *optstr, u32 *data); +static char *unparse_rxfhashopts(u64 opts); +static int dump_rxfhash(int fhash, u64 val); +static int do_srxclass(int fd, struct ifreq *ifr); +static int do_grxclass(int fd, struct ifreq *ifr); +static int do_grxfhindir(int fd, struct ifreq *ifr); +static int do_srxfhindir(int fd, struct ifreq *ifr); +static int do_srxntuple(int fd, struct ifreq *ifr); +static int do_grxntuple(int fd, struct ifreq *ifr); +static int do_flash(int fd, struct ifreq *ifr); +static int send_ioctl(int fd, struct ifreq *ifr); + +static enum { + MODE_HELP = -1, + MODE_GSET=0, + MODE_SSET, + MODE_GDRV, + MODE_GREGS, + MODE_NWAY_RST, + MODE_GEEPROM, + MODE_SEEPROM, + MODE_TEST, + MODE_PHYS_ID, + MODE_GPAUSE, + MODE_SPAUSE, + MODE_GCOALESCE, + MODE_SCOALESCE, + MODE_GRING, + MODE_SRING, + MODE_GOFFLOAD, + MODE_SOFFLOAD, + MODE_GSTATS, + MODE_GNFC, + MODE_SNFC, + MODE_GRXFHINDIR, + MODE_SRXFHINDIR, + MODE_SNTUPLE, + MODE_GNTUPLE, + MODE_FLASHDEV, +} mode = MODE_GSET; + +static struct option { + char *srt, *lng; + int Mode; + char *help; + char *opthelp; +} args[] = { + { "-s", "--change", MODE_SSET, "Change generic options", + " [ speed %d ]\n" + " [ duplex half|full ]\n" + " [ port tp|aui|bnc|mii|fibre ]\n" + " [ autoneg on|off ]\n" + " [ advertise %x ]\n" + " [ phyad %d ]\n" + " [ xcvr internal|external ]\n" + " [ wol p|u|m|b|a|g|s|d... ]\n" + " [ sopass %x:%x:%x:%x:%x:%x ]\n" + " [ msglvl %d | msglvl type on|off ... ]\n" }, + { "-a", "--show-pause", MODE_GPAUSE, "Show pause options" }, + { "-A", "--pause", MODE_SPAUSE, "Set pause options", + " [ autoneg on|off ]\n" + " [ rx on|off ]\n" + " [ tx on|off ]\n" }, + { "-c", "--show-coalesce", MODE_GCOALESCE, "Show coalesce options" }, + { "-C", "--coalesce", MODE_SCOALESCE, "Set coalesce options", + " [adaptive-rx on|off]\n" + " [adaptive-tx on|off]\n" + " [rx-usecs N]\n" + " [rx-frames N]\n" + " [rx-usecs-irq N]\n" + " [rx-frames-irq N]\n" + " [tx-usecs N]\n" + " [tx-frames N]\n" + " [tx-usecs-irq N]\n" + " [tx-frames-irq N]\n" + " [stats-block-usecs N]\n" + " [pkt-rate-low N]\n" + " [rx-usecs-low N]\n" + " [rx-frames-low N]\n" + " [tx-usecs-low N]\n" + " [tx-frames-low N]\n" + " [pkt-rate-high N]\n" + " [rx-usecs-high N]\n" + " [rx-frames-high N]\n" + " [tx-usecs-high N]\n" + " [tx-frames-high N]\n" + " [sample-interval N]\n" }, + { "-g", "--show-ring", MODE_GRING, "Query RX/TX ring parameters" }, + { "-G", "--set-ring", MODE_SRING, "Set RX/TX ring parameters", + " [ rx N ]\n" + " [ rx-mini N ]\n" + " [ rx-jumbo N ]\n" + " [ tx N ]\n" }, + { "-k", "--show-offload", MODE_GOFFLOAD, "Get protocol offload information" }, + { "-K", "--offload", MODE_SOFFLOAD, "Set protocol offload", + " [ rx on|off ]\n" + " [ tx on|off ]\n" + " [ sg on|off ]\n" + " [ tso on|off ]\n" + " [ ufo on|off ]\n" + " [ gso on|off ]\n" + " [ gro on|off ]\n" + " [ lro on|off ]\n" + " [ ntuple on|off ]\n" + " [ rxhash on|off ]\n" + }, + { "-i", "--driver", MODE_GDRV, "Show driver information" }, + { "-d", "--register-dump", MODE_GREGS, "Do a register dump", + " [ raw on|off ]\n" + " [ file FILENAME ]\n" }, + { "-e", "--eeprom-dump", MODE_GEEPROM, "Do a EEPROM dump", + " [ raw on|off ]\n" + " [ offset N ]\n" + " [ length N ]\n" }, + { "-E", "--change-eeprom", MODE_SEEPROM, "Change bytes in device EEPROM", + " [ magic N ]\n" + " [ offset N ]\n" + " [ length N ]\n" + " [ value N ]\n" }, + { "-r", "--negotiate", MODE_NWAY_RST, "Restart N-WAY negotation" }, + { "-p", "--identify", MODE_PHYS_ID, "Show visible port identification (e.g. blinking)", + " [ TIME-IN-SECONDS ]\n" }, + { "-t", "--test", MODE_TEST, "Execute adapter self test", + " [ online | offline ]\n" }, + { "-S", "--statistics", MODE_GSTATS, "Show adapter statistics" }, + { "-n", "--show-nfc", MODE_GNFC, "Show Rx network flow classification" + "options", + " [ rx-flow-hash tcp4|udp4|ah4|sctp4|" + "tcp6|udp6|ah6|sctp6 ]\n" }, + { "-f", "--flash", MODE_FLASHDEV, "FILENAME " "Flash firmware image " + "from the specified file to a region on the device", + " [ REGION-NUMBER-TO-FLASH ]\n" }, + { "-N", "--config-nfc", MODE_SNFC, "Configure Rx network flow " + "classification options", + " [ rx-flow-hash tcp4|udp4|ah4|sctp4|" + "tcp6|udp6|ah6|sctp6 m|v|t|s|d|f|n|r... ]\n" }, + { "-x", "--show-rxfh-indir", MODE_GRXFHINDIR, "Show Rx flow hash " + "indirection" }, + { "-X", "--set-rxfh-indir", MODE_SRXFHINDIR, "Set Rx flow hash indirection", + " equal N | weight W0 W1 ...\n" }, + { "-U", "--config-ntuple", MODE_SNTUPLE, "Configure Rx ntuple filters " + "and actions", + " [ flow-type tcp4|udp4|sctp4 src-ip <addr> " + "src-ip-mask <mask> dst-ip <addr> dst-ip-mask <mask> " + "src-port <port> src-port-mask <mask> dst-port <port> " + "dst-port-mask <mask> vlan <VLAN tag> vlan-mask <mask> " + "user-def <data> user-def-mask <mask> " + "action <queue or drop>\n" }, + { "-u", "--show-ntuple", MODE_GNTUPLE, + "Get Rx ntuple filters and actions\n" }, + { "-h", "--help", MODE_HELP, "Show this help" }, + {} +}; + + +static void show_usage(int badarg) __attribute__((noreturn)); + +static void show_usage(int badarg) +{ + int i; + if (badarg != 0) { + fprintf(stderr, + "ethtool: bad command line argument(s)\n" + "For more information run ethtool -h\n" + ); + } + else { + /* ethtool -h */ + fprintf(stdout, PACKAGE " version " VERSION "\n"); + fprintf(stdout, + "Usage:\n" + "ethtool DEVNAME\tDisplay standard information about device\n"); + for (i = 0; args[i].srt; i++) { + fprintf(stdout, " ethtool %s|%s %s\t%s\n%s", + args[i].srt, args[i].lng, + strstr(args[i].srt, "-h") ? "\t" : "DEVNAME", + args[i].help, + args[i].opthelp ? args[i].opthelp : ""); + } + } + exit(badarg); +} + +static char *devname = NULL; + +static int goffload_changed = 0; +static int off_csum_rx_wanted = -1; +static int off_csum_tx_wanted = -1; +static int off_sg_wanted = -1; +static int off_tso_wanted = -1; +static int off_ufo_wanted = -1; +static int off_gso_wanted = -1; +static u32 off_flags_wanted = 0; +static u32 off_flags_unwanted = 0; +static int off_gro_wanted = -1; + +static struct ethtool_pauseparam epause; +static int gpause_changed = 0; +static int pause_autoneg_wanted = -1; +static int pause_rx_wanted = -1; +static int pause_tx_wanted = -1; + +static struct ethtool_ringparam ering; +static int gring_changed = 0; +static s32 ring_rx_wanted = -1; +static s32 ring_rx_mini_wanted = -1; +static s32 ring_rx_jumbo_wanted = -1; +static s32 ring_tx_wanted = -1; + +static struct ethtool_coalesce ecoal; +static int gcoalesce_changed = 0; +static s32 coal_stats_wanted = -1; +static int coal_adaptive_rx_wanted = -1; +static int coal_adaptive_tx_wanted = -1; +static s32 coal_sample_rate_wanted = -1; +static s32 coal_pkt_rate_low_wanted = -1; +static s32 coal_pkt_rate_high_wanted = -1; +static s32 coal_rx_usec_wanted = -1; +static s32 coal_rx_frames_wanted = -1; +static s32 coal_rx_usec_irq_wanted = -1; +static s32 coal_rx_frames_irq_wanted = -1; +static s32 coal_tx_usec_wanted = -1; +static s32 coal_tx_frames_wanted = -1; +static s32 coal_tx_usec_irq_wanted = -1; +static s32 coal_tx_frames_irq_wanted = -1; +static s32 coal_rx_usec_low_wanted = -1; +static s32 coal_rx_frames_low_wanted = -1; +static s32 coal_tx_usec_low_wanted = -1; +static s32 coal_tx_frames_low_wanted = -1; +static s32 coal_rx_usec_high_wanted = -1; +static s32 coal_rx_frames_high_wanted = -1; +static s32 coal_tx_usec_high_wanted = -1; +static s32 coal_tx_frames_high_wanted = -1; + +static int speed_wanted = -1; +static int duplex_wanted = -1; +static int port_wanted = -1; +static int autoneg_wanted = -1; +static int phyad_wanted = -1; +static int xcvr_wanted = -1; +static int advertising_wanted = -1; +static int gset_changed = 0; /* did anything in GSET change? */ +static u32 wol_wanted = 0; +static int wol_change = 0; +static u8 sopass_wanted[SOPASS_MAX]; +static int sopass_change = 0; +static int gwol_changed = 0; /* did anything in GWOL change? */ +static int phys_id_time = 0; +static int gregs_changed = 0; +static int gregs_dump_raw = 0; +static int gregs_dump_hex = 0; +static char *gregs_dump_file = NULL; +static int geeprom_changed = 0; +static int geeprom_dump_raw = 0; +static s32 geeprom_offset = 0; +static s32 geeprom_length = -1; +static int seeprom_changed = 0; +static s32 seeprom_magic = 0; +static s32 seeprom_length = -1; +static s32 seeprom_offset = 0; +static s32 seeprom_value = EOF; +static int rx_fhash_get = 0; +static int rx_fhash_set = 0; +static u32 rx_fhash_val = 0; +static int rx_fhash_changed = 0; +static int rxfhindir_equal = 0; +static char **rxfhindir_weight = NULL; +static int sntuple_changed = 0; +static struct ethtool_rx_ntuple_flow_spec ntuple_fs; +static char *flash_file = NULL; +static int flash = -1; +static int flash_region = -1; + +static int msglvl_changed; +static u32 msglvl_wanted = 0; +static u32 msglvl_unwanted =0; + +static enum { + ONLINE=0, + OFFLINE, +} test_type = OFFLINE; + +typedef enum { + CMDL_NONE, + CMDL_BOOL, + CMDL_S32, + CMDL_U16, + CMDL_U32, + CMDL_U64, + CMDL_BE16, + CMDL_IP4, + CMDL_STR, + CMDL_FLAG, +} cmdline_type_t; + +struct cmdline_info { + const char *name; + cmdline_type_t type; + /* Points to int (BOOL), s32, u16, u32 (U32/FLAG/IP4), u64 or + * char * (STR). For FLAG, the value accumulates all flags + * to be set. */ + void *wanted_val; + void *ioctl_val; + /* For FLAG, the flag value to be set/cleared */ + u32 flag_val; + /* For FLAG, accumulates all flags to be cleared */ + u32 *unwanted_val; +}; + +static struct cmdline_info cmdline_gregs[] = { + { "raw", CMDL_BOOL, &gregs_dump_raw, NULL }, + { "hex", CMDL_BOOL, &gregs_dump_hex, NULL }, + { "file", CMDL_STR, &gregs_dump_file, NULL }, +}; + +static struct cmdline_info cmdline_geeprom[] = { + { "offset", CMDL_S32, &geeprom_offset, NULL }, + { "length", CMDL_S32, &geeprom_length, NULL }, + { "raw", CMDL_BOOL, &geeprom_dump_raw, NULL }, +}; + +static struct cmdline_info cmdline_seeprom[] = { + { "magic", CMDL_S32, &seeprom_magic, NULL }, + { "offset", CMDL_S32, &seeprom_offset, NULL }, + { "length", CMDL_S32, &seeprom_length, NULL }, + { "value", CMDL_S32, &seeprom_value, NULL }, +}; + +static struct cmdline_info cmdline_offload[] = { + { "rx", CMDL_BOOL, &off_csum_rx_wanted, NULL }, + { "tx", CMDL_BOOL, &off_csum_tx_wanted, NULL }, + { "sg", CMDL_BOOL, &off_sg_wanted, NULL }, + { "tso", CMDL_BOOL, &off_tso_wanted, NULL }, + { "ufo", CMDL_BOOL, &off_ufo_wanted, NULL }, + { "gso", CMDL_BOOL, &off_gso_wanted, NULL }, + { "lro", CMDL_FLAG, &off_flags_wanted, NULL, + ETH_FLAG_LRO, &off_flags_unwanted }, + { "gro", CMDL_BOOL, &off_gro_wanted, NULL }, + { "ntuple", CMDL_FLAG, &off_flags_wanted, NULL, + ETH_FLAG_NTUPLE, &off_flags_unwanted }, + { "rxhash", CMDL_FLAG, &off_flags_wanted, NULL, + ETH_FLAG_RXHASH, &off_flags_unwanted }, +}; + +static struct cmdline_info cmdline_pause[] = { + { "autoneg", CMDL_BOOL, &pause_autoneg_wanted, &epause.autoneg }, + { "rx", CMDL_BOOL, &pause_rx_wanted, &epause.rx_pause }, + { "tx", CMDL_BOOL, &pause_tx_wanted, &epause.tx_pause }, +}; + +static struct cmdline_info cmdline_ring[] = { + { "rx", CMDL_S32, &ring_rx_wanted, &ering.rx_pending }, + { "rx-mini", CMDL_S32, &ring_rx_mini_wanted, &ering.rx_mini_pending }, + { "rx-jumbo", CMDL_S32, &ring_rx_jumbo_wanted, &ering.rx_jumbo_pending }, + { "tx", CMDL_S32, &ring_tx_wanted, &ering.tx_pending }, +}; + +static struct cmdline_info cmdline_coalesce[] = { + { "adaptive-rx", CMDL_BOOL, &coal_adaptive_rx_wanted, &ecoal.use_adaptive_rx_coalesce }, + { "adaptive-tx", CMDL_BOOL, &coal_adaptive_tx_wanted, &ecoal.use_adaptive_tx_coalesce }, + { "sample-interval", CMDL_S32, &coal_sample_rate_wanted, &ecoal.rate_sample_interval }, + { "stats-block-usecs", CMDL_S32, &coal_stats_wanted, &ecoal.stats_block_coalesce_usecs }, + { "pkt-rate-low", CMDL_S32, &coal_pkt_rate_low_wanted, &ecoal.pkt_rate_low }, + { "pkt-rate-high", CMDL_S32, &coal_pkt_rate_high_wanted, &ecoal.pkt_rate_high }, + { "rx-usecs", CMDL_S32, &coal_rx_usec_wanted, &ecoal.rx_coalesce_usecs }, + { "rx-frames", CMDL_S32, &coal_rx_frames_wanted, &ecoal.rx_max_coalesced_frames }, + { "rx-usecs-irq", CMDL_S32, &coal_rx_usec_irq_wanted, &ecoal.rx_coalesce_usecs_irq }, + { "rx-frames-irq", CMDL_S32, &coal_rx_frames_irq_wanted, &ecoal.rx_max_coalesced_frames_irq }, + { "tx-usecs", CMDL_S32, &coal_tx_usec_wanted, &ecoal.tx_coalesce_usecs }, + { "tx-frames", CMDL_S32, &coal_tx_frames_wanted, &ecoal.tx_max_coalesced_frames }, + { "tx-usecs-irq", CMDL_S32, &coal_tx_usec_irq_wanted, &ecoal.tx_coalesce_usecs_irq }, + { "tx-frames-irq", CMDL_S32, &coal_tx_frames_irq_wanted, &ecoal.tx_max_coalesced_frames_irq }, + { "rx-usecs-low", CMDL_S32, &coal_rx_usec_low_wanted, &ecoal.rx_coalesce_usecs_low }, + { "rx-frames-low", CMDL_S32, &coal_rx_frames_low_wanted, &ecoal.rx_max_coalesced_frames_low }, + { "tx-usecs-low", CMDL_S32, &coal_tx_usec_low_wanted, &ecoal.tx_coalesce_usecs_low }, + { "tx-frames-low", CMDL_S32, &coal_tx_frames_low_wanted, &ecoal.tx_max_coalesced_frames_low }, + { "rx-usecs-high", CMDL_S32, &coal_rx_usec_high_wanted, &ecoal.rx_coalesce_usecs_high }, + { "rx-frames-high", CMDL_S32, &coal_rx_frames_high_wanted, &ecoal.rx_max_coalesced_frames_high }, + { "tx-usecs-high", CMDL_S32, &coal_tx_usec_high_wanted, &ecoal.tx_coalesce_usecs_high }, + { "tx-frames-high", CMDL_S32, &coal_tx_frames_high_wanted, &ecoal.tx_max_coalesced_frames_high }, +}; + +static struct cmdline_info cmdline_ntuple[] = { + { "src-ip", CMDL_IP4, &ntuple_fs.h_u.tcp_ip4_spec.ip4src, NULL }, + { "src-ip-mask", CMDL_IP4, &ntuple_fs.m_u.tcp_ip4_spec.ip4src, NULL }, + { "dst-ip", CMDL_IP4, &ntuple_fs.h_u.tcp_ip4_spec.ip4dst, NULL }, + { "dst-ip-mask", CMDL_IP4, &ntuple_fs.m_u.tcp_ip4_spec.ip4dst, NULL }, + { "src-port", CMDL_BE16, &ntuple_fs.h_u.tcp_ip4_spec.psrc, NULL }, + { "src-port-mask", CMDL_BE16, &ntuple_fs.m_u.tcp_ip4_spec.psrc, NULL }, + { "dst-port", CMDL_BE16, &ntuple_fs.h_u.tcp_ip4_spec.pdst, NULL }, + { "dst-port-mask", CMDL_BE16, &ntuple_fs.m_u.tcp_ip4_spec.pdst, NULL }, + { "vlan", CMDL_U16, &ntuple_fs.vlan_tag, NULL }, + { "vlan-mask", CMDL_U16, &ntuple_fs.vlan_tag_mask, NULL }, + { "user-def", CMDL_U64, &ntuple_fs.data, NULL }, + { "user-def-mask", CMDL_U64, &ntuple_fs.data_mask, NULL }, + { "action", CMDL_S32, &ntuple_fs.action, NULL }, +}; + +static struct cmdline_info cmdline_msglvl[] = { + { "drv", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_DRV, &msglvl_unwanted }, + { "probe", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_PROBE, &msglvl_unwanted }, + { "link", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_LINK, &msglvl_unwanted }, + { "timer", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_TIMER, &msglvl_unwanted }, + { "ifdown", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_IFDOWN, &msglvl_unwanted }, + { "ifup", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_IFUP, &msglvl_unwanted }, + { "rx_err", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_RX_ERR, &msglvl_unwanted }, + { "tx_err", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_TX_ERR, &msglvl_unwanted }, + { "tx_queued", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_TX_QUEUED, &msglvl_unwanted }, + { "intr", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_INTR, &msglvl_unwanted }, + { "tx_done", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_TX_DONE, &msglvl_unwanted }, + { "rx_status", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_RX_STATUS, &msglvl_unwanted }, + { "pktdata", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_PKTDATA, &msglvl_unwanted }, + { "hw", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_HW, &msglvl_unwanted }, + { "wol", CMDL_FLAG, &msglvl_wanted, NULL, + NETIF_MSG_WOL, &msglvl_unwanted }, +}; + +static long long +get_int_range(char *str, int base, long long min, long long max) +{ + long long v; + char *endp; + + if (!str) + show_usage(1); + errno = 0; + v = strtoll(str, &endp, base); + if (errno || *endp || v < min || v > max) + show_usage(1); + return v; +} + +static unsigned long long +get_uint_range(char *str, int base, unsigned long long max) +{ + unsigned long long v; + char *endp; + + if (!str) + show_usage(1); + errno = 0; + v = strtoull(str, &endp, base); + if ( errno || *endp || v > max) + show_usage(1); + return v; +} + +static int get_int(char *str, int base) +{ + return get_int_range(str, base, INT_MIN, INT_MAX); +} + +static u32 get_u32(char *str, int base) +{ + return get_uint_range(str, base, 0xffffffff); +} + +static void parse_generic_cmdline(int argc, char **argp, + int first_arg, int *changed, + struct cmdline_info *info, + unsigned int n_info) +{ + int i, idx; + int found; + + for (i = first_arg; i < argc; i++) { + found = 0; + for (idx = 0; idx < n_info; idx++) { + if (!strcmp(info[idx].name, argp[i])) { + found = 1; + *changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + switch (info[idx].type) { + case CMDL_BOOL: { + int *p = info[idx].wanted_val; + if (!strcmp(argp[i], "on")) + *p = 1; + else if (!strcmp(argp[i], "off")) + *p = 0; + else + show_usage(1); + break; + } + case CMDL_S32: { + s32 *p = info[idx].wanted_val; + *p = get_int_range(argp[i], 0, + -0x80000000LL, + 0x7fffffff); + break; + } + case CMDL_U16: { + u16 *p = info[idx].wanted_val; + *p = get_uint_range(argp[i], 0, 0xffff); + break; + } + case CMDL_U32: { + u32 *p = info[idx].wanted_val; + *p = get_uint_range(argp[i], 0, + 0xffffffff); + break; + } + case CMDL_U64: { + u64 *p = info[idx].wanted_val; + *p = get_uint_range( + argp[i], 0, + 0xffffffffffffffffLL); + break; + } + case CMDL_BE16: { + u16 *p = info[idx].wanted_val; + *p = cpu_to_be16( + get_uint_range(argp[i], 0, + 0xffff)); + break; + } + case CMDL_IP4: { + u32 *p = info[idx].wanted_val; + struct in_addr in; + if (!inet_aton(argp[i], &in)) + show_usage(1); + *p = in.s_addr; + break; + } + case CMDL_FLAG: { + u32 *p; + if (!strcmp(argp[i], "on")) + p = info[idx].wanted_val; + else if (!strcmp(argp[i], "off")) + p = info[idx].unwanted_val; + else + show_usage(1); + *p |= info[idx].flag_val; + break; + } + case CMDL_STR: { + char **s = info[idx].wanted_val; + *s = strdup(argp[i]); + break; + } + default: + show_usage(1); + } + break; + } + } + if( !found) + show_usage(1); + } +} + +static void +print_flags(const struct cmdline_info *info, unsigned int n_info, u32 value) +{ + const char *sep = ""; + + while (n_info) { + if (info->type == CMDL_FLAG && value & info->flag_val) { + printf("%s%s", sep, info->name); + sep = " "; + value &= ~info->flag_val; + } + ++info; + --n_info; + } + + /* Print any unrecognised flags in hex */ + if (value) + printf("%s%#x", sep, value); +} + +static int rxflow_str_to_type(const char *str) +{ + int flow_type = 0; + + if (!strcmp(str, "tcp4")) + flow_type = TCP_V4_FLOW; + else if (!strcmp(str, "udp4")) + flow_type = UDP_V4_FLOW; + else if (!strcmp(str, "ah4")) + flow_type = AH_ESP_V4_FLOW; + else if (!strcmp(str, "sctp4")) + flow_type = SCTP_V4_FLOW; + else if (!strcmp(str, "tcp6")) + flow_type = TCP_V6_FLOW; + else if (!strcmp(str, "udp6")) + flow_type = UDP_V6_FLOW; + else if (!strcmp(str, "ah6")) + flow_type = AH_ESP_V6_FLOW; + else if (!strcmp(str, "sctp6")) + flow_type = SCTP_V6_FLOW; + + return flow_type; +} + +static void parse_cmdline(int argc, char **argp) +{ + int i, k; + + for (i = 1; i < argc; i++) { + switch (i) { + case 1: + for (k = 0; args[k].srt; k++) + if (!strcmp(argp[i], args[k].srt) || + !strcmp(argp[i], args[k].lng)) { + mode = args[k].Mode; + break; + } + if (mode == MODE_HELP || + (!args[k].srt && argp[i][0] == '-')) + show_usage(0); + else + devname = argp[i]; + break; + case 2: + if ((mode == MODE_SSET) || + (mode == MODE_GDRV) || + (mode == MODE_GREGS)|| + (mode == MODE_NWAY_RST) || + (mode == MODE_TEST) || + (mode == MODE_GEEPROM) || + (mode == MODE_SEEPROM) || + (mode == MODE_GPAUSE) || + (mode == MODE_SPAUSE) || + (mode == MODE_GCOALESCE) || + (mode == MODE_SCOALESCE) || + (mode == MODE_GRING) || + (mode == MODE_SRING) || + (mode == MODE_GOFFLOAD) || + (mode == MODE_SOFFLOAD) || + (mode == MODE_GSTATS) || + (mode == MODE_GNFC) || + (mode == MODE_SNFC) || + (mode == MODE_GRXFHINDIR) || + (mode == MODE_SRXFHINDIR) || + (mode == MODE_SNTUPLE) || + (mode == MODE_GNTUPLE) || + (mode == MODE_PHYS_ID) || + (mode == MODE_FLASHDEV)) { + devname = argp[i]; + break; + } + /* fallthrough */ + case 3: + if (mode == MODE_TEST) { + if (!strcmp(argp[i], "online")) { + test_type = ONLINE; + } else if (!strcmp(argp[i], "offline")) { + test_type = OFFLINE; + } else { + show_usage(1); + } + break; + } else if (mode == MODE_PHYS_ID) { + phys_id_time = get_int(argp[i],0); + break; + } else if (mode == MODE_FLASHDEV) { + flash_file = argp[i]; + flash = 1; + break; + } + /* fallthrough */ + default: + if (mode == MODE_GREGS) { + parse_generic_cmdline(argc, argp, i, + &gregs_changed, + cmdline_gregs, + ARRAY_SIZE(cmdline_gregs)); + i = argc; + break; + } + if (mode == MODE_GEEPROM) { + parse_generic_cmdline(argc, argp, i, + &geeprom_changed, + cmdline_geeprom, + ARRAY_SIZE(cmdline_geeprom)); + i = argc; + break; + } + if (mode == MODE_SEEPROM) { + parse_generic_cmdline(argc, argp, i, + &seeprom_changed, + cmdline_seeprom, + ARRAY_SIZE(cmdline_seeprom)); + i = argc; + break; + } + if (mode == MODE_SPAUSE) { + parse_generic_cmdline(argc, argp, i, + &gpause_changed, + cmdline_pause, + ARRAY_SIZE(cmdline_pause)); + i = argc; + break; + } + if (mode == MODE_SRING) { + parse_generic_cmdline(argc, argp, i, + &gring_changed, + cmdline_ring, + ARRAY_SIZE(cmdline_ring)); + i = argc; + break; + } + if (mode == MODE_SCOALESCE) { + parse_generic_cmdline(argc, argp, i, + &gcoalesce_changed, + cmdline_coalesce, + ARRAY_SIZE(cmdline_coalesce)); + i = argc; + break; + } + if (mode == MODE_SOFFLOAD) { + parse_generic_cmdline(argc, argp, i, + &goffload_changed, + cmdline_offload, + ARRAY_SIZE(cmdline_offload)); + i = argc; + break; + } + if (mode == MODE_SNTUPLE) { + if (!strcmp(argp[i], "flow-type")) { + i += 1; + if (i >= argc) { + show_usage(1); + break; + } + ntuple_fs.flow_type = + rxflow_str_to_type(argp[i]); + i += 1; + parse_generic_cmdline(argc, argp, i, + &sntuple_changed, + cmdline_ntuple, + ARRAY_SIZE(cmdline_ntuple)); + i = argc; + break; + } else { + show_usage(1); + } + break; + } + if (mode == MODE_GNFC) { + if (!strcmp(argp[i], "rx-flow-hash")) { + i += 1; + if (i >= argc) { + show_usage(1); + break; + } + rx_fhash_get = + rxflow_str_to_type(argp[i]); + if (!rx_fhash_get) + show_usage(1); + } else + show_usage(1); + break; + } + if (mode == MODE_FLASHDEV) { + flash_region = strtol(argp[i], NULL, 0); + if ((flash_region < 0)) + show_usage(1); + break; + } + if (mode == MODE_SNFC) { + if (!strcmp(argp[i], "rx-flow-hash")) { + i += 1; + if (i >= argc) { + show_usage(1); + break; + } + rx_fhash_set = + rxflow_str_to_type(argp[i]); + if (!rx_fhash_set) { + show_usage(1); + break; + } + i += 1; + if (i >= argc) { + show_usage(1); + break; + } + if (parse_rxfhashopts(argp[i], + &rx_fhash_val) < 0) + show_usage(1); + else + rx_fhash_changed = 1; + } else + show_usage(1); + break; + } + if (mode == MODE_SRXFHINDIR) { + if (!strcmp(argp[i], "equal")) { + if (argc != i + 2) { + show_usage(1); + break; + } + i += 1; + rxfhindir_equal = + get_int_range(argp[i], 0, 1, + INT_MAX); + i += 1; + } else if (!strcmp(argp[i], "weight")) { + i += 1; + if (i >= argc) { + show_usage(1); + break; + } + rxfhindir_weight = argp + i; + i = argc; + } else { + show_usage(1); + } + break; + } + if (mode != MODE_SSET) + show_usage(1); + if (!strcmp(argp[i], "speed")) { + gset_changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + speed_wanted = get_int(argp[i],10); + break; + } else if (!strcmp(argp[i], "duplex")) { + gset_changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + if (!strcmp(argp[i], "half")) + duplex_wanted = DUPLEX_HALF; + else if (!strcmp(argp[i], "full")) + duplex_wanted = DUPLEX_FULL; + else + show_usage(1); + break; + } else if (!strcmp(argp[i], "port")) { + gset_changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + if (!strcmp(argp[i], "tp")) + port_wanted = PORT_TP; + else if (!strcmp(argp[i], "aui")) + port_wanted = PORT_AUI; + else if (!strcmp(argp[i], "bnc")) + port_wanted = PORT_BNC; + else if (!strcmp(argp[i], "mii")) + port_wanted = PORT_MII; + else if (!strcmp(argp[i], "fibre")) + port_wanted = PORT_FIBRE; + else + show_usage(1); + break; + } else if (!strcmp(argp[i], "autoneg")) { + i += 1; + if (i >= argc) + show_usage(1); + if (!strcmp(argp[i], "on")) { + gset_changed = 1; + autoneg_wanted = AUTONEG_ENABLE; + } else if (!strcmp(argp[i], "off")) { + gset_changed = 1; + autoneg_wanted = AUTONEG_DISABLE; + } else { + show_usage(1); + } + break; + } else if (!strcmp(argp[i], "advertise")) { + gset_changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + advertising_wanted = get_int(argp[i], 16); + break; + } else if (!strcmp(argp[i], "phyad")) { + gset_changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + phyad_wanted = get_int(argp[i], 0); + break; + } else if (!strcmp(argp[i], "xcvr")) { + gset_changed = 1; + i += 1; + if (i >= argc) + show_usage(1); + if (!strcmp(argp[i], "internal")) + xcvr_wanted = XCVR_INTERNAL; + else if (!strcmp(argp[i], "external")) + xcvr_wanted = XCVR_EXTERNAL; + else + show_usage(1); + break; + } else if (!strcmp(argp[i], "wol")) { + gwol_changed = 1; + i++; + if (i >= argc) + show_usage(1); + if (parse_wolopts(argp[i], &wol_wanted) < 0) + show_usage(1); + wol_change = 1; + break; + } else if (!strcmp(argp[i], "sopass")) { + gwol_changed = 1; + i++; + if (i >= argc) + show_usage(1); + if (parse_sopass(argp[i], sopass_wanted) < 0) + show_usage(1); + sopass_change = 1; + break; + } else if (!strcmp(argp[i], "msglvl")) { + i++; + if (i >= argc) + show_usage(1); + if (isdigit((unsigned char)argp[i][0])) { + msglvl_changed = 1; + msglvl_unwanted = ~0; + msglvl_wanted = + get_uint_range(argp[i], 0, + 0xffffffff); + } else { + parse_generic_cmdline( + argc, argp, i, + &msglvl_changed, + cmdline_msglvl, + ARRAY_SIZE(cmdline_msglvl)); + i = argc; + } + break; + } + show_usage(1); + } + } + + if ((autoneg_wanted == AUTONEG_ENABLE) && (advertising_wanted < 0)) { + if (speed_wanted == SPEED_10 && duplex_wanted == DUPLEX_HALF) + advertising_wanted = ADVERTISED_10baseT_Half; + else if (speed_wanted == SPEED_10 && + duplex_wanted == DUPLEX_FULL) + advertising_wanted = ADVERTISED_10baseT_Full; + else if (speed_wanted == SPEED_100 && + duplex_wanted == DUPLEX_HALF) + advertising_wanted = ADVERTISED_100baseT_Half; + else if (speed_wanted == SPEED_100 && + duplex_wanted == DUPLEX_FULL) + advertising_wanted = ADVERTISED_100baseT_Full; + else if (speed_wanted == SPEED_1000 && + duplex_wanted == DUPLEX_HALF) + advertising_wanted = ADVERTISED_1000baseT_Half; + else if (speed_wanted == SPEED_1000 && + duplex_wanted == DUPLEX_FULL) + advertising_wanted = ADVERTISED_1000baseT_Full; + else if (speed_wanted == SPEED_2500 && + duplex_wanted == DUPLEX_FULL) + advertising_wanted = ADVERTISED_2500baseX_Full; + else if (speed_wanted == SPEED_10000 && + duplex_wanted == DUPLEX_FULL) + advertising_wanted = ADVERTISED_10000baseT_Full; + else + /* auto negotiate without forcing, + * all supported speed will be assigned in do_sset() + */ + advertising_wanted = 0; + + } + + if (devname == NULL) + show_usage(1); + if (strlen(devname) >= IFNAMSIZ) + show_usage(1); +} + +static void dump_supported(struct ethtool_cmd *ep) +{ + u_int32_t mask = ep->supported; + int did1; + + fprintf(stdout, " Supported ports: [ "); + if (mask & SUPPORTED_TP) + fprintf(stdout, "TP "); + if (mask & SUPPORTED_AUI) + fprintf(stdout, "AUI "); + if (mask & SUPPORTED_BNC) + fprintf(stdout, "BNC "); + if (mask & SUPPORTED_MII) + fprintf(stdout, "MII "); + if (mask & SUPPORTED_FIBRE) + fprintf(stdout, "FIBRE "); + fprintf(stdout, "]\n"); + + fprintf(stdout, " Supported link modes: "); + did1 = 0; + if (mask & SUPPORTED_10baseT_Half) { + did1++; fprintf(stdout, "10baseT/Half "); + } + if (mask & SUPPORTED_10baseT_Full) { + did1++; fprintf(stdout, "10baseT/Full "); + } + if (did1 && (mask & (SUPPORTED_100baseT_Half|SUPPORTED_100baseT_Full))) { + fprintf(stdout, "\n"); + fprintf(stdout, " "); + } + if (mask & SUPPORTED_100baseT_Half) { + did1++; fprintf(stdout, "100baseT/Half "); + } + if (mask & SUPPORTED_100baseT_Full) { + did1++; fprintf(stdout, "100baseT/Full "); + } + if (did1 && (mask & (SUPPORTED_1000baseT_Half|SUPPORTED_1000baseT_Full))) { + fprintf(stdout, "\n"); + fprintf(stdout, " "); + } + if (mask & SUPPORTED_1000baseT_Half) { + did1++; fprintf(stdout, "1000baseT/Half "); + } + if (mask & SUPPORTED_1000baseT_Full) { + did1++; fprintf(stdout, "1000baseT/Full "); + } + if (did1 && (mask & SUPPORTED_2500baseX_Full)) { + fprintf(stdout, "\n"); + fprintf(stdout, " "); + } + if (mask & SUPPORTED_2500baseX_Full) { + did1++; fprintf(stdout, "2500baseX/Full "); + } + if (did1 && (mask & SUPPORTED_10000baseT_Full)) { + fprintf(stdout, "\n"); + fprintf(stdout, " "); + } + if (mask & SUPPORTED_10000baseT_Full) { + did1++; fprintf(stdout, "10000baseT/Full "); + } + fprintf(stdout, "\n"); + + fprintf(stdout, " Supports auto-negotiation: "); + if (mask & SUPPORTED_Autoneg) + fprintf(stdout, "Yes\n"); + else + fprintf(stdout, "No\n"); +} + +static void dump_advertised(struct ethtool_cmd *ep, + const char *prefix, u_int32_t mask) +{ + int indent = strlen(prefix) + 14; + int did1; + + fprintf(stdout, " %s link modes: ", prefix); + did1 = 0; + if (mask & ADVERTISED_10baseT_Half) { + did1++; fprintf(stdout, "10baseT/Half "); + } + if (mask & ADVERTISED_10baseT_Full) { + did1++; fprintf(stdout, "10baseT/Full "); + } + if (did1 && (mask & (ADVERTISED_100baseT_Half|ADVERTISED_100baseT_Full))) { + fprintf(stdout, "\n"); + fprintf(stdout, " %*s", indent, ""); + } + if (mask & ADVERTISED_100baseT_Half) { + did1++; fprintf(stdout, "100baseT/Half "); + } + if (mask & ADVERTISED_100baseT_Full) { + did1++; fprintf(stdout, "100baseT/Full "); + } + if (did1 && (mask & (ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full))) { + fprintf(stdout, "\n"); + fprintf(stdout, " %*s", indent, ""); + } + if (mask & ADVERTISED_1000baseT_Half) { + did1++; fprintf(stdout, "1000baseT/Half "); + } + if (mask & ADVERTISED_1000baseT_Full) { + did1++; fprintf(stdout, "1000baseT/Full "); + } + if (did1 && (mask & ADVERTISED_2500baseX_Full)) { + fprintf(stdout, "\n"); + fprintf(stdout, " %*s", indent, ""); + } + if (mask & ADVERTISED_2500baseX_Full) { + did1++; fprintf(stdout, "2500baseX/Full "); + } + if (did1 && (mask & ADVERTISED_10000baseT_Full)) { + fprintf(stdout, "\n"); + fprintf(stdout, " %*s", indent, ""); + } + if (mask & ADVERTISED_10000baseT_Full) { + did1++; fprintf(stdout, "10000baseT/Full "); + } + if (did1 == 0) + fprintf(stdout, "Not reported"); + fprintf(stdout, "\n"); + + fprintf(stdout, " %s pause frame use: ", prefix); + if (mask & ADVERTISED_Pause) { + fprintf(stdout, "Symmetric"); + if (mask & ADVERTISED_Asym_Pause) + fprintf(stdout, " Receive-only"); + fprintf(stdout, "\n"); + } else { + if (mask & ADVERTISED_Asym_Pause) + fprintf(stdout, "Transmit-only\n"); + else + fprintf(stdout, "No\n"); + } + + fprintf(stdout, " %s auto-negotiation: ", prefix); + if (mask & ADVERTISED_Autoneg) + fprintf(stdout, "Yes\n"); + else + fprintf(stdout, "No\n"); +} + +static int dump_ecmd(struct ethtool_cmd *ep) +{ + u32 speed; + + dump_supported(ep); + dump_advertised(ep, "Advertised", ep->advertising); + if (ep->lp_advertising) + dump_advertised(ep, "Link partner advertised", + ep->lp_advertising); + + fprintf(stdout, " Speed: "); + speed = ethtool_cmd_speed(ep); + if (speed == 0 || speed == (u16)(-1) || speed == (u32)(-1)) + fprintf(stdout, "Unknown!\n"); + else + fprintf(stdout, "%uMb/s\n", speed); + + fprintf(stdout, " Duplex: "); + switch (ep->duplex) { + case DUPLEX_HALF: + fprintf(stdout, "Half\n"); + break; + case DUPLEX_FULL: + fprintf(stdout, "Full\n"); + break; + default: + fprintf(stdout, "Unknown! (%i)\n", ep->duplex); + break; + }; + + fprintf(stdout, " Port: "); + switch (ep->port) { + case PORT_TP: + fprintf(stdout, "Twisted Pair\n"); + break; + case PORT_AUI: + fprintf(stdout, "AUI\n"); + break; + case PORT_BNC: + fprintf(stdout, "BNC\n"); + break; + case PORT_MII: + fprintf(stdout, "MII\n"); + break; + case PORT_FIBRE: + fprintf(stdout, "FIBRE\n"); + break; + case PORT_DA: + fprintf(stdout, "Direct Attach Copper\n"); + break; + case PORT_NONE: + fprintf(stdout, "None\n"); + break; + case PORT_OTHER: + fprintf(stdout, "Other\n"); + break; + default: + fprintf(stdout, "Unknown! (%i)\n", ep->port); + break; + }; + + fprintf(stdout, " PHYAD: %d\n", ep->phy_address); + fprintf(stdout, " Transceiver: "); + switch (ep->transceiver) { + case XCVR_INTERNAL: + fprintf(stdout, "internal\n"); + break; + case XCVR_EXTERNAL: + fprintf(stdout, "external\n"); + break; + default: + fprintf(stdout, "Unknown!\n"); + break; + }; + + fprintf(stdout, " Auto-negotiation: %s\n", + (ep->autoneg == AUTONEG_DISABLE) ? + "off" : "on"); + + if (ep->port == PORT_TP) { + fprintf(stdout, " MDI-X: "); + switch (ep->eth_tp_mdix) { + case ETH_TP_MDI: + fprintf(stdout, "off\n"); + break; + case ETH_TP_MDI_X: + fprintf(stdout, "on\n"); + break; + default: + fprintf(stdout, "Unknown\n"); + break; + } + } + + return 0; +} + +static int dump_drvinfo(struct ethtool_drvinfo *info) +{ + fprintf(stdout, + "driver: %s\n" + "version: %s\n" + "firmware-version: %s\n" + "bus-info: %s\n", + info->driver, + info->version, + info->fw_version, + info->bus_info); + + return 0; +} + +static int dump_wol(struct ethtool_wolinfo *wol) +{ + fprintf(stdout, " Supports Wake-on: %s\n", + unparse_wolopts(wol->supported)); + fprintf(stdout, " Wake-on: %s\n", + unparse_wolopts(wol->wolopts)); + if (wol->supported & WAKE_MAGICSECURE) { + int i; + int delim = 0; + fprintf(stdout, " SecureOn password: "); + for (i = 0; i < SOPASS_MAX; i++) { + fprintf(stdout, "%s%02x", delim?":":"", wol->sopass[i]); + delim=1; + } + fprintf(stdout, "\n"); + } + + return 0; +} + +static int parse_wolopts(char *optstr, u32 *data) +{ + *data = 0; + while (*optstr) { + switch (*optstr) { + case 'p': + *data |= WAKE_PHY; + break; + case 'u': + *data |= WAKE_UCAST; + break; + case 'm': + *data |= WAKE_MCAST; + break; + case 'b': + *data |= WAKE_BCAST; + break; + case 'a': + *data |= WAKE_ARP; + break; + case 'g': + *data |= WAKE_MAGIC; + break; + case 's': + *data |= WAKE_MAGICSECURE; + break; + case 'd': + *data = 0; + break; + default: + return -1; + } + optstr++; + } + return 0; +} + +static char *unparse_wolopts(int wolopts) +{ + static char buf[16]; + char *p = buf; + + memset(buf, 0, sizeof(buf)); + + if (wolopts) { + if (wolopts & WAKE_PHY) + *p++ = 'p'; + if (wolopts & WAKE_UCAST) + *p++ = 'u'; + if (wolopts & WAKE_MCAST) + *p++ = 'm'; + if (wolopts & WAKE_BCAST) + *p++ = 'b'; + if (wolopts & WAKE_ARP) + *p++ = 'a'; + if (wolopts & WAKE_MAGIC) + *p++ = 'g'; + if (wolopts & WAKE_MAGICSECURE) + *p++ = 's'; + } else { + *p = 'd'; + } + + return buf; +} + +static int parse_sopass(char *src, unsigned char *dest) +{ + int count; + int i; + int buf[SOPASS_MAX]; + + count = sscanf(src, "%2x:%2x:%2x:%2x:%2x:%2x", + &buf[0], &buf[1], &buf[2], &buf[3], &buf[4], &buf[5]); + if (count != SOPASS_MAX) { + return -1; + } + + for (i = 0; i < count; i++) { + dest[i] = buf[i]; + } + return 0; +} + +static int parse_rxfhashopts(char *optstr, u32 *data) +{ + *data = 0; + while (*optstr) { + switch (*optstr) { + case 'm': + *data |= RXH_L2DA; + break; + case 'v': + *data |= RXH_VLAN; + break; + case 't': + *data |= RXH_L3_PROTO; + break; + case 's': + *data |= RXH_IP_SRC; + break; + case 'd': + *data |= RXH_IP_DST; + break; + case 'f': + *data |= RXH_L4_B_0_1; + break; + case 'n': + *data |= RXH_L4_B_2_3; + break; + case 'r': + *data |= RXH_DISCARD; + break; + default: + return -1; + } + optstr++; + } + return 0; +} + +static char *unparse_rxfhashopts(u64 opts) +{ + static char buf[300]; + + memset(buf, 0, sizeof(buf)); + + if (opts) { + if (opts & RXH_L2DA) { + strcat(buf, "L2DA\n"); + } + if (opts & RXH_VLAN) { + strcat(buf, "VLAN tag\n"); + } + if (opts & RXH_L3_PROTO) { + strcat(buf, "L3 proto\n"); + } + if (opts & RXH_IP_SRC) { + strcat(buf, "IP SA\n"); + } + if (opts & RXH_IP_DST) { + strcat(buf, "IP DA\n"); + } + if (opts & RXH_L4_B_0_1) { + strcat(buf, "L4 bytes 0 & 1 [TCP/UDP src port]\n"); + } + if (opts & RXH_L4_B_2_3) { + strcat(buf, "L4 bytes 2 & 3 [TCP/UDP dst port]\n"); + } + } else { + sprintf(buf, "None"); + } + + return buf; +} + +static struct { + const char *name; + int (*func)(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + +} driver_list[] = { + { "8139cp", realtek_dump_regs }, + { "8139too", realtek_dump_regs }, + { "r8169", realtek_dump_regs }, + { "de2104x", de2104x_dump_regs }, + { "e1000", e1000_dump_regs }, + { "e1000e", e1000_dump_regs }, + { "igb", igb_dump_regs }, + { "ixgb", ixgb_dump_regs }, + { "ixgbe", ixgbe_dump_regs }, + { "natsemi", natsemi_dump_regs }, + { "e100", e100_dump_regs }, + { "amd8111e", amd8111e_dump_regs }, + { "pcnet32", pcnet32_dump_regs }, + { "fec_8xx", fec_8xx_dump_regs }, + { "ibm_emac", ibm_emac_dump_regs }, + { "tg3", tg3_dump_regs }, + { "skge", skge_dump_regs }, + { "sky2", sky2_dump_regs }, + { "vioc", vioc_dump_regs }, + { "smsc911x", smsc911x_dump_regs }, + { "at76c50x-usb", at76c50x_usb_dump_regs }, + { "sfc", sfc_dump_regs }, +}; + +static int dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + int i; + + if (gregs_dump_raw) { + fwrite(regs->data, regs->len, 1, stdout); + return 0; + } + + if (gregs_dump_file) { + FILE *f = fopen(gregs_dump_file, "r"); + struct stat st; + + if (!f || fstat(fileno(f), &st) < 0) { + fprintf(stderr, "Can't open '%s': %s\n", + gregs_dump_file, strerror(errno)); + return -1; + } + + regs = realloc(regs, sizeof(*regs) + st.st_size); + regs->len = st.st_size; + fread(regs->data, regs->len, 1, f); + fclose(f); + } + + if (!gregs_dump_hex) + for (i = 0; i < ARRAY_SIZE(driver_list); i++) + if (!strncmp(driver_list[i].name, info->driver, + ETHTOOL_BUSINFO_LEN)) + return driver_list[i].func(info, regs); + + fprintf(stdout, "Offset\tValues\n"); + fprintf(stdout, "--------\t-----"); + for (i = 0; i < regs->len; i++) { + if (i%16 == 0) + fprintf(stdout, "\n%03x:\t", i); + fprintf(stdout, " %02x", regs->data[i]); + } + fprintf(stdout, "\n\n"); + return 0; +} + +static int dump_eeprom(struct ethtool_drvinfo *info, struct ethtool_eeprom *ee) +{ + int i; + + if (geeprom_dump_raw) { + fwrite(ee->data, 1, ee->len, stdout); + return 0; + } + + if (!strncmp("natsemi", info->driver, ETHTOOL_BUSINFO_LEN)) { + return natsemi_dump_eeprom(info, ee); + } else if (!strncmp("tg3", info->driver, ETHTOOL_BUSINFO_LEN)) { + return tg3_dump_eeprom(info, ee); + } + + fprintf(stdout, "Offset\t\tValues\n"); + fprintf(stdout, "------\t\t------"); + for (i = 0; i < ee->len; i++) { + if(!(i%16)) fprintf(stdout, "\n0x%04x\t\t", i + ee->offset); + fprintf(stdout, "%02x ", ee->data[i]); + } + fprintf(stdout, "\n"); + return 0; +} + +static int dump_test(struct ethtool_drvinfo *info, struct ethtool_test *test, + struct ethtool_gstrings *strings) +{ + int i, rc; + + rc = test->flags & ETH_TEST_FL_FAILED; + fprintf(stdout, "The test result is %s\n", rc ? "FAIL" : "PASS"); + + if (info->testinfo_len) + fprintf(stdout, "The test extra info:\n"); + + for (i = 0; i < info->testinfo_len; i++) { + fprintf(stdout, "%s\t %d\n", + (char *)(strings->data + i * ETH_GSTRING_LEN), + (u32) test->data[i]); + } + + fprintf(stdout, "\n"); + return rc; +} + +static int dump_pause(void) +{ + fprintf(stdout, + "Autonegotiate: %s\n" + "RX: %s\n" + "TX: %s\n", + epause.autoneg ? "on" : "off", + epause.rx_pause ? "on" : "off", + epause.tx_pause ? "on" : "off"); + + fprintf(stdout, "\n"); + return 0; +} + +static int dump_ring(void) +{ + fprintf(stdout, + "Pre-set maximums:\n" + "RX: %u\n" + "RX Mini: %u\n" + "RX Jumbo: %u\n" + "TX: %u\n", + ering.rx_max_pending, + ering.rx_mini_max_pending, + ering.rx_jumbo_max_pending, + ering.tx_max_pending); + + fprintf(stdout, + "Current hardware settings:\n" + "RX: %u\n" + "RX Mini: %u\n" + "RX Jumbo: %u\n" + "TX: %u\n", + ering.rx_pending, + ering.rx_mini_pending, + ering.rx_jumbo_pending, + ering.tx_pending); + + fprintf(stdout, "\n"); + return 0; +} + +static int dump_coalesce(void) +{ + fprintf(stdout, "Adaptive RX: %s TX: %s\n", + ecoal.use_adaptive_rx_coalesce ? "on" : "off", + ecoal.use_adaptive_tx_coalesce ? "on" : "off"); + + fprintf(stdout, + "stats-block-usecs: %u\n" + "sample-interval: %u\n" + "pkt-rate-low: %u\n" + "pkt-rate-high: %u\n" + "\n" + "rx-usecs: %u\n" + "rx-frames: %u\n" + "rx-usecs-irq: %u\n" + "rx-frames-irq: %u\n" + "\n" + "tx-usecs: %u\n" + "tx-frames: %u\n" + "tx-usecs-irq: %u\n" + "tx-frames-irq: %u\n" + "\n" + "rx-usecs-low: %u\n" + "rx-frame-low: %u\n" + "tx-usecs-low: %u\n" + "tx-frame-low: %u\n" + "\n" + "rx-usecs-high: %u\n" + "rx-frame-high: %u\n" + "tx-usecs-high: %u\n" + "tx-frame-high: %u\n" + "\n", + ecoal.stats_block_coalesce_usecs, + ecoal.rate_sample_interval, + ecoal.pkt_rate_low, + ecoal.pkt_rate_high, + + ecoal.rx_coalesce_usecs, + ecoal.rx_max_coalesced_frames, + ecoal.rx_coalesce_usecs_irq, + ecoal.rx_max_coalesced_frames_irq, + + ecoal.tx_coalesce_usecs, + ecoal.tx_max_coalesced_frames, + ecoal.tx_coalesce_usecs_irq, + ecoal.tx_max_coalesced_frames_irq, + + ecoal.rx_coalesce_usecs_low, + ecoal.rx_max_coalesced_frames_low, + ecoal.tx_coalesce_usecs_low, + ecoal.tx_max_coalesced_frames_low, + + ecoal.rx_coalesce_usecs_high, + ecoal.rx_max_coalesced_frames_high, + ecoal.tx_coalesce_usecs_high, + ecoal.tx_max_coalesced_frames_high); + + return 0; +} + +static int dump_offload(int rx, int tx, int sg, int tso, int ufo, int gso, + int gro, int lro, int ntuple, int rxhash) +{ + fprintf(stdout, + "rx-checksumming: %s\n" + "tx-checksumming: %s\n" + "scatter-gather: %s\n" + "tcp-segmentation-offload: %s\n" + "udp-fragmentation-offload: %s\n" + "generic-segmentation-offload: %s\n" + "generic-receive-offload: %s\n" + "large-receive-offload: %s\n" + "ntuple-filters: %s\n" + "receive-hashing: %s\n", + rx ? "on" : "off", + tx ? "on" : "off", + sg ? "on" : "off", + tso ? "on" : "off", + ufo ? "on" : "off", + gso ? "on" : "off", + gro ? "on" : "off", + lro ? "on" : "off", + ntuple ? "on" : "off", + rxhash ? "on" : "off"); + + return 0; +} + +static int dump_rxfhash(int fhash, u64 val) +{ + switch (fhash) { + case TCP_V4_FLOW: + fprintf(stdout, "TCP over IPV4 flows"); + break; + case UDP_V4_FLOW: + fprintf(stdout, "UDP over IPV4 flows"); + break; + case SCTP_V4_FLOW: + fprintf(stdout, "SCTP over IPV4 flows"); + break; + case AH_ESP_V4_FLOW: + fprintf(stdout, "IPSEC AH over IPV4 flows"); + break; + case TCP_V6_FLOW: + fprintf(stdout, "TCP over IPV6 flows"); + break; + case UDP_V6_FLOW: + fprintf(stdout, "UDP over IPV6 flows"); + break; + case SCTP_V6_FLOW: + fprintf(stdout, "SCTP over IPV6 flows"); + break; + case AH_ESP_V6_FLOW: + fprintf(stdout, "IPSEC AH over IPV6 flows"); + break; + default: + break; + } + + if (val & RXH_DISCARD) { + fprintf(stdout, " - All matching flows discarded on RX\n"); + return 0; + } + fprintf(stdout, " use these fields for computing Hash flow key:\n"); + + fprintf(stdout, "%s\n", unparse_rxfhashopts(val)); + + return 0; +} + +static int doit(void) +{ + struct ifreq ifr; + int fd; + + /* Setup our control structures. */ + memset(&ifr, 0, sizeof(ifr)); + strcpy(ifr.ifr_name, devname); + + /* Open control socket. */ + fd = socket(AF_INET, SOCK_DGRAM, 0); + if (fd < 0) { + perror("Cannot get control socket"); + return 70; + } + + /* all of these are expected to populate ifr->ifr_data as needed */ + if (mode == MODE_GDRV) { + return do_gdrv(fd, &ifr); + } else if (mode == MODE_GSET) { + return do_gset(fd, &ifr); + } else if (mode == MODE_SSET) { + return do_sset(fd, &ifr); + } else if (mode == MODE_GREGS) { + return do_gregs(fd, &ifr); + } else if (mode == MODE_NWAY_RST) { + return do_nway_rst(fd, &ifr); + } else if (mode == MODE_GEEPROM) { + return do_geeprom(fd, &ifr); + } else if (mode == MODE_SEEPROM) { + return do_seeprom(fd, &ifr); + } else if (mode == MODE_TEST) { + return do_test(fd, &ifr); + } else if (mode == MODE_PHYS_ID) { + return do_phys_id(fd, &ifr); + } else if (mode == MODE_GPAUSE) { + return do_gpause(fd, &ifr); + } else if (mode == MODE_SPAUSE) { + return do_spause(fd, &ifr); + } else if (mode == MODE_GCOALESCE) { + return do_gcoalesce(fd, &ifr); + } else if (mode == MODE_SCOALESCE) { + return do_scoalesce(fd, &ifr); + } else if (mode == MODE_GRING) { + return do_gring(fd, &ifr); + } else if (mode == MODE_SRING) { + return do_sring(fd, &ifr); + } else if (mode == MODE_GOFFLOAD) { + return do_goffload(fd, &ifr); + } else if (mode == MODE_SOFFLOAD) { + return do_soffload(fd, &ifr); + } else if (mode == MODE_GSTATS) { + return do_gstats(fd, &ifr); + } else if (mode == MODE_GNFC) { + return do_grxclass(fd, &ifr); + } else if (mode == MODE_SNFC) { + return do_srxclass(fd, &ifr); + } else if (mode == MODE_GRXFHINDIR) { + return do_grxfhindir(fd, &ifr); + } else if (mode == MODE_SRXFHINDIR) { + return do_srxfhindir(fd, &ifr); + } else if (mode == MODE_SNTUPLE) { + return do_srxntuple(fd, &ifr); + } else if (mode == MODE_GNTUPLE) { + return do_grxntuple(fd, &ifr); + } else if (mode == MODE_FLASHDEV) { + return do_flash(fd, &ifr); + } + + return 69; +} + +static int do_gdrv(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_drvinfo drvinfo; + + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr->ifr_data = (caddr_t)&drvinfo; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get driver information"); + return 71; + } + return dump_drvinfo(&drvinfo); +} + +static int do_gpause(int fd, struct ifreq *ifr) +{ + int err; + + fprintf(stdout, "Pause parameters for %s:\n", devname); + + epause.cmd = ETHTOOL_GPAUSEPARAM; + ifr->ifr_data = (caddr_t)&epause; + err = send_ioctl(fd, ifr); + if (err == 0) { + err = dump_pause(); + if (err) + return err; + } else { + perror("Cannot get device pause settings"); + return 76; + } + + return 0; +} + +static void do_generic_set1(struct cmdline_info *info, int *changed_out) +{ + int wanted, *v1, *v2; + + v1 = info->wanted_val; + wanted = *v1; + + if (wanted < 0) + return; + + v2 = info->ioctl_val; + if (wanted == *v2) { + fprintf(stderr, "%s unmodified, ignoring\n", info->name); + } else { + *v2 = wanted; + *changed_out = 1; + } +} + +static void do_generic_set(struct cmdline_info *info, + unsigned int n_info, + int *changed_out) +{ + unsigned int i; + + for (i = 0; i < n_info; i++) + do_generic_set1(&info[i], changed_out); +} + +static int do_spause(int fd, struct ifreq *ifr) +{ + int err, changed = 0; + + epause.cmd = ETHTOOL_GPAUSEPARAM; + ifr->ifr_data = (caddr_t)&epause; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot get device pause settings"); + return 77; + } + + do_generic_set(cmdline_pause, ARRAY_SIZE(cmdline_pause), &changed); + + if (!changed) { + fprintf(stderr, "no pause parameters changed, aborting\n"); + return 78; + } + + epause.cmd = ETHTOOL_SPAUSEPARAM; + ifr->ifr_data = (caddr_t)&epause; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device pause parameters"); + return 79; + } + + return 0; +} + +static int do_sring(int fd, struct ifreq *ifr) +{ + int err, changed = 0; + + ering.cmd = ETHTOOL_GRINGPARAM; + ifr->ifr_data = (caddr_t)&ering; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot get device ring settings"); + return 76; + } + + do_generic_set(cmdline_ring, ARRAY_SIZE(cmdline_ring), &changed); + + if (!changed) { + fprintf(stderr, "no ring parameters changed, aborting\n"); + return 80; + } + + ering.cmd = ETHTOOL_SRINGPARAM; + ifr->ifr_data = (caddr_t)&ering; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device ring parameters"); + return 81; + } + + return 0; +} + +static int do_gring(int fd, struct ifreq *ifr) +{ + int err; + + fprintf(stdout, "Ring parameters for %s:\n", devname); + + ering.cmd = ETHTOOL_GRINGPARAM; + ifr->ifr_data = (caddr_t)&ering; + err = send_ioctl(fd, ifr); + if (err == 0) { + err = dump_ring(); + if (err) + return err; + } else { + perror("Cannot get device ring settings"); + return 76; + } + + return 0; +} + +static int do_gcoalesce(int fd, struct ifreq *ifr) +{ + int err; + + fprintf(stdout, "Coalesce parameters for %s:\n", devname); + + ecoal.cmd = ETHTOOL_GCOALESCE; + ifr->ifr_data = (caddr_t)&ecoal; + err = send_ioctl(fd, ifr); + if (err == 0) { + err = dump_coalesce(); + if (err) + return err; + } else { + perror("Cannot get device coalesce settings"); + return 82; + } + + return 0; +} + +static int do_scoalesce(int fd, struct ifreq *ifr) +{ + int err, changed = 0; + + ecoal.cmd = ETHTOOL_GCOALESCE; + ifr->ifr_data = (caddr_t)&ecoal; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot get device coalesce settings"); + return 76; + } + + do_generic_set(cmdline_coalesce, ARRAY_SIZE(cmdline_coalesce), + &changed); + + if (!changed) { + fprintf(stderr, "no coalesce parameters changed, aborting\n"); + return 80; + } + + ecoal.cmd = ETHTOOL_SCOALESCE; + ifr->ifr_data = (caddr_t)&ecoal; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device coalesce parameters"); + return 81; + } + + return 0; +} + +static int do_goffload(int fd, struct ifreq *ifr) +{ + struct ethtool_value eval; + int err, allfail = 1, rx = 0, tx = 0, sg = 0; + int tso = 0, ufo = 0, gso = 0, gro = 0, lro = 0, ntuple = 0, rxhash = 0; + + fprintf(stdout, "Offload parameters for %s:\n", devname); + + eval.cmd = ETHTOOL_GRXCSUM; + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) + perror("Cannot get device rx csum settings"); + else { + rx = eval.data; + allfail = 0; + } + + eval.cmd = ETHTOOL_GTXCSUM; + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) + perror("Cannot get device tx csum settings"); + else { + tx = eval.data; + allfail = 0; + } + + eval.cmd = ETHTOOL_GSG; + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) + perror("Cannot get device scatter-gather settings"); + else { + sg = eval.data; + allfail = 0; + } + + eval.cmd = ETHTOOL_GTSO; + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) + perror("Cannot get device tcp segmentation offload settings"); + else { + tso = eval.data; + allfail = 0; + } + + eval.cmd = ETHTOOL_GUFO; + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) + perror("Cannot get device udp large send offload settings"); + else { + ufo = eval.data; + allfail = 0; + } + + eval.cmd = ETHTOOL_GGSO; + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) + perror("Cannot get device generic segmentation offload settings"); + else { + gso = eval.data; + allfail = 0; + } + + eval.cmd = ETHTOOL_GFLAGS; + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) { + perror("Cannot get device flags"); + } else { + lro = (eval.data & ETH_FLAG_LRO) != 0; + ntuple = (eval.data & ETH_FLAG_NTUPLE) != 0; + rxhash = (eval.data & ETH_FLAG_RXHASH) != 0; + allfail = 0; + } + + eval.cmd = ETHTOOL_GGRO; + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) + perror("Cannot get device GRO settings"); + else { + gro = eval.data; + allfail = 0; + } + + if (allfail) { + fprintf(stdout, "no offload info available\n"); + return 83; + } + + return dump_offload(rx, tx, sg, tso, ufo, gso, gro, lro, ntuple, rxhash); +} + +static int do_soffload(int fd, struct ifreq *ifr) +{ + struct ethtool_value eval; + int err, changed = 0; + + if (off_csum_rx_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_SRXCSUM; + eval.data = (off_csum_rx_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device rx csum settings"); + return 84; + } + } + + if (off_csum_tx_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_STXCSUM; + eval.data = (off_csum_tx_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device tx csum settings"); + return 85; + } + } + + if (off_sg_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_SSG; + eval.data = (off_sg_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device scatter-gather settings"); + return 86; + } + } + + if (off_tso_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_STSO; + eval.data = (off_tso_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = send_ioctl(fd, ifr); + if (err) { + perror("Cannot set device tcp segmentation offload settings"); + return 88; + } + } + if (off_ufo_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_SUFO; + eval.data = (off_ufo_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) { + perror("Cannot set device udp large send offload settings"); + return 89; + } + } + if (off_gso_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_SGSO; + eval.data = (off_gso_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) { + perror("Cannot set device generic segmentation offload settings"); + return 90; + } + } + if (off_flags_wanted || off_flags_unwanted) { + changed = 1; + eval.cmd = ETHTOOL_GFLAGS; + eval.data = 0; + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) { + perror("Cannot get device flag settings"); + return 91; + } + + eval.cmd = ETHTOOL_SFLAGS; + eval.data = ((eval.data & ~off_flags_unwanted) | + off_flags_wanted); + + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) { + perror("Cannot set device flag settings"); + return 92; + } + } + if (off_gro_wanted >= 0) { + changed = 1; + eval.cmd = ETHTOOL_SGRO; + eval.data = (off_gro_wanted == 1); + ifr->ifr_data = (caddr_t)&eval; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err) { + perror("Cannot set device GRO settings"); + return 93; + } + } + + if (!changed) { + fprintf(stdout, "no offload settings changed\n"); + } + + return 0; +} + +static int do_gset(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_cmd ecmd; + struct ethtool_wolinfo wolinfo; + struct ethtool_value edata; + int allfail = 1; + + fprintf(stdout, "Settings for %s:\n", devname); + + ecmd.cmd = ETHTOOL_GSET; + ifr->ifr_data = (caddr_t)&ecmd; + err = send_ioctl(fd, ifr); + if (err == 0) { + err = dump_ecmd(&ecmd); + if (err) + return err; + allfail = 0; + } else if (errno != EOPNOTSUPP) { + perror("Cannot get device settings"); + } + + wolinfo.cmd = ETHTOOL_GWOL; + ifr->ifr_data = (caddr_t)&wolinfo; + err = send_ioctl(fd, ifr); + if (err == 0) { + err = dump_wol(&wolinfo); + if (err) + return err; + allfail = 0; + } else if (errno != EOPNOTSUPP) { + perror("Cannot get wake-on-lan settings"); + } + + edata.cmd = ETHTOOL_GMSGLVL; + ifr->ifr_data = (caddr_t)&edata; + err = send_ioctl(fd, ifr); + if (err == 0) { + fprintf(stdout, " Current message level: 0x%08x (%d)\n" + " ", + edata.data, edata.data); + print_flags(cmdline_msglvl, ARRAY_SIZE(cmdline_msglvl), + edata.data); + fprintf(stdout, "\n"); + allfail = 0; + } else if (errno != EOPNOTSUPP) { + perror("Cannot get message level"); + } + + edata.cmd = ETHTOOL_GLINK; + ifr->ifr_data = (caddr_t)&edata; + err = send_ioctl(fd, ifr); + if (err == 0) { + fprintf(stdout, " Link detected: %s\n", + edata.data ? "yes":"no"); + allfail = 0; + } else if (errno != EOPNOTSUPP) { + perror("Cannot get link status"); + } + + if (allfail) { + fprintf(stdout, "No data available\n"); + return 75; + } + return 0; +} + +static int do_sset(int fd, struct ifreq *ifr) +{ + int err; + + if (gset_changed) { + struct ethtool_cmd ecmd; + + ecmd.cmd = ETHTOOL_GSET; + ifr->ifr_data = (caddr_t)&ecmd; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get current device settings"); + } else { + /* Change everything the user specified. */ + if (speed_wanted != -1) + ethtool_cmd_speed_set(&ecmd, speed_wanted); + if (duplex_wanted != -1) + ecmd.duplex = duplex_wanted; + if (port_wanted != -1) + ecmd.port = port_wanted; + if (autoneg_wanted != -1) + ecmd.autoneg = autoneg_wanted; + if (phyad_wanted != -1) + ecmd.phy_address = phyad_wanted; + if (xcvr_wanted != -1) + ecmd.transceiver = xcvr_wanted; + if (advertising_wanted != -1) { + if (advertising_wanted == 0) + ecmd.advertising = ecmd.supported & + (ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_1000baseT_Half | + ADVERTISED_1000baseT_Full | + ADVERTISED_2500baseX_Full | + ADVERTISED_10000baseT_Full); + else + ecmd.advertising = advertising_wanted; + } + + /* Try to perform the update. */ + ecmd.cmd = ETHTOOL_SSET; + ifr->ifr_data = (caddr_t)&ecmd; + err = send_ioctl(fd, ifr); + if (err < 0) + perror("Cannot set new settings"); + } + if (err < 0) { + if (speed_wanted != -1) + fprintf(stderr, " not setting speed\n"); + if (duplex_wanted != -1) + fprintf(stderr, " not setting duplex\n"); + if (port_wanted != -1) + fprintf(stderr, " not setting port\n"); + if (autoneg_wanted != -1) + fprintf(stderr, " not setting autoneg\n"); + if (phyad_wanted != -1) + fprintf(stderr, " not setting phy_address\n"); + if (xcvr_wanted != -1) + fprintf(stderr, " not setting transceiver\n"); + } + } + + if (gwol_changed) { + struct ethtool_wolinfo wol; + + wol.cmd = ETHTOOL_GWOL; + ifr->ifr_data = (caddr_t)&wol; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get current wake-on-lan settings"); + } else { + /* Change everything the user specified. */ + if (wol_change) { + wol.wolopts = wol_wanted; + } + if (sopass_change) { + int i; + for (i = 0; i < SOPASS_MAX; i++) { + wol.sopass[i] = sopass_wanted[i]; + } + } + + /* Try to perform the update. */ + wol.cmd = ETHTOOL_SWOL; + ifr->ifr_data = (caddr_t)&wol; + err = send_ioctl(fd, ifr); + if (err < 0) + perror("Cannot set new wake-on-lan settings"); + } + if (err < 0) { + if (wol_change) + fprintf(stderr, " not setting wol\n"); + if (sopass_change) + fprintf(stderr, " not setting sopass\n"); + } + } + + if (msglvl_changed) { + struct ethtool_value edata; + + edata.cmd = ETHTOOL_GMSGLVL; + ifr->ifr_data = (caddr_t)&edata; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get msglvl"); + } else { + edata.cmd = ETHTOOL_SMSGLVL; + edata.data = ((edata.data & ~msglvl_unwanted) | + msglvl_wanted); + ifr->ifr_data = (caddr_t)&edata; + err = send_ioctl(fd, ifr); + if (err < 0) + perror("Cannot set new msglvl"); + } + } + + return 0; +} + +static int do_gregs(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_drvinfo drvinfo; + struct ethtool_regs *regs; + + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr->ifr_data = (caddr_t)&drvinfo; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get driver information"); + return 72; + } + + regs = calloc(1, sizeof(*regs)+drvinfo.regdump_len); + if (!regs) { + perror("Cannot allocate memory for register dump"); + return 73; + } + regs->cmd = ETHTOOL_GREGS; + regs->len = drvinfo.regdump_len; + ifr->ifr_data = (caddr_t)regs; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get register dump"); + free(regs); + return 74; + } + if(dump_regs(&drvinfo, regs) < 0) { + perror("Cannot dump registers"); + free(regs); + return 75; + } + free(regs); + + return 0; +} + +static int do_nway_rst(int fd, struct ifreq *ifr) +{ + struct ethtool_value edata; + int err; + + edata.cmd = ETHTOOL_NWAY_RST; + ifr->ifr_data = (caddr_t)&edata; + err = send_ioctl(fd, ifr); + if (err < 0) + perror("Cannot restart autonegotiation"); + + return err; +} + +static int do_geeprom(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_drvinfo drvinfo; + struct ethtool_eeprom *eeprom; + + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr->ifr_data = (caddr_t)&drvinfo; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get driver information"); + return 74; + } + + if (geeprom_length <= 0) + geeprom_length = drvinfo.eedump_len; + + if (drvinfo.eedump_len < geeprom_offset + geeprom_length) + geeprom_length = drvinfo.eedump_len - geeprom_offset; + + eeprom = calloc(1, sizeof(*eeprom)+geeprom_length); + if (!eeprom) { + perror("Cannot allocate memory for EEPROM data"); + return 75; + } + eeprom->cmd = ETHTOOL_GEEPROM; + eeprom->len = geeprom_length; + eeprom->offset = geeprom_offset; + ifr->ifr_data = (caddr_t)eeprom; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get EEPROM data"); + free(eeprom); + return 74; + } + err = dump_eeprom(&drvinfo, eeprom); + free(eeprom); + + return err; +} + +static int do_seeprom(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_drvinfo drvinfo; + struct ethtool_eeprom *eeprom; + + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr->ifr_data = (caddr_t)&drvinfo; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get driver information"); + return 74; + } + + if (seeprom_value != EOF) + seeprom_length = 1; + + if (seeprom_length <= 0) + seeprom_length = drvinfo.eedump_len; + + if (drvinfo.eedump_len < seeprom_offset + seeprom_length) + seeprom_length = drvinfo.eedump_len - seeprom_offset; + + eeprom = calloc(1, sizeof(*eeprom)+seeprom_length); + if (!eeprom) { + perror("Cannot allocate memory for EEPROM data"); + return 75; + } + + eeprom->cmd = ETHTOOL_SEEPROM; + eeprom->len = seeprom_length; + eeprom->offset = seeprom_offset; + eeprom->magic = seeprom_magic; + eeprom->data[0] = seeprom_value; + + /* Multi-byte write: read input from stdin */ + if (seeprom_value == EOF) + eeprom->len = fread(eeprom->data, 1, eeprom->len, stdin); + + ifr->ifr_data = (caddr_t)eeprom; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot set EEPROM data"); + err = 87; + } + free(eeprom); + + return err; +} + +static int do_test(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_drvinfo drvinfo; + struct ethtool_test *test; + struct ethtool_gstrings *strings; + + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr->ifr_data = (caddr_t)&drvinfo; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get driver information"); + return 72; + } + + test = calloc(1, sizeof(*test) + drvinfo.testinfo_len * sizeof(u64)); + if (!test) { + perror("Cannot allocate memory for test info"); + return 73; + } + memset (test->data, 0, drvinfo.testinfo_len * sizeof(u64)); + test->cmd = ETHTOOL_TEST; + test->len = drvinfo.testinfo_len; + if (test_type == OFFLINE) + test->flags = ETH_TEST_FL_OFFLINE; + else + test->flags = 0; + ifr->ifr_data = (caddr_t)test; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot test"); + free (test); + return 74; + } + + strings = calloc(1, sizeof(*strings) + + drvinfo.testinfo_len * ETH_GSTRING_LEN); + if (!strings) { + perror("Cannot allocate memory for strings"); + free(test); + return 73; + } + memset (strings->data, 0, drvinfo.testinfo_len * ETH_GSTRING_LEN); + strings->cmd = ETHTOOL_GSTRINGS; + strings->string_set = ETH_SS_TEST; + strings->len = drvinfo.testinfo_len; + ifr->ifr_data = (caddr_t)strings; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get strings"); + free (test); + free (strings); + return 74; + } + err = dump_test(&drvinfo, test, strings); + free(test); + free(strings); + + return err; +} + +static int do_phys_id(int fd, struct ifreq *ifr) +{ + int err; + struct ethtool_value edata; + + edata.cmd = ETHTOOL_PHYS_ID; + edata.data = phys_id_time; + ifr->ifr_data = (caddr_t)&edata; + err = send_ioctl(fd, ifr); + if (err < 0) + perror("Cannot identify NIC"); + + return err; +} + +static int do_gstats(int fd, struct ifreq *ifr) +{ + struct ethtool_drvinfo drvinfo; + struct ethtool_gstrings *strings; + struct ethtool_stats *stats; + unsigned int n_stats, sz_str, sz_stats, i; + int err; + + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr->ifr_data = (caddr_t)&drvinfo; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get driver information"); + return 71; + } + + n_stats = drvinfo.n_stats; + if (n_stats < 1) { + fprintf(stderr, "no stats available\n"); + return 94; + } + + sz_str = n_stats * ETH_GSTRING_LEN; + sz_stats = n_stats * sizeof(u64); + + strings = calloc(1, sz_str + sizeof(struct ethtool_gstrings)); + stats = calloc(1, sz_stats + sizeof(struct ethtool_stats)); + if (!strings || !stats) { + fprintf(stderr, "no memory available\n"); + return 95; + } + + strings->cmd = ETHTOOL_GSTRINGS; + strings->string_set = ETH_SS_STATS; + strings->len = n_stats; + ifr->ifr_data = (caddr_t) strings; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get stats strings information"); + free(strings); + free(stats); + return 96; + } + + stats->cmd = ETHTOOL_GSTATS; + stats->n_stats = n_stats; + ifr->ifr_data = (caddr_t) stats; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get stats information"); + free(strings); + free(stats); + return 97; + } + + /* todo - pretty-print the strings per-driver */ + fprintf(stdout, "NIC statistics:\n"); + for (i = 0; i < n_stats; i++) { + fprintf(stdout, " %.*s: %llu\n", + ETH_GSTRING_LEN, + &strings->data[i * ETH_GSTRING_LEN], + stats->data[i]); + } + free(strings); + free(stats); + + return 0; +} + + +static int do_srxclass(int fd, struct ifreq *ifr) +{ + int err; + + if (rx_fhash_changed) { + struct ethtool_rxnfc nfccmd; + + nfccmd.cmd = ETHTOOL_SRXFH; + nfccmd.flow_type = rx_fhash_set; + nfccmd.data = rx_fhash_val; + + ifr->ifr_data = (caddr_t)&nfccmd; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err < 0) + perror("Cannot change RX network flow hashing options"); + + } + + return 0; +} + +static int do_grxclass(int fd, struct ifreq *ifr) +{ + int err; + + if (rx_fhash_get) { + struct ethtool_rxnfc nfccmd; + + nfccmd.cmd = ETHTOOL_GRXFH; + nfccmd.flow_type = rx_fhash_get; + ifr->ifr_data = (caddr_t)&nfccmd; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err < 0) + perror("Cannot get RX network flow hashing options"); + else + dump_rxfhash(rx_fhash_get, nfccmd.data); + } + + return 0; +} + +static int do_grxfhindir(int fd, struct ifreq *ifr) +{ + struct ethtool_rxnfc ring_count; + struct ethtool_rxfh_indir indir_head; + struct ethtool_rxfh_indir *indir; + u32 i; + int err; + + ring_count.cmd = ETHTOOL_GRXRINGS; + ifr->ifr_data = (caddr_t) &ring_count; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get RX ring count"); + return 102; + } + + indir_head.cmd = ETHTOOL_GRXFHINDIR; + indir_head.size = 0; + ifr->ifr_data = (caddr_t) &indir_head; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get RX flow hash indirection table size"); + return 103; + } + + indir = malloc(sizeof(*indir) + + indir_head.size * sizeof(*indir->ring_index)); + indir->cmd = ETHTOOL_GRXFHINDIR; + indir->size = indir_head.size; + ifr->ifr_data = (caddr_t) indir; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get RX flow hash indirection table"); + return 103; + } + + printf("RX flow hash indirection table for %s with %llu RX ring(s):\n", + devname, ring_count.data); + for (i = 0; i < indir->size; i++) { + if (i % 8 == 0) + printf("%5u: ", i); + printf(" %5u", indir->ring_index[i]); + if (i % 8 == 7) + fputc('\n', stdout); + } + return 0; +} + +static int do_srxfhindir(int fd, struct ifreq *ifr) +{ + struct ethtool_rxfh_indir indir_head; + struct ethtool_rxfh_indir *indir; + u32 i; + int err; + + if (!rxfhindir_equal && !rxfhindir_weight) + show_usage(1); + + indir_head.cmd = ETHTOOL_GRXFHINDIR; + indir_head.size = 0; + ifr->ifr_data = (caddr_t) &indir_head; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get RX flow hash indirection table size"); + return 104; + } + + indir = malloc(sizeof(*indir) + + indir_head.size * sizeof(*indir->ring_index)); + indir->cmd = ETHTOOL_SRXFHINDIR; + indir->size = indir_head.size; + + if (rxfhindir_equal) { + for (i = 0; i < indir->size; i++) + indir->ring_index[i] = i % rxfhindir_equal; + } else { + u32 j, weight, sum = 0, partial = 0; + + for (j = 0; rxfhindir_weight[j]; j++) { + weight = get_u32(rxfhindir_weight[j], 0); + sum += weight; + } + + if (sum == 0) { + fprintf(stderr, + "At least one weight must be non-zero\n"); + exit(1); + } + + if (sum > indir->size) { + fprintf(stderr, + "Total weight exceeds the size of the " + "indirection table\n"); + exit(1); + } + + j = -1; + for (i = 0; i < indir->size; i++) { + while (i >= indir->size * partial / sum) { + j += 1; + weight = get_u32(rxfhindir_weight[j], 0); + partial += weight; + } + indir->ring_index[i] = j; + } + } + + ifr->ifr_data = (caddr_t) indir; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot set RX flow hash indirection table"); + return 105; + } + + return 0; +} + +static int do_flash(int fd, struct ifreq *ifr) +{ + struct ethtool_flash efl; + int err; + + if (flash < 0) { + fprintf(stdout, "Missing filename argument\n"); + show_usage(1); + return 98; + } + + if (strlen(flash_file) > ETHTOOL_FLASH_MAX_FILENAME - 1) { + fprintf(stdout, "Filename too long\n"); + return 99; + } + + efl.cmd = ETHTOOL_FLASHDEV; + strcpy(efl.data, flash_file); + + if (flash_region < 0) + efl.region = ETHTOOL_FLASH_ALL_REGIONS; + else + efl.region = flash_region; + + ifr->ifr_data = (caddr_t)&efl; + err = send_ioctl(fd, ifr); + if (err < 0) + perror("Flashing failed"); + + return err; +} + +static int do_srxntuple(int fd, struct ifreq *ifr) +{ + int err; + + if (sntuple_changed) { + struct ethtool_rx_ntuple ntuplecmd; + + ntuplecmd.cmd = ETHTOOL_SRXNTUPLE; + memcpy(&ntuplecmd.fs, &ntuple_fs, + sizeof(struct ethtool_rx_ntuple_flow_spec)); + + ifr->ifr_data = (caddr_t)&ntuplecmd; + err = ioctl(fd, SIOCETHTOOL, ifr); + if (err < 0) + perror("Cannot add new RX n-tuple filter"); + } else { + show_usage(1); + } + + return 0; +} + +static int do_grxntuple(int fd, struct ifreq *ifr) +{ + struct ethtool_sset_info *sset_info; + struct ethtool_gstrings *strings; + int sz_str, n_strings, err, i; + + sset_info = malloc(sizeof(struct ethtool_sset_info) + sizeof(u32)); + sset_info->cmd = ETHTOOL_GSSET_INFO; + sset_info->sset_mask = (1ULL << ETH_SS_NTUPLE_FILTERS); + ifr->ifr_data = (caddr_t)sset_info; + err = send_ioctl(fd, ifr); + + if ((err < 0) || + (!(sset_info->sset_mask & (1ULL << ETH_SS_NTUPLE_FILTERS)))) { + perror("Cannot get driver strings info"); + return 100; + } + + n_strings = sset_info->data[0]; + free(sset_info); + sz_str = n_strings * ETH_GSTRING_LEN; + + strings = calloc(1, sz_str + sizeof(struct ethtool_gstrings)); + if (!strings) { + fprintf(stderr, "no memory available\n"); + return 95; + } + + strings->cmd = ETHTOOL_GRXNTUPLE; + strings->string_set = ETH_SS_NTUPLE_FILTERS; + strings->len = n_strings; + ifr->ifr_data = (caddr_t) strings; + err = send_ioctl(fd, ifr); + if (err < 0) { + perror("Cannot get Rx n-tuple information"); + free(strings); + return 101; + } + + n_strings = strings->len; + fprintf(stdout, "Rx n-tuple filters:\n"); + for (i = 0; i < n_strings; i++) + fprintf(stdout, "%s", &strings->data[i * ETH_GSTRING_LEN]); + + free(strings); + + return 0; +} + +static int send_ioctl(int fd, struct ifreq *ifr) +{ + return ioctl(fd, SIOCETHTOOL, ifr); +} + +int main(int argc, char **argp, char **envp) +{ + parse_cmdline(argc, argp); + return doit(); +}
diff --git a/ethtool-2.6.35/ethtool.spec b/ethtool-2.6.35/ethtool.spec new file mode 100644 index 0000000..0bf078b --- /dev/null +++ b/ethtool-2.6.35/ethtool.spec
@@ -0,0 +1,42 @@ +Name : ethtool +Version : 2.6.35 +Release : 1 +Group : Utilities + +Summary : A tool for setting ethernet parameters + +License : GPL +URL : http://sourceforge.net/projects/gkernel/ + +Buildroot : %{_tmppath}/%{name}-%{version} +Source : %{name}-%{version}.tar.gz + + +%description +Ethtool is a small utility to get and set values from your your ethernet +controllers. Not all ethernet drivers support ethtool, but it is getting +better. If your ethernet driver doesn't support it, ask the maintainer to +write support - it's not hard! + + +%prep +%setup -q + + +%build +CFLAGS="${RPM_OPT_FLAGS}" ./configure --prefix=/usr --mandir=%{_mandir} +make + + +%install +make install DESTDIR=${RPM_BUILD_ROOT} + + +%files +%defattr(-,root,root) +/usr/sbin/ethtool +%{_mandir}/man8/ethtool.8* +%doc AUTHORS COPYING INSTALL NEWS README ChangeLog + + +%changelog
diff --git a/ethtool-2.6.35/ethtool.spec.in b/ethtool-2.6.35/ethtool.spec.in new file mode 100644 index 0000000..4ff736a --- /dev/null +++ b/ethtool-2.6.35/ethtool.spec.in
@@ -0,0 +1,42 @@ +Name : @PACKAGE@ +Version : @VERSION@ +Release : 1 +Group : Utilities + +Summary : A tool for setting ethernet parameters + +License : GPL +URL : http://sourceforge.net/projects/gkernel/ + +Buildroot : %{_tmppath}/%{name}-%{version} +Source : %{name}-%{version}.tar.gz + + +%description +Ethtool is a small utility to get and set values from your your ethernet +controllers. Not all ethernet drivers support ethtool, but it is getting +better. If your ethernet driver doesn't support it, ask the maintainer to +write support - it's not hard! + + +%prep +%setup -q + + +%build +CFLAGS="${RPM_OPT_FLAGS}" ./configure --prefix=/usr --mandir=%{_mandir} +make + + +%install +make install DESTDIR=${RPM_BUILD_ROOT} + + +%files +%defattr(-,root,root) +/usr/sbin/ethtool +%{_mandir}/man8/ethtool.8* +%doc AUTHORS COPYING INSTALL NEWS README ChangeLog + + +%changelog
diff --git a/ethtool-2.6.35/fec_8xx.c b/ethtool-2.6.35/fec_8xx.c new file mode 100644 index 0000000..06a25d9 --- /dev/null +++ b/ethtool-2.6.35/fec_8xx.c
@@ -0,0 +1,81 @@ +/* + * Copyright (C) 2004 Intracom S.A. + * Pantelis Antoniou <panto@intracom.gr> + */ + +#include <stdio.h> +#include <stdint.h> +#include <stddef.h> + +#include "ethtool-util.h" + +struct fec { + uint32_t addr_low; /* lower 32 bits of station address */ + uint32_t addr_high; /* upper 16 bits of station address||0 */ + uint32_t hash_table_high;/* upper 32-bits of hash table */ + uint32_t hash_table_low; /* lower 32-bits of hash table */ + uint32_t r_des_start; /* beginning of Rx descriptor ring */ + uint32_t x_des_start; /* beginning of Tx descriptor ring */ + uint32_t r_buff_size; /* Rx buffer size */ + uint32_t res2[9]; /* reserved */ + uint32_t ecntrl; /* ethernet control register */ + uint32_t ievent; /* interrupt event register */ + uint32_t imask; /* interrupt mask register */ + uint32_t ivec; /* interrupt level and vector status */ + uint32_t r_des_active; /* Rx ring updated flag */ + uint32_t x_des_active; /* Tx ring updated flag */ + uint32_t res3[10]; /* reserved */ + uint32_t mii_data; /* MII data register */ + uint32_t mii_speed; /* MII speed control register */ + uint32_t res4[17]; /* reserved */ + uint32_t r_bound; /* end of RAM (read-only) */ + uint32_t r_fstart; /* Rx FIFO start address */ + uint32_t res5[6]; /* reserved */ + uint32_t x_fstart; /* Tx FIFO start address */ + uint32_t res6[17]; /* reserved */ + uint32_t fun_code; /* fec SDMA function code */ + uint32_t res7[3]; /* reserved */ + uint32_t r_cntrl; /* Rx control register */ + uint32_t r_hash; /* Rx hash register */ + uint32_t res8[14]; /* reserved */ + uint32_t x_cntrl; /* Tx control register */ + uint32_t res9[0x1e]; /* reserved */ +}; + +#define DUMP_REG(f, x) fprintf(stdout, \ + "0x%04lx: %-16s 0x%08x\n", \ + (unsigned long)(offsetof(struct fec, x)), \ + #x, f->x) + +int fec_8xx_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + struct fec *f = (struct fec *)regs->data; + + fprintf(stdout, "Descriptor Registers\n"); + fprintf(stdout, "---------------------\n"); + + DUMP_REG(f, addr_low); + DUMP_REG(f, addr_high); + DUMP_REG(f, hash_table_high); + DUMP_REG(f, hash_table_low); + DUMP_REG(f, r_des_start); + DUMP_REG(f, x_des_start); + DUMP_REG(f, r_buff_size); + DUMP_REG(f, ecntrl); + DUMP_REG(f, ievent); + DUMP_REG(f, imask); + DUMP_REG(f, ivec); + DUMP_REG(f, r_des_active); + DUMP_REG(f, x_des_active); + DUMP_REG(f, mii_data); + DUMP_REG(f, mii_speed); + DUMP_REG(f, r_bound); + DUMP_REG(f, r_fstart); + DUMP_REG(f, x_fstart); + DUMP_REG(f, fun_code); + DUMP_REG(f, r_cntrl); + DUMP_REG(f, r_hash); + DUMP_REG(f, x_cntrl); + + return 0; +}
diff --git a/ethtool-2.6.35/ibm_emac.c b/ethtool-2.6.35/ibm_emac.c new file mode 100644 index 0000000..7974836 --- /dev/null +++ b/ethtool-2.6.35/ibm_emac.c
@@ -0,0 +1,244 @@ +/* + * Copyright (c) 2004, 2005 Zultys Technologies + * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> + */ +#include <stdio.h> +#include <stdint.h> +#include <stddef.h> + +#include "ethtool-util.h" + +/* Ethtool get_regs complex data. + * we want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH + * when available. + * + * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, + * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. + * Each register component is preceded with emac_ethtool_regs_subhdr. + * Order of the optional headers follows their relative bit posititions + * in emac_ethtool_regs_hdr.components + */ +#define EMAC_ETHTOOL_REGS_ZMII 0x00000001 +#define EMAC_ETHTOOL_REGS_RGMII 0x00000002 +#define EMAC_ETHTOOL_REGS_TAH 0x00000004 + +struct emac_ethtool_regs_hdr { + u32 components; +}; + +struct emac_ethtool_regs_subhdr { + u32 version; + u32 index; +}; + +struct emac_regs { + u32 mr0; + u32 mr1; + u32 tmr0; + u32 tmr1; + u32 rmr; + u32 isr; + u32 iser; + u32 iahr; + u32 ialr; + u32 vtpid; + u32 vtci; + u32 ptr; + u32 iaht1; + u32 iaht2; + u32 iaht3; + u32 iaht4; + u32 gaht1; + u32 gaht2; + u32 gaht3; + u32 gaht4; + u32 lsah; + u32 lsal; + u32 ipgvr; + u32 stacr; + u32 trtr; + u32 rwmr; + u32 octx; + u32 ocrx; + u32 ipcr; +}; + +struct mal_regs { + u32 tx_count; + u32 rx_count; + + u32 cfg; + u32 esr; + u32 ier; + u32 tx_casr; + u32 tx_carr; + u32 tx_eobisr; + u32 tx_deir; + u32 rx_casr; + u32 rx_carr; + u32 rx_eobisr; + u32 rx_deir; + u32 tx_ctpr[32]; + u32 rx_ctpr[32]; + u32 rcbs[32]; +}; + +struct zmii_regs { + u32 fer; + u32 ssr; + u32 smiisr; +}; + +struct rgmii_regs { + u32 fer; + u32 ssr; +}; + +struct tah_regs { + u32 revid; + u32 pad[3]; + u32 mr; + u32 ssr0; + u32 ssr1; + u32 ssr2; + u32 ssr3; + u32 ssr4; + u32 ssr5; + u32 tsr; +}; + +static void *print_emac_regs(void *buf) +{ + struct emac_ethtool_regs_subhdr *hdr = buf; + struct emac_regs *p = (struct emac_regs *)(hdr + 1); + void *res = p + 1; + + printf("EMAC%d Registers\n", hdr->index); + printf("-----------------\n"); + printf("MR0 = 0x%08x MR1 = 0x%08x RMR = 0x%08x\n" + "ISR = 0x%08x ISER = 0x%08x\n" + "TMR0 = 0x%08x TMR1 = 0x%08x\n" + "TRTR = 0x%08x RWMR = 0x%08x\n" + "IAR = %04x%08x\n" + "LSA = %04x%08x\n" + "IAHT = 0x%04x 0x%04x 0x%04x 0x%04x\n" + "GAHT = 0x%04x 0x%04x 0x%04x 0x%04x\n" + "VTPID = 0x%04x VTCI = 0x%04x\n" + "IPGVR = 0x%04x STACR = 0x%08x\n" + "OCTX = 0x%08x OCRX = 0x%08x\n", + p->mr0, p->mr1, p->rmr, + p->isr, p->iser, + p->tmr0, p->tmr1, + p->trtr, p->rwmr, + p->iahr, p->ialr, + p->lsah, p->lsal, + p->iaht1, p->iaht2, p->iaht3, p->iaht4, + p->gaht1, p->gaht2, p->gaht3, p->gaht4, + p->vtpid, p->vtci, p->ipgvr, p->stacr, p->octx, p->ocrx); + + if (hdr->version) + printf(" IPCR = 0x%08x\n\n", p->ipcr); + else { + printf("\n\n"); + res -= sizeof(u32); + } + return res; +} + +static void *print_mal_regs(void *buf) +{ + struct emac_ethtool_regs_subhdr *hdr = buf; + struct mal_regs *p = (struct mal_regs *)(hdr + 1); + int i; + + printf("MAL%d Registers\n", hdr->index); + printf("-----------------\n"); + printf("CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n" + "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n" + "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n", + p->cfg, p->esr, p->ier, + p->tx_casr, p->tx_carr, p->tx_eobisr, p->tx_deir, + p->rx_casr, p->rx_carr, p->rx_eobisr, p->rx_deir); + + printf("TX|"); + for (i = 0; i < p->tx_count; ++i) { + if (i && !(i % 4)) + printf("\n "); + printf("CTP%d = 0x%08x ", i, p->tx_ctpr[i]); + } + printf("\nRX|"); + for (i = 0; i < p->rx_count; ++i) { + if (i && !(i % 4)) + printf("\n "); + printf("CTP%d = 0x%08x ", i, p->rx_ctpr[i]); + } + printf("\n "); + for (i = 0; i < p->rx_count; ++i) { + u32 r = p->rcbs[i]; + if (i && !(i % 3)) + printf("\n "); + printf("RCBS%d = 0x%08x (%d) ", i, r, r * 16); + } + printf("\n\n"); + return p + 1; +} + +static void *print_zmii_regs(void *buf) +{ + struct emac_ethtool_regs_subhdr *hdr = buf; + struct zmii_regs *p = (struct zmii_regs *)(hdr + 1); + + printf("ZMII%d Registers\n", hdr->index); + printf("-----------------\n"); + printf("FER = %08x SSR = %08x\n" + "SMIISR = %08x\n\n", p->fer, p->ssr, p->smiisr); + + return p + 1; +} + +static void *print_rgmii_regs(void *buf) +{ + struct emac_ethtool_regs_subhdr *hdr = buf; + struct rgmii_regs *p = (struct rgmii_regs *)(hdr + 1); + + printf("RGMII%d Registers\n", hdr->index); + printf("-----------------\n"); + printf("FER = %08x SSR = %08x\n\n", p->fer, p->ssr); + + return p + 1; +} + +static void *print_tah_regs(void *buf) +{ + struct emac_ethtool_regs_subhdr *hdr = buf; + struct tah_regs *p = (struct tah_regs *)(hdr + 1); + + printf("TAH%d Registers\n", hdr->index); + printf("-----------------\n"); + + printf("REVID = %08x MR = %08x TSR = %08x\n" + "SSR0 = %08x SSR1 = %08x SSR2 = %08x\n" + "SSR3 = %08x SSR4 = %08x SSR5 = %08x\n\n", + p->revid, p->mr, p->tsr, + p->ssr0, p->ssr1, p->ssr2, p->ssr3, p->ssr4, p->ssr5); + + return p + 1; +} + +int ibm_emac_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + struct emac_ethtool_regs_hdr *hdr = + (struct emac_ethtool_regs_hdr *)regs->data; + void *buf = hdr + 1; + + buf = print_mal_regs(buf); + buf = print_emac_regs(buf); + if (hdr->components & EMAC_ETHTOOL_REGS_ZMII) + buf = print_zmii_regs(buf); + if (hdr->components & EMAC_ETHTOOL_REGS_RGMII) + buf = print_rgmii_regs(buf); + if (hdr->components & EMAC_ETHTOOL_REGS_TAH) + print_tah_regs(buf); + + return 0; +}
diff --git a/ethtool-2.6.35/igb.c b/ethtool-2.6.35/igb.c new file mode 100644 index 0000000..4b836d9 --- /dev/null +++ b/ethtool-2.6.35/igb.c
@@ -0,0 +1,864 @@ +/* Copyright (c) 2007 Intel Corporation */ +#include <stdio.h> +#include "ethtool-util.h" + +/* Register Bit Masks */ +/* Device Control */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +#define E1000_CTRL_GIOMASTERD 0x00000008 /* GIO Master Disable*/ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_SDP0_GPIEN 0x00010000 /* General Purpose Interrupt Detection Enable for SDP0 */ +#define E1000_CTRL_SDP1_GPIEN 0x00020000 /* General Purpose Interrupt Detection Enable for SDP1 */ +#define E1000_CTRL_SDP0_DATA 0x00040000 /* SDP0 Data */ +#define E1000_CTRL_SDP1_DATA 0x00080000 /* SDP1 Data */ +#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3Cold WakeUp Capability Advertisement Enable */ +#define E1000_CTRL_SDP0_WDE 0x00200000 /* Watchdog Indication for SDP0 */ +#define E1000_CTRL_SDP1_IODIR 0x00400000 /* SDP1 Directionality */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +/* Device Status */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_LANID 0x00000008 /* LAN ID */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_SPEED_MASK 0x000000C0 /* Speed Mask */ +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ +#define E1000_STATUS_GIOMASTEREN 0x00080000 /* GIO Master Enable Status */ +#define E1000_STATUS_DMA_CGEN 0x80000000 /* DMA clock gating Enable */ + +/* Receive Control */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_MASK 0x000000C0 /* Loopback mode mask */ +#define E1000_RCTL_LBM_NORM 0x00000000 /* normal loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SERDES 0x000000C0 /* SERDES loopback mode */ +#define E1000_RCTL_RDMTS 0x00000300 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO 0x00003000 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 47:36 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 46:35 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 45:34 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 43:32 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +#define E1000_RCTL_BSIZE 0x00030000 /* rx buffer size */ +#define E1000_RCTL_BSIZE_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_BSIZE_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_BSIZE_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_BSIZE_256 0x00030000 /* rx buffer size 256 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC from packet.0=No strip;1=strip */ + +/* Transmit Control */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_BST 0x003ff000 /* Backoff Slot time */ +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ + +int +igb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *regs_buff = (u32 *)regs->data; + u32 reg; + u8 i; + u8 version = (u8)(regs->version >> 24); + + if (version != 1) + return -1; + + /* Device control register */ + reg = regs_buff[0]; + fprintf(stdout, + "0x00000: CTRL (Device control register) 0x%08X\n" + " Invert Loss-Of-Signal: %s\n" + " Receive flow control: %s\n" + " Transmit flow control: %s\n" + " VLAN mode: %s\n" + " Set link up: %s\n" + " D3COLD WakeUp capability advertisement: %s\n", + reg, + reg & E1000_CTRL_ILOS ? "yes" : "no", + reg & E1000_CTRL_RFCE ? "enabled" : "disabled", + reg & E1000_CTRL_TFCE ? "enabled" : "disabled", + reg & E1000_CTRL_VME ? "enabled" : "disabled", + reg & E1000_CTRL_SLU ? "1" : "0", + reg & E1000_CTRL_ADVD3WUC ? "enabled" : "disabled"); + fprintf(stdout, + " Auto speed detect: %s\n" + " Speed select: %s\n" + " Force speed: %s\n" + " Force duplex: %s\n", + reg & E1000_CTRL_ASDE ? "enabled" : "disabled", + (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_10 ? "10Mb/s" : + (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_100 ? "100Mb/s" : + (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_1000 ? "1000Mb/s" : + "not used", + reg & E1000_CTRL_FRCSPD ? "yes" : "no", + reg & E1000_CTRL_FRCDPX ? "yes" : "no"); + + /* Device status register */ + reg = regs_buff[1]; + fprintf(stdout, + "0x00008: STATUS (Device status register) 0x%08X\n" + " Duplex: %s\n" + " Link up: %s\n" + " Transmission: %s\n" + " DMA clock gating: %s\n", + reg, + reg & E1000_STATUS_FD ? "full" : "half", + reg & E1000_STATUS_LU ? "link config" : "no link config", + reg & E1000_STATUS_TXOFF ? "paused" : "on", + reg & E1000_STATUS_DMA_CGEN ? "enabled" : "disabled"); + fprintf(stdout, + " TBI mode: %s\n" + " Link speed: %s\n" + " Bus type: %s\n", + reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled", + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ? + "10Mb/s" : + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ? + "100Mb/s" : + (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ? + "1000Mb/s" : "not used", + "PCI Express"); + + /* Receive control register */ + reg = regs_buff[32]; + fprintf(stdout, + "0x00100: RCTL (Receive control register) 0x%08X\n" + " Receiver: %s\n" + " Store bad packets: %s\n" + " Unicast promiscuous: %s\n" + " Multicast promiscuous: %s\n" + " Long packet: %s\n" + " Descriptor minimum threshold size: %s\n" + " Broadcast accept mode: %s\n" + " VLAN filter: %s\n" + " Cononical form indicator: %s\n" + " Discard pause frames: %s\n" + " Pass MAC control frames: %s\n" + " Loopback mode: %s\n", + reg, + reg & E1000_RCTL_EN ? "enabled" : "disabled", + reg & E1000_RCTL_SBP ? "enabled" : "disabled", + reg & E1000_RCTL_UPE ? "enabled" : "disabled", + reg & E1000_RCTL_MPE ? "enabled" : "disabled", + reg & E1000_RCTL_LPE ? "enabled" : "disabled", + (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_HALF ? "1/2" : + (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_QUAT ? "1/4" : + (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_EIGTH ? "1/8" : + "reserved", + reg & E1000_RCTL_BAM ? "accept" : "ignore", + reg & E1000_RCTL_VFE ? "enabled" : "disabled", + reg & E1000_RCTL_CFIEN ? "enabled" : "disabled", + reg & E1000_RCTL_DPF ? "ignored" : "filtered", + reg & E1000_RCTL_PMCF ? "pass" : "don't pass", + (reg & E1000_RCTL_LBM_MASK) == E1000_RCTL_LBM_NORM ? "normal" : + (reg & E1000_RCTL_LBM_MASK) == E1000_RCTL_LBM_MAC ? "MAC": + (reg & E1000_RCTL_LBM_MASK) == E1000_RCTL_LBM_SERDES ? "SERDES": + "undefined"); + fprintf(stdout, + " Receive buffer size: %s\n", + (reg & E1000_RCTL_BSIZE)==E1000_RCTL_BSIZE_2048 ? "2048" : + (reg & E1000_RCTL_BSIZE)==E1000_RCTL_BSIZE_1024 ? "1024" : + (reg & E1000_RCTL_BSIZE)==E1000_RCTL_BSIZE_512 ? "512" : + "256"); + + /* Receive descriptor registers */ + fprintf(stdout, + "0x02808: RDLEN (Receive desc length) 0x%08X\n", + regs_buff[142]); + fprintf(stdout, + "0x02810: RDH (Receive desc head) 0x%08X\n", + regs_buff[146]); + fprintf(stdout, + "0x02818: RDT (Receive desc tail) 0x%08X\n", + regs_buff[150]); + + /* Transmit control register */ + reg = regs_buff[38]; + fprintf(stdout, + "0x00400: TCTL (Transmit ctrl register) 0x%08X\n" + " Transmitter: %s\n" + " Pad short packets: %s\n" + " Software XOFF Transmission: %s\n", + reg, + reg & E1000_TCTL_EN ? "enabled" : "disabled", + reg & E1000_TCTL_PSP ? "enabled" : "disabled", + reg & E1000_TCTL_SWXOFF ? "enabled" : "disabled"); + fprintf(stdout, + " Re-transmit on late collision: %s\n", + reg & E1000_TCTL_RTLC ? "enabled" : "disabled"); + + /* Transmit descriptor registers */ + fprintf(stdout, + "0x03808: TDLEN (Transmit desc length) 0x%08X\n", + regs_buff[214]); + fprintf(stdout, + "0x03810: TDH (Transmit desc head) 0x%08X\n", + regs_buff[218]); + fprintf(stdout, + "0x03818: TDT (Transmit desc tail) 0x%08X\n", + regs_buff[222]); + + + fprintf(stdout, + "0x00018: CTRL_EXT (Extended device control) 0x%08X\n", + regs_buff[2]); + + fprintf(stdout, + "0x00018: MDIC (MDI control) 0x%08X\n", + regs_buff[3]); + + fprintf(stdout, + "0x00024: SCTL (SERDES ANA) 0x%08X\n", + regs_buff[4]); + + fprintf(stdout, + "0x00034: CONNSW (Copper/Fiber switch control) 0x%08X\n", + regs_buff[5]); + + fprintf(stdout, + "0x00038: VET (VLAN Ether type) 0x%08X\n", + regs_buff[6]); + + fprintf(stdout, + "0x00E00: LEDCTL (LED control) 0x%08X\n", + regs_buff[7]); + + fprintf(stdout, + "0x01000: PBA (Packet buffer allocation) 0x%08X\n", + regs_buff[8]); + + fprintf(stdout, + "0x01008: PBS (Packet buffer size) 0x%08X\n", + regs_buff[9]); + + fprintf(stdout, + "0x01048: FRTIMER (Free running timer) 0x%08X\n", + regs_buff[10]); + + fprintf(stdout, + "0x0104C: TCPTIMER (TCP timer) 0x%08X\n", + regs_buff[11]); + + fprintf(stdout, + "0x00010: EEC (EEPROM/FLASH control) 0x%08X\n", + regs_buff[12]); + + fprintf(stdout, + "0x01580: EICR (Extended interrupt cause) 0x%08X\n", + regs_buff[13]); + + fprintf(stdout, + "0x01520: EICS (Extended interrupt cause set) 0x%08X\n", + regs_buff[14]); + + fprintf(stdout, + "0x01524: EIMS (Extended interrup set/read) 0x%08X\n", + regs_buff[15]); + + fprintf(stdout, + "0x01528: EIMC (Extended interrupt mask clear) 0x%08X\n", + regs_buff[16]); + + fprintf(stdout, + "0x0152C: EIAC (Extended interrupt auto clear) 0x%08X\n", + regs_buff[17]); + + fprintf(stdout, + "0x01530: EIAM (Extended interrupt auto mask) 0x%08X\n", + regs_buff[18]); + + fprintf(stdout, + "0x01500: ICR (Interrupt cause read) 0x%08X\n", + regs_buff[19]); + + fprintf(stdout, + "0x01504: ICS (Interrupt cause set) 0x%08X\n", + regs_buff[20]); + + fprintf(stdout, + "0x01508: IMS (Interrupt mask set/read) 0x%08X\n", + regs_buff[21]); + + fprintf(stdout, + "0x0150C: IMC (Interrupt mask clear) 0x%08X\n", + regs_buff[22]); + + fprintf(stdout, + "0x04100: IAC (Interrupt assertion count) 0x%08X\n", + regs_buff[23]); + + fprintf(stdout, + "0x01510: IAM (Interr acknowledge auto-mask) 0x%08X\n", + regs_buff[24]); + + fprintf(stdout, + "0x05AC0: IMIRVP (Immed interr rx VLAN priority) 0x%08X\n", + regs_buff[25]); + + fprintf(stdout, + "0x00028: FCAL (Flow control address low) 0x%08X\n", + regs_buff[26]); + + fprintf(stdout, + "0x0002C: FCAH (Flow control address high) 0x%08X\n", + regs_buff[27]); + + fprintf(stdout, + "0x00170: FCTTV (Flow control tx timer value) 0x%08X\n", + regs_buff[28]); + + fprintf(stdout, + "0x02160: FCRTL (Flow control rx threshold low) 0x%08X\n", + regs_buff[29]); + + fprintf(stdout, + "0x02168: FCRTH (Flow control rx threshold high) 0x%08X\n", + regs_buff[30]); + + fprintf(stdout, + "0x02460: FCRTV (Flow control refresh threshold) 0x%08X\n", + regs_buff[31]); + + fprintf(stdout, + "0x05000: RXCSUM (Receive checksum control) 0x%08X\n", + regs_buff[33]); + + fprintf(stdout, + "0x05004: RLPML (Receive long packet max length) 0x%08X\n", + regs_buff[34]); + + fprintf(stdout, + "0x05008: RFCTL (Receive filter control) 0x%08X\n", + regs_buff[35]); + + fprintf(stdout, + "0x05818: MRQC (Multiple rx queues command) 0x%08X\n", + regs_buff[36]); + + fprintf(stdout, + "0x0581C: VMD_CTL (VMDq control) 0x%08X\n", + regs_buff[37]); + + fprintf(stdout, + "0x00404: TCTL_EXT (Transmit control extended) 0x%08X\n", + regs_buff[39]); + + fprintf(stdout, + "0x00410: TIPG (Transmit IPG) 0x%08X\n", + regs_buff[40]); + + fprintf(stdout, + "0x03590: DTXCTL (DMA tx control) 0x%08X\n", + regs_buff[41]); + + fprintf(stdout, + "0x05800: WUC (Wake up control) 0x%08X\n", + regs_buff[42]); + + fprintf(stdout, + "0x05808: WUFC (Wake up filter control) 0x%08X\n", + regs_buff[43]); + + fprintf(stdout, + "0x05810: WUS (Wake up status) 0x%08X\n", + regs_buff[44]); + + fprintf(stdout, + "0x05838: IPAV (IP address valid) 0x%08X\n", + regs_buff[45]); + + fprintf(stdout, + "0x05900: WUPL (Wake up packet length) 0x%08X\n", + regs_buff[46]); + + fprintf(stdout, + "0x04200: PCS_CFG (PCS configuration 0) 0x%08X\n", + regs_buff[47]); + + fprintf(stdout, + "0x04208: PCS_LCTL (PCS link control) 0x%08X\n", + regs_buff[48]); + + fprintf(stdout, + "0x0420C: PCS_LSTS (PCS link status) 0x%08X\n", + regs_buff[49]); + + fprintf(stdout, + "0x04218: PCS_ANADV (AN advertisement) 0x%08X\n", + regs_buff[50]); + + fprintf(stdout, + "0x0421C: PCS_LPAB (Link partner ability) 0x%08X\n", + regs_buff[51]); + + fprintf(stdout, + "0x04220: PCS_NPTX (Next Page transmit) 0x%08X\n", + regs_buff[52]); + + fprintf(stdout, + "0x04224: PCS_LPABNP (Link partner ability Next Page) 0x%08X\n", + regs_buff[53]); + + fprintf(stdout, + "0x04000: CRCERRS (CRC error count) 0x%08X\n", + regs_buff[54]); + + fprintf(stdout, + "0x04004: ALGNERRC (Alignment error count) 0x%08X\n", + regs_buff[55]); + + fprintf(stdout, + "0x04008: SYMERRS (Symbol error count) 0x%08X\n", + regs_buff[56]); + + fprintf(stdout, + "0x0400C: RXERRC (RX error count) 0x%08X\n", + regs_buff[57]); + + fprintf(stdout, + "0x04010: MPC (Missed packets count) 0x%08X\n", + regs_buff[58]); + + fprintf(stdout, + "0x04014: SCC (Single collision count) 0x%08X\n", + regs_buff[59]); + + fprintf(stdout, + "0x04018: ECOL (Excessive collisions count) 0x%08X\n", + regs_buff[60]); + + fprintf(stdout, + "0x0401C: MCC (Multiple collision count) 0x%08X\n", + regs_buff[61]); + + fprintf(stdout, + "0x04020: LATECOL (Late collisions count) 0x%08X\n", + regs_buff[62]); + + fprintf(stdout, + "0x04028: COLC (Collision count) 0x%08X\n", + regs_buff[63]); + + fprintf(stdout, + "0x04030: DC (Defer count) 0x%08X\n", + regs_buff[64]); + + fprintf(stdout, + "0x04034: TNCRS (Transmit with no CRS) 0x%08X\n", + regs_buff[65]); + + fprintf(stdout, + "0x04038: SEC (Sequence error count) 0x%08X\n", + regs_buff[66]); + + fprintf(stdout, + "0x0403C: HTDPMC (Host tx discrd pkts MAC count) 0x%08X\n", + regs_buff[67]); + + fprintf(stdout, + "0x04040: RLEC (Receive length error count) 0x%08X\n", + regs_buff[68]); + + fprintf(stdout, + "0x04048: XONRXC (XON received count) 0x%08X\n", + regs_buff[69]); + + fprintf(stdout, + "0x0404C: XONTXC (XON transmitted count) 0x%08X\n", + regs_buff[70]); + + fprintf(stdout, + "0x04050: XOFFRXC (XOFF received count) 0x%08X\n", + regs_buff[71]); + + fprintf(stdout, + "0x04054: XOFFTXC (XOFF transmitted count) 0x%08X\n", + regs_buff[72]); + + fprintf(stdout, + "0x04058: FCRUC (FC received unsupported count) 0x%08X\n", + regs_buff[73]); + + fprintf(stdout, + "0x0405C: PRC64 (Packets rx (64 B) count) 0x%08X\n", + regs_buff[74]); + + fprintf(stdout, + "0x04060: PRC127 (Packets rx (65-127 B) count) 0x%08X\n", + regs_buff[75]); + + fprintf(stdout, + "0x04064: PRC255 (Packets rx (128-255 B) count) 0x%08X\n", + regs_buff[76]); + + fprintf(stdout, + "0x04068: PRC511 (Packets rx (256-511 B) count) 0x%08X\n", + regs_buff[77]); + + fprintf(stdout, + "0x0406C: PRC1023 (Packets rx (512-1023 B) count) 0x%08X\n", + regs_buff[78]); + + fprintf(stdout, + "0x04070: PRC1522 (Packets rx (1024-max B) count) 0x%08X\n", + regs_buff[79]); + + fprintf(stdout, + "0x04074: GPRC (Good packets received count) 0x%08X\n", + regs_buff[80]); + + fprintf(stdout, + "0x04078: BPRC (Broadcast packets rx count) 0x%08X\n", + regs_buff[81]); + + fprintf(stdout, + "0x0407C: MPRC (Multicast packets rx count) 0x%08X\n", + regs_buff[82]); + + fprintf(stdout, + "0x04080: GPTC (Good packets tx count) 0x%08X\n", + regs_buff[83]); + + fprintf(stdout, + "0x04088: GORCL (Good octets rx count lower) 0x%08X\n", + regs_buff[84]); + + fprintf(stdout, + "0x0408C: GORCH (Good octets rx count upper) 0x%08X\n", + regs_buff[85]); + + fprintf(stdout, + "0x04090: GOTCL (Good octets tx count lower) 0x%08X\n", + regs_buff[86]); + + fprintf(stdout, + "0x04094: GOTCH (Good octets tx count upper) 0x%08X\n", + regs_buff[87]); + + fprintf(stdout, + "0x040A0: RNBC (Receive no buffers count) 0x%08X\n", + regs_buff[88]); + + fprintf(stdout, + "0x040A4: RUC (Receive undersize count) 0x%08X\n", + regs_buff[89]); + + fprintf(stdout, + "0x040A8: RFC (Receive fragment count) 0x%08X\n", + regs_buff[90]); + + fprintf(stdout, + "0x040AC: ROC (Receive oversize count) 0x%08X\n", + regs_buff[91]); + + fprintf(stdout, + "0x040B0: RJC (Receive jabber count) 0x%08X\n", + regs_buff[92]); + + fprintf(stdout, + "0x040B4: MGPRC (Management packets rx count) 0x%08X\n", + regs_buff[93]); + + fprintf(stdout, + "0x040B8: MGPDC (Management pkts dropped count) 0x%08X\n", + regs_buff[94]); + + fprintf(stdout, + "0x040BC: MGPTC (Management packets tx count) 0x%08X\n", + regs_buff[95]); + + fprintf(stdout, + "0x040C0: TORL (Total octets received lower) 0x%08X\n", + regs_buff[96]); + + fprintf(stdout, + "0x040C4: TORH (Total octets received upper) 0x%08X\n", + regs_buff[97]); + + fprintf(stdout, + "0x040C8: TOTL (Total octets transmitted lower) 0x%08X\n", + regs_buff[98]); + + fprintf(stdout, + "0x040CC: TOTH (Total octets transmitted upper) 0x%08X\n", + regs_buff[99]); + + fprintf(stdout, + "0x040D0: TPR (Total packets received) 0x%08X\n", + regs_buff[100]); + + fprintf(stdout, + "0x040D4: TPT (Total packets transmitted) 0x%08X\n", + regs_buff[101]); + + fprintf(stdout, + "0x040D8: PTC64 (Packets tx (64 B) count) 0x%08X\n", + regs_buff[102]); + + fprintf(stdout, + "0x040DC: PTC127 (Packets tx (65-127 B) count) 0x%08X\n", + regs_buff[103]); + + fprintf(stdout, + "0x040E0: PTC255 (Packets tx (128-255 B) count) 0x%08X\n", + regs_buff[104]); + + fprintf(stdout, + "0x040E4: PTC511 (Packets tx (256-511 B) count) 0x%08X\n", + regs_buff[105]); + + fprintf(stdout, + "0x040E8: PTC1023 (Packets tx (512-1023 B) count) 0x%08X\n", + regs_buff[106]); + + fprintf(stdout, + "0x040EC: PTC1522 (Packets tx (> 1024 B) count) 0x%08X\n", + regs_buff[107]); + + fprintf(stdout, + "0x040F0: MPTC (Multicast packets tx count) 0x%08X\n", + regs_buff[108]); + + fprintf(stdout, + "0x040F4: BPTC (Broadcast packets tx count) 0x%08X\n", + regs_buff[109]); + + fprintf(stdout, + "0x040F8: TSCTC (TCP segment context tx count) 0x%08X\n", + regs_buff[110]); + + fprintf(stdout, + "0x04100: IAC (Interrupt assertion count) 0x%08X\n", + regs_buff[111]); + + fprintf(stdout, + "0x04104: RPTHC (Rx packets to host count) 0x%08X\n", + regs_buff[112]); + + fprintf(stdout, + "0x04118: HGPTC (Host good packets tx count) 0x%08X\n", + regs_buff[113]); + + fprintf(stdout, + "0x04128: HGORCL (Host good octets rx cnt lower) 0x%08X\n", + regs_buff[114]); + + fprintf(stdout, + "0x0412C: HGORCH (Host good octets rx cnt upper) 0x%08X\n", + regs_buff[115]); + + fprintf(stdout, + "0x04130: HGOTCL (Host good octets tx cnt lower) 0x%08X\n", + regs_buff[116]); + + fprintf(stdout, + "0x04134: HGOTCH (Host good octets tx cnt upper) 0x%08X\n", + regs_buff[117]); + + fprintf(stdout, + "0x04138: LENNERS (Length error count) 0x%08X\n", + regs_buff[118]); + + fprintf(stdout, + "0x04228: SCVPC (SerDes/SGMII code viol pkt cnt) 0x%08X\n", + regs_buff[119]); + + fprintf(stdout, + "0x0A018: HRMPC (Header redir missed pkt count) 0x%08X\n", + regs_buff[120]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: SRRCTL%d (Split and replic rx ctl%d) 0x%08X\n", + 0x0280C + (0x100 * i), i, i, regs_buff[121 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: PSRTYPE%d (Packet split receive type%d) 0x%08X\n", + 0x05480 + (0x4 * i), i, i, regs_buff[125 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: RDBAL%d (Rx desc base addr low%d) 0x%08X\n", + 0x02800 + (0x100 * i), i, i, regs_buff[129 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: RDBAH%d (Rx desc base addr high%d) 0x%08X\n", + 0x02804 + (0x100 * i), i, i, regs_buff[133 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: RDLEN%d (Rx descriptor length%d) 0x%08X\n", + 0x02808 + (0x100 * i), i, i, regs_buff[137 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: RDH%d (Rx descriptor head%d) 0x%08X\n", + 0x02810 + (0x100 * i), i, i, regs_buff[141 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: RDT%d (Rx descriptor tail%d) 0x%08X\n", + 0x02818 + (0x100 * i), i, i, regs_buff[145 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: RXDCTL%d (Rx descriptor control%d) 0x%08X\n", + 0x02828 + (0x100 * i), i, i, regs_buff[149 + i]); + + for (i = 0; i < 10; i++) + fprintf(stdout, + "0x0%02X: EITR%d (Interrupt throttle%d) 0x%08X\n", + 0x01680 + (0x4 * i), i, i, regs_buff[153 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x0%02X: IMIR%d (Immediate interrupt Rx%d) 0x%08X\n", + 0x05A80 + (0x4 * i), i, i, regs_buff[163 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x0%02X: IMIREXT%d (Immediate interr Rx extended%d) 0x%08X\n", + 0x05AA0 + (0x4 * i), i, i, regs_buff[171 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x0%02X: RAL%02d (Receive address low%02d) 0x%08X\n", + 0x05400 + (0x8 * i), i,i, regs_buff[179 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x0%02X: RAH%02d (Receive address high%02d) 0x%08X\n", + 0x05404 + (0x8 * i), i, i, regs_buff[195 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDBAL%d (Tx desc base address low%d) 0x%08X\n", + 0x03800 + (0x100 * i), i, i, regs_buff[211 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDBAH%d (Tx desc base address high%d) 0x%08X\n", + 0x03804 + (0x100 * i), i, i, regs_buff[215 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDLEN%d (Tx descriptor length%d) 0x%08X\n", + 0x03808 + (0x100 * i), i, i, regs_buff[219 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDH%d (Transmit descriptor head%d) 0x%08X\n", + 0x03810 + (0x100 * i), i, i, regs_buff[223 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDT%d (Transmit descriptor tail%d) 0x%08X\n", + 0x03818 + (0x100 * i), i, i, regs_buff[227 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TXDCTL%d (Transmit descriptor control%d) 0x%08X\n", + 0x03828 + (0x100 * i), i, i, regs_buff[231 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDWBAL%d (Tx desc complete wb addr low%d) 0x%08X\n", + 0x03838 + (0x100 * i), i, i, regs_buff[235 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: TDWBAH%d (Tx desc complete wb addr hi%d) 0x%08X\n", + 0x0383C + (0x100 * i), i, i, regs_buff[239 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: DCA_TXCTRL%d (Tx DCA control%d) 0x%08X\n", + 0x03814 + (0x100 * i), i, i, regs_buff[243 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: IP4AT%d (IPv4 address table%d) 0x%08X\n", + 0x05840 + (0x8 * i), i, i, regs_buff[247 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: IP6AT%d (IPv6 address table%d) 0x%08X\n", + 0x05880 + (0x4 * i), i, i, regs_buff[251 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x0%02X: WUPM%02d (Wake up packet memory%02d) 0x%08X\n", + 0x05A00 + (0x4 * i), i, i, regs_buff[255 + i]); + + for (i = 0; i < 128; i++) + fprintf(stdout, + "0x0%02X: FFMT%03d (Flexible filter mask table%03d) 0x%08X\n", + 0x09000 + (0x8 * i), i, i, regs_buff[287 + i]); + + for (i = 0; i < 128; i++) + fprintf(stdout, + "0x0%02X: FFVT%03d (Flexible filter value table%03d) 0x%08X\n", + 0x09800 + (0x8 * i), i, i, regs_buff[415 + i]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x0%02X: FFLT%d (Flexible filter length table%d) 0x%08X\n", + 0x05F00 + (0x8 * i), i, i, regs_buff[543 + i]); + + fprintf(stdout, + "0x03410: TDFH (Tx data FIFO head) 0x%08X\n", + regs_buff[547]); + + fprintf(stdout, + "0x03418: TDFT (Tx data FIFO tail) 0x%08X\n", + regs_buff[548]); + + fprintf(stdout, + "0x03420: TDFHS (Tx data FIFO head saved) 0x%08X\n", + regs_buff[549]); + + fprintf(stdout, + "0x03430: TDFPC (Tx data FIFO packet count) 0x%08X\n", + regs_buff[550]); + + return 0; +} +
diff --git a/ethtool-2.6.35/install-sh b/ethtool-2.6.35/install-sh new file mode 100755 index 0000000..a5897de --- /dev/null +++ b/ethtool-2.6.35/install-sh
@@ -0,0 +1,519 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2006-12-25.00 + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# `make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +nl=' +' +IFS=" "" $nl" + +# set DOITPROG to echo to test this script + +# Don't use :- since 4.3BSD and earlier shells don't like it. +doit=${DOITPROG-} +if test -z "$doit"; then + doit_exec=exec +else + doit_exec=$doit +fi + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_glob='?' +initialize_posix_glob=' + test "$posix_glob" != "?" || { + if (set -f) 2>/dev/null; then + posix_glob= + else + posix_glob=: + fi + } +' + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +no_target_directory= + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve the last data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -s $stripprog installed files. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *' '* | *' +'* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -s) stripcmd=$stripprog;; + + -t) dst_arg=$2 + shift;; + + -T) no_target_directory=true;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call `install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + trap '(exit $?); exit' 1 2 13 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names starting with `-'. + case $src in + -*) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + + dst=$dst_arg + # Protect names starting with `-'. + case $dst in + -*) dst=./$dst;; + esac + + # If destination is a directory, append the input filename; won't work + # if double slashes aren't ignored. + if test -d "$dst"; then + if test -n "$no_target_directory"; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dst=$dstdir/`basename "$src"` + dstdir_status=0 + else + # Prefer dirname, but fall back on a substitute if dirname fails. + dstdir=` + (dirname "$dst") 2>/dev/null || + expr X"$dst" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$dst" : 'X\(//\)[^/]' \| \ + X"$dst" : 'X\(//\)$' \| \ + X"$dst" : 'X\(/\)' \| . 2>/dev/null || + echo X"$dst" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q' + ` + + test -d "$dstdir" + dstdir_status=$? + fi + fi + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # Create intermediate dirs using mode 755 as modified by the umask. + # This is like FreeBSD 'install' as of 1997-10-28. + umask=`umask` + case $stripcmd.$umask in + # Optimize common cases. + *[2367][2367]) mkdir_umask=$umask;; + .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; + + *[0-7]) + mkdir_umask=`expr $umask + 22 \ + - $umask % 100 % 40 + $umask % 20 \ + - $umask % 10 % 4 + $umask % 2 + `;; + *) mkdir_umask=$umask,go-w;; + esac + + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + case $umask in + *[123567][0-7][0-7]) + # POSIX mkdir -p sets u+wx bits regardless of umask, which + # is incompatible with FreeBSD 'install' when (umask & 300) != 0. + ;; + *) + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + trap 'ret=$?; rmdir "$tmpdir/d" "$tmpdir" 2>/dev/null; exit $ret' 0 + + if (umask $mkdir_umask && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/d") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writeable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + ls_ld_tmpdir=`ls -ld "$tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/d" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- 2>/dev/null + fi + trap '' 0;; + esac;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # The umask is ridiculous, or mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + -*) prefix='./';; + *) prefix='';; + esac + + eval "$initialize_posix_glob" + + oIFS=$IFS + IFS=/ + $posix_glob set -f + set fnord $dstdir + shift + $posix_glob set +f + IFS=$oIFS + + prefixes= + + for d + do + test -z "$d" && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask=$mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=$dstdir/_inst.$$_ + rmtmp=$dstdir/_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + + eval "$initialize_posix_glob" && + $posix_glob set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + $posix_glob set +f && + + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd -f "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-end: "$" +# End:
diff --git a/ethtool-2.6.35/ixgb.c b/ethtool-2.6.35/ixgb.c new file mode 100644 index 0000000..00c90d3 --- /dev/null +++ b/ethtool-2.6.35/ixgb.c
@@ -0,0 +1,147 @@ +/* Copyright (c) 2006 Intel Corporation */ +#include <stdio.h> +#include "ethtool-util.h" + +/* CTRL0 Bit Masks */ +#define IXGB_CTRL0_LRST 0x00000008 +#define IXGB_CTRL0_VME 0x40000000 + +/* STATUS Bit Masks */ +#define IXGB_STATUS_LU 0x00000002 +#define IXGB_STATUS_BUS64 0x00001000 +#define IXGB_STATUS_PCIX_MODE 0x00002000 +#define IXGB_STATUS_PCIX_SPD_100 0x00004000 +#define IXGB_STATUS_PCIX_SPD_133 0x00008000 + +/* RCTL Bit Masks */ +#define IXGB_RCTL_RXEN 0x00000002 +#define IXGB_RCTL_SBP 0x00000004 +#define IXGB_RCTL_UPE 0x00000008 +#define IXGB_RCTL_MPE 0x00000010 +#define IXGB_RCTL_RDMTS_MASK 0x00000300 +#define IXGB_RCTL_RDMTS_1_2 0x00000000 +#define IXGB_RCTL_RDMTS_1_4 0x00000100 +#define IXGB_RCTL_RDMTS_1_8 0x00000200 +#define IXGB_RCTL_BAM 0x00008000 +#define IXGB_RCTL_BSIZE_MASK 0x00030000 +#define IXGB_RCTL_BSIZE_4096 0x00010000 +#define IXGB_RCTL_BSIZE_8192 0x00020000 +#define IXGB_RCTL_BSIZE_16384 0x00030000 +#define IXGB_RCTL_VFE 0x00040000 +#define IXGB_RCTL_CFIEN 0x00080000 + +/* TCTL Bit Masks */ +#define IXGB_TCTL_TXEN 0x00000002 + +/* RAH Bit Masks */ +#define IXGB_RAH_ASEL_DEST 0x00000000 +#define IXGB_RAH_ASEL_SRC 0x00010000 +#define IXGB_RAH_AV 0x80000000 + +int +ixgb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *regs_buff = (u32 *)regs->data; + u8 version = (u8)(regs->version >> 24); + u32 reg; + + if (version != 1) + return -1; + fprintf(stdout, "MAC Registers\n"); + fprintf(stdout, "-------------\n"); + + /* Device control register */ + reg = regs_buff[0]; + fprintf(stdout, + "0x00000: CTRL0 (Device control register) 0x%08X\n" + " Link reset: %s\n" + " VLAN mode: %s\n", + reg, + reg & IXGB_CTRL0_LRST ? "reset" : "normal", + reg & IXGB_CTRL0_VME ? "enabled" : "disabled"); + + /* Device status register */ + reg = regs_buff[2]; + fprintf(stdout, + "0x00010: STATUS (Device status register) 0x%08X\n" + " Link up: %s\n" + " Bus type: %s\n" + " Bus speed: %s\n" + " Bus width: %s\n", + reg, + (reg & IXGB_STATUS_LU) ? "link config" : "no link config", + (reg & IXGB_STATUS_PCIX_MODE) ? "PCI-X" : "PCI", + ((reg & IXGB_STATUS_PCIX_SPD_133) ? "133MHz" : + (reg & IXGB_STATUS_PCIX_SPD_100) ? "100MHz" : + "66MHz"), + (reg & IXGB_STATUS_BUS64) ? "64-bit" : "32-bit"); + /* Receive control register */ + reg = regs_buff[9]; + fprintf(stdout, + "0x00100: RCTL (Receive control register) 0x%08X\n" + " Receiver: %s\n" + " Store bad packets: %s\n" + " Unicast promiscuous: %s\n" + " Multicast promiscuous: %s\n" + " Descriptor minimum threshold size: %s\n" + " Broadcast accept mode: %s\n" + " VLAN filter: %s\n" + " Cononical form indicator: %s\n", + reg, + reg & IXGB_RCTL_RXEN ? "enabled" : "disabled", + reg & IXGB_RCTL_SBP ? "enabled" : "disabled", + reg & IXGB_RCTL_UPE ? "enabled" : "disabled", + reg & IXGB_RCTL_MPE ? "enabled" : "disabled", + (reg & IXGB_RCTL_RDMTS_MASK) == IXGB_RCTL_RDMTS_1_2 ? "1/2" : + (reg & IXGB_RCTL_RDMTS_MASK) == IXGB_RCTL_RDMTS_1_4 ? "1/4" : + (reg & IXGB_RCTL_RDMTS_MASK) == IXGB_RCTL_RDMTS_1_8 ? "1/8" : + "reserved", + reg & IXGB_RCTL_BAM ? "accept" : "ignore", + reg & IXGB_RCTL_VFE ? "enabled" : "disabled", + reg & IXGB_RCTL_CFIEN ? "enabled" : "disabled"); + fprintf(stdout, + " Receive buffer size: %s\n", + (reg & IXGB_RCTL_BSIZE_MASK) == IXGB_RCTL_BSIZE_16384 ? "16384" : + (reg & IXGB_RCTL_BSIZE_MASK) == IXGB_RCTL_BSIZE_8192 ? "8192" : + (reg & IXGB_RCTL_BSIZE_MASK) == IXGB_RCTL_BSIZE_4096 ? "4096" : + "2048"); + + /* Receive descriptor registers */ + fprintf(stdout, + "0x00120: RDLEN (Receive desc length) 0x%08X\n", + regs_buff[14]); + fprintf(stdout, + "0x00128: RDH (Receive desc head) 0x%08X\n", + regs_buff[15]); + fprintf(stdout, + "0x00130: RDT (Receive desc tail) 0x%08X\n", + regs_buff[16]); + fprintf(stdout, + "0x00138: RDTR (Receive delay timer) 0x%08X\n", + regs_buff[17]); + + /* Transmit control register */ + reg = regs_buff[53]; + fprintf(stdout, + "0x00600: TCTL (Transmit ctrl register) 0x%08X\n" + " Transmitter: %s\n", + reg, + reg & IXGB_TCTL_TXEN ? "enabled" : "disabled"); + + /* Transmit descriptor registers */ + fprintf(stdout, + "0x00610: TDLEN (Transmit desc length) 0x%08X\n", + regs_buff[56]); + fprintf(stdout, + "0x00618: TDH (Transmit desc head) 0x%08X\n", + regs_buff[57]); + fprintf(stdout, + "0x00620: TDT (Transmit desc tail) 0x%08X\n", + regs_buff[58]); + fprintf(stdout, + "0x00628: TIDV (Transmit delay timer) 0x%08X\n", + regs_buff[59]); + + return 0; +} +
diff --git a/ethtool-2.6.35/ixgbe.c b/ethtool-2.6.35/ixgbe.c new file mode 100644 index 0000000..998c008 --- /dev/null +++ b/ethtool-2.6.35/ixgbe.c
@@ -0,0 +1,1017 @@ +/* Copyright (c) 2007 Intel Corporation */ +#include <stdio.h> +#include "ethtool-util.h" + +/* Register Bit Masks */ +#define IXGBE_FCTRL_SBP 0x00000002 +#define IXGBE_FCTRL_MPE 0x00000100 +#define IXGBE_FCTRL_UPE 0x00000200 +#define IXGBE_FCTRL_BAM 0x00000400 +#define IXGBE_FCTRL_PMCF 0x00001000 +#define IXGBE_FCTRL_DPF 0x00002000 +#define IXGBE_FCTRL_RPFCE 0x00004000 +#define IXGBE_FCTRL_RFCE 0x00008000 +#define IXGBE_VLNCTRL_VET 0x0000FFFF +#define IXGBE_VLNCTRL_CFI 0x10000000 +#define IXGBE_VLNCTRL_CFIEN 0x20000000 +#define IXGBE_VLNCTRL_VFE 0x40000000 +#define IXGBE_VLNCTRL_VME 0x80000000 +#define IXGBE_LINKS_UP 0x40000000 +#define IXGBE_LINKS_SPEED 0x20000000 +#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F +#define IXGBE_HLREG0_TXCRCEN 0x00000001 +#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 +#define IXGBE_HLREG0_JUMBOEN 0x00000004 +#define IXGBE_HLREG0_TXPADEN 0x00000400 +#define IXGBE_HLREG0_LPBK 0x00008000 +#define IXGBE_RMCS_TFCE_802_3X 0x00000008 +#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 + +int +ixgbe_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *regs_buff = (u32 *)regs->data; + u32 reg; + u8 i; + u8 version = (u8)(regs->version >> 24); + + if (version != 1) + return -1; + + reg = regs_buff[1065]; + fprintf(stdout, + "0x042A4: LINKS (Link Status register) 0x%08X\n" + " Link Status: %s\n" + " Link Speed: %s\n", + reg, + reg & IXGBE_LINKS_UP ? "up" : "down", + reg & IXGBE_LINKS_SPEED ? "10G" : "1G"); + + reg = regs_buff[515]; + fprintf(stdout, + "0x05080: FCTRL (Filter Control register) 0x%08X\n" + " Receive Flow Control Packets: %s\n" + " Receive Priority Flow Control Packets: %s\n" + " Discard Pause Frames: %s\n" + " Pass MAC Control Frames: %s\n" + " Broadcast Accept: %s\n" + " Unicast Promiscuous: %s\n" + " Multicast Promiscuous: %s\n" + " Store Bad Packets: %s\n", + reg, + reg & IXGBE_FCTRL_RFCE ? "enabled" : "disabled", + reg & IXGBE_FCTRL_RPFCE ? "enabled" : "disabled", + reg & IXGBE_FCTRL_DPF ? "enabled" : "disabled", + reg & IXGBE_FCTRL_PMCF ? "enabled" : "disabled", + reg & IXGBE_FCTRL_BAM ? "enabled" : "disabled", + reg & IXGBE_FCTRL_UPE ? "enabled" : "disabled", + reg & IXGBE_FCTRL_MPE ? "enabled" : "disabled", + reg & IXGBE_FCTRL_SBP ? "enabled" : "disabled"); + + reg = regs_buff[516]; + fprintf(stdout, + "0x05088: VLNCTRL (VLAN Control register) 0x%08X\n" + " VLAN Mode: %s\n" + " VLAN Filter: %s\n", + reg, + reg & IXGBE_VLNCTRL_VME ? "enabled" : "disabled", + reg & IXGBE_VLNCTRL_VFE ? "enabled" : "disabled"); + + reg = regs_buff[437]; + fprintf(stdout, + "0x02100: SRRCTL0 (Split and Replic Rx Control 0) 0x%08X\n" + " Receive Buffer Size: %uKB\n", + reg, + (reg & IXGBE_SRRCTL_BSIZEPKT_MASK) <= 0x10 ? (reg & IXGBE_SRRCTL_BSIZEPKT_MASK) : 0x10); + + reg = regs_buff[829]; + fprintf(stdout, + "0x03D00: RMCS (Receive Music Control register) 0x%08X\n" + " Transmit Flow Control: %s\n" + " Priority Flow Control: %s\n", + reg, + reg & IXGBE_RMCS_TFCE_802_3X ? "enabled" : "disabled", + reg & IXGBE_RMCS_TFCE_PRIORITY ? "enabled" : "disabled"); + + reg = regs_buff[1047]; + fprintf(stdout, + "0x04250: HLREG0 (Highlander Control 0 register) 0x%08X\n" + " Transmit CRC: %s\n" + " Receive CRC Strip: %s\n" + " Jumbo Frames: %s\n" + " Pad Short Frames: %s\n" + " Loopback: %s\n", + reg, + reg & IXGBE_HLREG0_TXCRCEN ? "enabled" : "disabled", + reg & IXGBE_HLREG0_RXCRCSTRP ? "enabled" : "disabled", + reg & IXGBE_HLREG0_JUMBOEN ? "enabled" : "disabled", + reg & IXGBE_HLREG0_TXPADEN ? "enabled" : "disabled", + reg & IXGBE_HLREG0_LPBK ? "enabled" : "disabled"); + + /* General Registers */ + fprintf(stdout, + "0x00000: CTRL (Device Control) 0x%08X\n", + regs_buff[0]); + + fprintf(stdout, + "0x00008: STATUS (Device Status) 0x%08X\n", + regs_buff[1]); + + fprintf(stdout, + "0x00018: CTRL_EXT (Extended Device Control) 0x%08X\n", + regs_buff[2]); + + fprintf(stdout, + "0x00020: ESDP (Extended SDP Control) 0x%08X\n", + regs_buff[3]); + + fprintf(stdout, + "0x00028: EODSDP (Extended OD SDP Control) 0x%08X\n", + regs_buff[4]); + + fprintf(stdout, + "0x00200: LEDCTL (LED Control) 0x%08X\n", + regs_buff[5]); + + fprintf(stdout, + "0x00048: FRTIMER (Free Running Timer) 0x%08X\n", + regs_buff[6]); + + fprintf(stdout, + "0x0004C: TCPTIMER (TCP Timer) 0x%08X\n", + regs_buff[7]); + + /* NVM Register */ + fprintf(stdout, + "0x10010: EEC (EEPROM/Flash Control) 0x%08X\n", + regs_buff[8]); + + fprintf(stdout, + "0x10014: EERD (EEPROM Read) 0x%08X\n", + regs_buff[9]); + + fprintf(stdout, + "0x1001C: FLA (Flash Access) 0x%08X\n", + regs_buff[10]); + + fprintf(stdout, + "0x10110: EEMNGCTL (Manageability EEPROM Control) 0x%08X\n", + regs_buff[11]); + + fprintf(stdout, + "0x10114: EEMNGDATA (Manageability EEPROM R/W Data) 0x%08X\n", + regs_buff[12]); + + fprintf(stdout, + "0x10110: FLMNGCTL (Manageability Flash Control) 0x%08X\n", + regs_buff[13]); + + fprintf(stdout, + "0x1011C: FLMNGDATA (Manageability Flash Read Data) 0x%08X\n", + regs_buff[14]); + + fprintf(stdout, + "0x10120: FLMNGCNT (Manageability Flash Read Count) 0x%08X\n", + regs_buff[15]); + + fprintf(stdout, + "0x1013C: FLOP (Flash Opcode) 0x%08X\n", + regs_buff[16]); + + fprintf(stdout, + "0x10200: GRC (General Receive Control) 0x%08X\n", + regs_buff[17]); + + /* Interrupt */ + fprintf(stdout, + "0x00800: EICR (Extended Interrupt Cause) 0x%08X\n", + regs_buff[18]); + + fprintf(stdout, + "0x00808: EICS (Extended Interrupt Cause Set) 0x%08X\n", + regs_buff[19]); + + fprintf(stdout, + "0x00880: EIMS (Extended Interr. Mask Set/Read) 0x%08X\n", + regs_buff[20]); + + fprintf(stdout, + "0x00888: EIMC (Extended Interrupt Mask Clear) 0x%08X\n", + regs_buff[21]); + + fprintf(stdout, + "0x00810: EIAC (Extended Interrupt Auto Clear) 0x%08X\n", + regs_buff[22]); + + fprintf(stdout, + "0x00890: EIAM (Extended Interr. Auto Mask EN) 0x%08X\n", + regs_buff[23]); + + fprintf(stdout, + "0x00820: EITR0 (Extended Interrupt Throttle 0) 0x%08X\n", + regs_buff[24]); + + fprintf(stdout, + "0x00900: IVAR0 (Interrupt Vector Allocation 0) 0x%08X\n", + regs_buff[25]); + + fprintf(stdout, + "0x00000: MSIXT (MSI-X Table) 0x%08X\n", + regs_buff[26]); + + fprintf(stdout, + "0x02000: MSIXPBA (MSI-X Pending Bit Array) 0x%08X\n", + regs_buff[27]); + + fprintf(stdout, + "0x11068: PBACL (MSI-X PBA Clear) 0x%08X\n", + regs_buff[28]); + + fprintf(stdout, + "0x00898: GPIE (General Purpose Interrupt EN) 0x%08X\n", + regs_buff[29]); + + /* Flow Control */ + fprintf(stdout, + "0x03008: PFCTOP (Priority Flow Ctrl Type Opcode) 0x%08X\n", + regs_buff[30]); + + for (i = 0; i < 4; i++) + fprintf(stdout, + "0x%05X: FCCTV%d (Flow Ctrl Tx Timer Value %d) 0x%08X\n", + 0x03200 + (4 * i), i, i, regs_buff[31 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: FCRTL%d (Flow Ctrl Rx Threshold low %d) 0x%08X\n", + 0x3220 + (8 * i), i, i, regs_buff[35 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: FCRTH%d (Flow Ctrl Rx Threshold High %d) 0x%08X\n", + 0x3260 + (8 * i), i, i, regs_buff[43 + i]); + + fprintf(stdout, + "0x032A0: FCRTV (Flow Control Refresh Threshold) 0x%08X\n", + regs_buff[51]); + + fprintf(stdout, + "0x0CE00: TFCS (Transmit Flow Control Status) 0x%08X\n", + regs_buff[52]); + + /* Receive DMA */ + for (i = 0; i < 64; i++) + fprintf(stdout, + "0x%05X: RDBAL%02d (Rx Desc Base Addr Low %02d) 0x%08X\n", + 0x01000 + (0x40 * i), i, i, regs_buff[53 + i]); + + for (i = 0; i < 64; i++) + fprintf(stdout, + "0x%05X: RDBAH%02d (Rx Desc Base Addr High %02d) 0x%08X\n", + 0x01004 + (0x40 * i), i, i, regs_buff[117 + i]); + + for (i = 0; i < 64; i++) + fprintf(stdout, + "0x%05X: RDLEN%02d (Receive Descriptor Length %02d) 0x%08X\n", + 0x01008 + (0x40 * i), i, i, regs_buff[181 + i]); + + for (i = 0; i < 64; i++) + fprintf(stdout, + "0x%05X: RDH%02d (Receive Descriptor Head %02d) 0x%08X\n", + 0x01010 + (0x40 * i), i, i, regs_buff[245 + i]); + + for (i = 0; i < 64; i++) + fprintf(stdout, + "0x%05X: RDT%02d (Receive Descriptor Tail %02d) 0x%08X\n", + 0x01018 + (0x40 * i), i, i, regs_buff[309 + i]); + + for (i = 0; i < 64; i++) + fprintf(stdout, + "0x%05X: RXDCTL%02d (Receive Descriptor Control %02d) 0x%08X\n", + 0x01028 + (0x40 * i), i, i, regs_buff[373 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: SRRCTL%02d (Split and Replic Rx Control %02d) 0x%08X\n", + 0x02100 + (4 * i), i, i, regs_buff[437 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: DCA_RXCTRL%02d (Rx DCA Control %02d) 0x%08X\n", + 0x02200 + (4 * i), i, i, regs_buff[453 + i]); + + fprintf(stdout, + "0x02F00: RDRXCTL (Receive DMA Control) 0x%08X\n", + regs_buff[469]); + + for (i = 0; i < 8; i++ ) + fprintf(stdout, + "0x%05X: RXPBSIZE%d (Receive Packet Buffer Size %d) 0x%08X\n", + 0x3C00 + (4 * i), i, i, regs_buff[470 + i]); + + fprintf(stdout, + "0x03000: RXCTRL (Receive Control) 0x%08X\n", + regs_buff[478]); + + fprintf(stdout, + "0x03D04: DROPEN (Drop Enable Control) 0x%08X\n", + regs_buff[479]); + + /* Receive */ + fprintf(stdout, + "0x05000: RXCSUM (Receive Checksum Control) 0x%08X\n", + regs_buff[480]); + + fprintf(stdout, + "0x05008: RFCTL (Receive Filter Control) 0x%08X\n", + regs_buff[481]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: RAL%02d (Receive Address Low%02d) 0x%08X\n", + 0x05400 + (8 * i), i, i, regs_buff[482 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: RAH%02d (Receive Address High %02d) 0x%08X\n", + 0x05404 + (8 * i), i, i, regs_buff[498 + i]); + + fprintf(stdout, + "0x05480: PSRTYPE (Packet Split Receive Type) 0x%08X\n", + regs_buff[514]); + + fprintf(stdout, + "0x05090: MCSTCTRL (Multicast Control) 0x%08X\n", + regs_buff[517]); + + fprintf(stdout, + "0x05818: MRQC (Multiple Rx Queues Command) 0x%08X\n", + regs_buff[518]); + + fprintf(stdout, + "0x0581C: VMD_CTL (VMDq Control) 0x%08X\n", + regs_buff[519]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: IMIR%d (Immediate Interrupt Rx %d) 0x%08X\n", + 0x05A80 + (4 * i), i, i, regs_buff[520 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: IMIREXT%d (Immed. Interr. Rx Extended %d) 0x%08X\n", + 0x05AA0 + (4 * i), i, i, regs_buff[528 + i]); + + fprintf(stdout, + "0x05AC0: IMIRVP (Immed. Interr. Rx VLAN Prior.) 0x%08X\n", + regs_buff[536]); + + /* Transmit */ + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDBAL%02d (Tx Desc Base Addr Low %02d) 0x%08X\n", + 0x06000 + (0x40 * i), i, i, regs_buff[537 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDBAH%02d (Tx Desc Base Addr High %02d) 0x%08X\n", + 0x06004 + (0x40 * i), i, i, regs_buff[569 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDLEN%02d (Tx Descriptor Length %02d) 0x%08X\n", + 0x06008 + (0x40 * i), i, i, regs_buff[601 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDH%02d (Transmit Descriptor Head %02d) 0x%08X\n", + 0x06010 + (0x40 * i), i, i, regs_buff[633 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDT%02d (Transmit Descriptor Tail %02d) 0x%08X\n", + 0x06018 + (0x40 * i), i, i, regs_buff[665 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TXDCTL%02d (Tx Descriptor Control %02d) 0x%08X\n", + 0x06028 + (0x40 * i), i, i, regs_buff[697 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDWBAL%02d (Tx Desc Compl. WB Addr low %02d) 0x%08X\n", + 0x06038 + (0x40 * i), i, i, regs_buff[729 + i]); + + for (i = 0; i < 32; i++) + fprintf(stdout, + "0x%05X: TDWBAH%02d (Tx Desc Compl. WB Addr High %02d) 0x%08X\n", + 0x0603C + (0x40 * i), i, i, regs_buff[761 + i]); + + fprintf(stdout, + "0x07E00: DTXCTL (DMA Tx Control) 0x%08X\n", + regs_buff[793]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: DCA_TXCTRL%02d (Tx DCA Control %02d) 0x%08X\n", + 0x07200 + (4 * i), i, i, regs_buff[794 + i]); + + fprintf(stdout, + "0x0CB00: TIPG (Transmit IPG Control) 0x%08X\n", + regs_buff[810]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: TXPBSIZE%d (Transmit Packet Buffer Size %d) 0x%08X\n", + 0x0CC00 + (4 * i), i, i, regs_buff[811 + i]); + + fprintf(stdout, + "0x0CD10: MNGTXMAP (Manageability Tx TC Mapping) 0x%08X\n", + regs_buff[819]); + + /* Wake Up */ + fprintf(stdout, + "0x05800: WUC (Wake up Control) 0x%08X\n", + regs_buff[820]); + + fprintf(stdout, + "0x05808: WUFC (Wake Up Filter Control) 0x%08X\n", + regs_buff[821]); + + fprintf(stdout, + "0x05810: WUS (Wake Up Status) 0x%08X\n", + regs_buff[822]); + + fprintf(stdout, + "0x05838: IPAV (IP Address Valid) 0x%08X\n", + regs_buff[823]); + + fprintf(stdout, + "0x05840: IP4AT (IPv4 Address Table) 0x%08X\n", + regs_buff[824]); + + fprintf(stdout, + "0x05880: IP6AT (IPv6 Address Table) 0x%08X\n", + regs_buff[825]); + + fprintf(stdout, + "0x05900: WUPL (Wake Up Packet Length) 0x%08X\n", + regs_buff[826]); + + fprintf(stdout, + "0x05A00: WUPM (Wake Up Packet Memory) 0x%08X\n", + regs_buff[827]); + + fprintf(stdout, + "0x09000: FHFT (Flexible Host Filter Table) 0x%08X\n", + regs_buff[828]); + + /* DCE */ + fprintf(stdout, + "0x07F40: DPMCS (Desc. Plan Music Ctrl Status) 0x%08X\n", + regs_buff[830]); + + fprintf(stdout, + "0x0CD00: PDPMCS (Pkt Data Plan Music ctrl Stat) 0x%08X\n", + regs_buff[831]); + + fprintf(stdout, + "0x050A0: RUPPBMR (Rx User Prior to Pkt Buff Map) 0x%08X\n", + regs_buff[832]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: RT2CR%d (Receive T2 Configure %d) 0x%08X\n", + 0x03C20 + (4 * i), i, i, regs_buff[833 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: RT2SR%d (Recieve T2 Status %d) 0x%08X\n", + 0x03C40 + (4 * i), i, i, regs_buff[841 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: TDTQ2TCCR%d (Tx Desc TQ2 TC Config %d) 0x%08X\n", + 0x0602C + (0x40 * i), i, i, regs_buff[849 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: TDTQ2TCSR%d (Tx Desc TQ2 TC Status %d) 0x%08X\n", + 0x0622C + (0x40 * i), i, i, regs_buff[857 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: TDPT2TCCR%d (Tx Data Plane T2 TC Config %d) 0x%08X\n", + 0x0CD20 + (4 * i), i, i, regs_buff[865 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: TDPT2TCSR%d (Tx Data Plane T2 TC Status %d) 0x%08X\n", + 0x0CD40 + (4 * i), i, i, regs_buff[873 + i]); + + /* Statistics */ + fprintf(stdout, + "0x04000: crcerrs (CRC Error Count) 0x%08X\n", + regs_buff[881]); + + fprintf(stdout, + "0x04004: illerrc (Illegal Byte Error Count) 0x%08X\n", + regs_buff[882]); + + fprintf(stdout, + "0x04008: errbc (Error Byte Count) 0x%08X\n", + regs_buff[883]); + + fprintf(stdout, + "0x04010: mspdc (MAC Short Packet Discard Count) 0x%08X\n", + regs_buff[884]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: mpc%d (Missed Packets Count %d) 0x%08X\n", + 0x03FA0 + (4 * i), i, i, regs_buff[885 + i]); + + fprintf(stdout, + "0x04034: mlfc (MAC Local Fault Count) 0x%08X\n", + regs_buff[893]); + + fprintf(stdout, + "0x04038: mrfc (MAC Remote Fault Count) 0x%08X\n", + regs_buff[894]); + + fprintf(stdout, + "0x04040: rlec (Receive Length Error Count) 0x%08X\n", + regs_buff[895]); + + fprintf(stdout, + "0x03F60: lxontxc (Link XON Transmitted Count) 0x%08X\n", + regs_buff[896]); + + fprintf(stdout, + "0x0CF60: lxonrxc (Link XON Received Count) 0x%08X\n", + regs_buff[897]); + + fprintf(stdout, + "0x03F68: lxofftxc (Link XOFF Transmitted Count) 0x%08X\n", + regs_buff[898]); + + fprintf(stdout, + "0x0CF68: lxoffrxc (Link XOFF Received Count) 0x%08X\n", + regs_buff[899]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: pxontxc%d (Priority XON Tx Count %d) 0x%08X\n", + 0x03F00 + (4 * i), i, i, regs_buff[900 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: pxonrxc%d (Priority XON Received Count %d) 0x%08X\n", + 0x0CF00 + (4 * i), i, i, regs_buff[908 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: pxofftxc%d (Priority XOFF Tx Count %d) 0x%08X\n", + 0x03F20 + (4 * i), i, i, regs_buff[916 + i]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: pxoffrxc%d (Priority XOFF Received Count %d) 0x%08X\n", + 0x0CF20 + (4 * i), i, i, regs_buff[924 + i]); + + fprintf(stdout, + "0x0405C: prc64 (Packets Received (64B) Count) 0x%08X\n", + regs_buff[932]); + + fprintf(stdout, + "0x04060: prc127 (Packets Rx (65-127B) Count) 0x%08X\n", + regs_buff[933]); + + fprintf(stdout, + "0x04064: prc255 (Packets Rx (128-255B) Count) 0x%08X\n", + regs_buff[934]); + + fprintf(stdout, + "0x04068: prc511 (Packets Rx (256-511B) Count) 0x%08X\n", + regs_buff[935]); + + fprintf(stdout, + "0x0406C: prc1023 (Packets Rx (512-1023B) Count) 0x%08X\n", + regs_buff[936]); + + fprintf(stdout, + "0x04070: prc1522 (Packets Rx (1024-Max) Count) 0x%08X\n", + regs_buff[937]); + + fprintf(stdout, + "0x04074: gprc (Good Packets Received Count) 0x%08X\n", + regs_buff[938]); + + fprintf(stdout, + "0x04078: bprc (Broadcast Packets Rx Count) 0x%08X\n", + regs_buff[939]); + + fprintf(stdout, + "0x0407C: mprc (Multicast Packets Rx Count) 0x%08X\n", + regs_buff[940]); + + fprintf(stdout, + "0x04080: gptc (Good Packets Transmitted Count) 0x%08X\n", + regs_buff[941]); + + fprintf(stdout, + "0x04088: gorcl (Good Octets Rx Count Low) 0x%08X\n", + regs_buff[942]); + + fprintf(stdout, + "0x0408C: gorch (Good Octets Rx Count High) 0x%08X\n", + regs_buff[943]); + + fprintf(stdout, + "0x04090: gotcl (Good Octets Tx Count Low) 0x%08X\n", + regs_buff[944]); + + fprintf(stdout, + "0x04094: gotch (Good Octets Tx Count High) 0x%08X\n", + regs_buff[945]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: rnbc%d (Receive No Buffers Count %d) 0x%08X\n", + 0x03FC0 + (4 * i), i, i, regs_buff[946 + i]); + + fprintf(stdout, + "0x040A4: ruc (Receive Undersize count) 0x%08X\n", + regs_buff[954]); + + fprintf(stdout, + "0x040A8: rfc (Receive Fragment Count) 0x%08X\n", + regs_buff[955]); + + fprintf(stdout, + "0x040AC: roc (Receive Oversize Count) 0x%08X\n", + regs_buff[956]); + + fprintf(stdout, + "0x040B0: rjc (Receive Jabber Count) 0x%08X\n", + regs_buff[957]); + + fprintf(stdout, + "0x040B4: mngprc (Management Packets Rx Count) 0x%08X\n", + regs_buff[958]); + + fprintf(stdout, + "0x040B8: mngpdc (Management Pkts Dropped Count) 0x%08X\n", + regs_buff[959]); + + fprintf(stdout, + "0x0CF90: mngptc (Management Packets Tx Count) 0x%08X\n", + regs_buff[960]); + + fprintf(stdout, + "0x040C0: torl (Total Octets Rx Count Low) 0x%08X\n", + regs_buff[961]); + + fprintf(stdout, + "0x040C4: torh (Total Octets Rx Count High) 0x%08X\n", + regs_buff[962]); + + fprintf(stdout, + "0x040D0: tpr (Total Packets Received) 0x%08X\n", + regs_buff[963]); + + fprintf(stdout, + "0x040D4: tpt (Total Packets Transmitted) 0x%08X\n", + regs_buff[964]); + + fprintf(stdout, + "0x040D8: ptc64 (Packets Tx (64B) Count) 0x%08X\n", + regs_buff[965]); + + fprintf(stdout, + "0x040DC: ptc127 (Packets Tx (65-127B) Count) 0x%08X\n", + regs_buff[966]); + + fprintf(stdout, + "0x040E0: ptc255 (Packets Tx (128-255B) Count) 0x%08X\n", + regs_buff[967]); + + fprintf(stdout, + "0x040E4: ptc511 (Packets Tx (256-511B) Count) 0x%08X\n", + regs_buff[968]); + + fprintf(stdout, + "0x040E8: ptc1023 (Packets Tx (512-1023B) Count) 0x%08X\n", + regs_buff[969]); + + fprintf(stdout, + "0x040EC: ptc1522 (Packets Tx (1024-Max) Count) 0x%08X\n", + regs_buff[970]); + + fprintf(stdout, + "0x040F0: mptc (Multicast Packets Tx Count) 0x%08X\n", + regs_buff[971]); + + fprintf(stdout, + "0x040F4: bptc (Broadcast Packets Tx Count) 0x%08X\n", + regs_buff[972]); + + fprintf(stdout, + "0x04120: xec (XSUM Error Count) 0x%08X\n", + regs_buff[973]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: qprc%02d (Queue Packets Rx Count %02d) 0x%08X\n", + 0x01030 + (0x40 * i), i, i, regs_buff[974 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: qptc%02d (Queue Packets Tx Count %02d) 0x%08X\n", + 0x06030 + (0x40 * i), i, i, regs_buff[990 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: qbrc%02d (Queue Bytes Rx Count %02d) 0x%08X\n", + 0x01034 + (0x40 * i), i, i, regs_buff[1006 + i]); + + for (i = 0; i < 16; i++) + fprintf(stdout, + "0x%05X: qbtc%02d (Queue Bytes Tx Count %02d) 0x%08X\n", + 0x06034 + (0x40 * i), i, i, regs_buff[1022 + i]); + + /* MAC */ + fprintf(stdout, + "0x04200: PCS1GCFIG (PCS_1G Gloabal Config 1) 0x%08X\n", + regs_buff[1038]); + + fprintf(stdout, + "0x04208: PCS1GLCTL (PCS_1G Link Control) 0x%08X\n", + regs_buff[1039]); + + fprintf(stdout, + "0x0420C: PCS1GLSTA (PCS_1G Link Status) 0x%08X\n", + regs_buff[1040]); + + fprintf(stdout, + "0x04210: PCS1GDBG0 (PCS_1G Debug 0) 0x%08X\n", + regs_buff[1041]); + + fprintf(stdout, + "0x04214: PCS1GDBG1 (PCS_1G Debug 1) 0x%08X\n", + regs_buff[1042]); + + fprintf(stdout, + "0x04218: PCS1GANA (PCS-1G Auto Neg. Adv.) 0x%08X\n", + regs_buff[1043]); + + fprintf(stdout, + "0x0421C: PCS1GANLP (PCS-1G AN LP Ability) 0x%08X\n", + regs_buff[1044]); + + fprintf(stdout, + "0x04220: PCS1GANNP (PCS_1G Auto Neg Next Page Tx) 0x%08X\n", + regs_buff[1045]); + + fprintf(stdout, + "0x04224: PCS1GANLPNP (PCS_1G Auto Neg LPs Next Page) 0x%08X\n", + regs_buff[1046]); + + fprintf(stdout, + "0x04244: HLREG1 (Highlander Status 1) 0x%08X\n", + regs_buff[1048]); + + fprintf(stdout, + "0x04248: PAP (Pause and Pace) 0x%08X\n", + regs_buff[1049]); + + fprintf(stdout, + "0x0424C: MACA (MDI Auto-Scan Command and Addr) 0x%08X\n", + regs_buff[1050]); + + fprintf(stdout, + "0x04250: APAE (Auto-Scan PHY Address Enable) 0x%08X\n", + regs_buff[1051]); + + fprintf(stdout, + "0x04254: ARD (Auto-Scan Read Data) 0x%08X\n", + regs_buff[1052]); + + fprintf(stdout, + "0x04258: AIS (Auto-Scan Interrupt Status) 0x%08X\n", + regs_buff[1053]); + + fprintf(stdout, + "0x0425C: MSCA (MDI Single Command and Addr) 0x%08X\n", + regs_buff[1054]); + + fprintf(stdout, + "0x04260: MSRWD (MDI Single Read and Write Data) 0x%08X\n", + regs_buff[1055]); + + fprintf(stdout, + "0x04264: MLADD (MAC Address Low) 0x%08X\n", + regs_buff[1056]); + + fprintf(stdout, + "0x04268: MHADD (MAC Addr High/Max Frame size) 0x%08X\n", + regs_buff[1057]); + + fprintf(stdout, + "0x0426C: TREG (Test Register) 0x%08X\n", + regs_buff[1058]); + + fprintf(stdout, + "0x04288: PCSS1 (XGXS Status 1) 0x%08X\n", + regs_buff[1059]); + + fprintf(stdout, + "0x0428C: PCSS2 (XGXS Status 2) 0x%08X\n", + regs_buff[1060]); + + fprintf(stdout, + "0x04290: XPCSS (10GBASE-X PCS Status) 0x%08X\n", + regs_buff[1061]); + + fprintf(stdout, + "0x04298: SERDESC (SERDES Interface Control) 0x%08X\n", + regs_buff[1062]); + + fprintf(stdout, + "0x0429C: MACS (FIFO Status/CNTL Report) 0x%08X\n", + regs_buff[1063]); + + fprintf(stdout, + "0x042A0: AUTOC (Auto Negotiation Control) 0x%08X\n", + regs_buff[1064]); + + fprintf(stdout, + "0x042A8: AUTOC2 (Auto Negotiation Control 2) 0x%08X\n", + regs_buff[1066]); + + fprintf(stdout, + "0x042AC: AUTOC3 (Auto Negotiation Control 3) 0x%08X\n", + regs_buff[1067]); + + fprintf(stdout, + "0x042B0: ANLP1 (Auto Neg Lnk Part. Ctrl Word 1) 0x%08X\n", + regs_buff[1068]); + + fprintf(stdout, + "0x042B0: ANLP2 (Auto Neg Lnk Part. Ctrl Word 2) 0x%08X\n", + regs_buff[1069]); + + fprintf(stdout, + "0x04800: ATLASCTL (Atlas Analog Configuration) 0x%08X\n", + regs_buff[1070]); + + /* Diagnostic */ + fprintf(stdout, + "0x02C20: RDSTATCTL (Rx DMA Statistic Control) 0x%08X\n", + regs_buff[1071]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: RDSTAT%d (Rx DMA Statistics %d) 0x%08X\n", + 0x02C00 + (4 * i), i, i, regs_buff[1072 + i]); + + fprintf(stdout, + "0x02F08: RDHMPN (Rx Desc Handler Mem Page num) 0x%08X\n", + regs_buff[1080]); + + fprintf(stdout, + "0x02F10: RIC_DW0 (Rx Desc Hand. Mem Read Data 0) 0x%08X\n", + regs_buff[1081]); + + fprintf(stdout, + "0x02F14: RIC_DW1 (Rx Desc Hand. Mem Read Data 1) 0x%08X\n", + regs_buff[1082]); + + fprintf(stdout, + "0x02F18: RIC_DW2 (Rx Desc Hand. Mem Read Data 2) 0x%08X\n", + regs_buff[1083]); + + fprintf(stdout, + "0x02F1C: RIC_DW3 (Rx Desc Hand. Mem Read Data 3) 0x%08X\n", + regs_buff[1084]); + + fprintf(stdout, + "0x02F20: RDPROBE (Rx Probe Mode Status) 0x%08X\n", + regs_buff[1085]); + + fprintf(stdout, + "0x07C20: TDSTATCTL (Tx DMA Statistic Control) 0x%08X\n", + regs_buff[1086]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: TDSTAT%d (Tx DMA Statistics %d) 0x%08X\n", + 0x07C00 + (4 * i), i, i, regs_buff[1087 + i]); + + fprintf(stdout, + "0x07F08: TDHMPN (Tx Desc Handler Mem Page Num) 0x%08X\n", + regs_buff[1095]); + + fprintf(stdout, + "0x07F10: TIC_DW0 (Tx Desc Hand. Mem Read Data 0) 0x%08X\n", + regs_buff[1096]); + + fprintf(stdout, + "0x07F14: TIC_DW1 (Tx Desc Hand. Mem Read Data 1) 0x%08X\n", + regs_buff[1097]); + + fprintf(stdout, + "0x07F18: TIC_DW2 (Tx Desc Hand. Mem Read Data 2) 0x%08X\n", + regs_buff[1098]); + + fprintf(stdout, + "0x07F1C: TIC_DW3 (Tx Desc Hand. Mem Read Data 3) 0x%08X\n", + regs_buff[1099]); + + fprintf(stdout, + "0x07F20: TDPROBE (Tx Probe Mode Status) 0x%08X\n", + regs_buff[1100]); + + fprintf(stdout, + "0x0C600: TXBUFCTRL (TX Buffer Access Control) 0x%08X\n", + regs_buff[1101]); + + fprintf(stdout, + "0x0C610: TXBUFDATA0 (TX Buffer DATA 0) 0x%08X\n", + regs_buff[1102]); + + fprintf(stdout, + "0x0C614: TXBUFDATA1 (TX Buffer DATA 1) 0x%08X\n", + regs_buff[1103]); + + fprintf(stdout, + "0x0C618: TXBUFDATA2 (TX Buffer DATA 2) 0x%08X\n", + regs_buff[1104]); + + fprintf(stdout, + "0x0C61C: TXBUFDATA3 (TX Buffer DATA 3) 0x%08X\n", + regs_buff[1105]); + + fprintf(stdout, + "0x03600: RXBUFCTRL (RX Buffer Access Control) 0x%08X\n", + regs_buff[1106]); + + fprintf(stdout, + "0x03610: RXBUFDATA0 (RX Buffer DATA 0) 0x%08X\n", + regs_buff[1107]); + + fprintf(stdout, + "0x03614: RXBUFDATA1 (RX Buffer DATA 1) 0x%08X\n", + regs_buff[1108]); + + fprintf(stdout, + "0x03618: RXBUFDATA2 (RX Buffer DATA 2) 0x%08X\n", + regs_buff[1109]); + + fprintf(stdout, + "0x0361C: RXBUFDATA3 (RX Buffer DATA 3) 0x%08X\n", + regs_buff[1110]); + + for (i = 0; i < 8; i++) + fprintf(stdout, + "0x%05X: PCIE_DIAG%d (PCIe Diagnostic %d) 0x%08X\n", + 0x11090 + (4 * i), i, i, regs_buff[1111 + i]); + + fprintf(stdout, + "0x050A4: RFVAL (Receive Filter Validation) 0x%08X\n", + regs_buff[1119]); + + fprintf(stdout, + "0x042B8: MDFTC1 (MAC DFT Control 1) 0x%08X\n", + regs_buff[1120]); + + fprintf(stdout, + "0x042C0: MDFTC2 (MAC DFT Control 2) 0x%08X\n", + regs_buff[1121]); + + fprintf(stdout, + "0x042C4: MDFTFIFO1 (MAC DFT FIFO 1) 0x%08X\n", + regs_buff[1122]); + + fprintf(stdout, + "0x042C8: MDFTFIFO2 (MAC DFT FIFO 2) 0x%08X\n", + regs_buff[1123]); + + fprintf(stdout, + "0x042CC: MDFTS (MAC DFT Status) 0x%08X\n", + regs_buff[1124]); + + fprintf(stdout, + "0x1106C: PCIEECCCTL (PCIe ECC Control) 0x%08X\n", + regs_buff[1125]); + + fprintf(stdout, + "0x0C300: PBTXECC (Packet Buffer Tx ECC) 0x%08X\n", + regs_buff[1126]); + + fprintf(stdout, + "0x03300: PBRXECC (Packet Buffer Rx ECC) 0x%08X\n", + regs_buff[1127]); + + return 0; +}
diff --git a/ethtool-2.6.35/marvell.c b/ethtool-2.6.35/marvell.c new file mode 100644 index 0000000..af38c21 --- /dev/null +++ b/ethtool-2.6.35/marvell.c
@@ -0,0 +1,452 @@ +/* + * Code to dump Marvell SysKonnect registers for skge and sky2 drivers. + * + * Copyright (C) 2004, 2006 + * Stephen Hemminger <shemminger@osdl.org> + */ + +#include <stdio.h> + +#include "ethtool-util.h" + +static void dump_addr(int n, const u8 *a) +{ + int i; + + printf("Addr %d ", n); + for (i = 0; i < 6; i++) + printf("%02X%c", a[i], i == 5 ? '\n' : ' '); +} + +static void dump_timer(const char *name, const void *p) +{ + const u8 *a = p; + const u32 *r = p; + + printf("%s\n", name); + printf("\tInit 0x%08X Value 0x%08X\n", r[0], r[1]); + printf("\tTest 0x%02X Control 0x%02X\n", a[8], a[9]); +} + +static void dump_queue(const char *name, const void *a, int rx) +{ + struct desc { + u_int32_t ctl; + u_int32_t next; + u_int32_t data_lo; + u_int32_t data_hi; + u_int32_t status; + u_int32_t timestamp; + u_int16_t csum2; + u_int16_t csum1; + u_int16_t csum2_start; + u_int16_t csum1_start; + u_int32_t addr_lo; + u_int32_t addr_hi; + u_int32_t count_lo; + u_int32_t count_hi; + u_int32_t byte_count; + u_int32_t csr; + u_int32_t flag; + }; + const struct desc *d = a; + + /* is reset bit set? */ + if (!(d->ctl & 2)) { + printf("\n%s (disabled)\n", name); + return; + } + + printf("\n%s\n", name); + printf("---------------\n"); + printf("Descriptor Address 0x%08X%08X\n", + d->addr_hi, d->addr_lo); + printf("Address Counter 0x%08X%08X\n", + d->count_hi, d->count_lo); + printf("Current Byte Counter %d\n", d->byte_count); + printf("BMU Control/Status 0x%08X\n", d->csr); + printf("Flag & FIFO Address 0x%08X\n", d->flag); + printf("\n"); + printf("Control 0x%08X\n", d->ctl); + printf("Next 0x%08X\n", d->next); + printf("Data 0x%08X%08X\n", + d->data_hi, d->data_lo); + printf("Status 0x%08X\n", d->status); + printf("Timestamp 0x%08X\n", d->timestamp); + if (rx) { + printf("Csum1 Offset %4d Position %d\n", + d->csum1, d->csum1_start); + printf("Csum2 Offset %4d Position %d\n", + d->csum2, d->csum2_start); + } else + printf("Csum Start 0x%04X Pos %4d Write %d\n", + d->csum1, d->csum2_start, d->csum1_start); + +} + +static void dump_ram(const char *name, const void *p) +{ + const u32 *r = p; + + if (!(r[10] & 2)) { + printf("\n%s (disabled)\n", name); + return; + } + + printf("\n%s\n", name); + printf("---------------\n"); + printf("Start Address 0x%08X\n", r[0]); + printf("End Address 0x%08X\n", r[1]); + printf("Write Pointer 0x%08X\n", r[2]); + printf("Read Pointer 0x%08X\n", r[3]); + + if (*name == 'R') { /* Receive only */ + printf("Upper Threshold/Pause Packets 0x%08X\n", r[4]); + printf("Lower Threshold/Pause Packets 0x%08X\n", r[5]); + printf("Upper Threshold/High Priority 0x%08X\n", r[6]); + printf("Lower Threshold/High Priority 0x%08X\n", r[7]); + } + printf("Packet Counter 0x%08X\n", r[8]); + printf("Level 0x%08X\n", r[9]); + printf("Control 0x%08X\n", r[10]); +} + +static void dump_fifo(const char *name, const void *p) +{ + const u32 *r = p; + + printf("\n%s\n", name); + printf("---------------\n"); + printf("End Address 0x%08X\n", r[0]); + printf("Write Pointer 0x%08X\n", r[1]); + printf("Read Pointer 0x%08X\n", r[2]); + printf("Packet Counter 0x%08X\n", r[3]); + printf("Level 0x%08X\n", r[4]); + printf("Control 0x%08X\n", r[5]); + printf("Control/Test 0x%08X\n", r[6]); + dump_timer("LED", p + 0x20); +} + +static void dump_gmac_fifo(const char *name, const void *p) +{ + const u32 *r = p; + int i; + static const char *regs[] = { + "End Address", + "Almost Full Thresh", + "Control/Test", + "FIFO Flush Mask", + "FIFO Flush Threshold", + "Truncation Threshold", + "Upper Pause Threshold", + "Lower Pause Threshold", + "VLAN Tag", + "FIFO Write Pointer", + "FIFO Write Level", + "FIFO Read Pointer", + "FIFO Read Level", + }; + + printf("\n%s\n", name); + for (i = 0; i < sizeof(regs)/sizeof(regs[0]); ++i) + printf("%-32s 0x%08X\n", regs[i], r[i]); + +} + +static void dump_mac(const u8 *r) +{ + u8 id; + + printf("\nMAC Addresses\n"); + printf("---------------\n"); + dump_addr(1, r + 0x100); + dump_addr(2, r + 0x108); + dump_addr(3, r + 0x110); + printf("\n"); + + printf("Connector type 0x%02X (%c)\n", + r[0x118], (char)r[0x118]); + printf("PMD type 0x%02X (%c)\n", + r[0x119], (char)r[0x119]); + printf("PHY type 0x%02X\n", r[0x11d]); + + id = r[0x11b]; + printf("Chip Id 0x%02X ", id); + + switch (id) { + case 0x0a: printf("Genesis"); break; + case 0xb0: printf("Yukon"); break; + case 0xb1: printf("Yukon-Lite"); break; + case 0xb2: printf("Yukon-LP"); break; + case 0xb3: printf("Yukon-2 XL"); break; + case 0xb5: printf("Yukon Extreme"); break; + case 0xb4: printf("Yukon-2 EC Ultra"); break; + case 0xb6: printf("Yukon-2 EC"); break; + case 0xb7: printf("Yukon-2 FE"); break; + case 0xb8: printf("Yukon-2 FE Plus"); break; + case 0xb9: printf("Yukon Supreme"); break; + case 0xba: printf("Yukon Ultra 2"); break; + case 0xbc: printf("Yukon Optima"); break; + default: printf("(Unknown)"); break; + } + + printf(" (rev %d)\n", (r[0x11a] & 0xf0) >> 4); + + printf("Ram Buffer 0x%02X\n", r[0x11c]); + +} + +static void dump_gma(const char *name, const u8 *r) +{ + int i; + + printf("%12s address: ", name); + for (i = 0; i < 3; i++) { + u16 a = *(u16 *)(r + i * 4); + printf(" %02X %02X", a & 0xff, (a >> 8) & 0xff); + } + printf("\n"); +} + +static void dump_gmac(const char *name, const u8 *data) +{ + printf("\n%s\n", name); + + printf("Status 0x%04X\n", *(u16 *) data); + printf("Control 0x%04X\n", *(u16 *) (data + 4)); + printf("Transmit 0x%04X\n", *(u16 *) (data + 8)); + printf("Receive 0x%04X\n", *(u16 *) (data + 0xc)); + printf("Transmit flow control 0x%04X\n", *(u16 *) (data + 0x10)); + printf("Transmit parameter 0x%04X\n", *(u16 *) (data + 0x14)); + printf("Serial mode 0x%04X\n", *(u16 *) (data + 0x18)); + + dump_gma("Source", data + 0x1c); + dump_gma("Physical", data + 0x28); +} + +static void dump_pci(const u8 *cfg) +{ + int i; + + printf("\nPCI config\n----------\n"); + for(i = 0; i < 0x80; i++) { + if (!(i & 15)) + printf("%02x:", i); + printf(" %02x", cfg[i]); + if ((i & 15) == 15) + putchar('\n'); + } + putchar('\n'); +} + +static void dump_control(u8 *r) +{ + printf("Control Registers\n"); + printf("-----------------\n"); + + printf("Register Access Port 0x%02X\n", *r); + printf("LED Control/Status 0x%08X\n", *(u32 *) (r + 4)); + + printf("Interrupt Source 0x%08X\n", *(u32 *) (r + 8)); + printf("Interrupt Mask 0x%08X\n", *(u32 *) (r + 0xc)); + printf("Interrupt Hardware Error Source 0x%08X\n", *(u32 *) (r + 0x10)); + printf("Interrupt Hardware Error Mask 0x%08X\n", *(u32 *) (r + 0x14)); + printf("Interrupt Control 0x%08X\n", *(u32 *) (r + 0x2c)); + printf("Interrupt Moderation Mask 0x%08X\n", *(u32 *) (r + 0x14c)); + printf("Hardware Moderation Mask 0x%08X\n", *(u32 *) (r + 0x150)); + dump_timer("Moderation Timer", r + 0x140); + + printf("General Purpose I/O 0x%08X\n", *(u32 *) (r + 0x15c)); +} + +int skge_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + const u32 *r = (const u32 *) regs->data; + int dual = !(regs->data[0x11a] & 1); + + dump_pci(regs->data + 0x380); + + dump_control(regs->data); + + printf("\nBus Management Unit\n"); + printf("-------------------\n"); + printf("CSR Receive Queue 1 0x%08X\n", r[24]); + printf("CSR Sync Queue 1 0x%08X\n", r[26]); + printf("CSR Async Queue 1 0x%08X\n", r[27]); + if (dual) { + printf("CSR Receive Queue 2 0x%08X\n", r[25]); + printf("CSR Async Queue 2 0x%08X\n", r[29]); + printf("CSR Sync Queue 2 0x%08X\n", r[28]); + } + + dump_mac(regs->data); + dump_gmac("GMAC 1", regs->data + 0x2800); + + dump_timer("Timer", regs->data + 0x130); + dump_timer("Blink Source", regs->data +0x170); + + dump_queue("Receive Queue 1", regs->data +0x400, 1); + dump_queue("Sync Transmit Queue 1", regs->data +0x600, 0); + dump_queue("Async Transmit Queue 1", regs->data +0x680, 0); + + dump_ram("Receive RAMbuffer 1", regs->data+0x800); + dump_ram("Sync Transmit RAMbuffer 1", regs->data+0xa00); + dump_ram("Async Transmit RAMbuffer 1", regs->data+0xa80); + + dump_fifo("Receive MAC FIFO 1", regs->data+0xc00); + dump_fifo("Transmit MAC FIFO 1", regs->data+0xd00); + if (dual) { + dump_gmac("GMAC 1", regs->data + 0x2800); + + dump_queue("Receive Queue 2", regs->data +0x480, 1); + dump_queue("Async Transmit Queue 2", regs->data +0x780, 0); + dump_queue("Sync Transmit Queue 2", regs->data +0x700, 0); + + dump_ram("Receive RAMbuffer 2", regs->data+0x880); + dump_ram("Sync Transmit RAMbuffer 2", regs->data+0xb00); + dump_ram("Async Transmit RAMbuffer 21", regs->data+0xb80); + + dump_fifo("Receive MAC FIFO 2", regs->data+0xc80); + dump_fifo("Transmit MAC FIFO 2", regs->data+0xd80); + } + + dump_timer("Descriptor Poll", regs->data+0xe00); + return 0; + +} + +static void dump_queue2(const char *name, void *a, int rx) +{ + struct sky2_queue { + u16 buf_control; + u16 byte_count; + u32 rss; + u32 addr_lo, addr_hi; + u32 status; + u32 timestamp; + u16 csum1, csum2; + u16 csum1_start, csum2_start; + u16 length; + u16 vlan; + u16 rsvd1; + u16 done; + u32 req_lo, req_hi; + u16 rsvd2; + u16 req_count; + u32 csr; + } *d = a; + + printf("\n%s\n", name); + printf("---------------\n"); + + printf("Buffer control 0x%04X\n", d->buf_control); + + printf("Byte Counter %d\n", d->byte_count); + printf("Descriptor Address 0x%08X%08X\n", + d->addr_hi, d->addr_lo); + printf("Status 0x%08X\n", d->status); + printf("Timestamp 0x%08X\n", d->timestamp); + printf("BMU Control/Status 0x%08X\n", d->csr); + printf("Done 0x%04X\n", d->done); + printf("Request 0x%08X%08X\n", + d->req_hi, d->req_lo); + if (rx) { + printf("Csum1 Offset %4d Position %d\n", + d->csum1, d->csum1_start); + printf("Csum2 Offset %4d Position %d\n", + d->csum2, d->csum2_start); + } else + printf("Csum Start 0x%04X Pos %4d Write %d\n", + d->csum1, d->csum2_start, d->csum1_start); +} + +static void dump_prefetch(const char *name, const void *r) +{ + const u32 *reg = r; + + printf("\n%s Prefetch\n", name); + printf("Control 0x%08X\n", reg[0]); + printf("Last Index %u\n", reg[1]); + printf("Start Address 0x%08x%08x\n", reg[3], reg[2]); + if (*name == 'S') { /* Status unit */ + printf("TX1 report %u\n", reg[4]); + printf("TX2 report %u\n", reg[5]); + printf("TX threshold %u\n", reg[6]); + printf("Put Index %u\n", reg[7]); + } else { + printf("Get Index %u\n", reg[4]); + printf("Put Index %u\n", reg[5]); + } +} + +int sky2_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + const u32 *r = (const u32 *) regs->data; + int dual; + + dump_pci(regs->data + 0x1c00); + + dump_control(regs->data); + + printf("\nBus Management Unit\n"); + printf("-------------------\n"); + printf("CSR Receive Queue 1 0x%08X\n", r[24]); + printf("CSR Sync Queue 1 0x%08X\n", r[26]); + printf("CSR Async Queue 1 0x%08X\n", r[27]); + + dual = (regs->data[0x11e] & 2) != 0; + if (dual) { + printf("CSR Receive Queue 2 0x%08X\n", r[25]); + printf("CSR Async Queue 2 0x%08X\n", r[29]); + printf("CSR Sync Queue 2 0x%08X\n", r[28]); + } + + dump_mac(regs->data); + + dump_prefetch("Status", regs->data + 0xe80); + dump_prefetch("Receive 1", regs->data + 0x450); + dump_prefetch("Transmit 1", regs->data + 0x450 + 0x280); + + if (dual) { + dump_prefetch("Receive 2", regs->data + 0x450 + 0x80); + dump_prefetch("Transmit 2", regs->data + 0x450 + 0x380); + } + + printf("\nStatus FIFO\n"); + printf("\tWrite Pointer 0x%02X\n", regs->data[0xea0]); + printf("\tRead Pointer 0x%02X\n", regs->data[0xea4]); + printf("\tLevel 0x%02X\n", regs->data[0xea8]); + printf("\tWatermark 0x%02X\n", regs->data[0xeac]); + printf("\tISR Watermark 0x%02X\n", regs->data[0xead]); + + dump_timer("Status level", regs->data + 0xeb0); + dump_timer("TX status", regs->data + 0xec0); + dump_timer("ISR", regs->data + 0xed0); + + printf("\nGMAC control 0x%04X\n", *(u32 *)(regs->data + 0xf00)); + printf("GPHY control 0x%04X\n", *(u32 *)(regs->data + 0xf04)); + printf("LINK control 0x%02hX\n", *(u16 *)(regs->data + 0xf10)); + + dump_gmac("GMAC 1", regs->data + 0x2800); + dump_gmac_fifo("Rx GMAC 1", regs->data + 0xc40); + dump_gmac_fifo("Tx GMAC 1", regs->data + 0xd40); + + dump_queue2("Receive Queue 1", regs->data +0x400, 1); + dump_queue("Sync Transmit Queue 1", regs->data +0x600, 0); + dump_queue2("Async Transmit Queue 1", regs->data +0x680, 0); + + dump_ram("Receive RAMbuffer 1", regs->data+0x800); + dump_ram("Sync Transmit RAMbuffer 1", regs->data+0xa00); + dump_ram("Async Transmit RAMbuffer 1", regs->data+0xa80); + + if (dual) { + dump_ram("Receive RAMbuffer 2", regs->data+0x880); + dump_ram("Sync Transmit RAMbuffer 2", regs->data+0xb00); + dump_ram("Async Transmit RAMbuffer 21", regs->data+0xb80); + dump_gmac("GMAC 2", regs->data + 0x3800); + dump_gmac_fifo("Rx GMAC 2", regs->data + 0xc40 + 128); + dump_gmac_fifo("Tx GMAC 2", regs->data + 0xd40 + 128); + } + + return 0; +}
diff --git a/ethtool-2.6.35/missing b/ethtool-2.6.35/missing new file mode 100755 index 0000000..1c8ff70 --- /dev/null +++ b/ethtool-2.6.35/missing
@@ -0,0 +1,367 @@ +#! /bin/sh +# Common stub for a few missing GNU programs while installing. + +scriptversion=2006-05-10.23 + +# Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004, 2005, 2006 +# Free Software Foundation, Inc. +# Originally by Fran,cois Pinard <pinard@iro.umontreal.ca>, 1996. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# 02110-1301, USA. + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +if test $# -eq 0; then + echo 1>&2 "Try \`$0 --help' for more information" + exit 1 +fi + +run=: +sed_output='s/.* --output[ =]\([^ ]*\).*/\1/p' +sed_minuso='s/.* -o \([^ ]*\).*/\1/p' + +# In the cases where this matters, `missing' is being run in the +# srcdir already. +if test -f configure.ac; then + configure_ac=configure.ac +else + configure_ac=configure.in +fi + +msg="missing on your system" + +case $1 in +--run) + # Try to run requested program, and just exit if it succeeds. + run= + shift + "$@" && exit 0 + # Exit code 63 means version mismatch. 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PROGRAM [ARGUMENT]... + +Handle \`PROGRAM [ARGUMENT]...' for when PROGRAM is missing, or return an +error status if there is no known handling for PROGRAM. + +Options: + -h, --help display this help and exit + -v, --version output version information and exit + --run try to run the given command, and emulate it if it fails + +Supported PROGRAM values: + aclocal touch file \`aclocal.m4' + autoconf touch file \`configure' + autoheader touch file \`config.h.in' + autom4te touch the output file, or create a stub one + automake touch all \`Makefile.in' files + bison create \`y.tab.[ch]', if possible, from existing .[ch] + flex create \`lex.yy.c', if possible, from existing .c + help2man touch the output file + lex create \`lex.yy.c', if possible, from existing .c + makeinfo touch the output file + tar try tar, gnutar, gtar, then tar without non-portable flags + yacc create \`y.tab.[ch]', if possible, from existing .[ch] + +Send bug reports to <bug-automake@gnu.org>." + exit $? + ;; + + -v|--v|--ve|--ver|--vers|--versi|--versio|--version) + echo "missing $scriptversion (GNU Automake)" + exit $? + ;; + + -*) + echo 1>&2 "$0: Unknown \`$1' option" + echo 1>&2 "Try \`$0 --help' for more information" + exit 1 + ;; + +esac + +# Now exit if we have it, but it failed. Also exit now if we +# don't have it and --version was passed (most likely to detect +# the program). +case $1 in + lex|yacc) + # Not GNU programs, they don't have --version. + ;; + + tar) + if test -n "$run"; then + echo 1>&2 "ERROR: \`tar' requires --run" + exit 1 + elif test "x$2" = "x--version" || test "x$2" = "x--help"; then + exit 1 + fi + ;; + + *) + if test -z "$run" && ($1 --version) > /dev/null 2>&1; then + # We have it, but it failed. + exit 1 + elif test "x$2" = "x--version" || test "x$2" = "x--help"; then + # Could not run --version or --help. This is probably someone + # running `$TOOL --version' or `$TOOL --help' to check whether + # $TOOL exists and not knowing $TOOL uses missing. + exit 1 + fi + ;; +esac + +# If it does not exist, or fails to run (possibly an outdated version), +# try to emulate it. +case $1 in + aclocal*) + echo 1>&2 "\ +WARNING: \`$1' is $msg. You should only need it if + you modified \`acinclude.m4' or \`${configure_ac}'. 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You should only need it if + you modified a \`.texi' or \`.texinfo' file, or any other file + indirectly affecting the aspect of the manual. The spurious + call might also be the consequence of using a buggy \`make' (AIX, + DU, IRIX). You might want to install the \`Texinfo' package or + the \`GNU make' package. Grab either from any GNU archive site." + # The file to touch is that specified with -o ... + file=`echo "$*" | sed -n "$sed_output"` + test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"` + if test -z "$file"; then + # ... or it is the one specified with @setfilename ... + infile=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'` + file=`sed -n ' + /^@setfilename/{ + s/.* \([^ ]*\) *$/\1/ + p + q + }' $infile` + # ... or it is derived from the source name (dir/f.texi becomes f.info) + test -z "$file" && file=`echo "$infile" | sed 's,.*/,,;s,.[^.]*$,,'`.info + fi + # If the file does not exist, the user really needs makeinfo; + # let's fail without touching anything. + test -f $file || exit 1 + touch $file + ;; + + tar) + shift + + # We have already tried tar in the generic part. + # Look for gnutar/gtar before invocation to avoid ugly error + # messages. + if (gnutar --version > /dev/null 2>&1); then + gnutar "$@" && exit 0 + fi + if (gtar --version > /dev/null 2>&1); then + gtar "$@" && exit 0 + fi + firstarg="$1" + if shift; then + case $firstarg in + *o*) + firstarg=`echo "$firstarg" | sed s/o//` + tar "$firstarg" "$@" && exit 0 + ;; + esac + case $firstarg in + *h*) + firstarg=`echo "$firstarg" | sed s/h//` + tar "$firstarg" "$@" && exit 0 + ;; + esac + fi + + echo 1>&2 "\ +WARNING: I can't seem to be able to run \`tar' with the given arguments. + You may want to install GNU tar or Free paxutils, or check the + command line arguments." + exit 1 + ;; + + *) + echo 1>&2 "\ +WARNING: \`$1' is needed, and is $msg. + You might have modified some files without having the + proper tools for further handling them. Check the \`README' file, + it often tells you about the needed prerequisites for installing + this package. You may also peek at any GNU archive site, in case + some other package would contain this missing \`$1' program." + exit 1 + ;; +esac + +exit 0 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-end: "$" +# End:
diff --git a/ethtool-2.6.35/natsemi.c b/ethtool-2.6.35/natsemi.c new file mode 100644 index 0000000..24a7cb3 --- /dev/null +++ b/ethtool-2.6.35/natsemi.c
@@ -0,0 +1,985 @@ +/* Copyright 2001 Sun Microsystems (thockin@sun.com) */ +#include <stdio.h> +#include "ethtool-util.h" + +#define PCI_VENDOR_NATSEMI 0x100b +#define PCI_DEVICE_DP83815 0x0020 +#define NATSEMI_MAGIC (PCI_VENDOR_NATSEMI | \ + (PCI_DEVICE_DP83815<<16)) + +/* register indices in the ethtool_regs->data */ +#define REG_CR 0 +#define BIT_CR_TXE (1<<0) +#define BIT_CR_RXE (1<<2) +#define BIT_CR_RST (1<<8) +#define REG_CFG 1 +#define BIT_CFG_BEM (1<<0) +#define BIT_CFG_BROM_DIS (1<<2) +#define BIT_CFG_PHY_DIS (1<<9) +#define BIT_CFG_PHY_RST (1<<10) +#define BIT_CFG_EXT_PHY (1<<12) +#define BIT_CFG_ANEG_EN (1<<13) +#define BIT_CFG_ANEG_100 (1<<14) +#define BIT_CFG_ANEG_FDUP (1<<15) +#define BIT_CFG_PINT_ACEN (1<<17) +#define BIT_CFG_PHY_CFG (0x3f<<18) +#define BIT_CFG_ANEG_DN (1<<27) +#define BIT_CFG_POL (1<<28) +#define BIT_CFG_FDUP (1<<29) +#define BIT_CFG_SPEED100 (1<<30) +#define BIT_CFG_LNKSTS (1<<31) + +#define REG_MEAR 2 +#define REG_PTSCR 3 +#define BIT_PTSCR_EEBIST_FAIL (1<<0) +#define BIT_PTSCR_EELOAD_EN (1<<2) +#define BIT_PTSCR_RBIST_RXFFAIL (1<<3) +#define BIT_PTSCR_RBIST_TXFAIL (1<<4) +#define BIT_PTSCR_RBIST_RXFAIL (1<<5) +#define REG_ISR 4 +#define REG_IMR 5 +#define BIT_INTR_RXOK (1<<0) +#define NAME_INTR_RXOK "Rx Complete" +#define BIT_INTR_RXDESC (1<<1) +#define NAME_INTR_RXDESC "Rx Descriptor" +#define BIT_INTR_RXERR (1<<2) +#define NAME_INTR_RXERR "Rx Packet Error" +#define BIT_INTR_RXEARLY (1<<3) +#define NAME_INTR_RXEARLY "Rx Early Threshold" +#define BIT_INTR_RXIDLE (1<<4) +#define NAME_INTR_RXIDLE "Rx Idle" +#define BIT_INTR_RXORN (1<<5) +#define NAME_INTR_RXORN "Rx Overrun" +#define BIT_INTR_TXOK (1<<6) +#define NAME_INTR_TXOK "Tx Packet OK" +#define BIT_INTR_TXDESC (1<<7) +#define NAME_INTR_TXDESC "Tx Descriptor" +#define BIT_INTR_TXERR (1<<8) +#define NAME_INTR_TXERR "Tx Packet Error" +#define BIT_INTR_TXIDLE (1<<9) +#define NAME_INTR_TXIDLE "Tx Idle" +#define BIT_INTR_TXURN (1<<10) +#define NAME_INTR_TXURN "Tx Underrun" +#define BIT_INTR_MIB (1<<11) +#define NAME_INTR_MIB "MIB Service" +#define BIT_INTR_SWI (1<<12) +#define NAME_INTR_SWI "Software" +#define BIT_INTR_PME (1<<13) +#define NAME_INTR_PME "Power Management Event" +#define BIT_INTR_PHY (1<<14) +#define NAME_INTR_PHY "Phy" +#define BIT_INTR_HIBERR (1<<15) +#define NAME_INTR_HIBERR "High Bits Error" +#define BIT_INTR_RXSOVR (1<<16) +#define NAME_INTR_RXSOVR "Rx Status FIFO Overrun" +#define BIT_INTR_RTABT (1<<20) +#define NAME_INTR_RTABT "Received Target Abort" +#define BIT_INTR_RMABT (1<<20) +#define NAME_INTR_RMABT "Received Master Abort" +#define BIT_INTR_SSERR (1<<20) +#define NAME_INTR_SSERR "Signaled System Error" +#define BIT_INTR_DPERR (1<<20) +#define NAME_INTR_DPERR "Detected Parity Error" +#define BIT_INTR_RXRCMP (1<<20) +#define NAME_INTR_RXRCMP "Rx Reset Complete" +#define BIT_INTR_TXRCMP (1<<20) +#define NAME_INTR_TXRCMP "Tx Reset Complete" +#define REG_IER 6 +#define BIT_IER_IE (1<<0) +#define REG_TXDP 8 +#define REG_TXCFG 9 +#define BIT_TXCFG_DRTH (0x3f<<0) +#define BIT_TXCFG_FLTH (0x3f<<8) +#define BIT_TXCFG_MXDMA (0x7<<20) +#define BIT_TXCFG_ATP (1<<28) +#define BIT_TXCFG_MLB (1<<29) +#define BIT_TXCFG_HBI (1<<30) +#define BIT_TXCFG_CSI (1<<31) +#define REG_RXDP 12 +#define REG_RXCFG 13 +#define BIT_RXCFG_DRTH (0x1f<<1) +#define BIT_RXCFG_MXDMA (0x7<<20) +#define BIT_RXCFG_ALP (1<<27) +#define BIT_RXCFG_ATX (1<<28) +#define BIT_RXCFG_ARP (1<<30) +#define BIT_RXCFG_AEP (1<<31) +#define REG_CCSR 15 +#define BIT_CCSR_CLKRUN_EN (1<<0) +#define BIT_CCSR_PMEEN (1<<8) +#define BIT_CCSR_PMESTS (1<<15) +#define REG_WCSR 16 +#define BIT_WCSR_WKPHY (1<<0) +#define BIT_WCSR_WKUCP (1<<1) +#define BIT_WCSR_WKMCP (1<<2) +#define BIT_WCSR_WKBCP (1<<3) +#define BIT_WCSR_WKARP (1<<4) +#define BIT_WCSR_WKPAT0 (1<<5) +#define BIT_WCSR_WKPAT1 (1<<6) +#define BIT_WCSR_WKPAT2 (1<<7) +#define BIT_WCSR_WKPAT3 (1<<8) +#define BIT_WCSR_WKMAG (1<<9) +#define BIT_WCSR_MPSOE (1<<10) +#define BIT_WCSR_SOHACK (1<<20) +#define BIT_WCSR_PHYINT (1<<22) +#define BIT_WCSR_UCASTR (1<<23) +#define BIT_WCSR_MCASTR (1<<24) +#define BIT_WCSR_BCASTR (1<<25) +#define BIT_WCSR_ARPR (1<<26) +#define BIT_WCSR_PATM0 (1<<27) +#define BIT_WCSR_PATM1 (1<<28) +#define BIT_WCSR_PATM2 (1<<29) +#define BIT_WCSR_PATM3 (1<<30) +#define BIT_WCSR_MPR (1<<31) +#define REG_PCR 17 +#define BIT_PCR_PAUSE_CNT (0xffff<<0) +#define BIT_PCR_PSNEG (1<<21) +#define BIT_PCR_PS_RCVD (1<<22) +#define BIT_PCR_PS_DA (1<<29) +#define BIT_PCR_PSMCAST (1<<30) +#define BIT_PCR_PSEN (1<<31) +#define REG_RFCR 18 +#define BIT_RFCR_UHEN (1<<20) +#define BIT_RFCR_MHEN (1<<21) +#define BIT_RFCR_AARP (1<<22) +#define BIT_RFCR_APAT0 (1<<23) +#define BIT_RFCR_APAT1 (1<<24) +#define BIT_RFCR_APAT2 (1<<25) +#define BIT_RFCR_APAT3 (1<<26) +#define BIT_RFCR_APM (1<<27) +#define BIT_RFCR_AAU (1<<28) +#define BIT_RFCR_AAM (1<<29) +#define BIT_RFCR_AAB (1<<30) +#define BIT_RFCR_RFEN (1<<31) +#define REG_RFDR 19 +#define REG_BRAR 20 +#define BIT_BRAR_AUTOINC (1<<31) +#define REG_BRDR 21 +#define REG_SRR 22 +#define REG_MIBC 23 +#define BIT_MIBC_WRN (1<<0) +#define BIT_MIBC_FRZ (1<<1) +#define REG_MIB0 24 +#define REG_MIB1 25 +#define REG_MIB2 26 +#define REG_MIB3 27 +#define REG_MIB4 28 +#define REG_MIB5 29 +#define REG_MIB6 30 +#define REG_BMCR 32 +#define BIT_BMCR_FDUP (1<<8) +#define BIT_BMCR_ANRST (1<<9) +#define BIT_BMCR_ISOL (1<<10) +#define BIT_BMCR_PDOWN (1<<11) +#define BIT_BMCR_ANEN (1<<12) +#define BIT_BMCR_SPEED (1<<13) +#define BIT_BMCR_LOOP (1<<14) +#define BIT_BMCR_RST (1<<15) +#define REG_BMSR 33 +#define BIT_BMSR_JABBER (1<<1) +#define BIT_BMSR_LNK (1<<2) +#define BIT_BMSR_ANCAP (1<<3) +#define BIT_BMSR_RFAULT (1<<4) +#define BIT_BMSR_ANDONE (1<<5) +#define BIT_BMSR_PREAMBLE (1<<6) +#define BIT_BMSR_10HCAP (1<<11) +#define BIT_BMSR_10FCAP (1<<12) +#define BIT_BMSR_100HCAP (1<<13) +#define BIT_BMSR_100FCAP (1<<14) +#define BIT_BMSR_100T4CAP (1<<15) +#define REG_PHYIDR1 34 +#define REG_PHYIDR2 35 +#define BIT_PHYIDR2_OUILSB (0x3f<<10) +#define BIT_PHYIDR2_MODEL (0x3f<<4) +#define BIT_PHYIDR2_REV (0xf) +#define REG_ANAR 36 +#define BIT_ANAR_PROTO (0x1f<<0) +#define BIT_ANAR_10 (1<<5) +#define BIT_ANAR_10_FD (1<<6) +#define BIT_ANAR_TX (1<<7) +#define BIT_ANAR_TXFD (1<<8) +#define BIT_ANAR_T4 (1<<9) +#define BIT_ANAR_PAUSE (1<<10) +#define BIT_ANAR_RF (1<<13) +#define BIT_ANAR_NP (1<<15) +#define REG_ANLPAR 37 +#define BIT_ANLPAR_PROTO (0x1f<<0) +#define BIT_ANLPAR_10 (1<<5) +#define BIT_ANLPAR_10_FD (1<<6) +#define BIT_ANLPAR_TX (1<<7) +#define BIT_ANLPAR_TXFD (1<<8) +#define BIT_ANLPAR_T4 (1<<9) +#define BIT_ANLPAR_PAUSE (1<<10) +#define BIT_ANLPAR_RF (1<<13) +#define BIT_ANLPAR_ACK (1<<14) +#define BIT_ANLPAR_NP (1<<15) +#define REG_ANER 38 +#define BIT_ANER_LP_AN_ENABLE (1<<0) +#define BIT_ANER_PAGE_RX (1<<1) +#define BIT_ANER_NP_ABLE (1<<2) +#define BIT_ANER_LP_NP_ABLE (1<<3) +#define BIT_ANER_PDF (1<<4) +#define REG_ANNPTR 39 +#define REG_PHYSTS 48 +#define BIT_PHYSTS_LNK (1<<0) +#define BIT_PHYSTS_SPD10 (1<<1) +#define BIT_PHYSTS_FDUP (1<<2) +#define BIT_PHYSTS_LOOP (1<<3) +#define BIT_PHYSTS_ANDONE (1<<4) +#define BIT_PHYSTS_JABBER (1<<5) +#define BIT_PHYSTS_RF (1<<6) +#define BIT_PHYSTS_MINT (1<<7) +#define BIT_PHYSTS_FC (1<<11) +#define BIT_PHYSTS_POL (1<<12) +#define BIT_PHYSTS_RXERR (1<<13) +#define REG_MICR 49 +#define BIT_MICR_INTEN (1<<1) +#define REG_MISR 50 +#define BIT_MISR_MSK_RHF (1<<9) +#define BIT_MISR_MSK_FHF (1<<10) +#define BIT_MISR_MSK_ANC (1<<11) +#define BIT_MISR_MSK_RF (1<<12) +#define BIT_MISR_MSK_JAB (1<<13) +#define BIT_MISR_MSK_LNK (1<<14) +#define BIT_MISR_MINT (1<<15) +#define REG_PGSEL 51 +#define REG_FCSCR 52 +#define REG_RECR 53 +#define REG_PCSR 54 +#define BIT_PCSR_NRZI (1<<2) +#define BIT_PCSR_FORCE_100 (1<<5) +#define BIT_PCSR_SDOPT (1<<8) +#define BIT_PCSR_SDFORCE (1<<9) +#define BIT_PCSR_TQM (1<<10) +#define BIT_PCSR_CLK (1<<11) +#define BIT_PCSR_4B5B (1<<12) +#define REG_PHYCR 57 +#define BIT_PHYCR_PHYADDR (0x1f<<0) +#define BIT_PHYCR_PAUSE_STS (1<<7) +#define BIT_PHYCR_STRETCH (1<<8) +#define BIT_PHYCR_BIST (1<<9) +#define BIT_PHYCR_BIST_STAT (1<<10) +#define BIT_PHYCR_PSR15 (1<<11) +#define REG_TBTSCR 58 +#define BIT_TBTSCR_JAB (1<<0) +#define BIT_TBTSCR_BEAT (1<<1) +#define BIT_TBTSCR_AUTOPOL (1<<3) +#define BIT_TBTSCR_POL (1<<4) +#define BIT_TBTSCR_FPOL (1<<5) +#define BIT_TBTSCR_FORCE_10 (1<<6) +#define BIT_TBTSCR_PULSE (1<<7) +#define BIT_TBTSCR_LOOP (1<<8) +#define REG_PMDCSR 64 +#define REG_TSTDAT 65 +#define REG_DSPCFG 66 +#define REG_SDCFG 67 +#define REG_PMATCH0 68 +#define REG_PMATCH1 69 +#define REG_PMATCH2 70 +#define REG_PCOUNT0 71 +#define REG_PCOUNT1 72 +#define REG_SOPASS0 73 +#define REG_SOPASS1 74 +#define REG_SOPASS2 75 + +static void __print_intr(int d, int intr, const char *name, + const char *s1, const char *s2) +{ + if ((d) & intr) + fprintf(stdout, " %s Interrupt: %s\n", name, s1); + else if (s2) + fprintf(stdout, " %s Interrupt: %s\n", name, s2); +} + +#define PRINT_INTR(d, i, s1, s2) do { \ + int intr = BIT_INTR_ ## i; \ + const char *name = NAME_INTR_ ## i; \ + __print_intr(d, intr, name, s1, s2); \ +} while (0) + +#define PRINT_INTRS(d, s1, s2) do { \ + PRINT_INTR((d), RXOK, s1, s2); \ + PRINT_INTR((d), RXDESC, s1, s2); \ + PRINT_INTR((d), RXERR, s1, s2); \ + PRINT_INTR((d), RXEARLY, s1, s2); \ + PRINT_INTR((d), RXIDLE, s1, s2); \ + PRINT_INTR((d), RXORN, s1, s2); \ + PRINT_INTR((d), TXOK, s1, s2); \ + PRINT_INTR((d), TXDESC, s1, s2); \ + PRINT_INTR((d), TXERR, s1, s2); \ + PRINT_INTR((d), TXIDLE, s1, s2); \ + PRINT_INTR((d), TXURN, s1, s2); \ + PRINT_INTR((d), MIB, s1, s2); \ + PRINT_INTR((d), SWI, s1, s2); \ + PRINT_INTR((d), PME, s1, s2); \ + PRINT_INTR((d), PHY, s1, s2); \ + PRINT_INTR((d), HIBERR, s1, s2); \ + PRINT_INTR((d), RXSOVR, s1, s2); \ + PRINT_INTR((d), RTABT, s1, s2); \ + PRINT_INTR((d), RMABT, s1, s2); \ + PRINT_INTR((d), SSERR, s1, s2); \ + PRINT_INTR((d), DPERR, s1, s2); \ + PRINT_INTR((d), RXRCMP, s1, s2); \ + PRINT_INTR((d), TXRCMP, s1, s2); \ +} while (0) + +int +natsemi_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *data = (u32 *)regs->data; + u32 tmp; + + fprintf(stdout, "Mac/BIU Registers\n"); + fprintf(stdout, "-----------------\n"); + + /* command register */ + fprintf(stdout, + "0x00: CR (Command): 0x%08x\n", + data[REG_CR]); + fprintf(stdout, + " Transmit %s\n" + " Receive %s\n", + data[REG_CR] & BIT_CR_TXE ? "Active" : "Idle", + data[REG_CR] & BIT_CR_RXE ? "Active" : "Idle"); + if (data[REG_CR] & BIT_CR_RST) fprintf(stdout, + " Reset In Progress\n"); + + /* configuration register */ + fprintf(stdout, + "0x04: CFG (Configuration): 0x%08x\n", + data[REG_CFG]); + fprintf(stdout, + " %s Endian\n" + " Boot ROM %s\n" + " Internal Phy %s\n" + " Phy Reset %s\n" + " External Phy %s\n" + " Default Auto-Negotiation %s, %s %s Mb %s Duplex\n" + " Phy Interrupt %sAuto-Cleared\n" + " Phy Configuration = 0x%02x\n" + " Auto-Negotiation %s\n" + " %s Polarity\n" + " %s Duplex\n" + " %d Mb/s\n" + " Link %s\n", + data[REG_CFG] & BIT_CFG_BEM ? "Big" : "Little", + data[REG_CFG] & BIT_CFG_BROM_DIS ? "Disabled" : "Enabled", + data[REG_CFG] & BIT_CFG_PHY_DIS ? "Disabled" : "Enabled", + data[REG_CFG] & BIT_CFG_PHY_RST ? "In Progress" : "Idle", + data[REG_CFG] & BIT_CFG_EXT_PHY ? "Enabled" : "Disabled", + data[REG_CFG] & BIT_CFG_ANEG_EN ? "Enabled" : "Disabled", + data[REG_CFG] & BIT_CFG_ANEG_EN ? "Advertise" : "Force", + data[REG_CFG] & BIT_CFG_ANEG_100 ? + (data[REG_CFG] & BIT_CFG_ANEG_EN ? "10/100" : "100") + : "10", + data[REG_CFG] & BIT_CFG_ANEG_FDUP ? + (data[REG_CFG] & BIT_CFG_ANEG_EN ? "Half/Full" : "Full") + : "Half", + data[REG_CFG] & BIT_CFG_PINT_ACEN ? "" : "Not ", + data[REG_CFG] & BIT_CFG_PHY_CFG >> 18, + data[REG_CFG] & BIT_CFG_ANEG_DN ? "Done" : "Not Done", + data[REG_CFG] & BIT_CFG_POL ? "Reversed" : "Normal", + data[REG_CFG] & BIT_CFG_FDUP ? "Full" : "Half", + data[REG_CFG] & BIT_CFG_SPEED100 ? 100 : 10, + data[REG_CFG] & BIT_CFG_LNKSTS ? "Up" : "Down"); + + /* EEPROM access register */ + fprintf(stdout, + "0x08: MEAR (EEPROM Access): 0x%08x\n", + data[REG_MEAR]); + + /* PCI test control register */ + fprintf(stdout, + "0x0c: PTSCR (PCI Test Control): 0x%08x\n", + data[REG_PTSCR]); + fprintf(stdout, + " EEPROM Self Test %s\n" + " Rx Filter Self Test %s\n" + " Tx FIFO Self Test %s\n" + " Rx FIFO Self Test %s\n", + data[REG_PTSCR] & BIT_PTSCR_EEBIST_FAIL ? "Failed" : "Passed", + data[REG_PTSCR] & BIT_PTSCR_RBIST_RXFFAIL ? "Failed" : "Passed", + data[REG_PTSCR] & BIT_PTSCR_RBIST_TXFAIL ? "Failed" : "Passed", + data[REG_PTSCR] & BIT_PTSCR_RBIST_RXFAIL ? "Failed" : "Passed"); + if (data[REG_PTSCR] & BIT_PTSCR_EELOAD_EN) fprintf(stdout, + " EEPROM Reload In Progress\n"); + + /* Interrupt status register */ + fprintf(stdout, + "0x10: ISR (Interrupt Status): 0x%08x\n", + data[REG_ISR]); + if (data[REG_ISR]) + PRINT_INTRS(data[REG_ISR], "Active", (char *)NULL); + else + fprintf(stdout, " No Interrupts Active\n"); + + /* Interrupt mask register */ + fprintf(stdout, + "0x14: IMR (Interrupt Mask): 0x%08x\n", + data[REG_IMR]); + PRINT_INTRS(data[REG_IMR], "Enabled", "Masked"); + + /* Interrupt enable register */ + fprintf(stdout, + "0x18: IER (Interrupt Enable): 0x%08x\n", + data[REG_IER]); + fprintf(stdout, + " Interrupts %s\n", + data[REG_IER] & BIT_IER_IE ? "Enabled" : "Disabled"); + + /* Tx descriptor pointer register */ + fprintf(stdout, + "0x20: TXDP (Tx Descriptor Pointer): 0x%08x\n", + data[REG_TXDP]); + + /* Tx configuration register */ + fprintf(stdout, + "0x24: TXCFG (Tx Config): 0x%08x\n", + data[REG_TXCFG]); + tmp = (data[REG_TXCFG] & BIT_TXCFG_MXDMA)>>20; + fprintf(stdout, + " Drain Threshhold = %d bytes (%d)\n" + " Fill Threshhold = %d bytes (%d)\n" + " Max DMA Burst per Tx = %d bytes\n" + " Automatic Tx Padding %s\n" + " Mac Loopback %s\n" + " Heartbeat Ignore %s\n" + " Carrier Sense Ignore %s\n", + (data[REG_TXCFG] & BIT_TXCFG_DRTH) * 32, + data[REG_TXCFG] & BIT_TXCFG_DRTH, + ((data[REG_TXCFG] & BIT_TXCFG_FLTH)>>8) * 32, + data[REG_TXCFG] & BIT_TXCFG_FLTH, + tmp ? (1<<(tmp-1))*4 : 512, + data[REG_TXCFG] & BIT_TXCFG_ATP ? "Enabled" : "Disabled", + data[REG_TXCFG] & BIT_TXCFG_MLB ? "Enabled" : "Disabled", + data[REG_TXCFG] & BIT_TXCFG_HBI ? "Enabled" : "Disabled", + data[REG_TXCFG] & BIT_TXCFG_CSI ? "Enabled" : "Disabled"); + + + /* Rx descriptor pointer register */ + fprintf(stdout, + "0x30: RXDP (Rx Descriptor Pointer): 0x%08x\n", + data[REG_RXDP]); + + /* Rx configuration register */ + fprintf(stdout, + "0x34: RXCFG (Rx Config): 0x%08x\n", + data[REG_RXCFG]); + tmp = (data[REG_RXCFG] & BIT_RXCFG_MXDMA)>>20; + fprintf(stdout, + " Drain Threshhold = %d bytes (%d)\n" + " Max DMA Burst per Rx = %d bytes\n" + " Long Packets %s\n" + " Tx Packets %s\n" + " Runt Packets %s\n" + " Error Packets %s\n", + ((data[REG_RXCFG] & BIT_RXCFG_DRTH) >> 1) * 8, + (data[REG_RXCFG] & BIT_RXCFG_DRTH) >> 1, + tmp ? (1<<(tmp-1))*4 : 512, + data[REG_RXCFG] & BIT_RXCFG_ALP ? "Accepted" : "Rejected", + data[REG_RXCFG] & BIT_RXCFG_ATX ? "Accepted" : "Rejected", + data[REG_RXCFG] & BIT_RXCFG_ARP ? "Accepted" : "Rejected", + data[REG_RXCFG] & BIT_RXCFG_AEP ? "Accepted" : "Rejected"); + + /* CLKRUN control/status register */ + fprintf(stdout, + "0x3c: CCSR (CLKRUN Control/Status): 0x%08x\n", + data[REG_CCSR]); + fprintf(stdout, + " CLKRUNN %s\n" + " Power Management %s\n", + data[REG_CCSR] & BIT_CCSR_CLKRUN_EN ? "Enabled" : "Disabled", + data[REG_CCSR] & BIT_CCSR_PMEEN ? "Enabled" : "Disabled"); + if (data[REG_CCSR] & BIT_CCSR_PMESTS) fprintf(stdout, + " Power Management Event Pending\n"); + + /* WoL control/status register */ + fprintf(stdout, + "0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x\n", + data[REG_WCSR]); + if (data[REG_WCSR] & BIT_WCSR_WKPHY) fprintf(stdout, + " Wake on Phy Interrupt Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKUCP) fprintf(stdout, + " Wake on Unicast Packet Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKMCP) fprintf(stdout, + " Wake on Multicast Packet Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKBCP) fprintf(stdout, + " Wake on Broadcast Packet Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKARP) fprintf(stdout, + " Wake on Arp Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKPAT0) fprintf(stdout, + " Wake on Pattern 0 Match Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKPAT1) fprintf(stdout, + " Wake on Pattern 1 Match Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKPAT2) fprintf(stdout, + " Wake on Pattern 2 Match Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKPAT3) fprintf(stdout, + " Wake on Pattern 3 Match Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_WKMAG) fprintf(stdout, + " Wake on Magic Packet Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_MPSOE) fprintf(stdout, + " Magic Packet SecureOn Enabled\n"); + if (data[REG_WCSR] & BIT_WCSR_SOHACK) fprintf(stdout, + " SecureOn Hack Detected\n"); + if (data[REG_WCSR] & BIT_WCSR_PHYINT) fprintf(stdout, + " Phy Interrupt Received\n"); + if (data[REG_WCSR] & BIT_WCSR_UCASTR) fprintf(stdout, + " Unicast Packet Received\n"); + if (data[REG_WCSR] & BIT_WCSR_MCASTR) fprintf(stdout, + " Multicast Packet Received\n"); + if (data[REG_WCSR] & BIT_WCSR_BCASTR) fprintf(stdout, + " Broadcast Packet Received\n"); + if (data[REG_WCSR] & BIT_WCSR_ARPR) fprintf(stdout, + " Arp Received\n"); + if (data[REG_WCSR] & BIT_WCSR_PATM0) fprintf(stdout, + " Pattern 0 Received\n"); + if (data[REG_WCSR] & BIT_WCSR_PATM1) fprintf(stdout, + " Pattern 1 Received\n"); + if (data[REG_WCSR] & BIT_WCSR_PATM2) fprintf(stdout, + " Pattern 2 Received\n"); + if (data[REG_WCSR] & BIT_WCSR_PATM3) fprintf(stdout, + " Pattern 3 Received\n"); + if (data[REG_WCSR] & BIT_WCSR_MPR) fprintf(stdout, + " Magic Packet Received\n"); + + /* Pause control/status register */ + fprintf(stdout, + "0x44: PCR (Pause Control/Status): 0x%08x\n", + data[REG_PCR]); + fprintf(stdout, + " Pause Counter = %d\n" + " Pause %sNegotiated\n" + " Pause on DA %s\n" + " Pause on Mulitcast %s\n" + " Pause %s\n", + data[REG_PCR] & BIT_PCR_PAUSE_CNT, + data[REG_PCR] & BIT_PCR_PSNEG ? "" : "Not ", + data[REG_PCR] & BIT_PCR_PS_DA ? "Enabled" : "Disabled", + data[REG_PCR] & BIT_PCR_PSMCAST ? "Enabled" : "Disabled", + data[REG_PCR] & BIT_PCR_PSEN ? "Enabled" : "Disabled"); + if (data[REG_PCR] & BIT_PCR_PS_RCVD) fprintf(stdout, + " PS_RCVD: Pause Frame Received\n"); + + /* Rx Filter Control */ + fprintf(stdout, + "0x48: RFCR (Rx Filter Control): 0x%08x\n", + data[REG_RFCR]); + fprintf(stdout, + " Unicast Hash %s\n" + " Multicast Hash %s\n" + " Arp %s\n" + " Pattern 0 Match %s\n" + " Pattern 1 Match %s\n" + " Pattern 2 Match %s\n" + " Pattern 3 Match %s\n" + " Perfect Match %s\n" + " All Unicast %s\n" + " All Multicast %s\n" + " All Broadcast %s\n" + " Rx Filter %s\n", + data[REG_RFCR] & BIT_RFCR_UHEN ? "Enabled" : "Disabled", + data[REG_RFCR] & BIT_RFCR_MHEN ? "Enabled" : "Disabled", + data[REG_RFCR] & BIT_RFCR_AARP ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_APAT0 ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_APAT1 ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_APAT2 ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_APAT3 ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_APM ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_AAU ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_AAM ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_AAB ? "Accepted" : "Rejected", + data[REG_RFCR] & BIT_RFCR_RFEN ? "Enabled" : "Disabled"); + + /* Rx filter data register */ + fprintf(stdout, + "0x4c: RFDR (Rx Filter Data): 0x%08x\n", + data[REG_RFDR]); + if (regs->version >= 1) fprintf(stdout, + " PMATCH 1-0 = 0x%08x\n" + " PMATCH 3-2 = 0x%08x\n" + " PMATCH 5-4 = 0x%08x\n" + " PCOUNT 1-0 = 0x%08x\n" + " PCOUNT 3-2 = 0x%08x\n" + " SOPASS 1-0 = 0x%08x\n" + " SOPASS 3-2 = 0x%08x\n" + " SOPASS 5-4 = 0x%08x\n", + data[REG_PMATCH0], data[REG_PMATCH1], data[REG_PMATCH2], + data[REG_PCOUNT0], data[REG_PCOUNT1], + data[REG_SOPASS0], data[REG_SOPASS1], data[REG_SOPASS2]); + + + /* Boot ROM address register */ + fprintf(stdout, + "0x50: BRAR (Boot ROM Address): 0x%08x\n", + data[REG_BRAR]); + if (data[REG_BRAR] & BIT_BRAR_AUTOINC) fprintf(stdout, + " Automatically Increment Address\n"); + + /* Boot ROM data register */ + fprintf(stdout, + "0x54: BRDR (Boot ROM Data): 0x%08x\n", + data[REG_BRDR]); + + /* Silicon revison register */ + fprintf(stdout, + "0x58: SRR (Silicon Revision): 0x%08x\n", + data[REG_SRR]); + + /* Management information base control register */ + fprintf(stdout, + "0x5c: MIBC (Mgmt Info Base Control): 0x%08x\n", + data[REG_MIBC]); + if (data[REG_MIBC] & BIT_MIBC_WRN) fprintf(stdout, + " Counter Overflow Warning\n"); + if (data[REG_MIBC] & BIT_MIBC_FRZ) fprintf(stdout, + " Counters Frozen\n"); + + /* MIB registers */ + fprintf(stdout, + "0x60: MIB[0] (Rx Errored Packets): 0x%04x\n", + data[REG_MIB0]); + fprintf(stdout, " Value = %d\n", data[REG_MIB0]); + fprintf(stdout, + "0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x\n", + data[REG_MIB1]); + fprintf(stdout, " Value = %d\n", data[REG_MIB1]); + fprintf(stdout, + "0x68: MIB[2] (Rx Missed Packets): 0x%02x\n", + data[REG_MIB2]); + fprintf(stdout, " Value = %d\n", data[REG_MIB2]); + fprintf(stdout, + "0x6c: MIB[3] (Rx Alignment Errors): 0x%02x\n", + data[REG_MIB3]); + fprintf(stdout, " Value = %d\n", data[REG_MIB3]); + fprintf(stdout, + "0x70: MIB[4] (Rx Symbol Errors): 0x%02x\n", + data[REG_MIB4]); + fprintf(stdout, " Value = %d\n", data[REG_MIB4]); + fprintf(stdout, + "0x74: MIB[5] (Rx Long Frame Errors): 0x%02x\n", + data[REG_MIB5]); + fprintf(stdout, " Value = %d\n", data[REG_MIB5]); + fprintf(stdout, + "0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x\n", + data[REG_MIB6]); + fprintf(stdout, " Value = %d\n", data[REG_MIB6]); + + fprintf(stdout, "\n"); + fprintf(stdout, "Internal Phy Registers\n"); + fprintf(stdout, "----------------------\n"); + + /* Basic mode control register */ + fprintf(stdout, + "0x80: BMCR (Basic Mode Control): 0x%04x\n", + data[REG_BMCR]); + fprintf(stdout, + " %s Duplex\n" + " Port is Powered %s\n" + " Auto-Negotiation %s\n" + " %d Mb/s\n", + data[REG_BMCR] & BIT_BMCR_FDUP ? "Full" : "Half", + data[REG_BMCR] & BIT_BMCR_PDOWN ? "Down" : "Up", + data[REG_BMCR] & BIT_BMCR_ANEN ? "Enabled" : "Disabled", + data[REG_BMCR] & BIT_BMCR_SPEED ? 100 : 10); + if (data[REG_BMCR] & BIT_BMCR_ANRST) fprintf(stdout, + " Auto-Negotiation Restarting\n"); + if (data[REG_BMCR] & BIT_BMCR_ISOL) fprintf(stdout, + " Port Isolated\n"); + if (data[REG_BMCR] & BIT_BMCR_LOOP) fprintf(stdout, + " Loopback Enabled\n"); + if (data[REG_BMCR] & BIT_BMCR_RST) fprintf(stdout, + " Reset In Progress\n"); + + /* Basic mode status register */ + fprintf(stdout, + "0x84: BMSR (Basic Mode Status): 0x%04x\n", + data[REG_BMSR]); + fprintf(stdout, + " Link %s\n" + " %sCapable of Auto-Negotiation\n" + " Auto-Negotiation %sComplete\n" + " %sCapable of Preamble Suppression\n" + " %sCapable of 10Base-T Half Duplex\n" + " %sCapable of 10Base-T Full Duplex\n" + " %sCapable of 100Base-TX Half Duplex\n" + " %sCapable of 100Base-TX Full Duplex\n" + " %sCapable of 100Base-T4\n", + data[REG_BMSR] & BIT_BMSR_LNK ? "Up" : "Down", + data[REG_BMSR] & BIT_BMSR_ANCAP ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_ANDONE ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_PREAMBLE ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_10HCAP ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_10FCAP ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_100HCAP ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_100FCAP ? "" : "Not ", + data[REG_BMSR] & BIT_BMSR_100T4CAP ? "" : "Not "); + if (data[REG_BMSR] & BIT_BMSR_JABBER) fprintf(stdout, + " Jabber Condition Detected\n"); + if (data[REG_BMSR] & BIT_BMSR_RFAULT) fprintf(stdout, + " Remote Fault Detected\n"); + + /* PHY identification registers */ + fprintf(stdout, + "0x88: PHYIDR1 (PHY ID #1): 0x%04x\n", + data[REG_PHYIDR1]); + fprintf(stdout, + "0x8c: PHYIDR2 (PHY ID #2): 0x%04x\n", + data[REG_PHYIDR2]); + fprintf(stdout, + " OUI = 0x%06x\n" + " Model = 0x%02x (%d)\n" + " Revision = 0x%01x (%d)\n", + (data[REG_PHYIDR1] << 6) | (data[REG_PHYIDR2] >> 10), + (data[REG_PHYIDR2] & BIT_PHYIDR2_MODEL) >> 4 & 0x3f, + (data[REG_PHYIDR2] & BIT_PHYIDR2_MODEL) >> 4 & 0x3f, + data[REG_PHYIDR2] & BIT_PHYIDR2_REV, + data[REG_PHYIDR2] & BIT_PHYIDR2_REV); + + /* autonegotiation advertising register */ + fprintf(stdout, + "0x90: ANAR (Autoneg Advertising): 0x%04x\n", + data[REG_ANAR]); + fprintf(stdout, + " Protocol Selector = 0x%02x (%d)\n", + data[REG_ANAR] & BIT_ANAR_PROTO, + data[REG_ANAR] & BIT_ANAR_PROTO); + if (data[REG_ANAR] & BIT_ANAR_10) fprintf(stdout, + " Advertising 10Base-T Half Duplex\n"); + if (data[REG_ANAR] & BIT_ANAR_10_FD) fprintf(stdout, + " Advertising 10Base-T Full Duplex\n"); + if (data[REG_ANAR] & BIT_ANAR_TX) fprintf(stdout, + " Advertising 100Base-TX Half Duplex\n"); + if (data[REG_ANAR] & BIT_ANAR_TXFD) fprintf(stdout, + " Advertising 100Base-TX Full Duplex\n"); + if (data[REG_ANAR] & BIT_ANAR_T4) fprintf(stdout, + " Advertising 100Base-T4\n"); + if (data[REG_ANAR] & BIT_ANAR_PAUSE) fprintf(stdout, + " Advertising Pause\n"); + if (data[REG_ANAR] & BIT_ANAR_RF) fprintf(stdout, + " Indicating Remote Fault\n"); + if (data[REG_ANAR] & BIT_ANAR_NP) fprintf(stdout, + " Next Page Desired\n"); + + /* Autonegotiation link partner ability register */ + fprintf(stdout, + "0x94: ANLPAR (Autoneg Partner): 0x%04x\n", + data[REG_ANLPAR]); + fprintf(stdout, + " Protocol Selector = 0x%02x (%d)\n", + data[REG_ANLPAR] & BIT_ANLPAR_PROTO, + data[REG_ANLPAR] & BIT_ANLPAR_PROTO); + if (data[REG_ANLPAR] & BIT_ANLPAR_10) fprintf(stdout, + " Supports 10Base-T Half Duplex\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_10_FD) fprintf(stdout, + " Supports 10Base-T Full Duplex\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_TX) fprintf(stdout, + " Supports 100Base-TX Half Duplex\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_TXFD) fprintf(stdout, + " Supports 100Base-TX Full Duplex\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_T4) fprintf(stdout, + " Supports 100Base-T4\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_PAUSE) fprintf(stdout, + " Supports Pause\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_RF) fprintf(stdout, + " Indicates Remote Fault\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_ACK) fprintf(stdout, + " Indicates Acknowledgement\n"); + if (data[REG_ANLPAR] & BIT_ANLPAR_NP) fprintf(stdout, + " Next Page Desired\n"); + + /* Autonegotiation expansion register */ + fprintf(stdout, + "0x98: ANER (Autoneg Expansion): 0x%04x\n", + data[REG_ANER]); + fprintf(stdout, + " Link Partner Can %sAuto-Negotiate\n" + " Link Code Word %sReceived\n" + " Next Page %sSupported\n" + " Link Partner Next Page %sSupported\n", + data[REG_ANER] & BIT_ANER_LP_AN_ENABLE ? "" : "Not ", + data[REG_ANER] & BIT_ANER_PAGE_RX ? "" : "Not ", + data[REG_ANER] & BIT_ANER_NP_ABLE ? "" : "Not ", + data[REG_ANER] & BIT_ANER_LP_NP_ABLE ? "" : "Not "); + if (data[REG_ANER] & BIT_ANER_PDF) fprintf(stdout, + " Parallel Detection Fault\n"); + + /* Autonegotiation next-page tx register */ + fprintf(stdout, + "0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x\n", + data[REG_ANNPTR]); + + /* Phy status register */ + fprintf(stdout, + "0xc0: PHYSTS (Phy Status): 0x%04x\n", + data[REG_PHYSTS]); + fprintf(stdout, + " Link %s\n" + " %d Mb/s\n" + " %s Duplex\n" + " Auto-Negotiation %sComplete\n" + " %s Polarity\n", + data[REG_PHYSTS] & BIT_PHYSTS_LNK ? "Up" : "Down", + data[REG_PHYSTS] & BIT_PHYSTS_SPD10 ? 10 : 100, + data[REG_PHYSTS] & BIT_PHYSTS_FDUP ? "Full" : "Half", + data[REG_PHYSTS] & BIT_PHYSTS_ANDONE ? "" : "Not ", + data[REG_PHYSTS] & BIT_PHYSTS_POL ? "Reverse" : "Normal"); + if (data[REG_PHYSTS] & BIT_PHYSTS_LOOP) fprintf(stdout, + " Loopback Enabled\n"); + if (data[REG_PHYSTS] & BIT_PHYSTS_JABBER) fprintf(stdout, + " Jabber Condition Detected\n"); + if (data[REG_PHYSTS] & BIT_PHYSTS_RF) fprintf(stdout, + " Remote Fault Detected\n"); + if (data[REG_PHYSTS] & BIT_PHYSTS_MINT) fprintf(stdout, + " MII Interrupt Detected\n"); + if (data[REG_PHYSTS] & BIT_PHYSTS_FC) fprintf(stdout, + " False Carrier Detected\n"); + if (data[REG_PHYSTS] & BIT_PHYSTS_RXERR) fprintf(stdout, + " Rx Error Detected\n"); + + fprintf(stdout, + "0xc4: MICR (MII Interrupt Control): 0x%04x\n", + data[REG_MICR]); + fprintf(stdout, + " MII Interrupts %s\n", + data[REG_MICR] & BIT_MICR_INTEN ? "Enabled" : "Disabled"); + + fprintf(stdout, + "0xc8: MISR (MII Interrupt Status): 0x%04x\n", + data[REG_MISR]); + fprintf(stdout, + " Rx Error Counter Half-Full Interrupt %s\n" + " False Carrier Counter Half-Full Interrupt %s\n" + " Auto-Negotiation Complete Interrupt %s\n" + " Remote Fault Interrupt %s\n" + " Jabber Interrupt %s\n" + " Link Change Interrupt %s\n", + data[REG_MISR] & BIT_MISR_MSK_RHF ? "Masked" : "Enabled", + data[REG_MISR] & BIT_MISR_MSK_FHF ? "Masked" : "Enabled", + data[REG_MISR] & BIT_MISR_MSK_ANC ? "Masked" : "Enabled", + data[REG_MISR] & BIT_MISR_MSK_RF ? "Masked" : "Enabled", + data[REG_MISR] & BIT_MISR_MSK_JAB ? "Masked" : "Enabled", + data[REG_MISR] & BIT_MISR_MSK_LNK ? "Masked" : "Enabled"); + if (data[REG_MISR] & BIT_MISR_MINT) fprintf(stdout, + " MII Interrupt Pending\n"); + + /* Page select register (from section of spec on 'suggested values') */ + fprintf(stdout, + "0xcc: PGSEL (Phy Register Page Select): 0x%04x\n", + data[REG_PGSEL]); + + /* counters */ + fprintf(stdout, + "0xd0: FCSCR (False Carrier Counter): 0x%04x\n", + data[REG_FCSCR]); + fprintf(stdout, + " Value = %d\n", data[REG_FCSCR] & 0xff); + fprintf(stdout, + "0xd4: RECR (Rx Error Counter): 0x%04x\n", + data[REG_RECR]); + fprintf(stdout, + " Value = %d\n", data[REG_RECR] & 0xff); + + /* 100 Mbit configuration register */ + fprintf(stdout, + "0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x\n", + data[REG_PCSR]); + fprintf(stdout, + " NRZI Bypass %s\n" + " %s Signal Detect Algorithm\n" + " %s Signal Detect Operation\n" + " True Quiet Mode %s\n" + " Rx Clock is %s\n" + " 4B/5B Operation %s\n", + data[REG_PCSR] & BIT_PCSR_NRZI ? "Enabled" : "Disabled", + data[REG_PCSR] & BIT_PCSR_SDOPT ? "Enhanced" : "Reduced", + data[REG_PCSR] & BIT_PCSR_SDFORCE ? "Forced" : "Normal", + data[REG_PCSR] & BIT_PCSR_TQM ? "Enabled" : "Disabled", + data[REG_PCSR] & BIT_PCSR_CLK ? + "Free-Running" : "Phase-Adjusted", + data[REG_PCSR] & BIT_PCSR_4B5B ? "Bypassed" : "Normal"); + if (data[REG_PCSR] & BIT_PCSR_FORCE_100) fprintf(stdout, + " Forced 100 Mb/s Good Link\n"); + + /* Phy control register */ + fprintf(stdout, + "0xe4: PHYCR (Phy Control): 0x%04x\n", + data[REG_PHYCR]); + fprintf(stdout, + " Phy Address = 0x%x (%d)\n" + " %sPause Compatible with Link Partner\n" + " LED Stretching %s\n" + " Phy Self Test %s\n" + " Self Test Sequence = PSR%d\n", + data[REG_PHYCR] & BIT_PHYCR_PHYADDR, + data[REG_PHYCR] & BIT_PHYCR_PHYADDR, + data[REG_PHYCR] & BIT_PHYCR_PAUSE_STS ? "" : "Not ", + data[REG_PHYCR] & BIT_PHYCR_STRETCH ? "Bypassed" : "Enabled", + data[REG_PHYCR] & BIT_PHYCR_BIST ? "In Progress" : + data[REG_PHYCR] & BIT_PHYCR_BIST_STAT ? + "Passed" : "Failed or Not Run", + data[REG_PHYCR] & BIT_PHYCR_PSR15 ? 15 : 9); + + + /* 10 Mbit control and status register */ + fprintf(stdout, + "0xe8: TBTSCR (10Base-T Status/Control): 0x%04x\n", + data[REG_TBTSCR]); + fprintf(stdout, + " Jabber %s\n" + " Heartbeat %s\n" + " Polarity Auto-Sense/Correct %s\n" + " %s Polarity %s\n" + " Normal Link Pulse %s\n" + " 10 Mb/s Loopback %s\n", + data[REG_TBTSCR] & BIT_TBTSCR_JAB ? "Disabled" : "Enabled", + data[REG_TBTSCR] & BIT_TBTSCR_BEAT ? "Disabled" : "Enabled", + data[REG_TBTSCR] & BIT_TBTSCR_AUTOPOL ? "Disabled" : "Enabled", + data[REG_TBTSCR] & BIT_TBTSCR_AUTOPOL ? + data[REG_TBTSCR]&BIT_TBTSCR_FPOL ? "Reverse":"Normal" : + data[REG_TBTSCR]&BIT_TBTSCR_POL ? "Reverse":"Normal", + data[REG_TBTSCR] & BIT_TBTSCR_AUTOPOL ? "Forced" : "Detected", + data[REG_TBTSCR] & BIT_TBTSCR_PULSE ? "Disabled" : "Enabled", + data[REG_TBTSCR] & BIT_TBTSCR_LOOP ? "Enabled" : "Disabled"); + if (data[REG_TBTSCR] & BIT_TBTSCR_FORCE_10) fprintf(stdout, + " Forced 10 Mb/s Good Link\n"); + + /* the spec says to set these */ + fprintf(stdout, "\n"); + fprintf(stdout, "'Magic' Phy Registers\n"); + fprintf(stdout, "---------------------\n"); + fprintf(stdout, + "0xe4: PMDCSR: 0x%04x\n", + data[REG_PMDCSR]); + fprintf(stdout, + "0xf4: DSPCFG: 0x%04x\n", + data[REG_DSPCFG]); + fprintf(stdout, + "0xf8: SDCFG: 0x%04x\n", + data[REG_SDCFG]); + fprintf(stdout, + "0xfc: TSTDAT: 0x%04x\n", + data[REG_TSTDAT]); + + return 0; +} + +int +natsemi_dump_eeprom(struct ethtool_drvinfo *info, struct ethtool_eeprom *ee) +{ + int i; + u16 *eebuf = (u16 *)ee->data; + + if (ee->magic != NATSEMI_MAGIC) { + fprintf(stderr, "Magic number 0x%08x does not match 0x%08x\n", + ee->magic, NATSEMI_MAGIC); + return -1; + } + + fprintf(stdout, "Address\tData\n"); + fprintf(stdout, "-------\t------\n"); + for (i = 0; i < ee->len/2; i++) { + fprintf(stdout, "0x%02x \t0x%04x\n", i + ee->offset, eebuf[i]); + } + + return 0; +} +
diff --git a/ethtool-2.6.35/pcnet32.c b/ethtool-2.6.35/pcnet32.c new file mode 100644 index 0000000..1dac02d --- /dev/null +++ b/ethtool-2.6.35/pcnet32.c
@@ -0,0 +1,249 @@ +/* Copyright 2004 IBM Corporation (jklewis@us.ibm.com) */ + +#include <stdio.h> +#include <stdlib.h> +#include "ethtool-util.h" + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +int pcnet32_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + int i, csr; + u16 *data = (u16 *) regs->data; + int len = regs->len / 2; + u16 temp,*ptr; + + printf("Driver: %s\n",info->driver); + printf("Version: %s\n",info->version); + + printf("APROM: "); + for (i=0; i<8; i++) + printf(" %04x ", data[i]); + printf("\n"); + + csr = i; + for (; i<100; i++) + { + if (((i-csr) & 7) == 0) printf("CSR%02d: ", i-csr); + printf(" %04x ", data[i]); + if (((i-csr) & 7) == 7) printf("\n"); + } + if (((i-csr) & 7) != 7) printf("\n"); + + csr = i; + for (; i<136; i++) + { + if (((i-csr) & 7) == 0) printf("BCR%02d: ", i-csr); + printf(" %04x ", data[i]); + if (((i-csr) & 7) == 7) printf("\n"); + } + if (((i-csr) & 7) != 7) printf("\n"); + + csr = i; + for (; i<len; i++) + { + if (((i-csr) & 7) == 0) printf("MII%02d: ", (i-csr) & 0x1f); + printf(" %04x ", data[i]); + if (((i-csr) & 7) == 7) printf("\n"); + } + if (((i-csr) & 7) != 7) printf("\n"); + printf("\n"); + + ptr=&data[8]; /* start of the CSRs */ + + printf("CSR0: Status and Control 0x%04x\n ",ptr[0]); + temp=ptr[0]; + + if(temp & BIT15) printf("ERR "); + if(temp & BIT14) printf("BABL "); + if(temp & BIT13) printf("CERR "); + if(temp & BIT12) printf("MISS "); + if(temp & BIT11) printf("MERR "); + if(temp & BIT10) printf("RINT "); + if(temp & BIT9) printf("TINT "); + if(temp & BIT8) printf("IDON "); + if(temp & BIT7) printf("INTR "); + if(temp & BIT6) printf("INT "); + if(temp & BIT5) printf("RXON "); + if(temp & BIT4) printf("TXON "); + if(temp & BIT3) printf("TDMD "); + if(temp & BIT2) printf("STOP "); + if(temp & BIT1) printf("STRT "); + if(temp & BIT0) printf("INIT "); + + printf("\n"); + + printf("CSR3: Interrupt Mask 0x%04x\n ",ptr[3]); + temp=ptr[3]; + + if(temp & BIT14) printf("BABLM "); + if(temp & BIT12) printf("MISSM "); + if(temp & BIT11) printf("MERRM "); + if(temp & BIT10) printf("RINTM "); + if(temp & BIT9) printf("TINTM "); + if(temp & BIT8) printf("IDONM "); + if(temp & BIT6) printf("DXSUFLO "); + if(temp & BIT5) printf("LAPPEN "); + if(temp & BIT4) printf("DXMT2PD "); + if(temp & BIT3) printf("EMBA "); + if(temp & BIT2) printf("BSWP "); + + printf("\n"); + + printf("CSR4: Test and Features 0x%04x\n ",ptr[4]); + temp=ptr[4]; + + if(temp & BIT15) printf("EN124 "); + if(temp & BIT14) printf("DMAPLUS "); + if(temp & BIT12) printf("TXDPOLL "); + if(temp & BIT11) printf("APAD_XMT "); + if(temp & BIT10) printf("ASTRP_RCV "); + if(temp & BIT9) printf("MFCO "); + if(temp & BIT8) printf("MFCON "); + if(temp & BIT7) printf("UINTCMD "); + if(temp & BIT6) printf("UINT "); + if(temp & BIT5) printf("RCVCCO "); + if(temp & BIT4) printf("RCVCCOM "); + if(temp & BIT3) printf("TXSTRT "); + if(temp & BIT2) printf("TXSTRTM "); + if(temp & BIT1) printf("JAB "); + if(temp & BIT0) printf("JABM "); + + printf("\n"); + + printf("CSR5: Ext Control and Int 1 0x%04x\n ",ptr[5]); + temp=ptr[5]; + + if(temp & BIT15) printf("TOKINTD "); + if(temp & BIT14) printf("LTINTEN "); + if(temp & BIT11) printf("SINT "); + if(temp & BIT10) printf("SINTE "); + if(temp & BIT9) printf("SLPINT "); + if(temp & BIT8) printf("SLPINTE "); + if(temp & BIT7) printf("EXDINT "); + if(temp & BIT6) printf("EXDINTE "); + if(temp & BIT5) printf("MPPLBA "); + if(temp & BIT4) printf("MPINT "); + if(temp & BIT3) printf("MPINTE "); + if(temp & BIT2) printf("MPEN "); + if(temp & BIT1) printf("MPMODE "); + if(temp & BIT0) printf("SPND "); + + printf("\n"); + + printf("CSR7: Ext Control and Int 2 0x%04x\n ",ptr[7]); + temp=ptr[7]; + + if(temp & BIT15) printf("FASTSPNDE "); + if(temp & BIT14) printf("RXFRTG "); + if(temp & BIT13) printf("RDMD "); + if(temp & BIT12) printf("RXDPOLL "); + if(temp & BIT11) printf("STINT "); + if(temp & BIT10) printf("STINTE "); + if(temp & BIT9) printf("MREINT "); + if(temp & BIT8) printf("MREINTE "); + if(temp & BIT7) printf("MAPINT "); + if(temp & BIT6) printf("MAPINTE "); + if(temp & BIT5) printf("MCCINT "); + if(temp & BIT4) printf("MCCINTE "); + if(temp & BIT3) printf("MCCIINT "); + if(temp & BIT2) printf("MCCIINTE "); + if(temp & BIT1) printf("MIIPDTINT "); + if(temp & BIT0) printf("MIIPDTINTE "); + + printf("\n"); + + printf("CSR15: Mode 0x%04x\n",ptr[15]); + printf("CSR40: Current RX Byte Count 0x%04x\n",ptr[40]); + printf("CSR41: Current RX Status 0x%04x\n",ptr[41]); + printf("CSR42: Current TX Byte Count 0x%04x\n",ptr[42]); + printf("CSR43: Current TX Status 0x%04x\n",ptr[43]); + printf("CSR88: Chip ID Lower 0x%04x\n",ptr[88]); + temp = (((ptr[89] << 16) | ptr[88]) >> 12) & 0xffff; + switch (temp) { + case 0x2420: + printf(" PCnet/PCI 79C970\n"); + break; + case 0x2621: + printf(" PCnet/PCI II 79C970A\n"); + break; + case 0x2623: + printf(" PCnet/FAST 79C971\n"); + break; + case 0x2624: + printf(" PCnet/FAST+ 79C972\n"); + break; + case 0x2625: + printf(" PCnet/FAST III 79C973\n"); + break; + case 0x2626: + printf(" PCnet/Home 79C978\n"); + break; + case 0x2627: + printf(" PCnet/FAST III 79C975\n"); + break; + case 0x2628: + printf(" PCnet/PRO 79C976\n"); + break; + } + + printf("CSR89: Chip ID Upper 0x%04x\n ",ptr[89]); + temp=ptr[89]; + printf("VER: %04x PARTIDU: %04x\n",temp >> 12,temp & 0x00000fff); + + printf("CSR112: Missed Frame Count 0x%04x\n",ptr[90]); /* 90 is 112 */ + printf("CSR114: RX Collision Count 0x%04x\n",ptr[91]); + + printf("\n"); + + ptr=&data[100]; /* point to BCR 0 */ + + printf("BCR2: Misc. Configuration 0x%04x\n ",ptr[2]); + temp=ptr[2]; + + if(temp & BIT14) printf("TMAULOOP "); + if(temp & BIT12) printf("LEDPE "); + + if(temp & BIT8) printf("APROMWE "); + if(temp & BIT7) printf("INTLEVEL "); + + if(temp & BIT3) printf("EADISEL "); + if(temp & BIT2) printf("AWAKE "); + if(temp & BIT1) printf("ASEL "); + if(temp & BIT0) printf("XMAUSEL "); + + printf("\n"); + + printf("BCR9: Full-Duplex Control 0x%04x\n",ptr[9]); + printf("BCR18: Burst and Bus Control 0x%04x\n",ptr[18]); + + printf("BCR19: EEPROM Control and Status 0x%04x\n ",ptr[19]); + temp=ptr[19]; + if(temp & BIT15) printf("PVALID "); + if(temp & BIT13) printf("EEDET "); + printf("\n"); + + printf("BCR23: PCI Subsystem Vendor ID 0x%04x\n",ptr[23]); + printf("BCR24: PCI Subsystem ID 0x%04x\n",ptr[24]); + printf("BCR31: Software Timer 0x%04x\n",ptr[31]); + printf("BCR32: MII Control and Status 0x%04x\n",ptr[32]); + printf("BCR35: PCI Vendor ID 0x%04x\n",ptr[35]); + + return(0); +} +
diff --git a/ethtool-2.6.35/realtek.c b/ethtool-2.6.35/realtek.c new file mode 100644 index 0000000..11ed835 --- /dev/null +++ b/ethtool-2.6.35/realtek.c
@@ -0,0 +1,537 @@ +/* Copyright 2001 Sun Microsystems (thockin@sun.com) */ +#include <stdio.h> +#include <stdlib.h> +#include "ethtool-util.h" + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#define HW_REVID(b31, b30, b29, b28, b27, b26, b23, b22) \ + (b31<<31 | b30<<30 | b29<<29 | b28<<28 | \ + b27<<27 | b26<<26 | b23<<23 | b22<<22) + +enum chip_type { + RTLNONE, + RTL8139, + RTL8139_K, + RTL8139A, + RTL8139A_G, + RTL8139B, + RTL8130, + RTL8139C, + RTL8100, + RTL8100B_8139D, + RTL8139Cp, + RTL8101, + RTL8169, + RTL8169S, + RTL8110S, + RTL8169_8110SB, + RTL8169_8110SCd, + RTL8169_8110SCe, + RTL8168_8111Bb, + RTL8168_8111Bef, + RTL8101Ebc, + RTL8100E1, + RTL8100E2, +}; + +enum { + chip_type_mask = HW_REVID(1, 1, 1, 1, 1, 1, 1, 1) +}; + +static struct chip_info { + const char *name; + u32 id_mask; +} rtl_info_tbl[] = { + { "RTL-8139", HW_REVID(0, 1, 0, 0, 0, 0, 0, 0) }, + { "RTL-8139-K", HW_REVID(0, 1, 1, 0, 0, 0, 0, 0) }, + { "RTL-8139A", HW_REVID(0, 1, 1, 1, 0, 0, 0, 0) }, + { "RTL-8139A-G", HW_REVID(0, 1, 1, 1, 0, 0, 1, 0) }, + { "RTL-8139B", HW_REVID(0, 1, 1, 1, 1, 0, 0, 0) }, + { "RTL-8130", HW_REVID(0, 1, 1, 1, 1, 1, 0, 0) }, + { "RTL-8139C", HW_REVID(0, 1, 1, 1, 0, 1, 0, 0) }, + { "RTL-8100", HW_REVID(0, 1, 1, 1, 1, 0, 1, 0) }, + { "RTL-8100B/8139D", HW_REVID(0, 1, 1, 1, 0, 1, 0, 1) }, + { "RTL-8139C+", HW_REVID(0, 1, 1, 1, 0, 1, 1, 0) }, + { "RTL-8101", HW_REVID(0, 1, 1, 1, 0, 1, 1, 1) }, + { "RTL-8169", HW_REVID(0, 0, 0, 0, 0, 0, 0, 0) }, + { "RTL-8169S", HW_REVID(0, 0, 0, 0, 0, 0, 1, 0) }, + { "RTL-8110S", HW_REVID(0, 0, 0, 0, 0, 1, 0, 0) }, + { "RTL-8169/8110SB", HW_REVID(0, 0, 0, 1, 0, 0, 0, 0) }, + { "RTL-8169/8110SCd", HW_REVID(0, 0, 0, 1, 1, 0, 0, 0) }, + { "RTL-8169/8110SCe", HW_REVID(1, 0, 0, 1, 1, 0, 0, 0) }, + { "RTL-8168/8111Bb", HW_REVID(0, 0, 1, 1, 0, 0, 0, 0) }, + { "RTL-8168/8111Bef", HW_REVID(0, 0, 1, 1, 1, 0, 0, 0) }, + { "RTL-8101Ebc", HW_REVID(0, 0, 1, 1, 0, 1, 0, 0) }, + { "RTL-8100E(1)", HW_REVID(0, 0, 1, 1, 0, 0, 1, 0) }, + { "RTL-8100E(2)", HW_REVID(0, 0, 1, 1, 1, 0, 1, 0) }, + { } +}; + +static void +print_intr_bits(u16 mask) +{ + fprintf(stdout, + " %s%s%s%s%s%s%s%s%s%s%s\n", + mask & (1 << 15) ? "SERR " : "", + mask & (1 << 14) ? "TimeOut " : "", + mask & (1 << 8) ? "SWInt " : "", + mask & (1 << 7) ? "TxNoBuf " : "", + mask & (1 << 6) ? "RxFIFO " : "", + mask & (1 << 5) ? "LinkChg " : "", + mask & (1 << 4) ? "RxNoBuf " : "", + mask & (1 << 3) ? "TxErr " : "", + mask & (1 << 2) ? "TxOK " : "", + mask & (1 << 1) ? "RxErr " : "", + mask & (1 << 0) ? "RxOK " : ""); +} + +int +realtek_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + u32 *data = (u32 *) regs->data; + u8 *data8 = (u8 *) regs->data; + u32 v; + struct chip_info *ci; + unsigned int board_type = RTLNONE, i; + + v = data[0x40 >> 2] & chip_type_mask; + + ci = &rtl_info_tbl[0]; + while (ci->name) { + if (v == ci->id_mask) + break; + ci++; + } + if (v != ci->id_mask) { + fprintf(stderr, "Unknown RealTek chip (mask: 0x%08x)\n", v); + return 91; + } + for (i = 0; i < ARRAY_SIZE(rtl_info_tbl); i++) { + if (ci == &rtl_info_tbl[i]) + board_type = i + 1; + } + if (board_type == RTLNONE) + abort(); + + fprintf(stdout, + "RealTek %s registers:\n" + "--------------------------------------------------------\n", + ci->name); + + fprintf(stdout, + "0x00: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", + data8[0x00], + data8[0x01], + data8[0x02], + data8[0x03], + data8[0x04], + data8[0x05]); + + fprintf(stdout, + "0x08: Multicast Address Filter 0x%08x 0x%08x\n", + data[0x08 >> 2], + data[0x0c >> 2]); + + if (board_type == RTL8139Cp || board_type >= RTL8169) { + fprintf(stdout, + "0x10: Dump Tally Counter Command 0x%08x 0x%08x\n", + data[0x10 >> 2], + data[0x14 >> 2]); + + fprintf(stdout, + "0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x\n", + data[0x20 >> 2], + data[0x24 >> 2]); + + fprintf(stdout, + "0x28: Tx High Priority Ring Addr 0x%08x 0x%08x\n", + data[0x28 >> 2], + data[0x2C >> 2]); + } else { + fprintf(stdout, + "0x10: Transmit Status Desc 0 0x%08x\n" + "0x14: Transmit Status Desc 1 0x%08x\n" + "0x18: Transmit Status Desc 2 0x%08x\n" + "0x1C: Transmit Status Desc 3 0x%08x\n", + data[0x10 >> 2], + data[0x14 >> 2], + data[0x18 >> 2], + data[0x1C >> 2]); + fprintf(stdout, + "0x20: Transmit Start Addr 0 0x%08x\n" + "0x24: Transmit Start Addr 1 0x%08x\n" + "0x28: Transmit Start Addr 2 0x%08x\n" + "0x2C: Transmit Start Addr 3 0x%08x\n", + data[0x20 >> 2], + data[0x24 >> 2], + data[0x28 >> 2], + data[0x2C >> 2]); + } + + if (board_type != RTL8168_8111Bb && board_type != RTL8168_8111Bef) { + if (board_type >= RTL8169) { + fprintf(stdout, + "0x30: Flash memory read/write 0x%08x\n", + data[0x30 >> 2]); + } else { + fprintf(stdout, + "0x30: Rx buffer addr (C mode) 0x%08x\n", + data[0x30 >> 2]); + } + } + + v = data8[0x36]; + fprintf(stdout, + "0x34: Early Rx Byte Count %8u\n" + "0x36: Early Rx Status 0x%02x\n", + data[0x34 >> 2] & 0xffff, + v); + + if (v & 0xf) { + fprintf(stdout, + " %s%s%s%s\n", + v & (1 << 3) ? "ERxGood " : "", + v & (1 << 2) ? "ERxBad " : "", + v & (1 << 1) ? "ERxOverWrite " : "", + v & (1 << 0) ? "ERxOK " : ""); + } + + v = data8[0x37]; + fprintf(stdout, + "0x37: Command 0x%02x\n" + " Rx %s, Tx %s%s\n", + data8[0x37], + v & (1 << 3) ? "on" : "off", + v & (1 << 2) ? "on" : "off", + v & (1 << 4) ? ", RESET" : ""); + + if (board_type < RTL8169) { + fprintf(stdout, + "0x38: Current Address of Packet Read (C mode) 0x%04x\n" + "0x3A: Current Rx buffer address (C mode) 0x%04x\n", + data[0x38 >> 2] & 0xffff, + data[0x38 >> 2] >> 16); + } + + fprintf(stdout, + "0x3C: Interrupt Mask 0x%04x\n", + data[0x3c >> 2] & 0xffff); + print_intr_bits(data[0x3c >> 2] & 0xffff); + fprintf(stdout, + "0x3E: Interrupt Status 0x%04x\n", + data[0x3c >> 2] >> 16); + print_intr_bits(data[0x3c >> 2] >> 16); + + fprintf(stdout, + "0x40: Tx Configuration 0x%08x\n" + "0x44: Rx Configuration 0x%08x\n" + "0x48: Timer count 0x%08x\n" + "0x4C: Missed packet counter 0x%06x\n", + data[0x40 >> 2], + data[0x44 >> 2], + data[0x48 >> 2], + data[0x4C >> 2] & 0xffffff); + + fprintf(stdout, + "0x50: EEPROM Command 0x%02x\n" + "0x51: Config 0 0x%02x\n" + "0x52: Config 1 0x%02x\n", + data8[0x50], + data8[0x51], + data8[0x52]); + + if (board_type >= RTL8169) { + fprintf(stdout, + "0x53: Config 2 0x%02x\n" + "0x54: Config 3 0x%02x\n" + "0x55: Config 4 0x%02x\n" + "0x56: Config 5 0x%02x\n", + data8[0x53], + data8[0x54], + data8[0x55], + data8[0x56]); + fprintf(stdout, + "0x58: Timer interrupt 0x%08x\n", + data[0x58 >> 2]); + } + else { + if (board_type >= RTL8139A) { + fprintf(stdout, + "0x54: Timer interrupt 0x%08x\n", + data[0x54 >> 2]); + } + fprintf(stdout, + "0x58: Media status 0x%02x\n", + data8[0x58]); + if (board_type >= RTL8139A) { + fprintf(stdout, + "0x59: Config 3 0x%02x\n", + data8[0x59]); + } + if (board_type >= RTL8139B) { + fprintf(stdout, + "0x5A: Config 4 0x%02x\n", + data8[0x5A]); + } + } + + fprintf(stdout, + "0x5C: Multiple Interrupt Select 0x%04x\n", + data[0x5c >> 2] & 0xffff); + + if (board_type >= RTL8169) { + fprintf(stdout, + "0x60: PHY access 0x%08x\n", + data[0x60 >> 2]); + + if (board_type != RTL8168_8111Bb && board_type != RTL8168_8111Bef) { + fprintf(stdout, + "0x64: TBI control and status 0x%08x\n", + data[0x64 >> 2]); + fprintf(stdout, + "0x68: TBI Autonegotiation advertisement (ANAR) 0x%04x\n" + "0x6A: TBI Link partner ability (LPAR) 0x%04x\n", + data[0x68 >> 2] & 0xffff, + data[0x68 >> 2] >> 16); + } + + fprintf(stdout, + "0x6C: PHY status 0x%02x\n", + data8[0x6C]); + + fprintf(stdout, + "0x84: PM wakeup frame 0 0x%08x 0x%08x\n" + "0x8C: PM wakeup frame 1 0x%08x 0x%08x\n", + data[0x84 >> 2], + data[0x88 >> 2], + data[0x8C >> 2], + data[0x90 >> 2]); + + fprintf(stdout, + "0x94: PM wakeup frame 2 (low) 0x%08x 0x%08x\n" + "0x9C: PM wakeup frame 2 (high) 0x%08x 0x%08x\n", + data[0x94 >> 2], + data[0x98 >> 2], + data[0x9C >> 2], + data[0xA0 >> 2]); + + fprintf(stdout, + "0xA4: PM wakeup frame 3 (low) 0x%08x 0x%08x\n" + "0xAC: PM wakeup frame 3 (high) 0x%08x 0x%08x\n", + data[0xA4 >> 2], + data[0xA8 >> 2], + data[0xAC >> 2], + data[0xB0 >> 2]); + + fprintf(stdout, + "0xB4: PM wakeup frame 4 (low) 0x%08x 0x%08x\n" + "0xBC: PM wakeup frame 4 (high) 0x%08x 0x%08x\n", + data[0xB4 >> 2], + data[0xB8 >> 2], + data[0xBC >> 2], + data[0xC0 >> 2]); + + fprintf(stdout, + "0xC4: Wakeup frame 0 CRC 0x%04x\n" + "0xC6: Wakeup frame 1 CRC 0x%04x\n" + "0xC8: Wakeup frame 2 CRC 0x%04x\n" + "0xCA: Wakeup frame 3 CRC 0x%04x\n" + "0xCC: Wakeup frame 4 CRC 0x%04x\n", + data[0xC4 >> 2] & 0xffff, + data[0xC4 >> 2] >> 16, + data[0xC8 >> 2] & 0xffff, + data[0xC8 >> 2] >> 16, + data[0xCC >> 2] & 0xffff); + fprintf(stdout, + "0xDA: RX packet maximum size 0x%04x\n", + data[0xD8 >> 2] >> 16); + } + else { + fprintf(stdout, + "0x5E: PCI revision id 0x%02x\n", + data8[0x5e]); + fprintf(stdout, + "0x60: Transmit Status of All Desc (C mode) 0x%04x\n" + "0x62: MII Basic Mode Control Register 0x%04x\n", + data[0x60 >> 2] & 0xffff, + data[0x60 >> 2] >> 16); + fprintf(stdout, + "0x64: MII Basic Mode Status Register 0x%04x\n" + "0x66: MII Autonegotiation Advertising 0x%04x\n", + data[0x64 >> 2] & 0xffff, + data[0x64 >> 2] >> 16); + fprintf(stdout, + "0x68: MII Link Partner Ability 0x%04x\n" + "0x6A: MII Expansion 0x%04x\n", + data[0x68 >> 2] & 0xffff, + data[0x68 >> 2] >> 16); + fprintf(stdout, + "0x6C: MII Disconnect counter 0x%04x\n" + "0x6E: MII False carrier sense counter 0x%04x\n", + data[0x6C >> 2] & 0xffff, + data[0x6C >> 2] >> 16); + fprintf(stdout, + "0x70: MII Nway test 0x%04x\n" + "0x72: MII RX_ER counter 0x%04x\n", + data[0x70 >> 2] & 0xffff, + data[0x70 >> 2] >> 16); + fprintf(stdout, + "0x74: MII CS configuration 0x%04x\n", + data[0x74 >> 2] & 0xffff); + if (board_type >= RTL8139_K) { + fprintf(stdout, + "0x78: PHY parameter 1 0x%08x\n" + "0x7C: Twister parameter 0x%08x\n", + data[0x78 >> 2], + data[0x7C >> 2]); + if (board_type >= RTL8139A) { + fprintf(stdout, + "0x80: PHY parameter 2 0x%02x\n", + data8[0x80]); + } + } + if (board_type == RTL8139Cp) { + fprintf(stdout, + "0x82: Low addr of a Tx Desc w/ Tx DMA OK 0x%04x\n", + data[0x80 >> 2] >> 16); + } else if (board_type == RTL8130) { + fprintf(stdout, + "0x82: MII register 0x%02x\n", + data8[0x82]); + } + if (board_type >= RTL8139A) { + fprintf(stdout, + "0x84: PM CRC for wakeup frame 0 0x%02x\n" + "0x85: PM CRC for wakeup frame 1 0x%02x\n" + "0x86: PM CRC for wakeup frame 2 0x%02x\n" + "0x87: PM CRC for wakeup frame 3 0x%02x\n" + "0x88: PM CRC for wakeup frame 4 0x%02x\n" + "0x89: PM CRC for wakeup frame 5 0x%02x\n" + "0x8A: PM CRC for wakeup frame 6 0x%02x\n" + "0x8B: PM CRC for wakeup frame 7 0x%02x\n", + data8[0x84], + data8[0x85], + data8[0x86], + data8[0x87], + data8[0x88], + data8[0x89], + data8[0x8A], + data8[0x8B]); + fprintf(stdout, + "0x8C: PM wakeup frame 0 0x%08x 0x%08x\n" + "0x94: PM wakeup frame 1 0x%08x 0x%08x\n" + "0x9C: PM wakeup frame 2 0x%08x 0x%08x\n" + "0xA4: PM wakeup frame 3 0x%08x 0x%08x\n" + "0xAC: PM wakeup frame 4 0x%08x 0x%08x\n" + "0xB4: PM wakeup frame 5 0x%08x 0x%08x\n" + "0xBC: PM wakeup frame 6 0x%08x 0x%08x\n" + "0xC4: PM wakeup frame 7 0x%08x 0x%08x\n", + data[0x8C >> 2], + data[0x90 >> 2], + data[0x94 >> 2], + data[0x98 >> 2], + data[0x9C >> 2], + data[0xA0 >> 2], + data[0xA4 >> 2], + data[0xA8 >> 2], + data[0xAC >> 2], + data[0xB0 >> 2], + data[0xB4 >> 2], + data[0xB8 >> 2], + data[0xBC >> 2], + data[0xC0 >> 2], + data[0xC4 >> 2], + data[0xC8 >> 2]); + fprintf(stdout, + "0xCC: PM LSB CRC for wakeup frame 0 0x%02x\n" + "0xCD: PM LSB CRC for wakeup frame 1 0x%02x\n" + "0xCE: PM LSB CRC for wakeup frame 2 0x%02x\n" + "0xCF: PM LSB CRC for wakeup frame 3 0x%02x\n" + "0xD0: PM LSB CRC for wakeup frame 4 0x%02x\n" + "0xD1: PM LSB CRC for wakeup frame 5 0x%02x\n" + "0xD2: PM LSB CRC for wakeup frame 6 0x%02x\n" + "0xD3: PM LSB CRC for wakeup frame 7 0x%02x\n", + data8[0xCC], + data8[0xCD], + data8[0xCE], + data8[0xCF], + data8[0xD0], + data8[0xD1], + data8[0xD2], + data8[0xD3]); + } + if (board_type >= RTL8139B) { + if (board_type != RTL8100 && board_type != RTL8100B_8139D && + board_type != RTL8101) + fprintf(stdout, + "0xD4: Flash memory read/write 0x%08x\n", + data[0xD4 >> 2]); + if (board_type != RTL8130) + fprintf(stdout, + "0xD8: Config 5 0x%02x\n", + data8[0xD8]); + } + } + + if (board_type == RTL8139Cp || board_type >= RTL8169) { + v = data[0xE0 >> 2] & 0xffff; + fprintf(stdout, + "0xE0: C+ Command 0x%04x\n", + v); + if (v & (1 << 9)) + fprintf(stdout, " Big-endian mode\n"); + if (v & (1 << 8)) + fprintf(stdout, " Home LAN enable\n"); + if (v & (1 << 6)) + fprintf(stdout, " VLAN de-tagging\n"); + if (v & (1 << 5)) + fprintf(stdout, " RX checksumming\n"); + if (v & (1 << 4)) + fprintf(stdout, " PCI 64-bit DAC\n"); + if (v & (1 << 3)) + fprintf(stdout, " PCI Multiple RW\n"); + + v = data[0xe0 >> 2] >> 16; + fprintf(stdout, + "0xE2: Interrupt Mitigation 0x%04x\n" + " TxTimer: %u\n" + " TxPackets: %u\n" + " RxTimer: %u\n" + " RxPackets: %u\n", + v, + v >> 12, + (v >> 8) & 0xf, + (v >> 4) & 0xf, + v & 0xf); + + fprintf(stdout, + "0xE4: Rx Ring Addr 0x%08x 0x%08x\n", + data[0xE4 >> 2], + data[0xE8 >> 2]); + + fprintf(stdout, + "0xEC: Early Tx threshold 0x%02x\n", + data8[0xEC]); + + if (board_type == RTL8139Cp) { + fprintf(stdout, + "0xFC: External MII register 0x%08x\n", + data[0xFC >> 2]); + } else if (board_type >= RTL8169 && + board_type != RTL8168_8111Bb && + board_type != RTL8168_8111Bef) { + fprintf(stdout, + "0xF0: Func Event 0x%08x\n" + "0xF4: Func Event Mask 0x%08x\n" + "0xF8: Func Preset State 0x%08x\n" + "0xFC: Func Force Event 0x%08x\n", + data[0xF0 >> 2], + data[0xF4 >> 2], + data[0xF8 >> 2], + data[0xFC >> 2]); + } + } + + return 0; +}
diff --git a/ethtool-2.6.35/sfc.c b/ethtool-2.6.35/sfc.c new file mode 100644 index 0000000..2e4735f --- /dev/null +++ b/ethtool-2.6.35/sfc.c
@@ -0,0 +1,3859 @@ +/**************************************************************************** + * Support for Solarflare Solarstorm network controllers and boards + * Copyright 2010 Solarflare Communications Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation, incorporated herein by reference. + */ + +#include <stdio.h> +#include <string.h> +#include "ethtool-util.h" + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/* Register definitions (from linux-2.6/drivers/net/sfc/regs.h) */ + +/* ADR_REGION_REG: Address region register */ +#define FR_AZ_ADR_REGION 0x00000000 +#define FRF_AZ_ADR_REGION3_LBN 96 +#define FRF_AZ_ADR_REGION3_WIDTH 18 +#define FRF_AZ_ADR_REGION2_LBN 64 +#define FRF_AZ_ADR_REGION2_WIDTH 18 +#define FRF_AZ_ADR_REGION1_LBN 32 +#define FRF_AZ_ADR_REGION1_WIDTH 18 +#define FRF_AZ_ADR_REGION0_LBN 0 +#define FRF_AZ_ADR_REGION0_WIDTH 18 + +/* INT_EN_REG_KER: Kernel driver Interrupt enable register */ +#define FR_AZ_INT_EN_KER 0x00000010 +#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 +#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 +#define FRF_AZ_KER_INT_CHAR_LBN 4 +#define FRF_AZ_KER_INT_CHAR_WIDTH 1 +#define FRF_AZ_KER_INT_KER_LBN 3 +#define FRF_AZ_KER_INT_KER_WIDTH 1 +#define FRF_AZ_DRV_INT_EN_KER_LBN 0 +#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 + +/* INT_EN_REG_CHAR: Char Driver interrupt enable register */ +#define FR_BZ_INT_EN_CHAR 0x00000020 +#define FRF_BZ_CHAR_INT_LEVE_SEL_LBN 8 +#define FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH 6 +#define FRF_BZ_CHAR_INT_CHAR_LBN 4 +#define FRF_BZ_CHAR_INT_CHAR_WIDTH 1 +#define FRF_BZ_CHAR_INT_KER_LBN 3 +#define FRF_BZ_CHAR_INT_KER_WIDTH 1 +#define FRF_BZ_DRV_INT_EN_CHAR_LBN 0 +#define FRF_BZ_DRV_INT_EN_CHAR_WIDTH 1 + +/* INT_ADR_REG_KER: Interrupt host address for Kernel driver */ +#define FR_AZ_INT_ADR_KER 0x00000030 +#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 +#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 +#define FRF_AZ_INT_ADR_KER_LBN 0 +#define FRF_AZ_INT_ADR_KER_WIDTH 64 + +/* INT_ADR_REG_CHAR: Interrupt host address for Char driver */ +#define FR_BZ_INT_ADR_CHAR 0x00000040 +#define FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN 64 +#define FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 +#define FRF_BZ_INT_ADR_CHAR_LBN 0 +#define FRF_BZ_INT_ADR_CHAR_WIDTH 64 + +/* INT_ACK_KER: Kernel interrupt acknowledge register */ +#define FR_AA_INT_ACK_KER 0x00000050 +#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 +#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 + +/* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */ +#define FR_BZ_INT_ISR0 0x00000090 +#define FRF_BZ_INT_ISR_REG_LBN 0 +#define FRF_BZ_INT_ISR_REG_WIDTH 64 + +/* HW_INIT_REG: Hardware initialization register */ +#define FR_AZ_HW_INIT 0x000000c0 +#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 +#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 +#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 +#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 +#define FRF_CZ_TX_MRG_TAGS_LBN 120 +#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 +#define FRF_AB_TRGT_MASK_ALL_LBN 100 +#define FRF_AB_TRGT_MASK_ALL_WIDTH 1 +#define FRF_AZ_DOORBELL_DROP_LBN 92 +#define FRF_AZ_DOORBELL_DROP_WIDTH 8 +#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 +#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 +#define FRF_AB_PE_EIDLE_DIS_LBN 75 +#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 +#define FRF_AA_FC_BLOCKING_EN_LBN 45 +#define FRF_AA_FC_BLOCKING_EN_WIDTH 1 +#define FRF_BZ_B2B_REQ_EN_LBN 45 +#define FRF_BZ_B2B_REQ_EN_WIDTH 1 +#define FRF_AA_B2B_REQ_EN_LBN 44 +#define FRF_AA_B2B_REQ_EN_WIDTH 1 +#define FRF_BB_FC_BLOCKING_EN_LBN 44 +#define FRF_BB_FC_BLOCKING_EN_WIDTH 1 +#define FRF_AZ_POST_WR_MASK_LBN 40 +#define FRF_AZ_POST_WR_MASK_WIDTH 4 +#define FRF_AZ_TLP_TC_LBN 34 +#define FRF_AZ_TLP_TC_WIDTH 3 +#define FRF_AZ_TLP_ATTR_LBN 32 +#define FRF_AZ_TLP_ATTR_WIDTH 2 +#define FRF_AB_INTB_VEC_LBN 24 +#define FRF_AB_INTB_VEC_WIDTH 5 +#define FRF_AB_INTA_VEC_LBN 16 +#define FRF_AB_INTA_VEC_WIDTH 5 +#define FRF_AZ_WD_TIMER_LBN 8 +#define FRF_AZ_WD_TIMER_WIDTH 8 +#define FRF_AZ_US_DISABLE_LBN 5 +#define FRF_AZ_US_DISABLE_WIDTH 1 +#define FRF_AZ_TLP_EP_LBN 4 +#define FRF_AZ_TLP_EP_WIDTH 1 +#define FRF_AZ_ATTR_SEL_LBN 3 +#define FRF_AZ_ATTR_SEL_WIDTH 1 +#define FRF_AZ_TD_SEL_LBN 1 +#define FRF_AZ_TD_SEL_WIDTH 1 +#define FRF_AZ_TLP_TD_LBN 0 +#define FRF_AZ_TLP_TD_WIDTH 1 + +/* EE_SPI_HCMD_REG: SPI host command register */ +#define FR_AB_EE_SPI_HCMD 0x00000100 +#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 +#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 +#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 +#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 +#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 +#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 +#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 +#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 +#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 +#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 +#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 +#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 +#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 +#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 +#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 +#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 + +/* USR_EV_CFG: User Level Event Configuration register */ +#define FR_CZ_USR_EV_CFG 0x00000100 +#define FRF_CZ_USREV_DIS_LBN 16 +#define FRF_CZ_USREV_DIS_WIDTH 1 +#define FRF_CZ_DFLT_EVQ_LBN 0 +#define FRF_CZ_DFLT_EVQ_WIDTH 10 + +/* EE_SPI_HADR_REG: SPI host address register */ +#define FR_AB_EE_SPI_HADR 0x00000110 +#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 +#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 +#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 +#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 + +/* EE_SPI_HDATA_REG: SPI host data register */ +#define FR_AB_EE_SPI_HDATA 0x00000120 +#define FRF_AB_EE_SPI_HDATA3_LBN 96 +#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 +#define FRF_AB_EE_SPI_HDATA2_LBN 64 +#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 +#define FRF_AB_EE_SPI_HDATA1_LBN 32 +#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 +#define FRF_AB_EE_SPI_HDATA0_LBN 0 +#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 + +/* EE_BASE_PAGE_REG: Expansion ROM base mirror register */ +#define FR_AB_EE_BASE_PAGE 0x00000130 +#define FRF_AB_EE_EXPROM_MASK_LBN 16 +#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 +#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 +#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 + +/* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */ +#define FR_AB_EE_VPD_CFG0 0x00000140 +#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 +#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 +#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 +#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 +#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 +#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 +#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 +#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 +#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 +#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 +#define FRF_AB_EE_VPDW_LENGTH_LBN 80 +#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 +#define FRF_AB_EE_VPDW_BASE_LBN 64 +#define FRF_AB_EE_VPDW_BASE_WIDTH 15 +#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 +#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 +#define FRF_AB_EE_VPD_BASE_LBN 32 +#define FRF_AB_EE_VPD_BASE_WIDTH 24 +#define FRF_AB_EE_VPD_LENGTH_LBN 16 +#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 +#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 +#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 +#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 +#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 +#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 +#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 +#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 +#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 +#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 +#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 +#define FRF_AB_EE_VPD_EN_LBN 0 +#define FRF_AB_EE_VPD_EN_WIDTH 1 + +/* EE_VPD_SW_CNTL_REG: VPD access SW control register */ +#define FR_AB_EE_VPD_SW_CNTL 0x00000150 +#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 +#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 +#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 +#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 +#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 +#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 + +/* EE_VPD_SW_DATA_REG: VPD access SW data register */ +#define FR_AB_EE_VPD_SW_DATA 0x00000160 +#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 +#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 + +/* PBMX_DBG_IADDR_REG: Capture Module address register */ +#define FR_CZ_PBMX_DBG_IADDR 0x000001f0 +#define FRF_CZ_PBMX_DBG_IADDR_LBN 0 +#define FRF_CZ_PBMX_DBG_IADDR_WIDTH 32 + +/* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */ +#define FR_BB_PCIE_CORE_INDIRECT 0x000001f0 +#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 +#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 +#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 +#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 +#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 +#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 + +/* PBMX_DBG_IDATA_REG: Capture Module data register */ +#define FR_CZ_PBMX_DBG_IDATA 0x000001f8 +#define FRF_CZ_PBMX_DBG_IDATA_LBN 0 +#define FRF_CZ_PBMX_DBG_IDATA_WIDTH 64 + +/* NIC_STAT_REG: NIC status register */ +#define FR_AB_NIC_STAT 0x00000200 +#define FRF_BB_AER_DIS_LBN 34 +#define FRF_BB_AER_DIS_WIDTH 1 +#define FRF_BB_EE_STRAP_EN_LBN 31 +#define FRF_BB_EE_STRAP_EN_WIDTH 1 +#define FRF_BB_EE_STRAP_LBN 24 +#define FRF_BB_EE_STRAP_WIDTH 4 +#define FRF_BB_REVISION_ID_LBN 17 +#define FRF_BB_REVISION_ID_WIDTH 7 +#define FRF_AB_ONCHIP_SRAM_LBN 16 +#define FRF_AB_ONCHIP_SRAM_WIDTH 1 +#define FRF_AB_SF_PRST_LBN 9 +#define FRF_AB_SF_PRST_WIDTH 1 +#define FRF_AB_EE_PRST_LBN 8 +#define FRF_AB_EE_PRST_WIDTH 1 +#define FRF_AB_ATE_MODE_LBN 3 +#define FRF_AB_ATE_MODE_WIDTH 1 +#define FRF_AB_STRAP_PINS_LBN 0 +#define FRF_AB_STRAP_PINS_WIDTH 3 + +/* GPIO_CTL_REG: GPIO control register */ +#define FR_AB_GPIO_CTL 0x00000210 +#define FRF_AB_GPIO_OUT3_LBN 112 +#define FRF_AB_GPIO_OUT3_WIDTH 16 +#define FRF_AB_GPIO_IN3_LBN 104 +#define FRF_AB_GPIO_IN3_WIDTH 8 +#define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96 +#define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8 +#define FRF_AB_GPIO_OUT2_LBN 80 +#define FRF_AB_GPIO_OUT2_WIDTH 16 +#define FRF_AB_GPIO_IN2_LBN 72 +#define FRF_AB_GPIO_IN2_WIDTH 8 +#define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64 +#define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8 +#define FRF_AB_GPIO15_OEN_LBN 63 +#define FRF_AB_GPIO15_OEN_WIDTH 1 +#define FRF_AB_GPIO14_OEN_LBN 62 +#define FRF_AB_GPIO14_OEN_WIDTH 1 +#define FRF_AB_GPIO13_OEN_LBN 61 +#define FRF_AB_GPIO13_OEN_WIDTH 1 +#define FRF_AB_GPIO12_OEN_LBN 60 +#define FRF_AB_GPIO12_OEN_WIDTH 1 +#define FRF_AB_GPIO11_OEN_LBN 59 +#define FRF_AB_GPIO11_OEN_WIDTH 1 +#define FRF_AB_GPIO10_OEN_LBN 58 +#define FRF_AB_GPIO10_OEN_WIDTH 1 +#define FRF_AB_GPIO9_OEN_LBN 57 +#define FRF_AB_GPIO9_OEN_WIDTH 1 +#define FRF_AB_GPIO8_OEN_LBN 56 +#define FRF_AB_GPIO8_OEN_WIDTH 1 +#define FRF_AB_GPIO15_OUT_LBN 55 +#define FRF_AB_GPIO15_OUT_WIDTH 1 +#define FRF_AB_GPIO14_OUT_LBN 54 +#define FRF_AB_GPIO14_OUT_WIDTH 1 +#define FRF_AB_GPIO13_OUT_LBN 53 +#define FRF_AB_GPIO13_OUT_WIDTH 1 +#define FRF_AB_GPIO12_OUT_LBN 52 +#define FRF_AB_GPIO12_OUT_WIDTH 1 +#define FRF_AB_GPIO11_OUT_LBN 51 +#define FRF_AB_GPIO11_OUT_WIDTH 1 +#define FRF_AB_GPIO10_OUT_LBN 50 +#define FRF_AB_GPIO10_OUT_WIDTH 1 +#define FRF_AB_GPIO9_OUT_LBN 49 +#define FRF_AB_GPIO9_OUT_WIDTH 1 +#define FRF_AB_GPIO8_OUT_LBN 48 +#define FRF_AB_GPIO8_OUT_WIDTH 1 +#define FRF_AB_GPIO15_IN_LBN 47 +#define FRF_AB_GPIO15_IN_WIDTH 1 +#define FRF_AB_GPIO14_IN_LBN 46 +#define FRF_AB_GPIO14_IN_WIDTH 1 +#define FRF_AB_GPIO13_IN_LBN 45 +#define FRF_AB_GPIO13_IN_WIDTH 1 +#define FRF_AB_GPIO12_IN_LBN 44 +#define FRF_AB_GPIO12_IN_WIDTH 1 +#define FRF_AB_GPIO11_IN_LBN 43 +#define FRF_AB_GPIO11_IN_WIDTH 1 +#define FRF_AB_GPIO10_IN_LBN 42 +#define FRF_AB_GPIO10_IN_WIDTH 1 +#define FRF_AB_GPIO9_IN_LBN 41 +#define FRF_AB_GPIO9_IN_WIDTH 1 +#define FRF_AB_GPIO8_IN_LBN 40 +#define FRF_AB_GPIO8_IN_WIDTH 1 +#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 +#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 +#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 +#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 +#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 +#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 +#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 +#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 +#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_CLK156_OUT_EN_LBN 31 +#define FRF_AB_CLK156_OUT_EN_WIDTH 1 +#define FRF_AB_USE_NIC_CLK_LBN 30 +#define FRF_AB_USE_NIC_CLK_WIDTH 1 +#define FRF_AB_GPIO5_OEN_LBN 29 +#define FRF_AB_GPIO5_OEN_WIDTH 1 +#define FRF_AB_GPIO4_OEN_LBN 28 +#define FRF_AB_GPIO4_OEN_WIDTH 1 +#define FRF_AB_GPIO3_OEN_LBN 27 +#define FRF_AB_GPIO3_OEN_WIDTH 1 +#define FRF_AB_GPIO2_OEN_LBN 26 +#define FRF_AB_GPIO2_OEN_WIDTH 1 +#define FRF_AB_GPIO1_OEN_LBN 25 +#define FRF_AB_GPIO1_OEN_WIDTH 1 +#define FRF_AB_GPIO0_OEN_LBN 24 +#define FRF_AB_GPIO0_OEN_WIDTH 1 +#define FRF_AB_GPIO7_OUT_LBN 23 +#define FRF_AB_GPIO7_OUT_WIDTH 1 +#define FRF_AB_GPIO6_OUT_LBN 22 +#define FRF_AB_GPIO6_OUT_WIDTH 1 +#define FRF_AB_GPIO5_OUT_LBN 21 +#define FRF_AB_GPIO5_OUT_WIDTH 1 +#define FRF_AB_GPIO4_OUT_LBN 20 +#define FRF_AB_GPIO4_OUT_WIDTH 1 +#define FRF_AB_GPIO3_OUT_LBN 19 +#define FRF_AB_GPIO3_OUT_WIDTH 1 +#define FRF_AB_GPIO2_OUT_LBN 18 +#define FRF_AB_GPIO2_OUT_WIDTH 1 +#define FRF_AB_GPIO1_OUT_LBN 17 +#define FRF_AB_GPIO1_OUT_WIDTH 1 +#define FRF_AB_GPIO0_OUT_LBN 16 +#define FRF_AB_GPIO0_OUT_WIDTH 1 +#define FRF_AB_GPIO7_IN_LBN 15 +#define FRF_AB_GPIO7_IN_WIDTH 1 +#define FRF_AB_GPIO6_IN_LBN 14 +#define FRF_AB_GPIO6_IN_WIDTH 1 +#define FRF_AB_GPIO5_IN_LBN 13 +#define FRF_AB_GPIO5_IN_WIDTH 1 +#define FRF_AB_GPIO4_IN_LBN 12 +#define FRF_AB_GPIO4_IN_WIDTH 1 +#define FRF_AB_GPIO3_IN_LBN 11 +#define FRF_AB_GPIO3_IN_WIDTH 1 +#define FRF_AB_GPIO2_IN_LBN 10 +#define FRF_AB_GPIO2_IN_WIDTH 1 +#define FRF_AB_GPIO1_IN_LBN 9 +#define FRF_AB_GPIO1_IN_WIDTH 1 +#define FRF_AB_GPIO0_IN_LBN 8 +#define FRF_AB_GPIO0_IN_WIDTH 1 +#define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7 +#define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6 +#define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 +#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 +#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 +#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 +#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 +#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 +#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 +#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 + +/* GLB_CTL_REG: Global control register */ +#define FR_AB_GLB_CTL 0x00000220 +#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 +#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 +#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 +#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 +#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 +#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 +#define FRF_AA_PCIX_RST_CTL_LBN 60 +#define FRF_AA_PCIX_RST_CTL_WIDTH 1 +#define FRF_BB_BIU_RST_CTL_LBN 60 +#define FRF_BB_BIU_RST_CTL_WIDTH 1 +#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 +#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 +#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 +#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 +#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 +#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 +#define FRF_AB_XGRX_RST_CTL_LBN 56 +#define FRF_AB_XGRX_RST_CTL_WIDTH 1 +#define FRF_AB_XGTX_RST_CTL_LBN 55 +#define FRF_AB_XGTX_RST_CTL_WIDTH 1 +#define FRF_AB_EM_RST_CTL_LBN 54 +#define FRF_AB_EM_RST_CTL_WIDTH 1 +#define FRF_AB_EV_RST_CTL_LBN 53 +#define FRF_AB_EV_RST_CTL_WIDTH 1 +#define FRF_AB_SR_RST_CTL_LBN 52 +#define FRF_AB_SR_RST_CTL_WIDTH 1 +#define FRF_AB_RX_RST_CTL_LBN 51 +#define FRF_AB_RX_RST_CTL_WIDTH 1 +#define FRF_AB_TX_RST_CTL_LBN 50 +#define FRF_AB_TX_RST_CTL_WIDTH 1 +#define FRF_AB_EE_RST_CTL_LBN 49 +#define FRF_AB_EE_RST_CTL_WIDTH 1 +#define FRF_AB_CS_RST_CTL_LBN 48 +#define FRF_AB_CS_RST_CTL_WIDTH 1 +#define FRF_AB_HOT_RST_CTL_LBN 40 +#define FRF_AB_HOT_RST_CTL_WIDTH 2 +#define FRF_AB_RST_EXT_PHY_LBN 31 +#define FRF_AB_RST_EXT_PHY_WIDTH 1 +#define FRF_AB_RST_XAUI_SD_LBN 30 +#define FRF_AB_RST_XAUI_SD_WIDTH 1 +#define FRF_AB_RST_PCIE_SD_LBN 29 +#define FRF_AB_RST_PCIE_SD_WIDTH 1 +#define FRF_AA_RST_PCIX_LBN 28 +#define FRF_AA_RST_PCIX_WIDTH 1 +#define FRF_BB_RST_BIU_LBN 28 +#define FRF_BB_RST_BIU_WIDTH 1 +#define FRF_AB_RST_PCIE_STKY_LBN 27 +#define FRF_AB_RST_PCIE_STKY_WIDTH 1 +#define FRF_AB_RST_PCIE_NSTKY_LBN 26 +#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 +#define FRF_AB_RST_PCIE_CORE_LBN 25 +#define FRF_AB_RST_PCIE_CORE_WIDTH 1 +#define FRF_AB_RST_XGRX_LBN 24 +#define FRF_AB_RST_XGRX_WIDTH 1 +#define FRF_AB_RST_XGTX_LBN 23 +#define FRF_AB_RST_XGTX_WIDTH 1 +#define FRF_AB_RST_EM_LBN 22 +#define FRF_AB_RST_EM_WIDTH 1 +#define FRF_AB_RST_EV_LBN 21 +#define FRF_AB_RST_EV_WIDTH 1 +#define FRF_AB_RST_SR_LBN 20 +#define FRF_AB_RST_SR_WIDTH 1 +#define FRF_AB_RST_RX_LBN 19 +#define FRF_AB_RST_RX_WIDTH 1 +#define FRF_AB_RST_TX_LBN 18 +#define FRF_AB_RST_TX_WIDTH 1 +#define FRF_AB_RST_SF_LBN 17 +#define FRF_AB_RST_SF_WIDTH 1 +#define FRF_AB_RST_CS_LBN 16 +#define FRF_AB_RST_CS_WIDTH 1 +#define FRF_AB_INT_RST_DUR_LBN 4 +#define FRF_AB_INT_RST_DUR_WIDTH 3 +#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 +#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 +#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 +#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 +#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 +#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 +#define FFE_AB_EXT_PHY_RST_DUR_640US 3 +#define FFE_AB_EXT_PHY_RST_DUR_320US 2 +#define FFE_AB_EXT_PHY_RST_DUR_160US 1 +#define FFE_AB_EXT_PHY_RST_DUR_80US 0 +#define FRF_AB_SWRST_LBN 0 +#define FRF_AB_SWRST_WIDTH 1 + +/* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */ +#define FR_AZ_FATAL_INTR_KER 0x00000230 +#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 +#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 +#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 +#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 +#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 +#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 +#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 +#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 +#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 +#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 +#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 +#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 +#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 +#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 +#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 +#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 +#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 +#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 +#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 +#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 +#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 +#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 +#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 +#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 +#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 +#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 +#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 +#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 +#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 +#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 +#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 +#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 +#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 +#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 +#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 +#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 +#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 +#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 +#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 +#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 +#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 +#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 +#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 +#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 +#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 +#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 +#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 +#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 +#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 +#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 +#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 +#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 +#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 +#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 +#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 +#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 + +/* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */ +#define FR_BZ_FATAL_INTR_CHAR 0x00000240 +#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 +#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 +#define FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN 43 +#define FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 +#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 +#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN 42 +#define FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN 41 +#define FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN 40 +#define FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN 39 +#define FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN 38 +#define FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 +#define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 +#define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN 35 +#define FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN 34 +#define FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN 33 +#define FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 +#define FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN 32 +#define FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 +#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 +#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 +#define FRF_BB_PCI_BUSERR_INT_CHAR_LBN 11 +#define FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH 1 +#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 +#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 +#define FRF_BZ_SRAM_OOB_INT_CHAR_LBN 10 +#define FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH 1 +#define FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN 9 +#define FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 +#define FRF_BZ_MEM_PERR_INT_CHAR_LBN 8 +#define FRF_BZ_MEM_PERR_INT_CHAR_WIDTH 1 +#define FRF_BZ_RBUF_OWN_INT_CHAR_LBN 7 +#define FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH 1 +#define FRF_BZ_TBUF_OWN_INT_CHAR_LBN 6 +#define FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH 1 +#define FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN 5 +#define FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 +#define FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN 4 +#define FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 +#define FRF_BZ_EVQ_OWN_INT_CHAR_LBN 3 +#define FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH 1 +#define FRF_BZ_EVF_OFLO_INT_CHAR_LBN 2 +#define FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH 1 +#define FRF_BZ_ILL_ADR_INT_CHAR_LBN 1 +#define FRF_BZ_ILL_ADR_INT_CHAR_WIDTH 1 +#define FRF_BZ_SRM_PERR_INT_CHAR_LBN 0 +#define FRF_BZ_SRM_PERR_INT_CHAR_WIDTH 1 + +/* DP_CTRL_REG: Datapath control register */ +#define FR_BZ_DP_CTRL 0x00000250 +#define FRF_BZ_FLS_EVQ_ID_LBN 0 +#define FRF_BZ_FLS_EVQ_ID_WIDTH 12 + +/* MEM_STAT_REG: Memory status register */ +#define FR_AZ_MEM_STAT 0x00000260 +#define FRF_AB_MEM_PERR_VEC_LBN 53 +#define FRF_AB_MEM_PERR_VEC_WIDTH 38 +#define FRF_AB_MBIST_CORR_LBN 38 +#define FRF_AB_MBIST_CORR_WIDTH 15 +#define FRF_AB_MBIST_ERR_LBN 0 +#define FRF_AB_MBIST_ERR_WIDTH 40 +#define FRF_CZ_MEM_PERR_VEC_LBN 0 +#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 + +/* CS_DEBUG_REG: Debug register */ +#define FR_AZ_CS_DEBUG 0x00000270 +#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 +#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 +#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 +#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 +#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 +#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 +#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 +#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 +#define FRF_CZ_CS_PORT_NUM_LBN 40 +#define FRF_CZ_CS_PORT_NUM_WIDTH 2 +#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 +#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 +#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 +#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 +#define FRF_CZ_CS_PORT_FPE_LBN 1 +#define FRF_CZ_CS_PORT_FPE_WIDTH 35 +#define FRF_AB_EM_DEBUG_ADDR_LBN 26 +#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 +#define FRF_AB_SR_DEBUG_ADDR_LBN 21 +#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 +#define FRF_AB_EV_DEBUG_ADDR_LBN 16 +#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 +#define FRF_AB_RX_DEBUG_ADDR_LBN 11 +#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 +#define FRF_AB_TX_DEBUG_ADDR_LBN 6 +#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 +#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 +#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 +#define FRF_AZ_CS_DEBUG_EN_LBN 0 +#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 + +/* DRIVER_REG: Driver scratch register [0-7] */ +#define FR_AZ_DRIVER 0x00000280 +#define FR_AZ_DRIVER_STEP 16 +#define FR_AZ_DRIVER_ROWS 8 +#define FRF_AZ_DRIVER_DW0_LBN 0 +#define FRF_AZ_DRIVER_DW0_WIDTH 32 + +/* ALTERA_BUILD_REG: Altera build register */ +#define FR_AZ_ALTERA_BUILD 0x00000300 +#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 +#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 + +/* CSR_SPARE_REG: Spare register */ +#define FR_AZ_CSR_SPARE 0x00000310 +#define FRF_AB_MEM_PERR_EN_LBN 64 +#define FRF_AB_MEM_PERR_EN_WIDTH 38 +#define FRF_CZ_MEM_PERR_EN_LBN 64 +#define FRF_CZ_MEM_PERR_EN_WIDTH 35 +#define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72 +#define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2 +#define FRF_AZ_CSR_SPARE_BITS_LBN 0 +#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 + +/* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */ +#define FR_AB_PCIE_SD_CTL0123 0x00000320 +#define FRF_AB_PCIE_TESTSIG_H_LBN 96 +#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 +#define FRF_AB_PCIE_TESTSIG_L_LBN 64 +#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 +#define FRF_AB_PCIE_OFFSET_LBN 56 +#define FRF_AB_PCIE_OFFSET_WIDTH 8 +#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 +#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 +#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 +#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 +#define FRF_AB_PCIE_HIVMODE_H_LBN 53 +#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 +#define FRF_AB_PCIE_HIVMODE_L_LBN 52 +#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 +#define FRF_AB_PCIE_PARRESET_H_LBN 51 +#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 +#define FRF_AB_PCIE_PARRESET_L_LBN 50 +#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 +#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 +#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 +#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 +#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 +#define FRF_AB_PCIE_LPBK_LBN 40 +#define FRF_AB_PCIE_LPBK_WIDTH 8 +#define FRF_AB_PCIE_PARLPBK_LBN 32 +#define FRF_AB_PCIE_PARLPBK_WIDTH 8 +#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 +#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 +#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 +#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 +#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 +#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 +#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 +#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 +#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 +#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 +#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 +#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 +#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 +#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 +#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 +#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 +#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 +#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 +#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 +#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 +#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 +#define FFE_AB_PCIE_RXEQCTL_OFF 2 +#define FFE_AB_PCIE_RXEQCTL_MIN 1 +#define FFE_AB_PCIE_RXEQCTL_MAX 0 +#define FRF_AB_PCIE_HIDRV_LBN 8 +#define FRF_AB_PCIE_HIDRV_WIDTH 8 +#define FRF_AB_PCIE_LODRV_LBN 0 +#define FRF_AB_PCIE_LODRV_WIDTH 8 + +/* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */ +#define FR_AB_PCIE_SD_CTL45 0x00000330 +#define FRF_AB_PCIE_DTX7_LBN 60 +#define FRF_AB_PCIE_DTX7_WIDTH 4 +#define FRF_AB_PCIE_DTX6_LBN 56 +#define FRF_AB_PCIE_DTX6_WIDTH 4 +#define FRF_AB_PCIE_DTX5_LBN 52 +#define FRF_AB_PCIE_DTX5_WIDTH 4 +#define FRF_AB_PCIE_DTX4_LBN 48 +#define FRF_AB_PCIE_DTX4_WIDTH 4 +#define FRF_AB_PCIE_DTX3_LBN 44 +#define FRF_AB_PCIE_DTX3_WIDTH 4 +#define FRF_AB_PCIE_DTX2_LBN 40 +#define FRF_AB_PCIE_DTX2_WIDTH 4 +#define FRF_AB_PCIE_DTX1_LBN 36 +#define FRF_AB_PCIE_DTX1_WIDTH 4 +#define FRF_AB_PCIE_DTX0_LBN 32 +#define FRF_AB_PCIE_DTX0_WIDTH 4 +#define FRF_AB_PCIE_DEQ7_LBN 28 +#define FRF_AB_PCIE_DEQ7_WIDTH 4 +#define FRF_AB_PCIE_DEQ6_LBN 24 +#define FRF_AB_PCIE_DEQ6_WIDTH 4 +#define FRF_AB_PCIE_DEQ5_LBN 20 +#define FRF_AB_PCIE_DEQ5_WIDTH 4 +#define FRF_AB_PCIE_DEQ4_LBN 16 +#define FRF_AB_PCIE_DEQ4_WIDTH 4 +#define FRF_AB_PCIE_DEQ3_LBN 12 +#define FRF_AB_PCIE_DEQ3_WIDTH 4 +#define FRF_AB_PCIE_DEQ2_LBN 8 +#define FRF_AB_PCIE_DEQ2_WIDTH 4 +#define FRF_AB_PCIE_DEQ1_LBN 4 +#define FRF_AB_PCIE_DEQ1_WIDTH 4 +#define FRF_AB_PCIE_DEQ0_LBN 0 +#define FRF_AB_PCIE_DEQ0_WIDTH 4 + +/* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */ +#define FR_AB_PCIE_PCS_CTL_STAT 0x00000340 +#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 +#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 +#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 +#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 +#define FRF_AB_PCIE_PRBSERR_LBN 40 +#define FRF_AB_PCIE_PRBSERR_WIDTH 8 +#define FRF_AB_PCIE_PRBSERRH0_LBN 32 +#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 +#define FRF_AB_PCIE_FASTINIT_H_LBN 15 +#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 +#define FRF_AB_PCIE_FASTINIT_L_LBN 14 +#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 +#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 +#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 +#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 +#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 +#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 +#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 +#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 +#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 +#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 +#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 +#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 +#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 +#define FRF_AB_PCIE_PRBSSEL_LBN 0 +#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 + +/* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */ +#define FR_BB_DEBUG_DATA_OUT 0x00000350 +#define FRF_BB_DEBUG2_PORT_LBN 25 +#define FRF_BB_DEBUG2_PORT_WIDTH 15 +#define FRF_BB_DEBUG1_PORT_LBN 0 +#define FRF_BB_DEBUG1_PORT_WIDTH 25 + +/* EVQ_RPTR_REGP0: Event queue read pointer register */ +#define FR_BZ_EVQ_RPTR_P0 0x00000400 +#define FR_BZ_EVQ_RPTR_P0_STEP 8192 +#define FR_BZ_EVQ_RPTR_P0_ROWS 1024 +/* EVQ_RPTR_REG_KER: Event queue read pointer register */ +#define FR_AA_EVQ_RPTR_KER 0x00011b00 +#define FR_AA_EVQ_RPTR_KER_STEP 4 +#define FR_AA_EVQ_RPTR_KER_ROWS 4 +/* EVQ_RPTR_REG: Event queue read pointer register */ +#define FR_BZ_EVQ_RPTR 0x00fa0000 +#define FR_BZ_EVQ_RPTR_STEP 16 +#define FR_BB_EVQ_RPTR_ROWS 4096 +#define FR_CZ_EVQ_RPTR_ROWS 1024 +/* EVQ_RPTR_REGP123: Event queue read pointer register */ +#define FR_BB_EVQ_RPTR_P123 0x01000400 +#define FR_BB_EVQ_RPTR_P123_STEP 8192 +#define FR_BB_EVQ_RPTR_P123_ROWS 3072 +#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 +#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 +#define FRF_AZ_EVQ_RPTR_LBN 0 +#define FRF_AZ_EVQ_RPTR_WIDTH 15 + +/* TIMER_COMMAND_REGP0: Timer Command Registers */ +#define FR_BZ_TIMER_COMMAND_P0 0x00000420 +#define FR_BZ_TIMER_COMMAND_P0_STEP 8192 +#define FR_BZ_TIMER_COMMAND_P0_ROWS 1024 +/* TIMER_COMMAND_REG_KER: Timer Command Registers */ +#define FR_AA_TIMER_COMMAND_KER 0x00000420 +#define FR_AA_TIMER_COMMAND_KER_STEP 8192 +#define FR_AA_TIMER_COMMAND_KER_ROWS 4 +/* TIMER_COMMAND_REGP123: Timer Command Registers */ +#define FR_BB_TIMER_COMMAND_P123 0x01000420 +#define FR_BB_TIMER_COMMAND_P123_STEP 8192 +#define FR_BB_TIMER_COMMAND_P123_ROWS 3072 +#define FRF_CZ_TC_TIMER_MODE_LBN 14 +#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 +#define FRF_AB_TC_TIMER_MODE_LBN 12 +#define FRF_AB_TC_TIMER_MODE_WIDTH 2 +#define FRF_CZ_TC_TIMER_VAL_LBN 0 +#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 +#define FRF_AB_TC_TIMER_VAL_LBN 0 +#define FRF_AB_TC_TIMER_VAL_WIDTH 12 + +/* DRV_EV_REG: Driver generated event register */ +#define FR_AZ_DRV_EV 0x00000440 +#define FRF_AZ_DRV_EV_QID_LBN 64 +#define FRF_AZ_DRV_EV_QID_WIDTH 12 +#define FRF_AZ_DRV_EV_DATA_LBN 0 +#define FRF_AZ_DRV_EV_DATA_WIDTH 64 + +/* EVQ_CTL_REG: Event queue control register */ +#define FR_AZ_EVQ_CTL 0x00000450 +#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 +#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 +#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 +#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 +#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 +#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 +#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 +#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 +#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 +#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 + +/* EVQ_CNT1_REG: Event counter 1 register */ +#define FR_AZ_EVQ_CNT1 0x00000460 +#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 +#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 +#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 +#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 +#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 +#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 +#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 +#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 +#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 +#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 + +/* EVQ_CNT2_REG: Event counter 2 register */ +#define FR_AZ_EVQ_CNT2 0x00000470 +#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 +#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 +#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_RDY_CNT_LBN 80 +#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 +#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 +#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 +#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 +#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 +#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 +#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 + +/* USR_EV_REG: Event mailbox register */ +#define FR_CZ_USR_EV 0x00000540 +#define FR_CZ_USR_EV_STEP 8192 +#define FR_CZ_USR_EV_ROWS 1024 +#define FRF_CZ_USR_EV_DATA_LBN 0 +#define FRF_CZ_USR_EV_DATA_WIDTH 32 + +/* BUF_TBL_CFG_REG: Buffer table configuration register */ +#define FR_AZ_BUF_TBL_CFG 0x00000600 +#define FRF_AZ_BUF_TBL_MODE_LBN 3 +#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 + +/* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */ +#define FR_AZ_SRM_RX_DC_CFG 0x00000610 +#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 +#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 +#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 +#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 + +/* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */ +#define FR_AZ_SRM_TX_DC_CFG 0x00000620 +#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 +#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 + +/* SRM_CFG_REG: SRAM configuration register */ +#define FR_AZ_SRM_CFG 0x00000630 +#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 +#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 +#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 +#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 +#define FRF_AZ_SRM_INIT_EN_LBN 3 +#define FRF_AZ_SRM_INIT_EN_WIDTH 1 +#define FRF_AZ_SRM_NUM_BANK_LBN 2 +#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 +#define FRF_AZ_SRM_BANK_SIZE_LBN 0 +#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 + +/* BUF_TBL_UPD_REG: Buffer table update register */ +#define FR_AZ_BUF_TBL_UPD 0x00000650 +#define FRF_AZ_BUF_UPD_CMD_LBN 63 +#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 +#define FRF_AZ_BUF_CLR_CMD_LBN 62 +#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 +#define FRF_AZ_BUF_CLR_END_ID_LBN 32 +#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 +#define FRF_AZ_BUF_CLR_START_ID_LBN 0 +#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 + +/* SRM_UPD_EVQ_REG: Buffer table update register */ +#define FR_AZ_SRM_UPD_EVQ 0x00000660 +#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 +#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 + +/* SRAM_PARITY_REG: SRAM parity register. */ +#define FR_AZ_SRAM_PARITY 0x00000670 +#define FRF_CZ_BYPASS_ECC_LBN 3 +#define FRF_CZ_BYPASS_ECC_WIDTH 1 +#define FRF_CZ_SEC_INT_LBN 2 +#define FRF_CZ_SEC_INT_WIDTH 1 +#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 +#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 +#define FRF_AB_FORCE_SRAM_PERR_LBN 0 +#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 +#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 +#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 + +/* RX_CFG_REG: Receive configuration register */ +#define FR_AZ_RX_CFG 0x00000800 +#define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72 +#define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14 +#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 +#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 +#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 +#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 +#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 +#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 +#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 +#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 +#define FRF_BZ_RX_TCP_SUP_LBN 48 +#define FRF_BZ_RX_TCP_SUP_WIDTH 1 +#define FRF_BZ_RX_INGR_EN_LBN 47 +#define FRF_BZ_RX_INGR_EN_WIDTH 1 +#define FRF_BZ_RX_IP_HASH_LBN 46 +#define FRF_BZ_RX_IP_HASH_WIDTH 1 +#define FRF_BZ_RX_HASH_ALG_LBN 45 +#define FRF_BZ_RX_HASH_ALG_WIDTH 1 +#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 +#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 +#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 +#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 +#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 +#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 +#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 +#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 +#define FRF_BZ_RX_OWNERR_CTL_LBN 38 +#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 +#define FRF_BZ_RX_XON_TX_TH_LBN 33 +#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 +#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 +#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 +#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 +#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 +#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 +#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 +#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 +#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 +#define FRF_AA_RX_OWNERR_CTL_LBN 30 +#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 +#define FRF_AA_RX_XON_TX_TH_LBN 25 +#define FRF_AA_RX_XON_TX_TH_WIDTH 5 +#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 +#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 +#define FRF_AA_RX_XOFF_TX_TH_LBN 20 +#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 +#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 +#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 +#define FRF_BZ_RX_XON_MAC_TH_LBN 10 +#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 +#define FRF_AA_RX_XON_MAC_TH_LBN 6 +#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 +#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 +#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 +#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 +#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 +#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 +#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 + +/* RX_FILTER_CTL_REG: Receive filter control registers */ +#define FR_BZ_RX_FILTER_CTL 0x00000810 +#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 +#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 +#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 +#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 +#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 +#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 +#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 +#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 +#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 +#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 +#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 +#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 +#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 +#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 +#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 +#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 +#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 +#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 +#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 +#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 +#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 +#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 +#define FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN 32 +#define FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 +#define FRF_BZ_NUM_KER_LBN 24 +#define FRF_BZ_NUM_KER_WIDTH 2 +#define FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN 16 +#define FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 +#define FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN 8 +#define FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 +#define FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN 0 +#define FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 + +/* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */ +#define FR_AZ_RX_FLUSH_DESCQ 0x00000820 +#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 +#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 +#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 +#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 + +/* RX_DESC_UPD_REGP0: Receive descriptor update register. */ +#define FR_BZ_RX_DESC_UPD_P0 0x00000830 +#define FR_BZ_RX_DESC_UPD_P0_STEP 8192 +#define FR_BZ_RX_DESC_UPD_P0_ROWS 1024 +/* RX_DESC_UPD_REG_KER: Receive descriptor update register. */ +#define FR_AA_RX_DESC_UPD_KER 0x00000830 +#define FR_AA_RX_DESC_UPD_KER_STEP 8192 +#define FR_AA_RX_DESC_UPD_KER_ROWS 4 +/* RX_DESC_UPD_REGP123: Receive descriptor update register. */ +#define FR_BB_RX_DESC_UPD_P123 0x01000830 +#define FR_BB_RX_DESC_UPD_P123_STEP 8192 +#define FR_BB_RX_DESC_UPD_P123_ROWS 3072 +#define FRF_AZ_RX_DESC_WPTR_LBN 96 +#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 +#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 +#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 +#define FRF_AZ_RX_DESC_LBN 0 +#define FRF_AZ_RX_DESC_WIDTH 64 + +/* RX_DC_CFG_REG: Receive descriptor cache configuration register */ +#define FR_AZ_RX_DC_CFG 0x00000840 +#define FRF_AB_RX_MAX_PF_LBN 2 +#define FRF_AB_RX_MAX_PF_WIDTH 2 +#define FRF_AZ_RX_DC_SIZE_LBN 0 +#define FRF_AZ_RX_DC_SIZE_WIDTH 2 +#define FFE_AZ_RX_DC_SIZE_64 3 +#define FFE_AZ_RX_DC_SIZE_32 2 +#define FFE_AZ_RX_DC_SIZE_16 1 +#define FFE_AZ_RX_DC_SIZE_8 0 + +/* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */ +#define FR_AZ_RX_DC_PF_WM 0x00000850 +#define FRF_AZ_RX_DC_PF_HWM_LBN 6 +#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 +#define FRF_AZ_RX_DC_PF_LWM_LBN 0 +#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 + +/* RX_RSS_TKEY_REG: RSS Toeplitz hash key */ +#define FR_BZ_RX_RSS_TKEY 0x00000860 +#define FRF_BZ_RX_RSS_TKEY_HI_LBN 64 +#define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64 +#define FRF_BZ_RX_RSS_TKEY_LO_LBN 0 +#define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64 + +/* RX_NODESC_DROP_REG: Receive dropped packet counter register */ +#define FR_AZ_RX_NODESC_DROP 0x00000880 +#define FRF_CZ_RX_NODESC_DROP_CNT_LBN 0 +#define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32 +#define FRF_AB_RX_NODESC_DROP_CNT_LBN 0 +#define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16 + +/* RX_SELF_RST_REG: Receive self reset register */ +#define FR_AA_RX_SELF_RST 0x00000890 +#define FRF_AA_RX_ISCSI_DIS_LBN 17 +#define FRF_AA_RX_ISCSI_DIS_WIDTH 1 +#define FRF_AA_RX_SW_RST_REG_LBN 16 +#define FRF_AA_RX_SW_RST_REG_WIDTH 1 +#define FRF_AA_RX_NODESC_WAIT_DIS_LBN 9 +#define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH 1 +#define FRF_AA_RX_SELF_RST_EN_LBN 8 +#define FRF_AA_RX_SELF_RST_EN_WIDTH 1 +#define FRF_AA_RX_MAX_PF_LAT_LBN 4 +#define FRF_AA_RX_MAX_PF_LAT_WIDTH 4 +#define FRF_AA_RX_MAX_LU_LAT_LBN 0 +#define FRF_AA_RX_MAX_LU_LAT_WIDTH 4 + +/* RX_DEBUG_REG: undocumented register */ +#define FR_AZ_RX_DEBUG 0x000008a0 +#define FRF_AZ_RX_DEBUG_LBN 0 +#define FRF_AZ_RX_DEBUG_WIDTH 64 + +/* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */ +#define FR_AZ_RX_PUSH_DROP 0x000008b0 +#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 +#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 + +/* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */ +#define FR_CZ_RX_RSS_IPV6_REG1 0x000008d0 +#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 +#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 + +/* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */ +#define FR_CZ_RX_RSS_IPV6_REG2 0x000008e0 +#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 +#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 + +/* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */ +#define FR_CZ_RX_RSS_IPV6_REG3 0x000008f0 +#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 +#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 +#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 +#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 +#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 +#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 +#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 +#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 + +/* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */ +#define FR_AZ_TX_FLUSH_DESCQ 0x00000a00 +#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 +#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 +#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 +#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 + +/* TX_DESC_UPD_REGP0: Transmit descriptor update register. */ +#define FR_BZ_TX_DESC_UPD_P0 0x00000a10 +#define FR_BZ_TX_DESC_UPD_P0_STEP 8192 +#define FR_BZ_TX_DESC_UPD_P0_ROWS 1024 +/* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */ +#define FR_AA_TX_DESC_UPD_KER 0x00000a10 +#define FR_AA_TX_DESC_UPD_KER_STEP 8192 +#define FR_AA_TX_DESC_UPD_KER_ROWS 8 +/* TX_DESC_UPD_REGP123: Transmit descriptor update register. */ +#define FR_BB_TX_DESC_UPD_P123 0x01000a10 +#define FR_BB_TX_DESC_UPD_P123_STEP 8192 +#define FR_BB_TX_DESC_UPD_P123_ROWS 3072 +#define FRF_AZ_TX_DESC_WPTR_LBN 96 +#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 +#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 +#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 +#define FRF_AZ_TX_DESC_LBN 0 +#define FRF_AZ_TX_DESC_WIDTH 95 + +/* TX_DC_CFG_REG: Transmit descriptor cache configuration register */ +#define FR_AZ_TX_DC_CFG 0x00000a20 +#define FRF_AZ_TX_DC_SIZE_LBN 0 +#define FRF_AZ_TX_DC_SIZE_WIDTH 2 +#define FFE_AZ_TX_DC_SIZE_32 2 +#define FFE_AZ_TX_DC_SIZE_16 1 +#define FFE_AZ_TX_DC_SIZE_8 0 + +/* TX_CHKSM_CFG_REG: Transmit checksum configuration register */ +#define FR_AA_TX_CHKSM_CFG 0x00000a30 +#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 +#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 +#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 +#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 +#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 +#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 +#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 +#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 + +/* TX_CFG_REG: Transmit configuration register */ +#define FR_AZ_TX_CFG 0x00000a50 +#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 +#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 +#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 +#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 +#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 +#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 +#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 +#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 +#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 +#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 +#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 +#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 +#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 +#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 +#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 +#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 +#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 +#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 +#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 +#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 +#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 +#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 +#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 +#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 +#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 +#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 +#define FRF_AZ_TX_P1_PRI_EN_LBN 4 +#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 +#define FRF_AZ_TX_OWNERR_CTL_LBN 2 +#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 +#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 +#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 +#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 +#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 + +/* TX_PUSH_DROP_REG: Transmit push dropped register */ +#define FR_AZ_TX_PUSH_DROP 0x00000a60 +#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 +#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 + +/* TX_RESERVED_REG: Transmit configuration register */ +#define FR_AZ_TX_RESERVED 0x00000a80 +#define FRF_AZ_TX_EVT_CNT_LBN 121 +#define FRF_AZ_TX_EVT_CNT_WIDTH 7 +#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 +#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 +#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 +#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 +#define FRF_AZ_TX_PUSH_EN_LBN 89 +#define FRF_AZ_TX_PUSH_EN_WIDTH 1 +#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 +#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 +#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 +#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 +#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 +#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 +#define FRF_AZ_TX_DMAQ_ST_LBN 78 +#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 +#define FRF_AZ_TX_RX_SPACER_LBN 64 +#define FRF_AZ_TX_RX_SPACER_WIDTH 8 +#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 +#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 +#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 +#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 +#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 +#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 +#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 +#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 +#define FRF_AZ_TX_XP_TIMER_LBN 52 +#define FRF_AZ_TX_XP_TIMER_WIDTH 5 +#define FRF_AZ_TX_PREF_SPACER_LBN 44 +#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 +#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 +#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 +#define FRF_AZ_TX_ONLY1TAG_LBN 21 +#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 +#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 +#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 +#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 +#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 +#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 +#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 +#define FRF_AA_TX_DMA_FF_THR_LBN 16 +#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 +#define FRF_AZ_TX_DMA_SPACER_LBN 8 +#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 +#define FRF_AA_TX_TCP_DIS_LBN 7 +#define FRF_AA_TX_TCP_DIS_WIDTH 1 +#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 +#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 +#define FRF_AA_TX_IP_DIS_LBN 6 +#define FRF_AA_TX_IP_DIS_WIDTH 1 +#define FRF_AZ_TX_MAX_CPL_LBN 2 +#define FRF_AZ_TX_MAX_CPL_WIDTH 2 +#define FFE_AZ_TX_MAX_CPL_16 3 +#define FFE_AZ_TX_MAX_CPL_8 2 +#define FFE_AZ_TX_MAX_CPL_4 1 +#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 +#define FRF_AZ_TX_MAX_PREF_LBN 0 +#define FRF_AZ_TX_MAX_PREF_WIDTH 2 +#define FFE_AZ_TX_MAX_PREF_32 3 +#define FFE_AZ_TX_MAX_PREF_16 2 +#define FFE_AZ_TX_MAX_PREF_8 1 +#define FFE_AZ_TX_MAX_PREF_OFF 0 + +/* TX_PACE_REG: Transmit pace control register */ +#define FR_BZ_TX_PACE 0x00000a90 +#define FRF_BZ_TX_PACE_SB_NOT_AF_LBN 19 +#define FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH 10 +#define FRF_BZ_TX_PACE_SB_AF_LBN 9 +#define FRF_BZ_TX_PACE_SB_AF_WIDTH 10 +#define FRF_BZ_TX_PACE_FB_BASE_LBN 5 +#define FRF_BZ_TX_PACE_FB_BASE_WIDTH 4 +#define FRF_BZ_TX_PACE_BIN_TH_LBN 0 +#define FRF_BZ_TX_PACE_BIN_TH_WIDTH 5 + +/* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */ +#define FR_BZ_TX_PACE_DROP_QID 0x00000aa0 +#define FRF_BZ_TX_PACE_QID_DRP_CNT_LBN 0 +#define FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH 16 + +/* TX_VLAN_REG: Transmit VLAN tag register */ +#define FR_BB_TX_VLAN 0x00000ae0 +#define FRF_BB_TX_VLAN_EN_LBN 127 +#define FRF_BB_TX_VLAN_EN_WIDTH 1 +#define FRF_BB_TX_VLAN7_PORT1_EN_LBN 125 +#define FRF_BB_TX_VLAN7_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN7_PORT0_EN_LBN 124 +#define FRF_BB_TX_VLAN7_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN7_LBN 112 +#define FRF_BB_TX_VLAN7_WIDTH 12 +#define FRF_BB_TX_VLAN6_PORT1_EN_LBN 109 +#define FRF_BB_TX_VLAN6_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN6_PORT0_EN_LBN 108 +#define FRF_BB_TX_VLAN6_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN6_LBN 96 +#define FRF_BB_TX_VLAN6_WIDTH 12 +#define FRF_BB_TX_VLAN5_PORT1_EN_LBN 93 +#define FRF_BB_TX_VLAN5_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN5_PORT0_EN_LBN 92 +#define FRF_BB_TX_VLAN5_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN5_LBN 80 +#define FRF_BB_TX_VLAN5_WIDTH 12 +#define FRF_BB_TX_VLAN4_PORT1_EN_LBN 77 +#define FRF_BB_TX_VLAN4_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN4_PORT0_EN_LBN 76 +#define FRF_BB_TX_VLAN4_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN4_LBN 64 +#define FRF_BB_TX_VLAN4_WIDTH 12 +#define FRF_BB_TX_VLAN3_PORT1_EN_LBN 61 +#define FRF_BB_TX_VLAN3_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN3_PORT0_EN_LBN 60 +#define FRF_BB_TX_VLAN3_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN3_LBN 48 +#define FRF_BB_TX_VLAN3_WIDTH 12 +#define FRF_BB_TX_VLAN2_PORT1_EN_LBN 45 +#define FRF_BB_TX_VLAN2_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN2_PORT0_EN_LBN 44 +#define FRF_BB_TX_VLAN2_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN2_LBN 32 +#define FRF_BB_TX_VLAN2_WIDTH 12 +#define FRF_BB_TX_VLAN1_PORT1_EN_LBN 29 +#define FRF_BB_TX_VLAN1_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN1_PORT0_EN_LBN 28 +#define FRF_BB_TX_VLAN1_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN1_LBN 16 +#define FRF_BB_TX_VLAN1_WIDTH 12 +#define FRF_BB_TX_VLAN0_PORT1_EN_LBN 13 +#define FRF_BB_TX_VLAN0_PORT1_EN_WIDTH 1 +#define FRF_BB_TX_VLAN0_PORT0_EN_LBN 12 +#define FRF_BB_TX_VLAN0_PORT0_EN_WIDTH 1 +#define FRF_BB_TX_VLAN0_LBN 0 +#define FRF_BB_TX_VLAN0_WIDTH 12 + +/* TX_IPFIL_PORTEN_REG: Transmit filter control register */ +#define FR_BZ_TX_IPFIL_PORTEN 0x00000af0 +#define FRF_BZ_TX_MADR0_FIL_EN_LBN 64 +#define FRF_BZ_TX_MADR0_FIL_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL31_PORT_EN_LBN 62 +#define FRF_BB_TX_IPFIL31_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL30_PORT_EN_LBN 60 +#define FRF_BB_TX_IPFIL30_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL29_PORT_EN_LBN 58 +#define FRF_BB_TX_IPFIL29_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL28_PORT_EN_LBN 56 +#define FRF_BB_TX_IPFIL28_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL27_PORT_EN_LBN 54 +#define FRF_BB_TX_IPFIL27_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL26_PORT_EN_LBN 52 +#define FRF_BB_TX_IPFIL26_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL25_PORT_EN_LBN 50 +#define FRF_BB_TX_IPFIL25_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL24_PORT_EN_LBN 48 +#define FRF_BB_TX_IPFIL24_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL23_PORT_EN_LBN 46 +#define FRF_BB_TX_IPFIL23_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL22_PORT_EN_LBN 44 +#define FRF_BB_TX_IPFIL22_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL21_PORT_EN_LBN 42 +#define FRF_BB_TX_IPFIL21_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL20_PORT_EN_LBN 40 +#define FRF_BB_TX_IPFIL20_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL19_PORT_EN_LBN 38 +#define FRF_BB_TX_IPFIL19_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL18_PORT_EN_LBN 36 +#define FRF_BB_TX_IPFIL18_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL17_PORT_EN_LBN 34 +#define FRF_BB_TX_IPFIL17_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL16_PORT_EN_LBN 32 +#define FRF_BB_TX_IPFIL16_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL15_PORT_EN_LBN 30 +#define FRF_BB_TX_IPFIL15_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL14_PORT_EN_LBN 28 +#define FRF_BB_TX_IPFIL14_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL13_PORT_EN_LBN 26 +#define FRF_BB_TX_IPFIL13_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL12_PORT_EN_LBN 24 +#define FRF_BB_TX_IPFIL12_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL11_PORT_EN_LBN 22 +#define FRF_BB_TX_IPFIL11_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL10_PORT_EN_LBN 20 +#define FRF_BB_TX_IPFIL10_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL9_PORT_EN_LBN 18 +#define FRF_BB_TX_IPFIL9_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL8_PORT_EN_LBN 16 +#define FRF_BB_TX_IPFIL8_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL7_PORT_EN_LBN 14 +#define FRF_BB_TX_IPFIL7_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL6_PORT_EN_LBN 12 +#define FRF_BB_TX_IPFIL6_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL5_PORT_EN_LBN 10 +#define FRF_BB_TX_IPFIL5_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL4_PORT_EN_LBN 8 +#define FRF_BB_TX_IPFIL4_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL3_PORT_EN_LBN 6 +#define FRF_BB_TX_IPFIL3_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL2_PORT_EN_LBN 4 +#define FRF_BB_TX_IPFIL2_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL1_PORT_EN_LBN 2 +#define FRF_BB_TX_IPFIL1_PORT_EN_WIDTH 1 +#define FRF_BB_TX_IPFIL0_PORT_EN_LBN 0 +#define FRF_BB_TX_IPFIL0_PORT_EN_WIDTH 1 + +/* TX_IPFIL_TBL: Transmit IP source address filter table */ +#define FR_BB_TX_IPFIL_TBL 0x00000b00 +#define FR_BB_TX_IPFIL_TBL_STEP 16 +#define FR_BB_TX_IPFIL_TBL_ROWS 16 +#define FRF_BB_TX_IPFIL_MASK_1_LBN 96 +#define FRF_BB_TX_IPFIL_MASK_1_WIDTH 32 +#define FRF_BB_TX_IP_SRC_ADR_1_LBN 64 +#define FRF_BB_TX_IP_SRC_ADR_1_WIDTH 32 +#define FRF_BB_TX_IPFIL_MASK_0_LBN 32 +#define FRF_BB_TX_IPFIL_MASK_0_WIDTH 32 +#define FRF_BB_TX_IP_SRC_ADR_0_LBN 0 +#define FRF_BB_TX_IP_SRC_ADR_0_WIDTH 32 + +/* MD_TXD_REG: PHY management transmit data register */ +#define FR_AB_MD_TXD 0x00000c00 +#define FRF_AB_MD_TXD_LBN 0 +#define FRF_AB_MD_TXD_WIDTH 16 + +/* MD_RXD_REG: PHY management receive data register */ +#define FR_AB_MD_RXD 0x00000c10 +#define FRF_AB_MD_RXD_LBN 0 +#define FRF_AB_MD_RXD_WIDTH 16 + +/* MD_CS_REG: PHY management configuration & status register */ +#define FR_AB_MD_CS 0x00000c20 +#define FRF_AB_MD_RD_EN_CMD_LBN 15 +#define FRF_AB_MD_RD_EN_CMD_WIDTH 1 +#define FRF_AB_MD_WR_EN_CMD_LBN 14 +#define FRF_AB_MD_WR_EN_CMD_WIDTH 1 +#define FRF_AB_MD_ADDR_CMD_LBN 13 +#define FRF_AB_MD_ADDR_CMD_WIDTH 1 +#define FRF_AB_MD_PT_LBN 7 +#define FRF_AB_MD_PT_WIDTH 3 +#define FRF_AB_MD_PL_LBN 6 +#define FRF_AB_MD_PL_WIDTH 1 +#define FRF_AB_MD_INT_CLR_LBN 5 +#define FRF_AB_MD_INT_CLR_WIDTH 1 +#define FRF_AB_MD_GC_LBN 4 +#define FRF_AB_MD_GC_WIDTH 1 +#define FRF_AB_MD_PRSP_LBN 3 +#define FRF_AB_MD_PRSP_WIDTH 1 +#define FRF_AB_MD_RIC_LBN 2 +#define FRF_AB_MD_RIC_WIDTH 1 +#define FRF_AB_MD_RDC_LBN 1 +#define FRF_AB_MD_RDC_WIDTH 1 +#define FRF_AB_MD_WRC_LBN 0 +#define FRF_AB_MD_WRC_WIDTH 1 + +/* MD_PHY_ADR_REG: PHY management PHY address register */ +#define FR_AB_MD_PHY_ADR 0x00000c30 +#define FRF_AB_MD_PHY_ADR_LBN 0 +#define FRF_AB_MD_PHY_ADR_WIDTH 16 + +/* MD_ID_REG: PHY management ID register */ +#define FR_AB_MD_ID 0x00000c40 +#define FRF_AB_MD_PRT_ADR_LBN 11 +#define FRF_AB_MD_PRT_ADR_WIDTH 5 +#define FRF_AB_MD_DEV_ADR_LBN 6 +#define FRF_AB_MD_DEV_ADR_WIDTH 5 + +/* MD_STAT_REG: PHY management status & mask register */ +#define FR_AB_MD_STAT 0x00000c50 +#define FRF_AB_MD_PINT_LBN 4 +#define FRF_AB_MD_PINT_WIDTH 1 +#define FRF_AB_MD_DONE_LBN 3 +#define FRF_AB_MD_DONE_WIDTH 1 +#define FRF_AB_MD_BSERR_LBN 2 +#define FRF_AB_MD_BSERR_WIDTH 1 +#define FRF_AB_MD_LNFL_LBN 1 +#define FRF_AB_MD_LNFL_WIDTH 1 +#define FRF_AB_MD_BSY_LBN 0 +#define FRF_AB_MD_BSY_WIDTH 1 + +/* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */ +#define FR_AB_MAC_STAT_DMA 0x00000c60 +#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 +#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 +#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 +#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 + +/* MAC_CTRL_REG: Port MAC control register */ +#define FR_AB_MAC_CTRL 0x00000c80 +#define FRF_AB_MAC_XOFF_VAL_LBN 16 +#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 +#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 +#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 +#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 +#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 +#define FRF_AB_MAC_BCAD_ACPT_LBN 4 +#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 +#define FRF_AB_MAC_UC_PROM_LBN 3 +#define FRF_AB_MAC_UC_PROM_WIDTH 1 +#define FRF_AB_MAC_LINK_STATUS_LBN 2 +#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 +#define FRF_AB_MAC_SPEED_LBN 0 +#define FRF_AB_MAC_SPEED_WIDTH 2 +#define FFE_AB_MAC_SPEED_10G 3 +#define FFE_AB_MAC_SPEED_1G 2 +#define FFE_AB_MAC_SPEED_100M 1 +#define FFE_AB_MAC_SPEED_10M 0 + +/* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */ +#define FR_BB_GEN_MODE 0x00000c90 +#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 +#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 +#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 +#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 +#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 +#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 +#define FRF_BB_XG_PHY_INT_MASK_LBN 0 +#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 + +/* MAC_MC_HASH_REG0: Multicast address hash table */ +#define FR_AB_MAC_MC_HASH_REG0 0x00000ca0 +#define FRF_AB_MAC_MCAST_HASH0_LBN 0 +#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 + +/* MAC_MC_HASH_REG1: Multicast address hash table */ +#define FR_AB_MAC_MC_HASH_REG1 0x00000cb0 +#define FRF_AB_MAC_MCAST_HASH1_LBN 0 +#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 + +/* GM_CFG1_REG: GMAC configuration register 1 */ +#define FR_AB_GM_CFG1 0x00000e00 +#define FRF_AB_GM_SW_RST_LBN 31 +#define FRF_AB_GM_SW_RST_WIDTH 1 +#define FRF_AB_GM_SIM_RST_LBN 30 +#define FRF_AB_GM_SIM_RST_WIDTH 1 +#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 +#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 +#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 +#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 +#define FRF_AB_GM_RST_RX_FUNC_LBN 17 +#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 +#define FRF_AB_GM_RST_TX_FUNC_LBN 16 +#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 +#define FRF_AB_GM_LOOP_LBN 8 +#define FRF_AB_GM_LOOP_WIDTH 1 +#define FRF_AB_GM_RX_FC_EN_LBN 5 +#define FRF_AB_GM_RX_FC_EN_WIDTH 1 +#define FRF_AB_GM_TX_FC_EN_LBN 4 +#define FRF_AB_GM_TX_FC_EN_WIDTH 1 +#define FRF_AB_GM_SYNC_RXEN_LBN 3 +#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 +#define FRF_AB_GM_RX_EN_LBN 2 +#define FRF_AB_GM_RX_EN_WIDTH 1 +#define FRF_AB_GM_SYNC_TXEN_LBN 1 +#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 +#define FRF_AB_GM_TX_EN_LBN 0 +#define FRF_AB_GM_TX_EN_WIDTH 1 + +/* GM_CFG2_REG: GMAC configuration register 2 */ +#define FR_AB_GM_CFG2 0x00000e10 +#define FRF_AB_GM_PAMBL_LEN_LBN 12 +#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 +#define FRF_AB_GM_IF_MODE_LBN 8 +#define FRF_AB_GM_IF_MODE_WIDTH 2 +#define FFE_AB_IF_MODE_BYTE_MODE 2 +#define FFE_AB_IF_MODE_NIBBLE_MODE 1 +#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 +#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 +#define FRF_AB_GM_LEN_CHK_LBN 4 +#define FRF_AB_GM_LEN_CHK_WIDTH 1 +#define FRF_AB_GM_PAD_CRC_EN_LBN 2 +#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 +#define FRF_AB_GM_CRC_EN_LBN 1 +#define FRF_AB_GM_CRC_EN_WIDTH 1 +#define FRF_AB_GM_FD_LBN 0 +#define FRF_AB_GM_FD_WIDTH 1 + +/* GM_IPG_REG: GMAC IPG register */ +#define FR_AB_GM_IPG 0x00000e20 +#define FRF_AB_GM_NONB2B_IPG1_LBN 24 +#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 +#define FRF_AB_GM_NONB2B_IPG2_LBN 16 +#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 +#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 +#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 +#define FRF_AB_GM_B2B_IPG_LBN 0 +#define FRF_AB_GM_B2B_IPG_WIDTH 7 + +/* GM_HD_REG: GMAC half duplex register */ +#define FR_AB_GM_HD 0x00000e30 +#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 +#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 +#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 +#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 +#define FRF_AB_GM_BP_NO_BOFF_LBN 18 +#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 +#define FRF_AB_GM_DIS_BOFF_LBN 17 +#define FRF_AB_GM_DIS_BOFF_WIDTH 1 +#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 +#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 +#define FRF_AB_GM_RTRY_LIMIT_LBN 12 +#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 +#define FRF_AB_GM_COL_WIN_LBN 0 +#define FRF_AB_GM_COL_WIN_WIDTH 10 + +/* GM_MAX_FLEN_REG: GMAC maximum frame length register */ +#define FR_AB_GM_MAX_FLEN 0x00000e40 +#define FRF_AB_GM_MAX_FLEN_LBN 0 +#define FRF_AB_GM_MAX_FLEN_WIDTH 16 + +/* GM_TEST_REG: GMAC test register */ +#define FR_AB_GM_TEST 0x00000e70 +#define FRF_AB_GM_MAX_BOFF_LBN 3 +#define FRF_AB_GM_MAX_BOFF_WIDTH 1 +#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 +#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 +#define FRF_AB_GM_TEST_PAUSE_LBN 1 +#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 +#define FRF_AB_GM_SHORT_SLOT_LBN 0 +#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 + +/* GM_ADR1_REG: GMAC station address register 1 */ +#define FR_AB_GM_ADR1 0x00000f00 +#define FRF_AB_GM_ADR_B0_LBN 24 +#define FRF_AB_GM_ADR_B0_WIDTH 8 +#define FRF_AB_GM_ADR_B1_LBN 16 +#define FRF_AB_GM_ADR_B1_WIDTH 8 +#define FRF_AB_GM_ADR_B2_LBN 8 +#define FRF_AB_GM_ADR_B2_WIDTH 8 +#define FRF_AB_GM_ADR_B3_LBN 0 +#define FRF_AB_GM_ADR_B3_WIDTH 8 + +/* GM_ADR2_REG: GMAC station address register 2 */ +#define FR_AB_GM_ADR2 0x00000f10 +#define FRF_AB_GM_ADR_B4_LBN 24 +#define FRF_AB_GM_ADR_B4_WIDTH 8 +#define FRF_AB_GM_ADR_B5_LBN 16 +#define FRF_AB_GM_ADR_B5_WIDTH 8 + +/* GMF_CFG0_REG: GMAC FIFO configuration register 0 */ +#define FR_AB_GMF_CFG0 0x00000f20 +#define FRF_AB_GMF_FTFENRPLY_LBN 20 +#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 +#define FRF_AB_GMF_STFENRPLY_LBN 19 +#define FRF_AB_GMF_STFENRPLY_WIDTH 1 +#define FRF_AB_GMF_FRFENRPLY_LBN 18 +#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 +#define FRF_AB_GMF_SRFENRPLY_LBN 17 +#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 +#define FRF_AB_GMF_WTMENRPLY_LBN 16 +#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 +#define FRF_AB_GMF_FTFENREQ_LBN 12 +#define FRF_AB_GMF_FTFENREQ_WIDTH 1 +#define FRF_AB_GMF_STFENREQ_LBN 11 +#define FRF_AB_GMF_STFENREQ_WIDTH 1 +#define FRF_AB_GMF_FRFENREQ_LBN 10 +#define FRF_AB_GMF_FRFENREQ_WIDTH 1 +#define FRF_AB_GMF_SRFENREQ_LBN 9 +#define FRF_AB_GMF_SRFENREQ_WIDTH 1 +#define FRF_AB_GMF_WTMENREQ_LBN 8 +#define FRF_AB_GMF_WTMENREQ_WIDTH 1 +#define FRF_AB_GMF_HSTRSTFT_LBN 4 +#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 +#define FRF_AB_GMF_HSTRSTST_LBN 3 +#define FRF_AB_GMF_HSTRSTST_WIDTH 1 +#define FRF_AB_GMF_HSTRSTFR_LBN 2 +#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 +#define FRF_AB_GMF_HSTRSTSR_LBN 1 +#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 +#define FRF_AB_GMF_HSTRSTWT_LBN 0 +#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 + +/* GMF_CFG1_REG: GMAC FIFO configuration register 1 */ +#define FR_AB_GMF_CFG1 0x00000f30 +#define FRF_AB_GMF_CFGFRTH_LBN 16 +#define FRF_AB_GMF_CFGFRTH_WIDTH 5 +#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 +#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 + +/* GMF_CFG2_REG: GMAC FIFO configuration register 2 */ +#define FR_AB_GMF_CFG2 0x00000f40 +#define FRF_AB_GMF_CFGHWM_LBN 16 +#define FRF_AB_GMF_CFGHWM_WIDTH 6 +#define FRF_AB_GMF_CFGLWM_LBN 0 +#define FRF_AB_GMF_CFGLWM_WIDTH 6 + +/* GMF_CFG3_REG: GMAC FIFO configuration register 3 */ +#define FR_AB_GMF_CFG3 0x00000f50 +#define FRF_AB_GMF_CFGHWMFT_LBN 16 +#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 +#define FRF_AB_GMF_CFGFTTH_LBN 0 +#define FRF_AB_GMF_CFGFTTH_WIDTH 6 + +/* GMF_CFG4_REG: GMAC FIFO configuration register 4 */ +#define FR_AB_GMF_CFG4 0x00000f60 +#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 +#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 + +/* GMF_CFG5_REG: GMAC FIFO configuration register 5 */ +#define FR_AB_GMF_CFG5 0x00000f70 +#define FRF_AB_GMF_CFGHDPLX_LBN 22 +#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 +#define FRF_AB_GMF_SRFULL_LBN 21 +#define FRF_AB_GMF_SRFULL_WIDTH 1 +#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 +#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 +#define FRF_AB_GMF_CFGBYTMODE_LBN 19 +#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 +#define FRF_AB_GMF_HSTDRPLT64_LBN 18 +#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 +#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 +#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 + +/* TX_SRC_MAC_TBL: Transmit IP source address filter table */ +#define FR_BB_TX_SRC_MAC_TBL 0x00001000 +#define FR_BB_TX_SRC_MAC_TBL_STEP 16 +#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 +#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 +#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 +#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 +#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 + +/* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */ +#define FR_BB_TX_SRC_MAC_CTL 0x00001100 +#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 +#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 +#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 +#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 +#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 +#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 +#define FRF_BB_TX_MAC_QID_SEL_LBN 0 +#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 + +/* XM_ADR_LO_REG: XGMAC address register low */ +#define FR_AB_XM_ADR_LO 0x00001200 +#define FRF_AB_XM_ADR_LO_LBN 0 +#define FRF_AB_XM_ADR_LO_WIDTH 32 + +/* XM_ADR_HI_REG: XGMAC address register high */ +#define FR_AB_XM_ADR_HI 0x00001210 +#define FRF_AB_XM_ADR_HI_LBN 0 +#define FRF_AB_XM_ADR_HI_WIDTH 16 + +/* XM_GLB_CFG_REG: XGMAC global configuration */ +#define FR_AB_XM_GLB_CFG 0x00001220 +#define FRF_AB_XM_RMTFLT_GEN_LBN 17 +#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 +#define FRF_AB_XM_DEBUG_MODE_LBN 16 +#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 +#define FRF_AB_XM_RX_STAT_EN_LBN 11 +#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 +#define FRF_AB_XM_TX_STAT_EN_LBN 10 +#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 +#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 +#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 +#define FRF_AB_XM_WAN_MODE_LBN 5 +#define FRF_AB_XM_WAN_MODE_WIDTH 1 +#define FRF_AB_XM_INTCLR_MODE_LBN 3 +#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 +#define FRF_AB_XM_CORE_RST_LBN 0 +#define FRF_AB_XM_CORE_RST_WIDTH 1 + +/* XM_TX_CFG_REG: XGMAC transmit configuration */ +#define FR_AB_XM_TX_CFG 0x00001230 +#define FRF_AB_XM_TX_PROG_LBN 24 +#define FRF_AB_XM_TX_PROG_WIDTH 1 +#define FRF_AB_XM_IPG_LBN 16 +#define FRF_AB_XM_IPG_WIDTH 4 +#define FRF_AB_XM_FCNTL_LBN 10 +#define FRF_AB_XM_FCNTL_WIDTH 1 +#define FRF_AB_XM_TXCRC_LBN 8 +#define FRF_AB_XM_TXCRC_WIDTH 1 +#define FRF_AB_XM_EDRC_LBN 6 +#define FRF_AB_XM_EDRC_WIDTH 1 +#define FRF_AB_XM_AUTO_PAD_LBN 5 +#define FRF_AB_XM_AUTO_PAD_WIDTH 1 +#define FRF_AB_XM_TX_PRMBL_LBN 2 +#define FRF_AB_XM_TX_PRMBL_WIDTH 1 +#define FRF_AB_XM_TXEN_LBN 1 +#define FRF_AB_XM_TXEN_WIDTH 1 +#define FRF_AB_XM_TX_RST_LBN 0 +#define FRF_AB_XM_TX_RST_WIDTH 1 + +/* XM_RX_CFG_REG: XGMAC receive configuration */ +#define FR_AB_XM_RX_CFG 0x00001240 +#define FRF_AB_XM_PASS_LENERR_LBN 26 +#define FRF_AB_XM_PASS_LENERR_WIDTH 1 +#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 +#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 +#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 +#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 +#define FRF_AB_XM_REJ_BCAST_LBN 20 +#define FRF_AB_XM_REJ_BCAST_WIDTH 1 +#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 +#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 +#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 +#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 +#define FRF_AB_XM_AUTO_DEPAD_LBN 8 +#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 +#define FRF_AB_XM_RXCRC_LBN 3 +#define FRF_AB_XM_RXCRC_WIDTH 1 +#define FRF_AB_XM_RX_PRMBL_LBN 2 +#define FRF_AB_XM_RX_PRMBL_WIDTH 1 +#define FRF_AB_XM_RXEN_LBN 1 +#define FRF_AB_XM_RXEN_WIDTH 1 +#define FRF_AB_XM_RX_RST_LBN 0 +#define FRF_AB_XM_RX_RST_WIDTH 1 + +/* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */ +#define FR_AB_XM_MGT_INT_MASK 0x00001250 +#define FRF_AB_XM_MSK_STA_INTR_LBN 16 +#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 +#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 +#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 +#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 +#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 +#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 +#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 +#define FRF_AB_XM_MSK_RMTFLT_LBN 1 +#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 +#define FRF_AB_XM_MSK_LCLFLT_LBN 0 +#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 + +/* XM_FC_REG: XGMAC flow control register */ +#define FR_AB_XM_FC 0x00001270 +#define FRF_AB_XM_PAUSE_TIME_LBN 16 +#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 +#define FRF_AB_XM_RX_MAC_STAT_LBN 11 +#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 +#define FRF_AB_XM_TX_MAC_STAT_LBN 10 +#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 +#define FRF_AB_XM_MCNTL_PASS_LBN 8 +#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 +#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 +#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 +#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 +#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 +#define FRF_AB_XM_ZPAUSE_LBN 2 +#define FRF_AB_XM_ZPAUSE_WIDTH 1 +#define FRF_AB_XM_XMIT_PAUSE_LBN 1 +#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 +#define FRF_AB_XM_DIS_FCNTL_LBN 0 +#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 + +/* XM_PAUSE_TIME_REG: XGMAC pause time register */ +#define FR_AB_XM_PAUSE_TIME 0x00001290 +#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 +#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 +#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 +#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 + +/* XM_TX_PARAM_REG: XGMAC transmit parameter register */ +#define FR_AB_XM_TX_PARAM 0x000012d0 +#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 +#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 +#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 +#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 +#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 +#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 +#define FRF_AB_XM_PAD_CHAR_LBN 0 +#define FRF_AB_XM_PAD_CHAR_WIDTH 8 + +/* XM_RX_PARAM_REG: XGMAC receive parameter register */ +#define FR_AB_XM_RX_PARAM 0x000012e0 +#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 +#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 +#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 +#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 + +/* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */ +#define FR_AB_XM_MGT_INT_MSK 0x000012f0 +#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 +#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 +#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 +#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 +#define FRF_AB_XM_PRMBLE_ERR_LBN 2 +#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 +#define FRF_AB_XM_RMTFLT_LBN 1 +#define FRF_AB_XM_RMTFLT_WIDTH 1 +#define FRF_AB_XM_LCLFLT_LBN 0 +#define FRF_AB_XM_LCLFLT_WIDTH 1 + +/* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */ +#define FR_AB_XX_PWR_RST 0x00001300 +#define FRF_AB_XX_PWRDND_SIG_LBN 31 +#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 +#define FRF_AB_XX_PWRDNC_SIG_LBN 30 +#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 +#define FRF_AB_XX_PWRDNB_SIG_LBN 29 +#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 +#define FRF_AB_XX_PWRDNA_SIG_LBN 28 +#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 +#define FRF_AB_XX_SIM_MODE_LBN 27 +#define FRF_AB_XX_SIM_MODE_WIDTH 1 +#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 +#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 +#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 +#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 +#define FRF_AB_XX_RESETD_SIG_LBN 23 +#define FRF_AB_XX_RESETD_SIG_WIDTH 1 +#define FRF_AB_XX_RESETC_SIG_LBN 22 +#define FRF_AB_XX_RESETC_SIG_WIDTH 1 +#define FRF_AB_XX_RESETB_SIG_LBN 21 +#define FRF_AB_XX_RESETB_SIG_WIDTH 1 +#define FRF_AB_XX_RESETA_SIG_LBN 20 +#define FRF_AB_XX_RESETA_SIG_WIDTH 1 +#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 +#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 +#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 +#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 +#define FRF_AB_XX_SD_RST_ACT_LBN 16 +#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 +#define FRF_AB_XX_PWRDND_EN_LBN 15 +#define FRF_AB_XX_PWRDND_EN_WIDTH 1 +#define FRF_AB_XX_PWRDNC_EN_LBN 14 +#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 +#define FRF_AB_XX_PWRDNB_EN_LBN 13 +#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 +#define FRF_AB_XX_PWRDNA_EN_LBN 12 +#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 +#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 +#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 +#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 +#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 +#define FRF_AB_XX_RESETD_EN_LBN 7 +#define FRF_AB_XX_RESETD_EN_WIDTH 1 +#define FRF_AB_XX_RESETC_EN_LBN 6 +#define FRF_AB_XX_RESETC_EN_WIDTH 1 +#define FRF_AB_XX_RESETB_EN_LBN 5 +#define FRF_AB_XX_RESETB_EN_WIDTH 1 +#define FRF_AB_XX_RESETA_EN_LBN 4 +#define FRF_AB_XX_RESETA_EN_WIDTH 1 +#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 +#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 +#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 +#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 +#define FRF_AB_XX_RST_XX_EN_LBN 0 +#define FRF_AB_XX_RST_XX_EN_WIDTH 1 + +/* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */ +#define FR_AB_XX_SD_CTL 0x00001310 +#define FRF_AB_XX_TERMADJ1_LBN 17 +#define FRF_AB_XX_TERMADJ1_WIDTH 1 +#define FRF_AB_XX_TERMADJ0_LBN 16 +#define FRF_AB_XX_TERMADJ0_WIDTH 1 +#define FRF_AB_XX_HIDRVD_LBN 15 +#define FRF_AB_XX_HIDRVD_WIDTH 1 +#define FRF_AB_XX_LODRVD_LBN 14 +#define FRF_AB_XX_LODRVD_WIDTH 1 +#define FRF_AB_XX_HIDRVC_LBN 13 +#define FRF_AB_XX_HIDRVC_WIDTH 1 +#define FRF_AB_XX_LODRVC_LBN 12 +#define FRF_AB_XX_LODRVC_WIDTH 1 +#define FRF_AB_XX_HIDRVB_LBN 11 +#define FRF_AB_XX_HIDRVB_WIDTH 1 +#define FRF_AB_XX_LODRVB_LBN 10 +#define FRF_AB_XX_LODRVB_WIDTH 1 +#define FRF_AB_XX_HIDRVA_LBN 9 +#define FRF_AB_XX_HIDRVA_WIDTH 1 +#define FRF_AB_XX_LODRVA_LBN 8 +#define FRF_AB_XX_LODRVA_WIDTH 1 +#define FRF_AB_XX_LPBKD_LBN 3 +#define FRF_AB_XX_LPBKD_WIDTH 1 +#define FRF_AB_XX_LPBKC_LBN 2 +#define FRF_AB_XX_LPBKC_WIDTH 1 +#define FRF_AB_XX_LPBKB_LBN 1 +#define FRF_AB_XX_LPBKB_WIDTH 1 +#define FRF_AB_XX_LPBKA_LBN 0 +#define FRF_AB_XX_LPBKA_WIDTH 1 + +/* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */ +#define FR_AB_XX_TXDRV_CTL 0x00001320 +#define FRF_AB_XX_DEQD_LBN 28 +#define FRF_AB_XX_DEQD_WIDTH 4 +#define FRF_AB_XX_DEQC_LBN 24 +#define FRF_AB_XX_DEQC_WIDTH 4 +#define FRF_AB_XX_DEQB_LBN 20 +#define FRF_AB_XX_DEQB_WIDTH 4 +#define FRF_AB_XX_DEQA_LBN 16 +#define FRF_AB_XX_DEQA_WIDTH 4 +#define FRF_AB_XX_DTXD_LBN 12 +#define FRF_AB_XX_DTXD_WIDTH 4 +#define FRF_AB_XX_DTXC_LBN 8 +#define FRF_AB_XX_DTXC_WIDTH 4 +#define FRF_AB_XX_DTXB_LBN 4 +#define FRF_AB_XX_DTXB_WIDTH 4 +#define FRF_AB_XX_DTXA_LBN 0 +#define FRF_AB_XX_DTXA_WIDTH 4 + +/* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */ +#define FR_AB_XX_PRBS_CTL 0x00001330 +#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 +#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 +#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 +#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 +#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 +#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 +#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 +#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 +#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 +#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 +#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 +#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 +#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 +#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 +#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 +#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 +#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 +#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 +#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 +#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 +#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 +#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 +#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 +#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 +#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 +#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 +#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 +#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 + +/* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */ +#define FR_AB_XX_PRBS_CHK 0x00001340 +#define FRF_AB_XX_REV_LB_EN_LBN 16 +#define FRF_AB_XX_REV_LB_EN_WIDTH 1 +#define FRF_AB_XX_CH3_DEG_DET_LBN 15 +#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 +#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 +#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 +#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 +#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 +#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 +#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 +#define FRF_AB_XX_CH2_DEG_DET_LBN 11 +#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 +#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 +#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 +#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 +#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 +#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 +#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 +#define FRF_AB_XX_CH1_DEG_DET_LBN 7 +#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 +#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 +#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 +#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 +#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 +#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 +#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 +#define FRF_AB_XX_CH0_DEG_DET_LBN 3 +#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 +#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 +#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 +#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 +#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 +#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 +#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 + +/* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */ +#define FR_AB_XX_PRBS_ERR 0x00001350 +#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 +#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 +#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 +#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 +#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 +#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 +#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 +#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 + +/* XX_CORE_STAT_REG: XAUI XGXS core status register */ +#define FR_AB_XX_CORE_STAT 0x00001360 +#define FRF_AB_XX_FORCE_SIG3_LBN 31 +#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 +#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG2_LBN 29 +#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 +#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG1_LBN 27 +#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 +#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG0_LBN 25 +#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 +#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 +#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 +#define FRF_AB_XX_XGXS_LB_EN_LBN 23 +#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 +#define FRF_AB_XX_XGMII_LB_EN_LBN 22 +#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 +#define FRF_AB_XX_MATCH_FAULT_LBN 21 +#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 +#define FRF_AB_XX_ALIGN_DONE_LBN 20 +#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 +#define FRF_AB_XX_SYNC_STAT3_LBN 19 +#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 +#define FRF_AB_XX_SYNC_STAT2_LBN 18 +#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 +#define FRF_AB_XX_SYNC_STAT1_LBN 17 +#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 +#define FRF_AB_XX_SYNC_STAT0_LBN 16 +#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 +#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 +#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 +#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 +#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 +#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 +#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 +#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 +#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 +#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 +#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 +#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 +#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 +#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 +#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 +#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 +#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 +#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 +#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 +#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 +#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 +#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 +#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 +#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 +#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 +#define FRF_AB_XX_DISPERR_CH3_LBN 3 +#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 +#define FRF_AB_XX_DISPERR_CH2_LBN 2 +#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 +#define FRF_AB_XX_DISPERR_CH1_LBN 1 +#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 +#define FRF_AB_XX_DISPERR_CH0_LBN 0 +#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 + +/* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */ +#define FR_AA_RX_DESC_PTR_TBL_KER 0x00011800 +#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 +#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 +/* RX_DESC_PTR_TBL: Receive descriptor pointer table */ +#define FR_BZ_RX_DESC_PTR_TBL 0x00f40000 +#define FR_BZ_RX_DESC_PTR_TBL_STEP 16 +#define FR_BB_RX_DESC_PTR_TBL_ROWS 4096 +#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 +#define FRF_CZ_RX_HDR_SPLIT_LBN 90 +#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 +#define FRF_AA_RX_RESET_LBN 89 +#define FRF_AA_RX_RESET_WIDTH 1 +#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 +#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 +#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 +#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 +#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 +#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 +#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 +#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 +#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 +#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 +#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 +#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 +#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 +#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 +#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 +#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 +#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 +#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 +#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 +#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 +#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 +#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 +#define FFE_AZ_RX_DESCQ_SIZE_4K 3 +#define FFE_AZ_RX_DESCQ_SIZE_2K 2 +#define FFE_AZ_RX_DESCQ_SIZE_1K 1 +#define FFE_AZ_RX_DESCQ_SIZE_512 0 +#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 +#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 +#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 +#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 +#define FRF_AZ_RX_DESCQ_EN_LBN 0 +#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 + +/* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */ +#define FR_AA_TX_DESC_PTR_TBL_KER 0x00011900 +#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 +#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 +/* TX_DESC_PTR_TBL: Transmit descriptor pointer */ +#define FR_BZ_TX_DESC_PTR_TBL 0x00f50000 +#define FR_BZ_TX_DESC_PTR_TBL_STEP 16 +#define FR_BB_TX_DESC_PTR_TBL_ROWS 4096 +#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 +#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 +#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 +#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 +#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 +#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 +#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 +#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 +#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 +#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 +#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 +#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 +#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 +#define FRF_AZ_TX_DESCQ_EN_LBN 88 +#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 +#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 +#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 +#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 +#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 +#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 +#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 +#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 +#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 +#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 +#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 +#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 +#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 +#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 +#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 +#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 +#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 +#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 +#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 +#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 +#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 +#define FFE_AZ_TX_DESCQ_SIZE_4K 3 +#define FFE_AZ_TX_DESCQ_SIZE_2K 2 +#define FFE_AZ_TX_DESCQ_SIZE_1K 1 +#define FFE_AZ_TX_DESCQ_SIZE_512 0 +#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 +#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 +#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 +#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 + +/* EVQ_PTR_TBL_KER: Event queue pointer table */ +#define FR_AA_EVQ_PTR_TBL_KER 0x00011a00 +#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 +#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 +/* EVQ_PTR_TBL: Event queue pointer table */ +#define FR_BZ_EVQ_PTR_TBL 0x00f60000 +#define FR_BZ_EVQ_PTR_TBL_STEP 16 +#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 +#define FR_BB_EVQ_PTR_TBL_ROWS 4096 +#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 +#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 +#define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39 +#define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1 +#define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39 +#define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1 +#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 +#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 +#define FRF_AZ_EVQ_EN_LBN 23 +#define FRF_AZ_EVQ_EN_WIDTH 1 +#define FRF_AZ_EVQ_SIZE_LBN 20 +#define FRF_AZ_EVQ_SIZE_WIDTH 3 +#define FFE_AZ_EVQ_SIZE_32K 6 +#define FFE_AZ_EVQ_SIZE_16K 5 +#define FFE_AZ_EVQ_SIZE_8K 4 +#define FFE_AZ_EVQ_SIZE_4K 3 +#define FFE_AZ_EVQ_SIZE_2K 2 +#define FFE_AZ_EVQ_SIZE_1K 1 +#define FFE_AZ_EVQ_SIZE_512 0 +#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 +#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 + +/* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */ +#define FR_AA_BUF_HALF_TBL_KER 0x00018000 +#define FR_AA_BUF_HALF_TBL_KER_STEP 8 +#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 +/* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */ +#define FR_BZ_BUF_HALF_TBL 0x00800000 +#define FR_BZ_BUF_HALF_TBL_STEP 8 +#define FR_CZ_BUF_HALF_TBL_ROWS 147456 +#define FR_BB_BUF_HALF_TBL_ROWS 524288 +#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 +#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 +#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 +#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 +#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 +#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 +#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 +#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 + +/* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */ +#define FR_AA_BUF_FULL_TBL_KER 0x00018000 +#define FR_AA_BUF_FULL_TBL_KER_STEP 8 +#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 +/* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */ +#define FR_BZ_BUF_FULL_TBL 0x00800000 +#define FR_BZ_BUF_FULL_TBL_STEP 8 +#define FR_CZ_BUF_FULL_TBL_ROWS 147456 +#define FR_BB_BUF_FULL_TBL_ROWS 917504 +#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 +#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 +#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 +#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 +#define FRF_AZ_BUF_ADR_REGION_LBN 48 +#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 +#define FFE_AZ_BUF_ADR_REGN3 3 +#define FFE_AZ_BUF_ADR_REGN2 2 +#define FFE_AZ_BUF_ADR_REGN1 1 +#define FFE_AZ_BUF_ADR_REGN0 0 +#define FRF_AZ_BUF_ADR_FBUF_LBN 14 +#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 +#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 +#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 + +/* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */ +#define FR_BZ_RX_FILTER_TBL0 0x00f00000 +#define FR_BZ_RX_FILTER_TBL0_STEP 32 +#define FR_BZ_RX_FILTER_TBL0_ROWS 8192 +/* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */ +#define FR_BB_RX_FILTER_TBL1 0x00f00010 +#define FR_BB_RX_FILTER_TBL1_STEP 32 +#define FR_BB_RX_FILTER_TBL1_ROWS 8192 +#define FRF_BZ_RSS_EN_LBN 110 +#define FRF_BZ_RSS_EN_WIDTH 1 +#define FRF_BZ_SCATTER_EN_LBN 109 +#define FRF_BZ_SCATTER_EN_WIDTH 1 +#define FRF_BZ_TCP_UDP_LBN 108 +#define FRF_BZ_TCP_UDP_WIDTH 1 +#define FRF_BZ_RXQ_ID_LBN 96 +#define FRF_BZ_RXQ_ID_WIDTH 12 +#define FRF_BZ_DEST_IP_LBN 64 +#define FRF_BZ_DEST_IP_WIDTH 32 +#define FRF_BZ_DEST_PORT_TCP_LBN 48 +#define FRF_BZ_DEST_PORT_TCP_WIDTH 16 +#define FRF_BZ_SRC_IP_LBN 16 +#define FRF_BZ_SRC_IP_WIDTH 32 +#define FRF_BZ_SRC_TCP_DEST_UDP_LBN 0 +#define FRF_BZ_SRC_TCP_DEST_UDP_WIDTH 16 + +/* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */ +#define FR_CZ_RX_MAC_FILTER_TBL0 0x00f00010 +#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 +#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 +#define FRF_CZ_RMFT_RSS_EN_LBN 75 +#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 +#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 +#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 +#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 +#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 +#define FRF_CZ_RMFT_RXQ_ID_LBN 61 +#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 +#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 +#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 +#define FRF_CZ_RMFT_DEST_MAC_LBN 16 +#define FRF_CZ_RMFT_DEST_MAC_WIDTH 44 +#define FRF_CZ_RMFT_VLAN_ID_LBN 0 +#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 + +/* TIMER_TBL: Timer table */ +#define FR_BZ_TIMER_TBL 0x00f70000 +#define FR_BZ_TIMER_TBL_STEP 16 +#define FR_CZ_TIMER_TBL_ROWS 1024 +#define FR_BB_TIMER_TBL_ROWS 4096 +#define FRF_CZ_TIMER_Q_EN_LBN 33 +#define FRF_CZ_TIMER_Q_EN_WIDTH 1 +#define FRF_CZ_INT_ARMD_LBN 32 +#define FRF_CZ_INT_ARMD_WIDTH 1 +#define FRF_CZ_INT_PEND_LBN 31 +#define FRF_CZ_INT_PEND_WIDTH 1 +#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 +#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 +#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 +#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 +#define FRF_CZ_TIMER_MODE_LBN 14 +#define FRF_CZ_TIMER_MODE_WIDTH 2 +#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 +#define FFE_CZ_TIMER_MODE_TRIG_START 2 +#define FFE_CZ_TIMER_MODE_IMMED_START 1 +#define FFE_CZ_TIMER_MODE_DIS 0 +#define FRF_BB_TIMER_MODE_LBN 12 +#define FRF_BB_TIMER_MODE_WIDTH 2 +#define FFE_BB_TIMER_MODE_INT_HLDOFF 2 +#define FFE_BB_TIMER_MODE_TRIG_START 2 +#define FFE_BB_TIMER_MODE_IMMED_START 1 +#define FFE_BB_TIMER_MODE_DIS 0 +#define FRF_CZ_TIMER_VAL_LBN 0 +#define FRF_CZ_TIMER_VAL_WIDTH 14 +#define FRF_BB_TIMER_VAL_LBN 0 +#define FRF_BB_TIMER_VAL_WIDTH 12 + +/* TX_PACE_TBL: Transmit pacing table */ +#define FR_BZ_TX_PACE_TBL 0x00f80000 +#define FR_BZ_TX_PACE_TBL_STEP 16 +#define FR_CZ_TX_PACE_TBL_ROWS 1024 +#define FR_BB_TX_PACE_TBL_ROWS 4096 +#define FRF_BZ_TX_PACE_LBN 0 +#define FRF_BZ_TX_PACE_WIDTH 5 + +/* RX_INDIRECTION_TBL: RX Indirection Table */ +#define FR_BZ_RX_INDIRECTION_TBL 0x00fb0000 +#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 +#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 +#define FRF_BZ_IT_QUEUE_LBN 0 +#define FRF_BZ_IT_QUEUE_WIDTH 6 + +/* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */ +#define FR_CZ_TX_FILTER_TBL0 0x00fc0000 +#define FR_CZ_TX_FILTER_TBL0_STEP 16 +#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 +#define FRF_CZ_TIFT_TCP_UDP_LBN 108 +#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 +#define FRF_CZ_TIFT_TXQ_ID_LBN 96 +#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 +#define FRF_CZ_TIFT_DEST_IP_LBN 64 +#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 +#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 +#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 +#define FRF_CZ_TIFT_SRC_IP_LBN 16 +#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 +#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 +#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 + +/* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */ +#define FR_CZ_TX_MAC_FILTER_TBL0 0x00fe0000 +#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 +#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 +#define FRF_CZ_TMFT_TXQ_ID_LBN 61 +#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 +#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 +#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 +#define FRF_CZ_TMFT_SRC_MAC_LBN 16 +#define FRF_CZ_TMFT_SRC_MAC_WIDTH 44 +#define FRF_CZ_TMFT_VLAN_ID_LBN 0 +#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 + +/* MC_TREG_SMEM: MC Shared Memory */ +#define FR_CZ_MC_TREG_SMEM 0x00ff0000 +#define FR_CZ_MC_TREG_SMEM_STEP 4 +#define FR_CZ_MC_TREG_SMEM_ROWS 512 +#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 +#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 + +/* + * Register dump definition. This is mostly taken from + * linux-2.6/drivers/net/sfc/nic.c but has names and bitfield + * definitions added. + * + * The definitions of efx_nic_regs and efx_nic_reg_tables should be + * textually identical to those in the driver, though the structure + * definitions and the macros REGISTER and REGISTER_TABLE_DIMENSIONS + * are defined differently. + */ + +#define REGISTER_REVISION_A 1 +#define REGISTER_REVISION_B 2 +#define REGISTER_REVISION_C 3 +#define REGISTER_REVISION_Z 3 /* latest revision */ + +struct efx_nic_reg_field { + const char *name; + u32 lbn:7, width:8; + u32 min_revision:2, max_revision:2; +}; + +#define REGISTER_FIELD_RENAME(name, display_name, min_rev, max_rev) { \ + display_name, \ + FRF_ ## min_rev ## max_rev ## _ ## name ## _LBN, \ + FRF_ ## min_rev ## max_rev ## _ ## name ## _WIDTH, \ + REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ +} +#define REGISTER_FIELD(name, min_rev, max_rev) \ + REGISTER_FIELD_RENAME(name, #name, min_rev, max_rev) +#define REGISTER_FIELD_AA(name) REGISTER_FIELD(name, A, A) +#define REGISTER_FIELD_AB(name) REGISTER_FIELD(name, A, B) +#define REGISTER_FIELD_AZ(name) REGISTER_FIELD(name, A, Z) +#define REGISTER_FIELD_BB(name) REGISTER_FIELD(name, B, B) +#define REGISTER_FIELD_BZ(name) REGISTER_FIELD(name, B, Z) +#define REGISTER_FIELD_CZ(name) REGISTER_FIELD(name, C, Z) +#define REGISTER_FIELD_AZ_RENAME(name, display_name) \ + REGISTER_FIELD_RENAME(name, display_name, A, Z) +#define REGISTER_FIELD_BZ_RENAME(name, display_name) \ + REGISTER_FIELD_RENAME(name, display_name, B, Z) +#define REGISTER_FIELD_CZ_RENAME(name, display_name) \ + REGISTER_FIELD_RENAME(name, display_name, C, Z) + +static const struct efx_nic_reg_field efx_nic_reg_fields_ADR_REGION[] = { + REGISTER_FIELD_AZ(ADR_REGION0), + REGISTER_FIELD_AZ(ADR_REGION1), + REGISTER_FIELD_AZ(ADR_REGION2), + REGISTER_FIELD_AZ(ADR_REGION3), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_INT_EN_KER[] = { + REGISTER_FIELD_AZ(DRV_INT_EN_KER), + REGISTER_FIELD_AZ(KER_INT_KER), + REGISTER_FIELD_AZ(KER_INT_CHAR), + REGISTER_FIELD_AZ(KER_INT_LEVE_SEL), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_INT_EN_CHAR[] = { + REGISTER_FIELD_BZ(DRV_INT_EN_CHAR), + REGISTER_FIELD_BZ(CHAR_INT_KER), + REGISTER_FIELD_BZ(CHAR_INT_CHAR), + REGISTER_FIELD_BZ(CHAR_INT_LEVE_SEL), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_INT_ADR_KER[] = { + REGISTER_FIELD_AZ(INT_ADR_KER), + REGISTER_FIELD_AZ(NORM_INT_VEC_DIS_KER), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_INT_ADR_CHAR[] = { + REGISTER_FIELD_BZ(INT_ADR_CHAR), + REGISTER_FIELD_BZ(NORM_INT_VEC_DIS_CHAR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_HW_INIT[] = { + REGISTER_FIELD_AZ(TLP_TD), + REGISTER_FIELD_AZ(TD_SEL), + REGISTER_FIELD_AZ(ATTR_SEL), + REGISTER_FIELD_AZ(TLP_EP), + REGISTER_FIELD_AZ(US_DISABLE), + REGISTER_FIELD_AZ(WD_TIMER), + REGISTER_FIELD_AB(INTA_VEC), + REGISTER_FIELD_AB(INTB_VEC), + REGISTER_FIELD_AZ(TLP_ATTR), + REGISTER_FIELD_AZ(TLP_TC), + REGISTER_FIELD_AZ(POST_WR_MASK), + REGISTER_FIELD_BB(FC_BLOCKING_EN), + REGISTER_FIELD_AA(B2B_REQ_EN), + REGISTER_FIELD_BZ(B2B_REQ_EN), + REGISTER_FIELD_AA(FC_BLOCKING_EN), + REGISTER_FIELD_AB(PE_EIDLE_DIS), + REGISTER_FIELD_AB(TX_RREQ_MASK_EN), + REGISTER_FIELD_AZ(DOORBELL_DROP), + REGISTER_FIELD_AB(TRGT_MASK_ALL), + REGISTER_FIELD_CZ(TX_MRG_TAGS), + REGISTER_FIELD_BB(PCIE_CPL_TIMEOUT_CTRL), + REGISTER_FIELD_BB(BDMRD_CPLF_FULL), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_USR_EV_CFG[] = { + REGISTER_FIELD_CZ(DFLT_EVQ), + REGISTER_FIELD_CZ(USREV_DIS), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EE_SPI_HCMD[] = { + REGISTER_FIELD_AB(EE_SPI_HCMD_ENC), + REGISTER_FIELD_AB(EE_SPI_HCMD_ADBCNT), + REGISTER_FIELD_AB(EE_SPI_HCMD_DUBCNT), + REGISTER_FIELD_AB(EE_SPI_HCMD_READ), + REGISTER_FIELD_AB(EE_SPI_HCMD_DABCNT), + REGISTER_FIELD_AB(EE_SPI_HCMD_SF_SEL), + REGISTER_FIELD_AB(EE_WR_TIMER_ACTIVE), + REGISTER_FIELD_AB(EE_SPI_HCMD_CMD_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EE_SPI_HADR[] = { + REGISTER_FIELD_AB(EE_SPI_HADR_ADR), + REGISTER_FIELD_AB(EE_SPI_HADR_DUBYTE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EE_SPI_HDATA[] = { + REGISTER_FIELD_AB(EE_SPI_HDATA0), + REGISTER_FIELD_AB(EE_SPI_HDATA1), + REGISTER_FIELD_AB(EE_SPI_HDATA2), + REGISTER_FIELD_AB(EE_SPI_HDATA3), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EE_BASE_PAGE[] = { + REGISTER_FIELD_AB(EE_EXP_ROM_WINDOW_BASE), + REGISTER_FIELD_AB(EE_EXPROM_MASK), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EE_VPD_CFG0[] = { + REGISTER_FIELD_AB(EE_VPD_EN), + REGISTER_FIELD_AB(EE_VPD_EN_AD9_MODE), + REGISTER_FIELD_AB(EE_VPD_DEV_SF_SEL), + REGISTER_FIELD_AB(EE_VPD_ACCESS_BLOCK), + REGISTER_FIELD_AB(EE_VPD_ACCESS_ON), + REGISTER_FIELD_AB(EE_VPD_AD_SIZE), + REGISTER_FIELD_AB(EE_VPD_LENGTH), + REGISTER_FIELD_AB(EE_VPD_BASE), + REGISTER_FIELD_AB(EE_VPD_WR_CMD_EN), + REGISTER_FIELD_AB(EE_VPDW_BASE), + REGISTER_FIELD_AB(EE_VPDW_LENGTH), + REGISTER_FIELD_AB(EE_EE_WR_TMR_VALUE), + REGISTER_FIELD_AB(EE_EE_CLOCK_DIV), + REGISTER_FIELD_AB(EE_VPD_WIP_POLL), + REGISTER_FIELD_AB(EE_SF_CLOCK_DIV), + REGISTER_FIELD_AB(EE_SF_FASTRD_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_NIC_STAT[] = { + REGISTER_FIELD_AB(STRAP_PINS), + REGISTER_FIELD_AB(ATE_MODE), + REGISTER_FIELD_AB(EE_PRST), + REGISTER_FIELD_AB(SF_PRST), + REGISTER_FIELD_AB(ONCHIP_SRAM), + REGISTER_FIELD_BB(REVISION_ID), + REGISTER_FIELD_BB(EE_STRAP), + REGISTER_FIELD_BB(EE_STRAP_EN), + REGISTER_FIELD_BB(AER_DIS), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GPIO_CTL[] = { + REGISTER_FIELD_AB(GPIO0_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO1_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO2_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO3_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO4_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO5_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO6_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO7_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO0_IN), + REGISTER_FIELD_AB(GPIO1_IN), + REGISTER_FIELD_AB(GPIO2_IN), + REGISTER_FIELD_AB(GPIO3_IN), + REGISTER_FIELD_AB(GPIO4_IN), + REGISTER_FIELD_AB(GPIO5_IN), + REGISTER_FIELD_AB(GPIO6_IN), + REGISTER_FIELD_AB(GPIO7_IN), + REGISTER_FIELD_AB(GPIO0_OUT), + REGISTER_FIELD_AB(GPIO1_OUT), + REGISTER_FIELD_AB(GPIO2_OUT), + REGISTER_FIELD_AB(GPIO3_OUT), + REGISTER_FIELD_AB(GPIO4_OUT), + REGISTER_FIELD_AB(GPIO5_OUT), + REGISTER_FIELD_AB(GPIO6_OUT), + REGISTER_FIELD_AB(GPIO7_OUT), + REGISTER_FIELD_AB(GPIO0_OEN), + REGISTER_FIELD_AB(GPIO1_OEN), + REGISTER_FIELD_AB(GPIO2_OEN), + REGISTER_FIELD_AB(GPIO3_OEN), + REGISTER_FIELD_AB(GPIO4_OEN), + REGISTER_FIELD_AB(GPIO5_OEN), + REGISTER_FIELD_AB(USE_NIC_CLK), + REGISTER_FIELD_AB(CLK156_OUT_EN), + REGISTER_FIELD_AB(GPIO8_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO9_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO10_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO11_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO12_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO13_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO14_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO15_PWRUP_VALUE), + REGISTER_FIELD_AB(GPIO8_IN), + REGISTER_FIELD_AB(GPIO9_IN), + REGISTER_FIELD_AB(GPIO10_IN), + REGISTER_FIELD_AB(GPIO11_IN), + REGISTER_FIELD_AB(GPIO12_IN), + REGISTER_FIELD_AB(GPIO13_IN), + REGISTER_FIELD_AB(GPIO14_IN), + REGISTER_FIELD_AB(GPIO15_IN), + REGISTER_FIELD_AB(GPIO8_OUT), + REGISTER_FIELD_AB(GPIO9_OUT), + REGISTER_FIELD_AB(GPIO10_OUT), + REGISTER_FIELD_AB(GPIO11_OUT), + REGISTER_FIELD_AB(GPIO12_OUT), + REGISTER_FIELD_AB(GPIO13_OUT), + REGISTER_FIELD_AB(GPIO14_OUT), + REGISTER_FIELD_AB(GPIO15_OUT), + REGISTER_FIELD_AB(GPIO8_OEN), + REGISTER_FIELD_AB(GPIO9_OEN), + REGISTER_FIELD_AB(GPIO10_OEN), + REGISTER_FIELD_AB(GPIO11_OEN), + REGISTER_FIELD_AB(GPIO12_OEN), + REGISTER_FIELD_AB(GPIO13_OEN), + REGISTER_FIELD_AB(GPIO14_OEN), + REGISTER_FIELD_AB(GPIO15_OEN), + REGISTER_FIELD_AB(GPIO_PWRUP_VALUE2), + REGISTER_FIELD_AB(GPIO_IN2), + REGISTER_FIELD_AB(GPIO_OUT2), + REGISTER_FIELD_AB(GPIO_PWRUP_VALUE3), + REGISTER_FIELD_AB(GPIO_IN3), + REGISTER_FIELD_AB(GPIO_OUT3), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GLB_CTL[] = { + REGISTER_FIELD_AB(SWRST), + REGISTER_FIELD_AB(EXT_PHY_RST_DUR), + REGISTER_FIELD_AB(INT_RST_DUR), + REGISTER_FIELD_AB(RST_CS), + REGISTER_FIELD_AB(RST_SF), + REGISTER_FIELD_AB(RST_TX), + REGISTER_FIELD_AB(RST_RX), + REGISTER_FIELD_AB(RST_SR), + REGISTER_FIELD_AB(RST_EV), + REGISTER_FIELD_AB(RST_EM), + REGISTER_FIELD_AB(RST_XGTX), + REGISTER_FIELD_AB(RST_XGRX), + REGISTER_FIELD_AB(RST_PCIE_CORE), + REGISTER_FIELD_AB(RST_PCIE_NSTKY), + REGISTER_FIELD_AB(RST_PCIE_STKY), + REGISTER_FIELD_BB(RST_BIU), + REGISTER_FIELD_AA(RST_PCIX), + REGISTER_FIELD_AB(RST_PCIE_SD), + REGISTER_FIELD_AB(RST_XAUI_SD), + REGISTER_FIELD_AB(RST_EXT_PHY), + REGISTER_FIELD_AB(HOT_RST_CTL), + REGISTER_FIELD_AB(CS_RST_CTL), + REGISTER_FIELD_AB(EE_RST_CTL), + REGISTER_FIELD_AB(TX_RST_CTL), + REGISTER_FIELD_AB(RX_RST_CTL), + REGISTER_FIELD_AB(SR_RST_CTL), + REGISTER_FIELD_AB(EV_RST_CTL), + REGISTER_FIELD_AB(EM_RST_CTL), + REGISTER_FIELD_AB(XGTX_RST_CTL), + REGISTER_FIELD_AB(XGRX_RST_CTL), + REGISTER_FIELD_AB(PCIE_CORE_RST_CTL), + REGISTER_FIELD_AB(PCIE_NSTKY_RST_CTL), + REGISTER_FIELD_AB(PCIE_STKY_RST_CTL), + REGISTER_FIELD_BB(BIU_RST_CTL), + REGISTER_FIELD_AA(PCIX_RST_CTL), + REGISTER_FIELD_AB(PCIE_SD_RST_CTL), + REGISTER_FIELD_AB(XAUI_SD_RST_CTL), + REGISTER_FIELD_AB(EXT_PHY_RST_CTL), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_DP_CTRL[] = { + REGISTER_FIELD_BZ(FLS_EVQ_ID), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MEM_STAT[] = { + REGISTER_FIELD_CZ(MEM_PERR_VEC), + REGISTER_FIELD_AB(MBIST_ERR), + REGISTER_FIELD_AB(MBIST_CORR), + REGISTER_FIELD_AB(MEM_PERR_VEC), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_CS_DEBUG[] = { + /* This is not a complete list of fields */ + REGISTER_FIELD_AZ(CS_DEBUG_EN), + REGISTER_FIELD_CZ(CS_PORT_NUM), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_ALTERA_BUILD[] = { + REGISTER_FIELD_AZ(ALTERA_BUILD_VER), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_CSR_SPARE[] = { + REGISTER_FIELD_AZ(CSR_SPARE_BITS), + REGISTER_FIELD_AB(MEM_PERR_EN_TX_DATA), + REGISTER_FIELD_CZ(MEM_PERR_EN), + REGISTER_FIELD_AB(MEM_PERR_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_PCIE_SD_CTL0123[] = { + REGISTER_FIELD_AB(PCIE_LODRV), + REGISTER_FIELD_AB(PCIE_HIDRV), + REGISTER_FIELD_AB(PCIE_RXEQCTL_L), + REGISTER_FIELD_AB(PCIE_RXEQCTL_H), + REGISTER_FIELD_AB(PCIE_TXTERMADJ_L), + REGISTER_FIELD_AB(PCIE_TXTERMADJ_H), + REGISTER_FIELD_AB(PCIE_RXTERMADJ_L), + REGISTER_FIELD_AB(PCIE_RXTERMADJ_H), + REGISTER_FIELD_AB(PCIE_PARLPBK), + REGISTER_FIELD_AB(PCIE_LPBK), + REGISTER_FIELD_AB(PCIE_LPBKWDRV_L), + REGISTER_FIELD_AB(PCIE_LPBKWDRV_H), + REGISTER_FIELD_AB(PCIE_PARRESET_L), + REGISTER_FIELD_AB(PCIE_PARRESET_H), + REGISTER_FIELD_AB(PCIE_HIVMODE_L), + REGISTER_FIELD_AB(PCIE_HIVMODE_H), + REGISTER_FIELD_AB(PCIE_OFFSETEN_L), + REGISTER_FIELD_AB(PCIE_OFFSETEN_H), + REGISTER_FIELD_AB(PCIE_OFFSET), + REGISTER_FIELD_AB(PCIE_TESTSIG_L), + REGISTER_FIELD_AB(PCIE_TESTSIG_H), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_PCIE_SD_CTL45[] = { + REGISTER_FIELD_AB(PCIE_DEQ0), + REGISTER_FIELD_AB(PCIE_DEQ1), + REGISTER_FIELD_AB(PCIE_DEQ2), + REGISTER_FIELD_AB(PCIE_DEQ3), + REGISTER_FIELD_AB(PCIE_DEQ4), + REGISTER_FIELD_AB(PCIE_DEQ5), + REGISTER_FIELD_AB(PCIE_DEQ6), + REGISTER_FIELD_AB(PCIE_DEQ7), + REGISTER_FIELD_AB(PCIE_DTX0), + REGISTER_FIELD_AB(PCIE_DTX1), + REGISTER_FIELD_AB(PCIE_DTX2), + REGISTER_FIELD_AB(PCIE_DTX3), + REGISTER_FIELD_AB(PCIE_DTX4), + REGISTER_FIELD_AB(PCIE_DTX5), + REGISTER_FIELD_AB(PCIE_DTX6), + REGISTER_FIELD_AB(PCIE_DTX7), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_PCIE_PCS_CTL_STAT[] = { + REGISTER_FIELD_AB(PCIE_PRBSSEL), + REGISTER_FIELD_AB(PCIE_PRBSERRACK_L), + REGISTER_FIELD_AB(PCIE_PRBSERRACK_H), + REGISTER_FIELD_AB(PCIE_PRBSSYNC_L), + REGISTER_FIELD_AB(PCIE_PRBSSYNC_H), + REGISTER_FIELD_AB(PCIE_CTCDISABLE_L), + REGISTER_FIELD_AB(PCIE_CTCDISABLE_H), + REGISTER_FIELD_AB(PCIE_FASTINIT_L), + REGISTER_FIELD_AB(PCIE_FASTINIT_H), + REGISTER_FIELD_AB(PCIE_PRBSERRH0), + REGISTER_FIELD_AB(PCIE_PRBSERR), + REGISTER_FIELD_AB(PCIE_PRBSERRCOUNT0_L), + REGISTER_FIELD_AB(PCIE_PRBSERRCOUNT0_H), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EVQ_CTL[] = { + REGISTER_FIELD_AZ(EVQ_FIFO_NOTAF_TH), + REGISTER_FIELD_AZ(EVQ_FIFO_AF_TH), + REGISTER_FIELD_AZ(EVQ_OWNERR_CTL), + REGISTER_FIELD_BB(RX_EVQ_WAKEUP_MASK), + REGISTER_FIELD_CZ(RX_EVQ_WAKEUP_MASK), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EVQ_CNT1[] = { + REGISTER_FIELD_AZ(EVQ_ERR_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_CSR_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_EM_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_RX_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_TX_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_CNT_TOBIU), + REGISTER_FIELD_AZ(EVQ_CNT_PRE_FIFO), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_EVQ_CNT2[] = { + REGISTER_FIELD_AZ(EVQ_TM_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_INIT_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_WET_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_WU_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_RDY_CNT), + REGISTER_FIELD_AZ(EVQ_CLR_REQ_CNT), + REGISTER_FIELD_AZ(EVQ_UPD_REQ_CNT), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_BUF_TBL_CFG[] = { + REGISTER_FIELD_AZ(BUF_TBL_MODE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_SRM_RX_DC_CFG[] = { + REGISTER_FIELD_AZ(SRM_RX_DC_BASE_ADR), + REGISTER_FIELD_AZ(SRM_CLK_TMP_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_SRM_TX_DC_CFG[] = { + REGISTER_FIELD_AZ(SRM_TX_DC_BASE_ADR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_SRM_CFG[] = { + REGISTER_FIELD_AZ(SRM_BANK_SIZE), + REGISTER_FIELD_AZ(SRM_NUM_BANK), + REGISTER_FIELD_AZ(SRM_INIT_EN), + REGISTER_FIELD_AZ(SRM_OOB_BUF_INTEN), + REGISTER_FIELD_AZ(SRM_OOB_ADR_INTEN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_SRM_UPD_EVQ[] = { + REGISTER_FIELD_AZ(SRM_UPD_EVQ_ID), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_SRAM_PARITY[] = { + REGISTER_FIELD_CZ(FORCE_SRAM_SINGLE_ERR), + REGISTER_FIELD_AB(FORCE_SRAM_PERR), + REGISTER_FIELD_CZ(FORCE_SRAM_DOUBLE_ERR), + REGISTER_FIELD_CZ(SEC_INT), + REGISTER_FIELD_CZ(BYPASS_ECC), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_CFG[] = { + REGISTER_FIELD_AZ(RX_XOFF_MAC_EN), + REGISTER_FIELD_AA(RX_XOFF_MAC_TH), + REGISTER_FIELD_BZ(RX_XOFF_MAC_TH), + REGISTER_FIELD_AA(RX_XON_MAC_TH), + REGISTER_FIELD_BZ(RX_XON_MAC_TH), + REGISTER_FIELD_AA(RX_USR_BUF_SIZE), + REGISTER_FIELD_AA(RX_XOFF_TX_TH), + REGISTER_FIELD_BZ(RX_USR_BUF_SIZE), + REGISTER_FIELD_AA(RX_XON_TX_TH), + REGISTER_FIELD_AA(RX_OWNERR_CTL), + REGISTER_FIELD_BZ(RX_XOFF_TX_TH), + REGISTER_FIELD_AA(RX_PCI_BURST_SIZE), + REGISTER_FIELD_AA(RX_RDW_PATCH_EN), + REGISTER_FIELD_AA(RX_DESC_PUSH_EN), + REGISTER_FIELD_BZ(RX_XON_TX_TH), + REGISTER_FIELD_BZ(RX_OWNERR_CTL), + REGISTER_FIELD_BB(RX_PCI_BURST_SIZE), + REGISTER_FIELD_BZ(RX_RDW_PATCH_EN), + REGISTER_FIELD_BZ(RX_DESC_PUSH_EN), + REGISTER_FIELD_BZ(RX_HASH_INSRT_HDR), + REGISTER_FIELD_BZ(RX_HASH_ALG), + REGISTER_FIELD_BZ(RX_IP_HASH), + REGISTER_FIELD_BZ(RX_INGR_EN), + REGISTER_FIELD_BZ(RX_TCP_SUP), + REGISTER_FIELD_CZ(RX_PRE_RFF_IPG), + REGISTER_FIELD_CZ(RX_HDR_SPLIT_HDR_BUF_SIZE), + REGISTER_FIELD_CZ(RX_HDR_SPLIT_PLD_BUF_SIZE), + REGISTER_FIELD_CZ(RX_HDR_SPLIT_EN), + REGISTER_FIELD_CZ(RX_MIN_KBUF_SIZE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_FILTER_CTL[] = { + REGISTER_FIELD_BZ(TCP_FULL_SRCH_LIMIT), + REGISTER_FIELD_BZ(TCP_WILD_SRCH_LIMIT), + REGISTER_FIELD_BZ(UDP_WILD_SRCH_LIMIT), + REGISTER_FIELD_BZ(NUM_KER), + REGISTER_FIELD_BZ(UDP_FULL_SRCH_LIMIT), + REGISTER_FIELD_BZ(SCATTER_ENBL_NO_MATCH_Q), + REGISTER_FIELD_CZ(UNICAST_NOMATCH_IP_OVERRIDE), + REGISTER_FIELD_CZ(UNICAST_NOMATCH_RSS_ENABLED), + REGISTER_FIELD_CZ(UNICAST_NOMATCH_Q_ID), + REGISTER_FIELD_CZ(MULTICAST_NOMATCH_IP_OVERRIDE), + REGISTER_FIELD_CZ(MULTICAST_NOMATCH_RSS_ENABLED), + REGISTER_FIELD_CZ(MULTICAST_NOMATCH_Q_ID), + REGISTER_FIELD_CZ(RX_VLAN_MATCH_ETHERTYPE), + REGISTER_FIELD_CZ(RX_FILTER_ALL_VLAN_ETHERTYPES), + REGISTER_FIELD_CZ(ETHERNET_FULL_SEARCH_LIMIT), + REGISTER_FIELD_CZ(ETHERNET_WILDCARD_SEARCH_LIMIT), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_DC_CFG[] = { + REGISTER_FIELD_AZ(RX_DC_SIZE), + REGISTER_FIELD_AB(RX_MAX_PF), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_DC_PF_WM[] = { + REGISTER_FIELD_AZ(RX_DC_PF_LWM), + REGISTER_FIELD_AZ(RX_DC_PF_HWM), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_RSS_TKEY[] = { + REGISTER_FIELD_BZ(RX_RSS_TKEY_LO), + REGISTER_FIELD_BZ(RX_RSS_TKEY_HI), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_SELF_RST[] = { + REGISTER_FIELD_AA(RX_MAX_LU_LAT), + REGISTER_FIELD_AA(RX_MAX_PF_LAT), + REGISTER_FIELD_AA(RX_SELF_RST_EN), + REGISTER_FIELD_AA(RX_NODESC_WAIT_DIS), + REGISTER_FIELD_AA(RX_SW_RST_REG), + REGISTER_FIELD_AA(RX_ISCSI_DIS), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_RSS_IPV6_REG1[] = { + REGISTER_FIELD_CZ(RX_RSS_IPV6_TKEY_LO), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_RSS_IPV6_REG2[] = { + REGISTER_FIELD_CZ(RX_RSS_IPV6_TKEY_MID), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_RSS_IPV6_REG3[] = { + REGISTER_FIELD_CZ(RX_RSS_IPV6_TKEY_HI), + REGISTER_FIELD_CZ(RX_RSS_IPV6_TCP_SUPPRESS), + REGISTER_FIELD_CZ(RX_RSS_IPV6_IP_THASH_ENABLE), + REGISTER_FIELD_CZ(RX_RSS_IPV6_THASH_ENABLE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_DC_CFG[] = { + REGISTER_FIELD_AZ(TX_DC_SIZE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_CHKSM_CFG[] = { + REGISTER_FIELD_AA(TX_Q_CHKSM_DIS_0_31), + REGISTER_FIELD_AA(TX_Q_CHKSM_DIS_32_63), + REGISTER_FIELD_AA(TX_Q_CHKSM_DIS_64_95), + REGISTER_FIELD_AA(TX_Q_CHKSM_DIS_96_127), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_CFG[] = { + REGISTER_FIELD_AZ(TX_IP_ID_REP_EN), + REGISTER_FIELD_AA(TX_NON_IP_DROP_DIS), + REGISTER_FIELD_AZ(TX_OWNERR_CTL), + REGISTER_FIELD_AZ(TX_P1_PRI_EN), + REGISTER_FIELD_AZ(TX_NO_EOP_DISC_EN), + REGISTER_FIELD_AZ(TX_IP_ID_P0_OFS), + REGISTER_FIELD_CZ(TX_FILTER_EN_BIT), + REGISTER_FIELD_CZ(TX_VLAN_MATCH_ETHERTYPE_RANGE), + REGISTER_FIELD_CZ(TX_FILTER_ALL_VLAN_ETHERTYPES_BIT), + REGISTER_FIELD_CZ(TX_TCPIP_FILTER_FULL_SEARCH_RANGE), + REGISTER_FIELD_CZ(TX_TCPIP_FILTER_WILD_SEARCH_RANGE), + REGISTER_FIELD_CZ(TX_UDPIP_FILTER_FULL_SEARCH_RANGE), + REGISTER_FIELD_CZ(TX_UDPIP_FILTER_WILD_SEARCH_RANGE), + REGISTER_FIELD_CZ(TX_ETH_FILTER_FULL_SEARCH_RANGE), + REGISTER_FIELD_CZ(TX_ETH_FILTER_WILD_SEARCH_RANGE), + REGISTER_FIELD_CZ(TX_FILTER_TEST_MODE_BIT), + REGISTER_FIELD_CZ(TX_CONT_LOOKUP_THRESH_RANGE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_RESERVED[] = { + REGISTER_FIELD_AZ(TX_MAX_PREF), + REGISTER_FIELD_AZ(TX_MAX_CPL), + REGISTER_FIELD_AA(TX_IP_DIS), + REGISTER_FIELD_BZ(TX_FLUSH_MIN_LEN_EN), + REGISTER_FIELD_AA(TX_TCP_DIS), + REGISTER_FIELD_AZ(TX_DMA_SPACER), + REGISTER_FIELD_AA(TX_DMA_FF_THR), + REGISTER_FIELD_AZ(TX_DIS_NON_IP_EV), + REGISTER_FIELD_AZ(TX_ONE_PKT_PER_Q), + REGISTER_FIELD_AZ(TX_PREF_THRESHOLD), + REGISTER_FIELD_AZ(TX_ONLY1TAG), + REGISTER_FIELD_AZ(TX_PREF_WD_TMR), + REGISTER_FIELD_AZ(TX_PREF_SPACER), + REGISTER_FIELD_AZ(TX_XP_TIMER), + REGISTER_FIELD_AZ(TX_RX_SPACER_EN), + REGISTER_FIELD_AZ(TX_PS_EVT_DIS), + REGISTER_FIELD_AZ(TX_SOFT_EVT_EN), + REGISTER_FIELD_AZ(TX_DROP_ABORT_EN), + REGISTER_FIELD_AZ(TX_RX_SPACER), + REGISTER_FIELD_AZ(TX_DMAQ_ST), + REGISTER_FIELD_AZ(TX_DMAR_ST_P0), + REGISTER_FIELD_AZ(TX_D_FF_FULL_P0), + REGISTER_FIELD_AZ(TX_PUSH_CHK_DIS), + REGISTER_FIELD_AZ(TX_PUSH_EN), + REGISTER_FIELD_AZ(TX_RD_COMP_TMR), + REGISTER_FIELD_AZ(TX_PREF_AGE_CNT), + REGISTER_FIELD_AZ(TX_EVT_CNT), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_PACE[] = { + REGISTER_FIELD_BZ(TX_PACE_BIN_TH), + REGISTER_FIELD_BZ(TX_PACE_FB_BASE), + REGISTER_FIELD_BZ(TX_PACE_SB_AF), + REGISTER_FIELD_BZ(TX_PACE_SB_NOT_AF), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_PACE_DROP_QID[] = { + REGISTER_FIELD_BZ(TX_PACE_QID_DRP_CNT), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_VLAN[] = { + REGISTER_FIELD_BB(TX_VLAN0), + REGISTER_FIELD_BB(TX_VLAN0_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN0_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN1), + REGISTER_FIELD_BB(TX_VLAN1_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN1_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN2), + REGISTER_FIELD_BB(TX_VLAN2_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN2_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN3), + REGISTER_FIELD_BB(TX_VLAN3_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN3_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN4), + REGISTER_FIELD_BB(TX_VLAN4_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN4_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN5), + REGISTER_FIELD_BB(TX_VLAN5_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN5_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN6), + REGISTER_FIELD_BB(TX_VLAN6_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN6_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN7), + REGISTER_FIELD_BB(TX_VLAN7_PORT0_EN), + REGISTER_FIELD_BB(TX_VLAN7_PORT1_EN), + REGISTER_FIELD_BB(TX_VLAN_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_IPFIL_PORTEN[] = { + REGISTER_FIELD_BB(TX_IPFIL0_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL1_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL2_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL3_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL4_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL5_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL6_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL7_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL8_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL9_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL10_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL11_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL12_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL13_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL14_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL15_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL16_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL17_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL18_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL19_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL20_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL21_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL22_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL23_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL24_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL25_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL26_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL27_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL28_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL29_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL30_PORT_EN), + REGISTER_FIELD_BB(TX_IPFIL31_PORT_EN), + REGISTER_FIELD_BZ(TX_MADR0_FIL_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_IPFIL_TBL[] = { + REGISTER_FIELD_BB(TX_IP_SRC_ADR_0), + REGISTER_FIELD_BB(TX_IPFIL_MASK_0), + REGISTER_FIELD_BB(TX_IP_SRC_ADR_1), + REGISTER_FIELD_BB(TX_IPFIL_MASK_1), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MD_TXD[] = { + REGISTER_FIELD_AB(MD_TXD), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MD_RXD[] = { + REGISTER_FIELD_AB(MD_RXD), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MD_CS[] = { + REGISTER_FIELD_AB(MD_WRC), + REGISTER_FIELD_AB(MD_RDC), + REGISTER_FIELD_AB(MD_RIC), + REGISTER_FIELD_AB(MD_PRSP), + REGISTER_FIELD_AB(MD_GC), + REGISTER_FIELD_AB(MD_INT_CLR), + REGISTER_FIELD_AB(MD_PL), + REGISTER_FIELD_AB(MD_PT), + REGISTER_FIELD_AB(MD_ADDR_CMD), + REGISTER_FIELD_AB(MD_WR_EN_CMD), + REGISTER_FIELD_AB(MD_RD_EN_CMD), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MD_PHY_ADR[] = { + REGISTER_FIELD_AB(MD_PHY_ADR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MD_ID[] = { + REGISTER_FIELD_AB(MD_DEV_ADR), + REGISTER_FIELD_AB(MD_PRT_ADR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MAC_STAT_DMA[] = { + REGISTER_FIELD_AB(MAC_STAT_DMA_ADR), + REGISTER_FIELD_AB(MAC_STAT_DMA_CMD), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MAC_CTRL[] = { + REGISTER_FIELD_AB(MAC_SPEED), + REGISTER_FIELD_AB(MAC_LINK_STATUS), + REGISTER_FIELD_AB(MAC_UC_PROM), + REGISTER_FIELD_AB(MAC_BCAD_ACPT), + REGISTER_FIELD_AB(MAC_XG_DISTXCRC), + REGISTER_FIELD_BB(TXFIFO_DRAIN_EN), + REGISTER_FIELD_AB(MAC_XOFF_VAL), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GEN_MODE[] = { + REGISTER_FIELD_BB(XG_PHY_INT_MASK), + REGISTER_FIELD_BB(XFP_PHY_INT_MASK), + REGISTER_FIELD_BB(XG_PHY_INT_POL_SEL), + REGISTER_FIELD_BB(XFP_PHY_INT_POL_SEL), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MAC_MC_HASH_REG0[] = { + REGISTER_FIELD_AB(MAC_MCAST_HASH0), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MAC_MC_HASH_REG1[] = { + REGISTER_FIELD_AB(MAC_MCAST_HASH1), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GM_CFG1[] = { + REGISTER_FIELD_AB(GM_TX_EN), + REGISTER_FIELD_AB(GM_SYNC_TXEN), + REGISTER_FIELD_AB(GM_RX_EN), + REGISTER_FIELD_AB(GM_SYNC_RXEN), + REGISTER_FIELD_AB(GM_TX_FC_EN), + REGISTER_FIELD_AB(GM_RX_FC_EN), + REGISTER_FIELD_AB(GM_LOOP), + REGISTER_FIELD_AB(GM_RST_TX_FUNC), + REGISTER_FIELD_AB(GM_RST_RX_FUNC), + REGISTER_FIELD_AB(GM_RST_TX_MAC_CTL), + REGISTER_FIELD_AB(GM_RST_RX_MAC_CTL), + REGISTER_FIELD_AB(GM_SIM_RST), + REGISTER_FIELD_AB(GM_SW_RST), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GM_CFG2[] = { + REGISTER_FIELD_AB(GM_FD), + REGISTER_FIELD_AB(GM_CRC_EN), + REGISTER_FIELD_AB(GM_PAD_CRC_EN), + REGISTER_FIELD_AB(GM_LEN_CHK), + REGISTER_FIELD_AB(GM_HUGE_FRM_EN), + REGISTER_FIELD_AB(GM_IF_MODE), + REGISTER_FIELD_AB(GM_PAMBL_LEN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GM_MAX_FLEN[] = { + REGISTER_FIELD_AB(GM_MAX_FLEN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GM_ADR1[] = { + REGISTER_FIELD_AB(GM_ADR_B3), + REGISTER_FIELD_AB(GM_ADR_B2), + REGISTER_FIELD_AB(GM_ADR_B1), + REGISTER_FIELD_AB(GM_ADR_B0), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GM_ADR2[] = { + REGISTER_FIELD_AB(GM_ADR_B5), + REGISTER_FIELD_AB(GM_ADR_B4), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GMF_CFG0[] = { + REGISTER_FIELD_AB(GMF_HSTRSTWT), + REGISTER_FIELD_AB(GMF_HSTRSTSR), + REGISTER_FIELD_AB(GMF_HSTRSTFR), + REGISTER_FIELD_AB(GMF_HSTRSTST), + REGISTER_FIELD_AB(GMF_HSTRSTFT), + REGISTER_FIELD_AB(GMF_WTMENREQ), + REGISTER_FIELD_AB(GMF_SRFENREQ), + REGISTER_FIELD_AB(GMF_FRFENREQ), + REGISTER_FIELD_AB(GMF_STFENREQ), + REGISTER_FIELD_AB(GMF_FTFENREQ), + REGISTER_FIELD_AB(GMF_WTMENRPLY), + REGISTER_FIELD_AB(GMF_SRFENRPLY), + REGISTER_FIELD_AB(GMF_FRFENRPLY), + REGISTER_FIELD_AB(GMF_STFENRPLY), + REGISTER_FIELD_AB(GMF_FTFENRPLY), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GMF_CFG1[] = { + REGISTER_FIELD_AB(GMF_CFGXOFFRTX), + REGISTER_FIELD_AB(GMF_CFGFRTH), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GMF_CFG2[] = { + REGISTER_FIELD_AB(GMF_CFGLWM), + REGISTER_FIELD_AB(GMF_CFGHWM), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GMF_CFG3[] = { + REGISTER_FIELD_AB(GMF_CFGFTTH), + REGISTER_FIELD_AB(GMF_CFGHWMFT), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GMF_CFG4[] = { + REGISTER_FIELD_AB(GMF_HSTFLTRFRM), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_GMF_CFG5[] = { + REGISTER_FIELD_AB(GMF_HSTFLTRFRMDC), + REGISTER_FIELD_AB(GMF_HSTDRPLT64), + REGISTER_FIELD_AB(GMF_CFGBYTMODE), + REGISTER_FIELD_AB(GMF_HSTSRFULLCLR), + REGISTER_FIELD_AB(GMF_SRFULL), + REGISTER_FIELD_AB(GMF_CFGHDPLX), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_SRC_MAC_TBL[] = { + REGISTER_FIELD_BB(TX_SRC_MAC_ADR_0), + REGISTER_FIELD_BB(TX_SRC_MAC_ADR_1), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_SRC_MAC_CTL[] = { + REGISTER_FIELD_BB(TX_MAC_QID_SEL), + REGISTER_FIELD_BB(TX_DROP_CTR_CLR), + REGISTER_FIELD_BB(TX_SRC_FLTR_EN), + REGISTER_FIELD_BB(TX_SRC_DROP_CTR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_ADR_LO[] = { + REGISTER_FIELD_AB(XM_ADR_LO), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_ADR_HI[] = { + REGISTER_FIELD_AB(XM_ADR_HI), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_GLB_CFG[] = { + REGISTER_FIELD_AB(XM_CORE_RST), + REGISTER_FIELD_AB(XM_INTCLR_MODE), + REGISTER_FIELD_AB(XM_WAN_MODE), + REGISTER_FIELD_AB(XM_RX_JUMBO_MODE), + REGISTER_FIELD_AB(XM_TX_STAT_EN), + REGISTER_FIELD_AB(XM_RX_STAT_EN), + REGISTER_FIELD_AB(XM_DEBUG_MODE), + REGISTER_FIELD_AB(XM_RMTFLT_GEN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_TX_CFG[] = { + REGISTER_FIELD_AB(XM_TX_RST), + REGISTER_FIELD_AB(XM_TXEN), + REGISTER_FIELD_AB(XM_TX_PRMBL), + REGISTER_FIELD_AB(XM_AUTO_PAD), + REGISTER_FIELD_AB(XM_EDRC), + REGISTER_FIELD_AB(XM_TXCRC), + REGISTER_FIELD_AB(XM_FCNTL), + REGISTER_FIELD_AB(XM_IPG), + REGISTER_FIELD_AB(XM_TX_PROG), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_RX_CFG[] = { + REGISTER_FIELD_AB(XM_RX_RST), + REGISTER_FIELD_AB(XM_RXEN), + REGISTER_FIELD_AB(XM_RX_PRMBL), + REGISTER_FIELD_AB(XM_RXCRC), + REGISTER_FIELD_AB(XM_AUTO_DEPAD), + REGISTER_FIELD_AB(XM_ACPT_ALL_UCAST), + REGISTER_FIELD_AB(XM_ACPT_ALL_MCAST), + REGISTER_FIELD_AB(XM_REJ_BCAST), + REGISTER_FIELD_AB(XM_PASS_PRMBLE_ERR), + REGISTER_FIELD_AB(XM_PASS_CRC_ERR), + REGISTER_FIELD_AB(XM_PASS_LENERR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_MGT_INT_MASK[] = { + REGISTER_FIELD_AB(XM_MSK_LCLFLT), + REGISTER_FIELD_AB(XM_MSK_RMTFLT), + REGISTER_FIELD_AB(XM_MSK_PRMBLE_ERR), + REGISTER_FIELD_AB(XM_MSK_STAT_CNTR_OF), + REGISTER_FIELD_AB(XM_MSK_STAT_CNTR_HF), + REGISTER_FIELD_AB(XM_MSK_STA_INTR), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_FC[] = { + REGISTER_FIELD_AB(XM_DIS_FCNTL), + REGISTER_FIELD_AB(XM_XMIT_PAUSE), + REGISTER_FIELD_AB(XM_ZPAUSE), + REGISTER_FIELD_AB(XM_REJ_CNTL_MCAST), + REGISTER_FIELD_AB(XM_REJ_CNTL_UCAST), + REGISTER_FIELD_AB(XM_MCNTL_PASS), + REGISTER_FIELD_AB(XM_TX_MAC_STAT), + REGISTER_FIELD_AB(XM_RX_MAC_STAT), + REGISTER_FIELD_AB(XM_PAUSE_TIME), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_PAUSE_TIME[] = { + REGISTER_FIELD_AB(XM_RX_PAUSE_CNT), + REGISTER_FIELD_AB(XM_TX_PAUSE_CNT), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_TX_PARAM[] = { + REGISTER_FIELD_AB(XM_PAD_CHAR), + REGISTER_FIELD_AB(XM_MAX_TX_FRM_SIZE_LO), + REGISTER_FIELD_AB(XM_MAX_TX_FRM_SIZE_HI), + REGISTER_FIELD_AB(XM_TX_JUMBO_MODE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XM_RX_PARAM[] = { + REGISTER_FIELD_AB(XM_MAX_RX_FRM_SIZE_LO), + REGISTER_FIELD_AB(XM_MAX_RX_FRM_SIZE_HI), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XX_PWR_RST[] = { + REGISTER_FIELD_AB(XX_RST_XX_EN), + REGISTER_FIELD_AB(XX_RSTXGXSTX_EN), + REGISTER_FIELD_AB(XX_RSTXGXSRX_EN), + REGISTER_FIELD_AB(XX_RESETA_EN), + REGISTER_FIELD_AB(XX_RESETB_EN), + REGISTER_FIELD_AB(XX_RESETC_EN), + REGISTER_FIELD_AB(XX_RESETD_EN), + REGISTER_FIELD_AB(XX_RSTPLLAB_EN), + REGISTER_FIELD_AB(XX_RSTPLLCD_EN), + REGISTER_FIELD_AB(XX_PWRDNA_EN), + REGISTER_FIELD_AB(XX_PWRDNB_EN), + REGISTER_FIELD_AB(XX_PWRDNC_EN), + REGISTER_FIELD_AB(XX_PWRDND_EN), + REGISTER_FIELD_AB(XX_SD_RST_ACT), + REGISTER_FIELD_AB(XX_RSTXGXSTX_SIG), + REGISTER_FIELD_AB(XX_RSTXGXSRX_SIG), + REGISTER_FIELD_AB(XX_RESETA_SIG), + REGISTER_FIELD_AB(XX_RESETB_SIG), + REGISTER_FIELD_AB(XX_RESETC_SIG), + REGISTER_FIELD_AB(XX_RESETD_SIG), + REGISTER_FIELD_AB(XX_RSTPLLAB_SIG), + REGISTER_FIELD_AB(XX_RSTPLLCD_SIG), + REGISTER_FIELD_AB(XX_SIM_MODE), + REGISTER_FIELD_AB(XX_PWRDNA_SIG), + REGISTER_FIELD_AB(XX_PWRDNB_SIG), + REGISTER_FIELD_AB(XX_PWRDNC_SIG), + REGISTER_FIELD_AB(XX_PWRDND_SIG), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XX_SD_CTL[] = { + REGISTER_FIELD_AB(XX_LPBKA), + REGISTER_FIELD_AB(XX_LPBKB), + REGISTER_FIELD_AB(XX_LPBKC), + REGISTER_FIELD_AB(XX_LPBKD), + REGISTER_FIELD_AB(XX_LODRVA), + REGISTER_FIELD_AB(XX_HIDRVA), + REGISTER_FIELD_AB(XX_LODRVB), + REGISTER_FIELD_AB(XX_HIDRVB), + REGISTER_FIELD_AB(XX_LODRVC), + REGISTER_FIELD_AB(XX_HIDRVC), + REGISTER_FIELD_AB(XX_LODRVD), + REGISTER_FIELD_AB(XX_HIDRVD), + REGISTER_FIELD_AB(XX_TERMADJ0), + REGISTER_FIELD_AB(XX_TERMADJ1), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_XX_TXDRV_CTL[] = { + REGISTER_FIELD_AB(XX_DTXA), + REGISTER_FIELD_AB(XX_DTXB), + REGISTER_FIELD_AB(XX_DTXC), + REGISTER_FIELD_AB(XX_DTXD), + REGISTER_FIELD_AB(XX_DEQA), + REGISTER_FIELD_AB(XX_DEQB), + REGISTER_FIELD_AB(XX_DEQC), + REGISTER_FIELD_AB(XX_DEQD), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_DESC_PTR_TBL[] = { + /* Abbreviate field names to reduce the table width */ + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_EN, "EN"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_JUMBO, "JUMBO"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_TYPE, "TYPE"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_SIZE, "SIZE"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_LABEL, "LABEL"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_OWNER_ID, "OWNER"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_EVQ_ID, "EVQ"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_BUF_BASE_ID, "BUF_BASE"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_SW_WPTR, "SW_WPTR"), + REGISTER_FIELD_AZ_RENAME(RX_DESCQ_HW_RPTR, "HW_RPTR"), + REGISTER_FIELD_AZ_RENAME(RX_DC_HW_RPTR, "DC_HW_RPTR"), + REGISTER_FIELD_AZ_RENAME(RX_DESC_PREF_ACT, "PREF_ACT"), + REGISTER_FIELD_AZ_RENAME(RX_ISCSI_HDIG_EN, "HDIG"), + REGISTER_FIELD_AZ_RENAME(RX_ISCSI_DDIG_EN, "DDIG"), + REGISTER_FIELD_AA(RX_RESET), + REGISTER_FIELD_CZ_RENAME(RX_HDR_SPLIT, "HDR_SPLIT"), +}; +#define efx_nic_reg_fields_RX_DESC_PTR_TBL_KER efx_nic_reg_fields_RX_DESC_PTR_TBL +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_DESC_PTR_TBL[] = { + /* Abbreviate field names to reduce the table width */ + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_FLUSH, "FLUSH"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_TYPE, "TYPE"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_SIZE, "SIZE"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_LABEL, "LABEL"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_OWNER_ID, "OWNER"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_EVQ_ID, "EVQ"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_BUF_BASE_ID, "BUF_BASE"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_SW_WPTR, "SW_WPTR"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_HW_RPTR, "HW_RPTR"), + REGISTER_FIELD_AZ_RENAME(TX_DC_HW_RPTR, "DC_HW_RPTR"), + REGISTER_FIELD_AZ_RENAME(TX_ISCSI_HDIG_EN, "HDIG"), + REGISTER_FIELD_AZ_RENAME(TX_ISCSI_DDIG_EN, "DDIG"), + REGISTER_FIELD_AZ_RENAME(TX_DESCQ_EN, "EN"), + REGISTER_FIELD_BZ_RENAME(TX_TCP_CHKSM_DIS, "!TCP_CHKSM"), + REGISTER_FIELD_BZ_RENAME(TX_IP_CHKSM_DIS, "!IP_CHKSM"), + REGISTER_FIELD_BZ_RENAME(TX_NON_IP_DROP_DIS, "!NON_IP_DROP"), + REGISTER_FIELD_CZ_RENAME(TX_DPT_IP_FILT_EN, "IP_FILT"), + REGISTER_FIELD_CZ_RENAME(TX_DPT_ETH_FILT_EN, "ETH_FILT"), + REGISTER_FIELD_CZ_RENAME(TX_DPT_Q_MASK_WIDTH, "Q_MASK_WIDTH"), +}; +#define efx_nic_reg_fields_TX_DESC_PTR_TBL_KER efx_nic_reg_fields_TX_DESC_PTR_TBL +static const struct efx_nic_reg_field efx_nic_reg_fields_EVQ_PTR_TBL[] = { + REGISTER_FIELD_AZ(EVQ_BUF_BASE_ID), + REGISTER_FIELD_AZ(EVQ_SIZE), + REGISTER_FIELD_AZ(EVQ_EN), + REGISTER_FIELD_AZ(EVQ_NXT_WPTR), + REGISTER_FIELD_CZ(EVQ_DOS_PROTECT_EN), + REGISTER_FIELD_AB(EVQ_WKUP_OR_INT_EN), + REGISTER_FIELD_BZ(EVQ_RPTR_IGN), +}; +#define efx_nic_reg_fields_EVQ_PTR_TBL_KER efx_nic_reg_fields_EVQ_PTR_TBL +static const struct efx_nic_reg_field efx_nic_reg_fields_BUF_FULL_TBL[] = { + REGISTER_FIELD_AZ(BUF_OWNER_ID_FBUF), + REGISTER_FIELD_AZ(BUF_ADR_FBUF), + REGISTER_FIELD_AZ(BUF_ADR_REGION), + REGISTER_FIELD_AZ(IP_DAT_BUF_SIZE), + REGISTER_FIELD_AZ(BUF_FULL_UNUSED), +}; +#define efx_nic_reg_fields_BUF_FULL_TBL_KER efx_nic_reg_fields_BUF_FULL_TBL +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_FILTER_TBL0[] = { + REGISTER_FIELD_BZ(SRC_TCP_DEST_UDP), + REGISTER_FIELD_BZ(SRC_IP), + REGISTER_FIELD_BZ(DEST_PORT_TCP), + REGISTER_FIELD_BZ(DEST_IP), + REGISTER_FIELD_BZ(RXQ_ID), + REGISTER_FIELD_BZ(TCP_UDP), + REGISTER_FIELD_BZ(SCATTER_EN), + REGISTER_FIELD_BZ(RSS_EN), +}; +#define efx_nic_reg_fields_RX_FILTER_TBL1 efx_nic_reg_fields_RX_FILTER_TBL0 +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_MAC_FILTER_TBL0[] = { + REGISTER_FIELD_CZ(RMFT_VLAN_ID), + REGISTER_FIELD_CZ(RMFT_DEST_MAC), + REGISTER_FIELD_CZ(RMFT_WILDCARD_MATCH), + REGISTER_FIELD_CZ(RMFT_RXQ_ID), + REGISTER_FIELD_CZ(RMFT_IP_OVERRIDE), + REGISTER_FIELD_CZ(RMFT_SCATTER_EN), + REGISTER_FIELD_CZ(RMFT_RSS_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TIMER_TBL[] = { + REGISTER_FIELD_BB(TIMER_VAL), + REGISTER_FIELD_CZ(TIMER_VAL), + REGISTER_FIELD_BB(TIMER_MODE), + REGISTER_FIELD_CZ(TIMER_MODE), + REGISTER_FIELD_CZ(RELOAD_TIMER_VAL), + REGISTER_FIELD_CZ(HOST_NOTIFY_MODE), + REGISTER_FIELD_CZ(INT_PEND), + REGISTER_FIELD_CZ(INT_ARMD), + REGISTER_FIELD_CZ(TIMER_Q_EN), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_PACE_TBL[] = { + REGISTER_FIELD_BZ(TX_PACE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_RX_INDIRECTION_TBL[] = { + REGISTER_FIELD_BZ(IT_QUEUE), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_TX_MAC_FILTER_TBL0[] = { + REGISTER_FIELD_CZ(TMFT_VLAN_ID), + REGISTER_FIELD_CZ(TMFT_SRC_MAC), + REGISTER_FIELD_CZ(TMFT_WILDCARD_MATCH), + REGISTER_FIELD_CZ(TMFT_TXQ_ID), +}; +static const struct efx_nic_reg_field efx_nic_reg_fields_MC_TREG_SMEM[] = { + REGISTER_FIELD_CZ(MC_TREG_SMEM_ROW), +}; + +struct efx_nic_reg { + const char *name; + const struct efx_nic_reg_field *fields; + u32 field_count:7; + u32 min_revision:2, max_revision:2; +}; + +#define REGISTER(name, min_rev, max_rev) { \ + #name, \ + efx_nic_reg_fields_ ## name, \ + ARRAY_SIZE(efx_nic_reg_fields_ ## name), \ + REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ +} +#define REGISTER_AA(name) REGISTER(name, A, A) +#define REGISTER_AB(name) REGISTER(name, A, B) +#define REGISTER_AZ(name) REGISTER(name, A, Z) +#define REGISTER_BB(name) REGISTER(name, B, B) +#define REGISTER_BZ(name) REGISTER(name, B, Z) +#define REGISTER_CZ(name) REGISTER(name, C, Z) + +static const struct efx_nic_reg efx_nic_regs[] = { + REGISTER_AZ(ADR_REGION), + REGISTER_AZ(INT_EN_KER), + REGISTER_BZ(INT_EN_CHAR), + REGISTER_AZ(INT_ADR_KER), + REGISTER_BZ(INT_ADR_CHAR), + /* INT_ACK_KER is WO */ + /* INT_ISR0 is RC */ + REGISTER_AZ(HW_INIT), + REGISTER_CZ(USR_EV_CFG), + REGISTER_AB(EE_SPI_HCMD), + REGISTER_AB(EE_SPI_HADR), + REGISTER_AB(EE_SPI_HDATA), + REGISTER_AB(EE_BASE_PAGE), + REGISTER_AB(EE_VPD_CFG0), + /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */ + /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */ + /* PCIE_CORE_INDIRECT is indirect */ + REGISTER_AB(NIC_STAT), + REGISTER_AB(GPIO_CTL), + REGISTER_AB(GLB_CTL), + /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */ + REGISTER_BZ(DP_CTRL), + REGISTER_AZ(MEM_STAT), + REGISTER_AZ(CS_DEBUG), + REGISTER_AZ(ALTERA_BUILD), + REGISTER_AZ(CSR_SPARE), + REGISTER_AB(PCIE_SD_CTL0123), + REGISTER_AB(PCIE_SD_CTL45), + REGISTER_AB(PCIE_PCS_CTL_STAT), + /* DEBUG_DATA_OUT is not used */ + /* DRV_EV is WO */ + REGISTER_AZ(EVQ_CTL), + REGISTER_AZ(EVQ_CNT1), + REGISTER_AZ(EVQ_CNT2), + REGISTER_AZ(BUF_TBL_CFG), + REGISTER_AZ(SRM_RX_DC_CFG), + REGISTER_AZ(SRM_TX_DC_CFG), + REGISTER_AZ(SRM_CFG), + /* BUF_TBL_UPD is WO */ + REGISTER_AZ(SRM_UPD_EVQ), + REGISTER_AZ(SRAM_PARITY), + REGISTER_AZ(RX_CFG), + REGISTER_BZ(RX_FILTER_CTL), + /* RX_FLUSH_DESCQ is WO */ + REGISTER_AZ(RX_DC_CFG), + REGISTER_AZ(RX_DC_PF_WM), + REGISTER_BZ(RX_RSS_TKEY), + /* RX_NODESC_DROP is RC */ + REGISTER_AA(RX_SELF_RST), + /* RX_DEBUG, RX_PUSH_DROP are not used */ + REGISTER_CZ(RX_RSS_IPV6_REG1), + REGISTER_CZ(RX_RSS_IPV6_REG2), + REGISTER_CZ(RX_RSS_IPV6_REG3), + /* TX_FLUSH_DESCQ is WO */ + REGISTER_AZ(TX_DC_CFG), + REGISTER_AA(TX_CHKSM_CFG), + REGISTER_AZ(TX_CFG), + /* TX_PUSH_DROP is not used */ + REGISTER_AZ(TX_RESERVED), + REGISTER_BZ(TX_PACE), + /* TX_PACE_DROP_QID is RC */ + REGISTER_BB(TX_VLAN), + REGISTER_BZ(TX_IPFIL_PORTEN), + REGISTER_AB(MD_TXD), + REGISTER_AB(MD_RXD), + REGISTER_AB(MD_CS), + REGISTER_AB(MD_PHY_ADR), + REGISTER_AB(MD_ID), + /* MD_STAT is RC */ + REGISTER_AB(MAC_STAT_DMA), + REGISTER_AB(MAC_CTRL), + REGISTER_BB(GEN_MODE), + REGISTER_AB(MAC_MC_HASH_REG0), + REGISTER_AB(MAC_MC_HASH_REG1), + REGISTER_AB(GM_CFG1), + REGISTER_AB(GM_CFG2), + /* GM_IPG and GM_HD are not used */ + REGISTER_AB(GM_MAX_FLEN), + /* GM_TEST is not used */ + REGISTER_AB(GM_ADR1), + REGISTER_AB(GM_ADR2), + REGISTER_AB(GMF_CFG0), + REGISTER_AB(GMF_CFG1), + REGISTER_AB(GMF_CFG2), + REGISTER_AB(GMF_CFG3), + REGISTER_AB(GMF_CFG4), + REGISTER_AB(GMF_CFG5), + REGISTER_BB(TX_SRC_MAC_CTL), + REGISTER_AB(XM_ADR_LO), + REGISTER_AB(XM_ADR_HI), + REGISTER_AB(XM_GLB_CFG), + REGISTER_AB(XM_TX_CFG), + REGISTER_AB(XM_RX_CFG), + REGISTER_AB(XM_MGT_INT_MASK), + REGISTER_AB(XM_FC), + REGISTER_AB(XM_PAUSE_TIME), + REGISTER_AB(XM_TX_PARAM), + REGISTER_AB(XM_RX_PARAM), + /* XM_MGT_INT_MSK (note no 'A') is RC */ + REGISTER_AB(XX_PWR_RST), + REGISTER_AB(XX_SD_CTL), + REGISTER_AB(XX_TXDRV_CTL), + /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ + /* XX_CORE_STAT is partly RC */ +}; + +struct efx_nic_reg_table { + const char *name; + const struct efx_nic_reg_field *fields; + u32 field_count:7; + u32 min_revision:2, max_revision:2; + u32 step:6, rows:21; +}; + +#define REGISTER_TABLE_DIMENSIONS(name, _, min_rev, max_rev, step, rows) { \ + #name, \ + efx_nic_reg_fields_ ## name, \ + ARRAY_SIZE(efx_nic_reg_fields_ ## name), \ + REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ + step, rows \ +} +#define REGISTER_TABLE(name, min_rev, max_rev) \ + REGISTER_TABLE_DIMENSIONS( \ + name, FR_ ## min_rev ## max_rev ## _ ## name, \ + min_rev, max_rev, \ + FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ + FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) +#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) +#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) +#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) +#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) +#define REGISTER_TABLE_BB_CZ(name) \ + REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ + FR_BZ_ ## name ## _STEP, \ + FR_BB_ ## name ## _ROWS), \ + REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ + FR_BZ_ ## name ## _STEP, \ + FR_CZ_ ## name ## _ROWS) +#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) + +static const struct efx_nic_reg_table efx_nic_reg_tables[] = { + /* DRIVER is not used */ + /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */ + REGISTER_TABLE_BB(TX_IPFIL_TBL), + REGISTER_TABLE_BB(TX_SRC_MAC_TBL), + REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER), + REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL), + REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER), + REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL), + REGISTER_TABLE_AA(EVQ_PTR_TBL_KER), + REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL), + /* The register buffer is allocated with slab, so we can't + * reasonably read all of the buffer table (up to 8MB!). + * However this driver will only use a few entries. Reading + * 1K entries allows for some expansion of queue count and + * size before we need to change the version. */ + REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, + A, A, 8, 1024), + REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, + B, Z, 8, 1024), + /* RX_FILTER_TBL{0,1} is huge and not used by this driver */ + REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), + REGISTER_TABLE_BB_CZ(TIMER_TBL), + REGISTER_TABLE_BB_CZ(TX_PACE_TBL), + REGISTER_TABLE_BZ(RX_INDIRECTION_TBL), + /* TX_FILTER_TBL0 is huge and not used by this driver */ + REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0), + REGISTER_TABLE_CZ(MC_TREG_SMEM), + /* MSIX_PBA_TABLE is not mapped */ + /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ +}; + +static size_t column_width(const struct efx_nic_reg_field *field) +{ + size_t name_width, value_width; + + name_width = strlen(field->name); + value_width = (field->width + 3) >> 2; + + return name_width > value_width ? name_width : value_width; +} + +static size_t column_padding(const struct efx_nic_reg_field *field) +{ + size_t name_width, value_width; + + name_width = strlen(field->name); + value_width = (field->width + 3) >> 2; + + return name_width > value_width ? name_width - value_width : 0; +} + +static void +print_field_value(const struct efx_nic_reg_field *field, const u8 *buf) +{ + unsigned left, right, sig_bits, digit; + + right = field->lbn; + left = right + ((field->width + 3) & ~3); + + /* How many bits are valid for the most significant hex digit? */ + sig_bits = (field->width & 3) ? (field->width & 3) : 4; + + while (left > right) { + left -= 4; + digit = buf[left >> 3]; + if ((left & 7) + sig_bits > 8) + digit |= buf[(left >> 3) + 1] << 8; + digit = (digit >> (left & 7)) & ((1 << sig_bits) - 1); + printf("%x", digit); + sig_bits = 4; /* for all subsequent digits */ + } +} + +static const void * +print_single_register(unsigned revision, const struct efx_nic_reg *reg, + const void *buf) +{ + const struct efx_nic_reg_field *field; + int indent = 0; + size_t i; + + for (i = 0; i < reg->field_count; i++) { + field = ®->fields[i]; + if (revision >= field->min_revision && + revision <= field->max_revision) { + if (indent == 0) + indent = printf("%s: ", reg->name); + else + printf("%*s", indent, ""); + printf("%s = ", field->name); + print_field_value(field, buf); + fputc('\n', stdout); + } + } + + return (const u8 *)buf + 16; +} + +static const void * +print_simple_table(unsigned revision, const struct efx_nic_reg_table *table, + const void *buf) +{ + const struct efx_nic_reg_field *field = &table->fields[0]; + size_t value_width = (field->width + 3) >> 2; + size_t column_count = 72 / (value_width + 1); + size_t size = table->step > 16 ? 16 : table->step; + size_t i; + + for (i = 0; i < table->rows; i++) { + if (i % column_count == 0) { + if (i != 0) + fputc('\n', stdout); + printf("%4zu ", i); + } + fputc(' ', stdout); + print_field_value(field, buf); + buf = (const u8 *)buf + size; + } + fputc('\n', stdout); + + return buf; +} + +static const void * +print_complex_table(unsigned revision, const struct efx_nic_reg_table *table, + const void *buf) +{ + const struct efx_nic_reg_field *field; + size_t size = table->step > 16 ? 16 : table->step; + size_t i, j; + + /* Column headings */ + fputs("Row ", stdout); + for (i = 0; i < table->field_count; i++) { + field = &table->fields[i]; + if (revision >= field->min_revision && + revision <= field->max_revision) + printf(" %-*s", (int)column_width(field), + field->name); + } + fputc('\n', stdout); + fputs("----", stdout); + for (i = 0; i < table->field_count; i++) { + field = &table->fields[i]; + if (revision >= field->min_revision && + revision <= field->max_revision) { + fputc(' ', stdout); + for (j = column_width(field); j > 0; j--) + fputc('-', stdout); + } + } + fputc('\n', stdout); + + for (j = 0; j < table->rows; j++) { + printf("%4zu", j); + for (i = 0; i < table->field_count; i++) { + field = &table->fields[i]; + if (!(revision >= field->min_revision && + revision <= field->max_revision)) + continue; + printf(" %*s", (int)column_padding(field), ""); + print_field_value(field, buf); + } + fputc('\n', stdout); + buf = (const u8 *)buf + size; + } + + return buf; +} + +int +sfc_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + const struct efx_nic_reg *reg; + const struct efx_nic_reg_table *table; + unsigned revision = regs->version; + const void *buf = regs->data; + + if (revision > REGISTER_REVISION_Z) + return -1; + + for (reg = efx_nic_regs; + reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); + reg++) { + if (revision >= reg->min_revision && + revision <= reg->max_revision) + buf = print_single_register(revision, reg, buf); + } + + for (table = efx_nic_reg_tables; + table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables); + table++) { + if (revision >= table->min_revision && + revision <= table->max_revision) { + printf("\n%s:\n", table->name); + if (table->field_count == 1) + buf = print_simple_table(revision, table, buf); + else + buf = print_complex_table(revision, table, buf); + } + } + + return 0; +}
diff --git a/ethtool-2.6.35/smsc911x.c b/ethtool-2.6.35/smsc911x.c new file mode 100644 index 0000000..1aa39a1 --- /dev/null +++ b/ethtool-2.6.35/smsc911x.c
@@ -0,0 +1,90 @@ +#include <stdio.h> +#include <string.h> +#include "ethtool-util.h" + +int smsc911x_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + unsigned int *smsc_reg = (unsigned int *)regs->data; + + fprintf(stdout, "LAN911x Registers\n"); + fprintf(stdout, "offset 0x50, ID_REV = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x54, INT_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x58, INT_STS = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x5C, INT_EN = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x60, RESERVED = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x64, BYTE_TEST = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x68, FIFO_INT = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x6C, RX_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x70, TX_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x74, HW_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x78, RX_DP_CTRL = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x7C, RX_FIFO_INF = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x80, TX_FIFO_INF = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x84, PMT_CTRL = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x88, GPIO_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x8C, GPT_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x90, GPT_CNT = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x94, FPGA_REV = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x98, ENDIAN = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0x9C, FREE_RUN = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0xA0, RX_DROP = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0xA4, MAC_CSR_CMD = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0xA8, MAC_CSR_DATA = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0xAC, AFC_CFG = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0xB0, E2P_CMD = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "offset 0xB4, E2P_DATA = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "\n"); + + fprintf(stdout, "MAC Registers\n"); + fprintf(stdout, "index 1, MAC_CR = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 2, ADDRH = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 3, ADDRL = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 4, HASHH = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 5, HASHL = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 6, MII_ACC = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 7, MII_DATA = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 8, FLOW = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index 9, VLAN1 = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index A, VLAN2 = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index B, WUFF = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "index C, WUCSR = 0x%08X\n",*smsc_reg++); + fprintf(stdout, "\n"); + + fprintf(stdout, "PHY Registers\n"); + fprintf(stdout, "index 0, Basic Control Reg = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 1, Basic Status Reg = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 2, PHY identifier 1 = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 3, PHY identifier 2 = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 4, Auto Negotiation Advertisement Reg = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 6, Auto Negotiation Expansion Register = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 7, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 8, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 9, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 10, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 11, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 12, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 13, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 14, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 15, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 16, Silicon Revision Reg = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 17, Mode Control/Status Reg = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 18, Special Modes = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 19, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 20, TSTCNTL = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 21, TSTREAD1 = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 22, TSTREAD2 = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 23, TSTWRITE = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 24, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 25, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 26, Reserved = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 27, Control/Status Indication = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 28, Special internal testability = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 29, Interrupt Source Register = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 30, Interrupt Mask Register = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "index 31, PHY Special Control/Status Register = 0x%04X\n",*smsc_reg++); + fprintf(stdout, "\n"); + + return 0; +} +
diff --git a/ethtool-2.6.35/tg3.c b/ethtool-2.6.35/tg3.c new file mode 100644 index 0000000..1ce07a8 --- /dev/null +++ b/ethtool-2.6.35/tg3.c
@@ -0,0 +1,58 @@ +#include <stdio.h> +#include <string.h> +#include "ethtool-util.h" + +#define TG3_MAGIC 0x669955aa + +int +tg3_dump_eeprom(struct ethtool_drvinfo *info, struct ethtool_eeprom *ee) +{ + int i; + + if (ee->magic != TG3_MAGIC) { + fprintf(stderr, "Magic number 0x%08x does not match 0x%08x\n", + ee->magic, TG3_MAGIC); + return -1; + } + + fprintf(stdout, "Address \tData\n"); + fprintf(stdout, "----------\t----\n"); + for (i = 0; i < ee->len; i++) + fprintf(stdout, "0x%08x\t0x%02x\n", i + ee->offset, ee->data[i]); + + return 0; +} + +int +tg3_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + int i, j; + int reg_boundaries[] = { 0x015c, 0x0200, 0x0400, 0x0400, 0x08f0, 0x0c00, + 0x0ce0, 0x1000, 0x1004, 0x1400, 0x1480, 0x1800, + 0x1848, 0x1c00, 0x1c04, 0x2000, 0x225c, 0x2400, + 0x24c4, 0x2800, 0x2804, 0x2c00, 0x2c20, 0x3000, + 0x3014, 0x3400, 0x3408, 0x3800, 0x3808, 0x3c00, + 0x3d00, 0x4000, 0x4010, 0x4400, 0x4458, 0x4800, + 0x4808, 0x4c00, 0x4c08, 0x5000, 0x5280, 0x5400, + 0x5680, 0x5800, 0x5a10, 0x5c00, 0x5d20, 0x6000, + 0x600c, 0x6800, 0x6848, 0x7000, 0x7034, 0x7c00, + 0x7e40, 0x8000 }; + + fprintf(stdout, "Offset\tValue\n"); + fprintf(stdout, "------\t----------\n"); + for (i = 0, j = 0; i < regs->len; ) { + u32 reg; + + memcpy(®, ®s->data[i], 4); + fprintf(stdout, "0x%04x\t0x%08x\n", i, reg); + + i += 4; + if (i == reg_boundaries[j]) { + i = reg_boundaries[j + 1]; + j += 2; + fprintf(stdout, "\n"); + } + } + fprintf(stdout, "\n"); + return 0; +}
diff --git a/ethtool-2.6.35/vioc.c b/ethtool-2.6.35/vioc.c new file mode 100644 index 0000000..c771737 --- /dev/null +++ b/ethtool-2.6.35/vioc.c
@@ -0,0 +1,33 @@ +/* Copyright 2006 Fabric7 Systems, Inc */ + +#include <stdio.h> +#include <stdlib.h> +#include "ethtool-util.h" + +struct regs_line { + u32 addr; + u32 data; +}; + +#define VIOC_REGS_LINE_SIZE sizeof(struct regs_line) + +int vioc_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + unsigned int i; + unsigned int num_regs; + struct regs_line *reg_info = (struct regs_line *) regs->data; + + printf("ethtool_regs\n" + "%-20s = %04x\n" + "%-20s = %04x\n", + "cmd", regs->cmd, + "version", regs->version); + + num_regs = regs->len/VIOC_REGS_LINE_SIZE; + + for (i = 0; i < num_regs; i++){ + printf("%08x = %08x\n", reg_info[i].addr, reg_info[i].data); + } + + return 0; +}
diff --git a/ethtool.tar.gz b/ethtool.tar.gz new file mode 100644 index 0000000..a705ddb --- /dev/null +++ b/ethtool.tar.gz Binary files differ
diff --git a/ethtool.url b/ethtool.url new file mode 100644 index 0000000..dbea66b --- /dev/null +++ b/ethtool.url
@@ -0,0 +1 @@ +http://download.sourceforge.net/gkernel/ethtool-2.6.35.tar.gz
diff --git a/ethtool.version b/ethtool.version new file mode 100644 index 0000000..8f23ebb --- /dev/null +++ b/ethtool.version
@@ -0,0 +1 @@ +2.6.35