| # ARM V6 events |
| # |
| event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses |
| event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled |
| event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency |
| event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses |
| event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses |
| event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change |
| event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted |
| event:0x07 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED : instructions executed |
| event:0x09 counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS : data cache access, cacheable locations |
| event:0x0a counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS_ALL : data cache access, all locations |
| event:0x0b counters:0,1 um:zero minimum:500 name:DCACHE_MISS : data cache miss |
| event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline |
| event:0x0d counters:0,1 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch |
| event:0x0f counters:0,1 um:zero minimum:500 name:TLB_MISS : Main TLB miss |
| event:0x10 counters:0,1 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access |
| event:0x11 counters:0,1 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full |
| event:0x12 counters:0,1 um:zero minimum:500 name:WRITE_DRAIN : Times write buffer was drained |
| event:0x20 counters:0,1 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal was asserted |
| event:0x21 counters:0,1 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal was asserted |
| event:0x22 counters:0,1 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2 |
| event:0xff counters:0,1,2 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter |
