blob: 28da01e1508e5c66fc7f197b809e018d490ce134 [file] [log] [blame]
# Core Solo / Core Duo possible unit masks
name:zero type:mandatory default:0x0
0x0 No unit mask
name:one type:mandatory default:0x1
0x1 No unit mask
name:two type:mandatory default:0x2
0x2 No unit mask
name:x0f type:mandatory default:0xf
0xf No unit mask
name:x20 type:mandatory default:0x20
0x20 No unit mask
name:x40 type:mandatory default:0x40
0x40 No unit mask
name:xc0 type:mandatory default:0xc0
0xc0 No unit mask
name:nonhlt type:exclusive default:0x0
0x0 Unhalted core cycles
0x1 Unhalted bus cycles
0x2 Unhalted bus cycles of this core while the other core is halted
name:mesi type:bitmask default:0x0f
0x08 (M)odified cache state
0x04 (E)xclusive cache state
0x02 (S)hared cache state
0x01 (I)nvalid cache state
0x0f All cache states
0x10 HW prefetched line only
0x20 all prefetched line w/o regarding mask 0x10.
name:est_trans type:exclusive default:0x00
0x00 any transitions
0x10 Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions
0x20 any transactions
name:kni_prefetch type:exclusive default:0x0
0x00 prefetch NTA
0x01 prefetch T1
0x02 prefetch T2
0x03 weakly-ordered stores
# this bitmask can seems weirds but is correct, note there is no way to only
# count scalar SIMD instructions
name:sse_sse2_inst_retired type:exclusive default:0x0
0x00 SSE Packed Single
0x01 SSE Scalar-Single
0x02 SSE2 Packed-Double
0x03 SSE2 Scalar-Double
name:mmx_instr_type_exec type:bitmask default:0x3f
0x01 MMX packed multiplies
0x02 MMX packed shifts
0x04 MMX pack operations
0x08 MMX unpack operations
0x10 MMX packed logical
0x20 MMX packed arithmetic
0x3f all of the above
name:mmx_trans type:exclusive default:0x0
0x00 MMX->float operations
0x01 float->MMX operations
name:fused type:exclusive default:0x0
0x00 All fused micro-ops
0x01 Only load+Op micro-ops
0x02 Only std+sta micro-ops
name:dc_pend_miss type:exclusive default:0x0
0x00 Weighted cycles
0x01 Duration of cycles
name:sse_miss type:exclusive default:0x0
0x03 SSE streaming store instructions