blob: 4d4c1e3b92a4984324bfad67794dd80f1b7041e5 [file] [log] [blame]
# Intel "sandy-bridge" microarchitecture core events.
# See for help in identifying sandy-bridge based CPUs
# Note the minimum counts are not discovered experimentally and could be likely
# lowered in many cases without ill effect.
event:0x03 counters:cpuid um:ld_blocks minimum:100000 name:ld_blocks : blocked loads
event:0x05 counters:cpuid um:misalign_mem_ref minimum:2000000 name:misalign_mem_ref : Misaligned memory references
event:0x07 counters:cpuid um:ld_blocks_partial minimum:100000 name:ld_blocks_partial : Partial loads
event:0x08 counters:cpuid um:dtlb_load_misses minimum:2000000 name:dtlb_load_misses : D-TLB misses
event:0x0d counters:cpuid um:int_misc minimum:2000000 name:int_misc : Instruction decoder events
event:0x0e counters:0,1,2,3 um:uops_issued minimum:2000000 name:uops_issued : Number of Uops issued
event:0x14 counters:cpuid um:arith minimum:2000000 name:arith : Misc ALU events
event:0x17 counters:cpuid um:one minimum:2000000 name:insts_written_to_iq : Number of instructions written to Instruction Queue (IQ) this cycle.
event:0x24 counters:cpuid um:l2_rqsts minimum:200000 name:l2_rqsts : Requests from L2 cache
event:0x27 counters:cpuid um:l2_store_lock_rqsts minimum:200000 name:l2_store_lock_rqsts : L2 cache store lock requests
event:0x28 counters:cpuid um:l2_l1d_wb_rqsts minimum:200000 name:l2_l1d_wb_rqsts : writebacks from L1D to the L2 cache
event:0x48 counters:2 um:l1d_pend_miss minimum:2000000 name:l1d_pend_miss : Cycles with L1D load Misses outstanding.
event:0x49 counters:cpuid um:dtlb_store_misses minimum:2000000 name:dtlb_store_misses : D-TLB store misses
event:0x4c counters:cpuid um:load_hit_pre minimum:100000 name:load_hit_pre : Load dispatches that hit fill buffer
event:0x4e counters:cpuid um:x02 minimum:2000000 name:hw_pre_req : Hardware Prefetch requests
event:0x51 counters:cpuid um:l1d minimum:2000000 name:l1d : L1D cache events
event:0x59 counters:cpuid um:partial_rat_stalls minimum:2000000 name:partial_rat_stalls : Partial RAT stalls
event:0x5b counters:0,1,2,3 um:resource_stalls2 minimum:2000000 name:resource_stalls2 : Misc resource stalls
event:0x5c counters:cpuid um:cpl_cycles minimum:2000000 name:cpl_cycles : Unhalted core cycles in specific rings
event:0x5e counters:0,1,2,3 um:one minimum:2000000 name:rs_events : Events for the reservation station
event:0x60 counters:cpuid um:offcore_requests_outstanding minimum:2000000 name:offcore_requests_outstanding : Offcore outstanding transactions
event:0x63 counters:cpuid um:lock_cycles minimum:2000000 name:lock_cycles : Cycles due to LOCK prefixes.
event:0x79 counters:0,1,2,3 um:idq minimum:2000000 name:idq : Instruction Decode Queue events
event:0x80 counters:cpuid um:x02 minimum:200000 name:icache : Instruction cache events
event:0x85 counters:cpuid um:itlb_misses minimum:2000000 name:itlb_misses : I-TLB misses
event:0x87 counters:cpuid um:ild_stall minimum:2000000 name:ild_stall : Instruction decoding stalls
event:0x88 counters:cpuid um:br_inst_exec minimum:200000 name:br_inst_exec : Branch instructions
event:0x89 counters:cpuid um:br_misp_exec minimum:200000 name:br_misp_exec : Mispredicted branch instructions
event:0x9c counters:0,1,2,3 um:idq_uops_not_delivered minimum:2000000 name:idq_uops_not_delivered : uops not delivered to IDQ.
event:0xa1 counters:cpuid um:uops_dispatched_port minimum:2000000 name:uops_dispatched_port : Count on which ports uops are dispatched.
event:0xa2 counters:cpuid um:resource_stalls minimum:2000000 name:resource_stalls : Core resource stalls
event:0xab counters:cpuid um:dsb2mite_switches minimum:2000000 name:dsb2mite_switches : Number of Decode Stream Buffer (DSB) to MITE switches
event:0xac counters:cpuid um:dsb_fill minimum:2000000 name:dsb_fill : DSB fill events
event:0xae counters:cpuid um:one minimum:10000 name:itlb : ITLB events
event:0xb0 counters:cpuid um:offcore_requests minimum:100000 name:offcore_requests : Requests sent outside the core
event:0xb1 counters:0,1,2,3 um:uops_dispatched minimum:2000000 name:uops_dispatched : uops dispatched
event:0xb2 counters:cpuid um:one minimum:2000000 name:offcore_requests_buffer : Offcore requests buffer events
event:0xb6 counters:cpuid um:one minimum:100000 name:agu_bypass_cancel : AGU bypass cancel
event:0xbd counters:cpuid um:tlb_flush minimum:10000 name:tlb_flush : TLB flushes
event:0xbf counters:cpuid um:l1d_blocks minimum:100000 name:l1d_blocks : L1D cache blocking events
event:0xc0 counters:1 um:one minimum:2000000 name:inst_retired : Instructions retired
event:0xc1 counters:cpuid um:other_assists minimum:100000 name:other_assists : Instructions that needed an assist
event:0xc2 counters:0,1,2,3 um:uops_retired minimum:2000000 name:uops_retired : uops that actually retired.
event:0xc3 counters:cpuid um:machine_clears minimum:100000 name:machine_clears : Number of Machine Clears detected.
event:0xc4 counters:0,1,2,3 um:br_inst_retired minimum:400000 name:br_inst_retired : Counts branch instructions retired
event:0xc5 counters:0,1,2,3 um:br_misp_retired minimum:400000 name:br_misp_retired : Counts mispredicted branch instructions
event:0xca counters:0,1,2,3 um:fp_assist minimum:100000 name:fp_assist : Counts floating point assists
event:0xcb counters:cpuid um:one minimum:100000 name:hw_interrupts : Number of hardware interrupts received by the processor.
event:0xcc counters:cpuid um:x20 minimum:2000000 name:rob_misc_events : Count ROB (Register Reorder Buffer) events.
event:0xcd counters:3 um:x02 minimum:2000000 name:mem_trans_retired : Count memory transactions
event:0xd0 counters:0,1,2,3 um:mem_uops_retired minimum:2000000 name:mem_uops_retired : Count uops with memory accessed retired
event:0xd1 counters:0,1,2,3 um:mem_load_uops_retired minimum:2000000 name:mem_load_uops_retired : Memory load uops.
event:0xd2 counters:0,1,2,3 um:mem_load_uops_llc_hit_retired minimum:100000 name:mem_load_uops_llc_hit_retired : Memory load uops with LLC (Last level cache) hit
event:0xd4 counters:0,1,2,3 um:x02 minimum:10000 name:mem_load_uops_misc_retired : Memory load uops retired
event:0xf0 counters:cpuid um:l2_trans minimum:200000 name:l2_trans : L2 cache accesses
event:0xf1 counters:cpuid um:l2_lines_in minimum:100000 name:l2_lines_in : L2 cache lines in
event:0xf2 counters:cpuid um:l2_lines_out minimum:100000 name:l2_lines_out : L2 cache lines out
event:0xf4 counters:cpuid um:x10 minimum:100000 name:sq_misc : Store queue misc events