| # AMD Family 12 processor performance events |
| # |
| # Copyright OProfile authors |
| # Copyright (c) 2006-2011 Advanced Micro Devices |
| # Contributed by Ray Bryant <raybry at amd.com>, |
| # Jason Yeh <jason.yeh at amd.com> |
| # Suravee Suthikulpanit <suravee.suthikulpanit at amd.com> |
| # Paul Drongowski <paul.drongowski at amd.com> |
| # |
| # Sources: BIOS and Kernel Developer's Guide for AMD Family 12h Processors, |
| # Publication# 41131, Revision 1.13, March 01, 2011 |
| # |
| # Software Optimization Guide for AMD Family 10h and Family 12h Processors, |
| # Publication# 40546, Revision 3.13, February 2011 |
| # (Note: For IBS Derived Performance Events) |
| # |
| # Revision: 1.2 |
| # |
| # ChangeLog: |
| # 1.2: 09 March 2011 |
| # - Update with BKDG Rev.1.13 (preliminary) |
| # |
| # 1.1: 25 January 2010. |
| # - Update minimum value for RETIRED_UOPS |
| # - Update to BKDG Revision 1.12 |
| # |
| # 1.0: 08 December 2009. |
| # - Preliminary version |
| name:zero type:mandatory default:0x00 |
| 0x00 No unit mask |
| name:moesi type:bitmask default:0x1f |
| 0x01 (I)nvalid cache state |
| 0x02 (S)hared cache state |
| 0x04 (E)xclusive cache state |
| 0x08 (O)wned cache state |
| 0x10 (M)odified cache state |
| 0x1f All cache states |
| name:moess type:bitmask default:0x1e |
| 0x01 Refill from northbridge |
| 0x02 Shared-state line from L2 |
| 0x04 Exclusive-state line from L2 |
| 0x08 Owner-state line from L2 |
| 0x10 Modified-state line from L2 |
| 0x1e All cache states except refill from northbridge |
| name:fpu_ops type:bitmask default:0x3f |
| 0x01 Add pipe ops excluding load ops and SSE move ops |
| 0x02 Multiply pipe ops excluding load ops and SSE move ops |
| 0x04 Store pipe ops excluding load ops and SSE move ops |
| 0x08 Add pipe load ops and SSE move ops |
| 0x10 Multiply pipe load ops and SSE move ops |
| 0x20 Store pipe load ops and SSE move ops |
| 0x3f All ops |
| name:segregload type:bitmask default:0x7f |
| 0x01 ES register |
| 0x02 CS register |
| 0x04 SS register |
| 0x08 DS register |
| 0x10 FS register |
| 0x20 GS register |
| 0x40 HS register |
| name:fpu_instr type:bitmask default:0x07 |
| 0x01 x87 instructions |
| 0x02 MMX & 3DNow instructions |
| 0x04 SSE instructions (SSE, SSE2, SSE3, and SSE4A) |
| name:fpu_exceptions type:bitmask default:0x0f |
| 0x01 x87 reclass microfaults |
| 0x02 SSE retype microfaults |
| 0x04 SSE reclass microfaults |
| 0x08 SSE and x87 microtraps |
| name:page_access type:bitmask default:0xff |
| 0x01 DCT0 Page hit |
| 0x02 DCT0 Page miss |
| 0x04 DCT0 Page conflict |
| 0x08 DCT1 Page hit |
| 0x10 DCT1 Page miss |
| 0x20 DCT1 Page Conflict |
| 0x40 Write request |
| 0x80 Read request |
| name:mem_page_overflow type:bitmask default:0x03 |
| 0x01 DCT0 Page Table Overflow |
| 0x02 DCT0 Number of stale table entry hits |
| 0x04 DCT0 Page table idle cycle limit incremented |
| 0x08 DCT0 Page table idle cycle limit decremented |
| 0x10 DCT0 Page table is closed due to row inactivity |
| name:turnaround type:bitmask default:0x1b |
| 0x01 DCT0 read-to-write turnaround |
| 0x02 DCT0 write-to-read turnaround |
| 0x08 DCT1 read-to-write turnaround |
| 0x10 DCT1 write-to-read turnaround |
| name:rbd type:bitmask default:0x0c |
| 0x04 D18F2x[1,0]94[DcqBypassMax] counter reached |
| 0x08 Bank is closed due to bank conflict with an outstanding request in the RBD queue |
| name:slot_missed type:bitmask default:0xf0 |
| 0x10 DCT0 RBD |
| 0x20 DCT1 RBD |
| 0x40 DCT0 Prefetch |
| 0x80 DCT1 Prefetch |
| name:sizecmds type:bitmask default:0x3f |
| 0x01 Non-posted write byte (1-32 bytes) |
| 0x02 Non-posted write DWORD (1-16 DWORDs) |
| 0x04 Posted write byte (1-32 bytes) |
| 0x08 Posted write DWORD (1-16 DWORDs) |
| 0x10 Read byte (4 bytes) |
| 0x20 Read DWORD (1-16 DWORDs) |
| name:probe type:bitmask default:0xbf |
| 0x01 Probe miss |
| 0x02 Probe hit clean |
| 0x04 Probe hit dirty without memory cancel |
| 0x08 Probe hit dirty with memory cancel |
| 0x10 Upstream high priority reads |
| 0x20 Upstream low priority reads |
| 0x80 Upstream low priority writes |
| name:l2_internal type:bitmask default:0x3f |
| 0x01 IC fill |
| 0x02 DC fill |
| 0x04 TLB fill (page table walks) |
| 0x08 Tag snoop request |
| 0x10 Canceled request |
| 0x20 Hardware prefetch from data cache |
| name:l2_req_miss type:bitmask default:0x0f |
| 0x01 IC fill |
| 0x02 DC fill (includes possible replays) |
| 0x04 TLB page table walk |
| 0x08 Hardware prefetch from data cache |
| name:l2_fill type:bitmask default:0x03 |
| 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches) |
| 0x02 L2 writebacks to system |
| name:gart type:bitmask default:0x70 |
| 0x10 DEV hit |
| 0x20 DEV miss |
| 0x40 DEV error |
| name:cpiorequests type:bitmask default:0x08 |
| 0x01 IO to IO |
| 0x02 IO to Mem |
| 0x04 CPU to IO |
| 0x08 CPU to Mem |
| name:cacheblock type:bitmask default:0x3d |
| 0x01 Victim Block (Writeback) |
| 0x04 Read Block (Dcache load miss refill) |
| 0x08 Read Block Shared (Icache refill) |
| 0x10 Read Block Modified (Dcache store miss refill) |
| 0x20 Change-to-Dirty (first store to clean block already in cache) |
| name:dataprefetch type:bitmask default:0x03 |
| 0x01 Cancelled prefetches |
| 0x02 Prefetch attempts |
| name:memreqtype type:bitmask default:0x87 |
| 0x01 Requests to non-cacheable (UC) memory |
| 0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory |
| 0x04 Requests to cache-disabled (CD) memory |
| 0x80 Streaming store (SS) requests |
| name:systemreadresponse type:bitmask default:0x1f |
| 0x01 Exclusive |
| 0x02 Modified |
| 0x04 Shared |
| 0x08 Owned |
| 0x10 Data Error |
| name:l1_dtlb_miss_l2_hit type:bitmask default:0x07 |
| 0x01 L2 4K TLB hit |
| 0x02 L2 2M TLB hit |
| 0x04 L2 1G TLB hit |
| name:l1_l2_dtlb_miss type:bitmask default:0x07 |
| 0x01 4K TLB reload |
| 0x02 2M TLB reload |
| 0x04 1G TLB reload |
| name:prefetch type:bitmask default:0x07 |
| 0x01 Load (Prefetch, PrefetchT0/T1/T2) |
| 0x02 Store (PrefetchW) |
| 0x04 NTA (PrefetchNTA) |
| name:locked_instruction_dcache_miss type:bitmask default:0x02 |
| 0x02 Data cache misses by locked instructions |
| name:octword_transfer type:bitmask default:0x01 |
| 0x01 Octword write transfer |
| name:thermal_status type:bitmask default:0xe5 |
| 0x01 MEMHOT_L assertions |
| 0x04 Number of times the HTC transitions from inactive to active |
| 0x20 Number of clocks HTC P-state is inactive |
| 0x40 Number of clocks HTC P-state is active |
| 0x80 PROCHOT_L asserted by external source and caused a P-state change |
| name:mem_control_request type:bitmask default:0x78 |
| 0x01 Write requests |
| 0x02 Read Requests |
| 0x04 Prefetch Requests |
| 0x08 32 Bytes Sized Writes |
| 0x10 64 Bytes Sized Writes |
| 0x20 32 Bytes Sized Reads |
| 0x40 64 Byte Sized Reads |
| 0x80 Read requests while writes pending in DCQ |
| name:lock_ops type:bitmask default:0x0f |
| 0x01 Number of locked instructions executed |
| 0x02 Cycles in speculative phase |
| 0x04 Cycles in non-speculative phase (including cache miss penalty) |
| 0x08 Cache miss penalty in cycles |
| name:sse_ops type:bitmask default:0x7f |
| 0x01 Single Precision add/subtract ops |
| 0x02 Single precision multiply ops |
| 0x04 Single precision divide/square root ops |
| 0x08 Double precision add/subtract ops |
| 0x10 Double precision multiply ops |
| 0x20 Double precision divide/square root ops |
| 0x40 OP type: 0=uops 1=FLOPS |
| name:move_ops type:bitmask default:0x0f |
| 0x01 Merging low quadword move uops |
| 0x02 Merging high quadword move uops |
| 0x04 All other merging move uops |
| 0x08 All other move uops |
| name:serial_ops type:bitmask default:0x0f |
| 0x01 SSE bottom-executing uops retired |
| 0x02 SSE bottom-serializing uops retired |
| 0x04 x87 bottom-executing uops retired |
| 0x08 x87 bottom-serializing uops retired |
| name:serial_ops_sched type:bitmask default:0x03 |
| 0x01 Number of cycles a bottom-execute uops in FP scheduler |
| 0x02 Number of cycles a bottom-serializing uops in FP scheduler |
| name:store_to_load type:bitmask default:0x07 |
| 0x01 Address mismatches (starting byte not the same) |
| 0x02 Store is smaller than load |
| 0x04 Misaligned |
| name:moesi_gh type:bitmask default:0x1f |
| 0x01 (I)nvalid cache state |
| 0x02 (S)hared cache state |
| 0x04 (E)xclusive cache state |
| 0x08 (O)wned cache state |
| 0x10 (M)odified cache state |
| 0x20 Cache line evicted brought into the cache by PrefetchNTA |
| 0x40 Cache line evicted not brought into the cache by PrefetchNTA |
| name:l1_dtlb_hit type:bitmask default:0x07 |
| 0x01 L1 4K TLB hit |
| 0x02 L1 2M TLB hit |
| 0x04 L1 1G TLB hit |
| name:soft_prefetch type:bitmask default:0x09 |
| 0x01 Software prefetch hit in L1 |
| 0x08 Software prefetch hit in L2 |
| name:l1_l2_itlb_miss type:bitmask default:0x03 |
| 0x01 Instruction fetches to a 4K page |
| 0x02 Instruction fetches to a 2M page |
| name:icache_invalidated type:bitmask default:0x03 |
| 0x01 Invalidating probe that did not hit any in-flight instructions |
| 0x02 Invalidating probe that hit one or more in-flight instructions |
| 0x04 SMC that did not hit any in-flight instructions |
| 0x08 SMC that hit one or more in-flight instructions |
| name:page_size_mismatches type:bitmask default:0x07 |
| 0x01 Guest page size is larger than the host page size |
| 0x02 MTRR mismatch |
| 0x04 Host page size is larger than the guest page size |
| name:retired_x87_fp type:bitmask default:0x07 |
| 0x01 Add/subtract ops |
| 0x02 Multiply ops |
| 0x04 Divide ops |
| name:dct1_page_table_events type:bitmask default:0x1f |
| 0x01 DCT1 Page Table Overflow |
| 0x02 DCT1 Number of stale table entry hits |
| 0x04 DCT1 Page table idle cycle limit incremented |
| 0x08 DCT1 Page table idle cycle limit decremented |
| 0x10 DCT1 Page table is closed due to row inactivity |
| name:sideband_signals type:bitmask default:0x1e |
| 0x02 STOPGRANT |
| 0x04 SHUTDOWN |
| 0x08 WBINVD |
| 0x10 INVD |
| name:interrupt_events type:bitmask default:0xff |
| 0x01 Fixed and LPA |
| 0x02 LPA |
| 0x04 SMI |
| 0x08 NMI |
| 0x10 INIT |
| 0x20 STARTUP |
| 0x40 INT |
| 0x80 EOI |
| name:ibs_op type:bitmask default:0x01 |
| 0x00 Using IBS OP cycle count mode |
| 0x01 Using IBS OP dispatch count mode |
| 0x02 Enable IBS OP Memory Access Log |
| 0x04 Enable IBS OP Branch Target Address Log |
