Qualcomm adreno/snapdragon MDP5 display controller

Description:

This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.

MDSS:
Required properties:
- compatible:
  * "qcom,mdss" - MDSS
- reg: Physical base address and length of the controller's registers.
- reg-names: The names of register regions. The following regions are required:
  * "mdss_phys"
  * "vbif_phys"
- interrupts: The interrupt signal from MDSS.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  source, should be 1.
- power-domains: a power domain consumer specifier according to
  Documentation/devicetree/bindings/power/power_domain.txt
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
  * "iface_clk"
  * "bus_clk"
  * "vsync_clk"
- #address-cells: number of address cells for the MDSS children. Should be 1.
- #size-cells: Should be 1.
- ranges: parent bus address space is the same as the child bus address space.

Optional properties:
- clock-names: the following clocks are optional:
  * "lut_clk"

MDP5:
Required properties:
- compatible:
  * "qcom,mdp5" - MDP5
- reg: Physical base address and length of the controller's registers.
- reg-names: The names of register regions. The following regions are required:
  * "mdp_phys"
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
- interrupt-parent: phandle to the MDSS block
  through MDP block
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
-   * "bus_clk"
-   * "iface_clk"
-   * "core_clk"
-   * "vsync_clk"
- ports: contains the list of output ports from MDP. These connect to interfaces
  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
  special case since it is a part of the MDP block itself).

  Each output port contains an endpoint that describes how it is connected to an
  external interface. These are described by the standard properties documented
  here:
	Documentation/devicetree/bindings/graph.txt
	Documentation/devicetree/bindings/media/video-interfaces.txt

  The availability of output ports can vary across SoC revisions:

  For MSM8974 and APQ8084:
	 Port 0 -> MDP_INTF0 (eDP)
	 Port 1 -> MDP_INTF1 (DSI1)
	 Port 2 -> MDP_INTF2 (DSI2)
	 Port 3 -> MDP_INTF3 (HDMI)

  For MSM8916:
	 Port 0 -> MDP_INTF1 (DSI1)

  For MSM8994 and MSM8996:
	 Port 0 -> MDP_INTF1 (DSI1)
	 Port 1 -> MDP_INTF2 (DSI2)
	 Port 2 -> MDP_INTF3 (HDMI)

Optional properties:
- clock-names: the following clocks are optional:
  * "lut_clk"

Example:

/ {
	...

	mdss: mdss@1a00000 {
		compatible = "qcom,mdss";
		reg = <0x1a00000 0x1000>,
		      <0x1ac8000 0x3000>;
		reg-names = "mdss_phys", "vbif_phys";

		power-domains = <&gcc MDSS_GDSC>;

		clocks = <&gcc GCC_MDSS_AHB_CLK>,
			 <&gcc GCC_MDSS_AXI_CLK>,
			 <&gcc GCC_MDSS_VSYNC_CLK>;
		clock-names = "iface_clk",
			      "bus_clk",
			      "vsync_clk"

		interrupts = <0 72 0>;

		interrupt-controller;
		#interrupt-cells = <1>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mdp: mdp@1a01000 {
			compatible = "qcom,mdp5";
			reg = <0x1a01000 0x90000>;
			reg-names = "mdp_phys";

			interrupt-parent = <&mdss>;
			interrupts = <0 0>;

			clocks = <&gcc GCC_MDSS_AHB_CLK>,
				 <&gcc GCC_MDSS_AXI_CLK>,
				 <&gcc GCC_MDSS_MDP_CLK>,
				 <&gcc GCC_MDSS_VSYNC_CLK>;
			clock-names = "iface_clk",
				      "bus_clk",
				      "core_clk",
				      "vsync_clk";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					mdp5_intf1_out: endpoint {
						remote-endpoint = <&dsi0_in>;
					};
				};
			};
		};

		dsi0: dsi@1a98000 {
			...
			ports {
				...
				port@0 {
					reg = <0>;
					dsi0_in: endpoint {
						remote-endpoint = <&mdp5_intf1_out>;
					};
				};
				...
			};
			...
		};

		dsi_phy0: dsi-phy@1a98300 {
			...
		};
	};
};