/*
 *    Copyright (c) 2010 Nest Labs, Inc.
 *
 *    See file CREDITS for list of people who contributed to this
 *    project.
 *
 *    This program is free software; you can redistribute it and/or
 *    modify it under the terms of the GNU General Public License as
 *    published by the Free Software Foundation; either version 2 of
 *    the License, or (at your option) any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public
 *    License along with this program; if not, write to the Free
 *    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 *    MA 02111-1307 USA
 *
 *    Description:
 *      This file defines register and register field constants and
 *      macros for the Texas Instruments Open Multimedia Application
 *      Platform (OMAP) 3 General Purpose Memory Controller (GPMC).
 */

#ifndef _OMAP3_GPMC_H
#define _OMAP3_GPMC_H

#include <asm/arch/bits.h>

/*
 * GPMC Interconnect Configuration
 */
#define GPMC_SYSCONFIG_AUTOIDLE_DISABLE					ARM_REG_VAL(0, 0)
#define GPMC_SYSCONFIG_AUTOIDLE_ENABLE					ARM_REG_VAL(0, 1)
#define GPMC_SYSCONFIG_SOFTRESET						ARM_REG_VAL(1, 1)
#define GPMC_SYSCONFIG_IDLEMODE_FORCE					ARM_REG_VAL(3, 0)
#define GPMC_SYSCONFIG_IDLEMODE_NONE					ARM_REG_VAL(3, 1)
#define GPMC_SYSCONFIG_IDLEMODE_SMART					ARM_REG_VAL(3, 2)

#define GPMC_SYSCONFIG_IRQENABLE_FIFOEVENT_DISABLE		ARM_REG_VAL(0, 0)
#define GPMC_SYSCONFIG_IRQENABLE_FIFOEVENT_ENABLE		ARM_REG_VAL(0, 1)

#define GPMC_SYSCONFIG_IRQENABLE_TERMINALCOUNT_DISABLE	ARM_REG_VAL(0, 0)
#define GPMC_SYSCONFIG_IRQENABLE_TERMINALCOUNT_ENABLE	ARM_REG_VAL(0, 1)

#define GPMC_SYSCONFIG_IRQENABLE_TERMINALCOUNT_DISABLE	ARM_REG_VAL(0, 0)
#define GPMC_SYSCONFIG_IRQENABLE_TERMINALCOUNT_ENABLE	ARM_REG_VAL(0, 1)

/*
 * GPMC Interrupt Control
 */

#define GPMC_IRQENABLE_WAIT3EDGEDETECTION_DISABLE		ARM_REG_VAL(11, 0)
#define GPMC_IRQENABLE_WAIT3EDGEDETECTION_ENABLE		ARM_REG_VAL(11, 1)

#define GPMC_IRQENABLE_WAIT2EDGEDETECTION_DISABLE		ARM_REG_VAL(10, 0)
#define GPMC_IRQENABLE_WAIT2EDGEDETECTION_ENABLE		ARM_REG_VAL(10, 1)

#define GPMC_IRQENABLE_WAIT1EDGEDETECTION_DISABLE		ARM_REG_VAL(9, 0)
#define GPMC_IRQENABLE_WAIT1EDGEDETECTION_ENABLE		ARM_REG_VAL(9, 1)

#define GPMC_IRQENABLE_WAIT0EDGEDETECTION_DISABLE		ARM_REG_VAL(8, 0)
#define GPMC_IRQENABLE_WAIT0EDGEDETECTION_ENABLE		ARM_REG_VAL(8, 1)

#define GPMC_IRQENABLE_TERMINALCOUNTEVENT_DISABLE		ARM_REG_VAL(1, 0)
#define GPMC_IRQENABLE_TERMINALCOUNTEVENT_ENABLE		ARM_REG_VAL(1, 1)

#define GPMC_IRQENABLE_FIFOEVENTENABLE_DISABLE			ARM_REG_VAL(0, 0)
#define GPMC_IRQENABLE_FIFOEVENTENABLE_ENABLE			ARM_REG_VAL(0, 0)

#define GPMC_IRQENABLE_ALL_DISABLE					\
	(GPMC_IRQENABLE_WAIT3EDGEDETECTION_DISABLE |	\
	 GPMC_IRQENABLE_WAIT2EDGEDETECTION_DISABLE |	\
	 GPMC_IRQENABLE_WAIT1EDGEDETECTION_DISABLE |	\
	 GPMC_IRQENABLE_WAIT0EDGEDETECTION_DISABLE |	\
	 GPMC_IRQENABLE_TERMINALCOUNTEVENT_DISABLE |	\
	 GPMC_IRQENABLE_FIFOEVENTENABLE_DISABLE)

#define GPMC_IRQENABLE_ALL_ENABLE					\
	(GPMC_IRQENABLE_WAIT3EDGEDETECTION_ENABLE |		\
	 GPMC_IRQENABLE_WAIT2EDGEDETECTION_ENABLE |		\
	 GPMC_IRQENABLE_WAIT1EDGEDETECTION_ENABLE |		\
	 GPMC_IRQENABLE_WAIT0EDGEDETECTION_ENABLE |		\
	 GPMC_IRQENABLE_TERMINALCOUNTEVENT_ENABLE |		\
	 GPMC_IRQENABLE_FIFOEVENTENABLE_ENABLE)

/*
 * GPMC Timeout Counter Control
 */

#define GPMC_TIMEOUTSTARTVALUE_MASK						ARM_REG_VAL(4, 0x1FF)
#define GPMC_TIMEOUTSTARTVALUE_ENCODE(v)				ARM_REG_VAL_ENCODE(4, GPMC_TIMEOUTSTARTVALUE_MASK, v)
#define GPMC_TIMEOUTSTARTVALUE_DECODE(v)				ARM_REG_VAL_DECODE(4, GPMC_TIMEOUTSTARTVALUE_MASK, v)

#define GPMC_TIMEOUTENABLE_OFF							ARM_REG_VAL(0, 0)
#define GPMC_TIMEOUTENABLE_ON							ARM_REG_VAL(0, 1)

/*
 * GPMC Global Configuration
 */
#define GPMC_WAIT3PINPOLARITY_ACTIVE_LOW				ARM_REG_VAL(11, 0)
#define GPMC_WAIT3PINPOLARITY_ACTIVE_HIGH				ARM_REG_VAL(11, 1)

#define GPMC_WAIT2PINPOLARITY_ACTIVE_LOW				ARM_REG_VAL(10, 0)
#define GPMC_WAIT2PINPOLARITY_ACTIVE_HIGH				ARM_REG_VAL(10, 1)

#define GPMC_WAIT1PINPOLARITY_ACTIVE_LOW				ARM_REG_VAL(9, 0)
#define GPMC_WAIT1PINPOLARITY_ACTIVE_HIGH				ARM_REG_VAL(9, 1)

#define GPMC_WAIT0PINPOLARITY_ACTIVE_LOW				ARM_REG_VAL(8, 0)
#define GPMC_WAIT0PINPOLARITY_ACTIVE_HIGH				ARM_REG_VAL(8, 1)

#define GPMC_WRITEPROTECT_LOW							ARM_REG_VAL(4, 0)
#define GPMC_WRITEPROTECT_HIGH							ARM_REG_VAL(4, 1)

#define GPMC_LIMITEDADDRESS_DISABLED					ARM_REG_VAL(1, 0)
#define GPMC_LIMITEDADDRESS_ENABLED						ARM_REG_VAL(1, 1)

#define GPMC_NANDFORCEPOSTEDWRITE_DISABLED				ARM_REG_VAL(0, 0)
#define GPMC_NANDFORCEPOSTEDWRITE_ENABLED				ARM_REG_VAL(0, 1)

#define GPMC_CONFIG7_MASKADDRESS_MASK					ARM_REG_VAL(8, 0xF)
#define GPMC_CONFIG7_MASKADDRESS_ENCODE(v)				ARM_REG_VAL_ENCODE(8, GPMC_CONFIG7_MASKADDRESS_MASK, v)
#define GPMC_CONFIG7_MASKADDRESS_DECODE(v)				ARM_REG_VAL_DECODE(8, GPMC_CONFIG7_MASKADDRESS_MASK, v)
#define GPMC_CONFIG7_MASKADDRESS_256_MB					  0x0
#define GPMC_CONFIG7_MASKADDRESS_128_MB					  0x8
#define GPMC_CONFIG7_MASKADDRESS_64_MB					  0xC
#define GPMC_CONFIG7_MASKADDRESS_32_MB					  0xE
#define GPMC_CONFIG7_MASKADDRESS_16_MB					  0xF

#define GPMC_CONFIG7_CSVALID_DISABLED					ARM_REG_VAL(6, 0)
#define GPMC_CONFIG7_CSVALID_ENABLED					ARM_REG_VAL(6, 1)

#define GPMC_CONFIG7_BASEADDRESS_MASK					ARM_REG_VAL(0, 0x3F)
#define GPMC_CONFIG7_BASEADDRESS_ENCODE(v)				ARM_REG_VAL_ENCODE(0, GPMC_CONFIG7_BASEADDRESS_MASK, ((v) >> 24))
#define GPMC_CONFIG7_BASEADDRESS_DECODE(v)				(ARM_REG_VAL_DECODE(0, GPMC_CONFIG7_BASEADDRESS_MASK, v) << 24)


#endif /* _OMAP3_GPMC_H */