/*
 *    Copyright (c) 2010 Nest Labs, Inc.
 *
 *    See file CREDITS for list of people who contributed to this
 *    project.
 *
 *    This program is free software; you can redistribute it and/or
 *    modify it under the terms of the GNU General Public License as
 *    published by the Free Software Foundation; either version 2 of
 *    the License, or (at your option) any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public
 *    License along with this program; if not, write to the Free
 *    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 *    MA 02111-1307 USA
 *
 *    Description:
 *      This file defines register and register field constants and
 *      macros for the Texas Instruments Open Multimedia Application
 *      Platform (OMAP) 3 SDRAM Controller (SDRC).
 */

#ifndef _OMAP3_SDRC_H
#define _OMAP3_SDRC_H

#include <asm/arch/bits.h>

/*
 * SDRAM Controller Revision
 */
#define SDRC_REVISION_REV_MASK				ARM_REG_VAL(0, 0xFF)
#define SDRC_REVISION_REV_MAJOR_MASK		ARM_REG_VAL(4, 0xF)
#define SDRC_REVISION_REV_MINOR_MASK		ARM_REG_VAL(0, 0xF)
#define SDRC_REVISION_REV_MAJOR_DECODE(x)	ARM_REG_VAL_DECODE(4, SDRC_REVISION_REV_MAJOR_MASK, x)
#define SDRC_REVISION_REV_MINOR_DECODE(x)	ARM_REG_VAL_DECODE(0, SDRC_REVISION_REV_MINOR_MASK), x)

/*
 * SDRAM Controller System Configuration
 */
#define SDRC_SYSCONFIG_NOMEMORYMRS_DISABLE	ARM_REG_VAL(8, 0)
#define SDRC_SYSCONFIG_NOMEMORYMRS_ENABLE	ARM_REG_VAL(8, 1)
#define SDRC_SYSCONFIG_IDLEMODE_SMART		ARM_REG_VAL(3, 0x2)
#define SDRC_SYSCONFIG_SOFTRESET_CLEAR		ARM_REG_VAL(1, 0x0)
#define SDRC_SYSCONFIG_SOFTRESET_SET		ARM_REG_VAL(1, 0x1)

/*
 * SDRAM Controller System Status
 */
#define SDRC_SYSSTATUS_RESETDONE			ARM_REG_VAL(0, 1)

/*
 * SDRAM Controller Chip Select Configuration
 */

/*
 * SDRAM Controller Multiplexing
 */
#define SDRC_SHARING_LOCK_OFF				ARM_REG_VAL(30, 0)
#define SDRC_SHARING_LOCK_ON				ARM_REG_VAL(30, 1)
#define SDRC_SHARING_CS1MUXCFG_MASK			ARM_REG_VAL(12, 0x7)
#define SDRC_SHARING_CS1MUXCFG_ENCODE(v)	ARM_REG_VAL_ENCODE(12, SDRC_SHARING_CS1MUXCFG_MASK, v)
#define SDRC_SHARING_CS1MUXCFG_DECODE(v)	ARM_REG_VAL_DECODE(12, SDRC_SHARING_CS1MUXCFG_MASK, v)
#define SDRC_SHARING_CS1MUXCFG_32_BIT_31_0		0x0
#define SDRC_SHARING_CS1MUXCFG_16_BIT_31_16		0x2
#define SDRC_SHARING_CS1MUXCFG_16_BIT_16_0		0x3
#define SDRC_SHARING_CS0MUXCFG_MASK			ARM_REG_VAL(9, 0x7)
#define SDRC_SHARING_CS0MUXCFG_ENCODE(v)	ARM_REG_VAL_ENCODE(9, SDRC_SHARING_CS0MUXCFG_MASK, v)
#define SDRC_SHARING_CS0MUXCFG_DECODE(v)	ARM_REG_VAL_DECODE(9, SDRC_SHARING_CS0MUXCFG_MASK), v)
#define SDRC_SHARING_CS0MUXCFG_32_BIT_31_0		0x0
#define SDRC_SHARING_CS0MUXCFG_16_BIT_31_16		0x2
#define SDRC_SHARING_CS0MUXCFG_16_BIT_16_0		0x3
#define SDRC_SHARING_SDRCTRISTATE_ON		ARM_REG_VAL(8, 0)
#define SDRC_SHARING_SDRCTRISTATE_OFF		ARM_REG_VAL(8, 1)

/*
 * SDRAM Controller Error Address
 */

/*
 * SDRAM Controller Error Type
 */

/*
 * SDRAM Controller DDR A Fine Tuning Control
 */
#define SDRC_DLLA_CTRL_FIXED_DELAY_MASK		ARM_REG_VAL(24, 0xFF)
#define SDRC_DLLA_CTRL_FIXED_DELAY_ENCODE(v)	ARM_REG_VAL_ENCODE(24, SDRC_DLLA_CTRL_FIXED_DELAY_MASK, v)
#define SDRC_DLLA_CTRL_FIXED_DELAY_DECODE(v)	ARM_REG_VAL_DECODE(24, SDRC_DLLA_CTRL_FIXED_DELAY_MASK, v)

#define SDRC_DLLA_CTRL_INIT_LAT_MASK		ARM_REG_VAL(16, 0xFF)
#define SDRC_DLLA_CTRL_INIT_LAT_ENCODE(v)	ARM_REG_VAL_ENCODE(16, SDRC_DLLA_CTRL_INIT_LAT_MASK, v / 2)
#define SDRC_DLLA_CTRL_INIT_LAT_DECODE(v)	(ARM_REG_VAL_DECODE(16, SDRC_DLLA_CTRL_INIT_LAT_MASK, v) * 2)

#define SDRC_DLLA_CTRL_MODE_ON_IDLE_MASK	ARM_REG_VAL(5, 0x3)
#define SDRC_DLLA_CTRL_MODE_ON_IDLE_ENCODE(v)	ARM_REG_VAL_ENCODE(5, SDRC_DLLA_CTRL_MODE_ON_IDLE_MASK, v)
#define SDRC_DLLA_CTRL_MODE_ON_IDLE_DECODE(v)	ARM_REG_VAL_DECODE(5, SDRC_DLLA_CTRL_MODE_ON_IDLE_MASK, v)
#define SDRC_DLLA_CTRL_MODE_ON_IDLE_PWD			0x0
#define SDRC_DLLA_CTRL_MODE_ON_IDLE_IDLE		0x1
#define SDRC_DLLA_CTRL_MODE_ON_IDLE_IGNORE		0x2

#define SDRC_DLLA_CTRL_IDLE_DISABLE			ARM_REG_VAL(4, 0)
#define SDRC_DLLA_CTRL_IDLE_ENABLE			ARM_REG_VAL(4, 1)

#define SDRC_DLLA_CTRL_DLL_DISABLE			ARM_REG_VAL(3, 0)
#define SDRC_DLLA_CTRL_DLL_ENABLE			ARM_REG_VAL(3, 1)

#define SDRC_DLLA_CTRL_LOCK_TRACKINGDELAY	ARM_REG_VAL(2, 0)
#define SDRC_DLLA_CTRL_LOCK_FIXEDDELAY		ARM_REG_VAL(2, 1)

/*
 * SDRAM Controller DDR A Fine Tuning Status
 */

/*
 * SDRAM Controller Power Management Policy
 */

#define SDRC_POWER_REG_WAKEUP_DELAYED		ARM_REG_VAL(26, 0)
#define SDRC_POWER_REG_WAKEUP_IMMED			ARM_REG_VAL(26, 1)

#define SDRC_POWER_REG_AUTOCOUNT_MASK		ARM_REG_VAL(8, 0xFFFF)
#define SDRC_POWER_REG_AUTOCOUNT_ENCODE(v)	ARM_REG_VAL_ENCODE(8, SDRC_POWER_REG_AUTOCOUNT_MASK, v)
#define SDRC_POWER_REG_AUTOCOUNT_DECODE(v)	ARM_REG_VAL_DECODE(8, SDRC_POWER_REG_AUTOCOUNT_MASK), v)

#define SDRC_POWER_REG_SRFR_ON_RST_DISABLE	ARM_REG_VAL(7, 0)
#define SDRC_POWER_REG_SRFR_ON_RST_ENABLE	ARM_REG_VAL(7, 1)

#define SDRC_POWER_REG_SRFR_ON_IDLE_DISABLE	ARM_REG_VAL(6, 0)
#define SDRC_POWER_REG_SRFR_ON_IDLE_ENABLE	ARM_REG_VAL(6, 1)

#define SDRC_POWER_REG_CLKCTRL_MASK			ARM_REG_VAL(4, 0x3)
#define SDRC_POWER_REG_CLKCTRL_ENCODE(v)	ARM_REG_VAL_ENCODE(4, SDRC_POWER_REG_CLKCTRL_MASK, v)
#define SDRC_POWER_REG_CLKCTRL_DECODE(v)	ARM_REG_VAL_DECODE(4, SDRC_POWER_REG_CLKCTRL_MASK), v)
#define SDRC_POWER_REG_CLKCTRL_NONE				0x0
#define SDRC_POWER_REG_CLKCTRL_SELF_GATE		0x1
#define SDRC_POWER_REG_CLKCTRL_SELF_REFRESH		0x2

#define SDRC_POWER_REG_EXTCLKDIS_ON			ARM_REG_VAL(3, 1)
#define SDRC_POWER_REG_EXTCLKDIS_ON			ARM_REG_VAL(3, 1)

#define SDRC_POWER_REG_PWD_DISABLE			ARM_REG_VAL(2, 0)
#define SDRC_POWER_REG_PWD_ENABLE			ARM_REG_VAL(2, 1)

#define SDRC_POWER_REG_PAGEPOLICY_HPHB		ARM_REG_VAL(0, 1)

/*
 * SDRAM Controller Memory Configuration
 */
#define SDRC_MCFG_LOCKSTATUS_RW				ARM_REG_VAL(30, 0)
#define SDRC_MCFG_LOCKSTATUS_RO				ARM_REG_VAL(30, 1)

#define SDRC_MCFG_RASWIDTH_MASK				ARM_REG_VAL(24, 0x7)
#define SDRC_MCFG_RASWIDTH_ENCODE(v)		ARM_REG_VAL_ENCODE(24, SDRC_MCFG_RASWIDTH_MASK, v)
#define SDRC_MCFG_RASWIDTH_DECODE(v)		ARM_REG_VAL_DECODE(24, SDRC_MCFG_RASWIDTH_MASK), v)
#define SDRC_MCFG_RASWIDTH_11_BITS				0x0
#define SDRC_MCFG_RASWIDTH_12_BITS				0x1
#define SDRC_MCFG_RASWIDTH_13_BITS				0x2
#define SDRC_MCFG_RASWIDTH_14_BITS				0x3
#define SDRC_MCFG_RASWIDTH_15_BITS				0x4
#define SDRC_MCFG_RASWIDTH_16_BITS				0x5
#define SDRC_MCFG_RASWIDTH_17_BITS				0x6
#define SDRC_MCFG_RASWIDTH_18_BITS				0x7

#define SDRC_MCFG_CASWIDTH_MASK				ARM_REG_VAL(20, 0x7)
#define SDRC_MCFG_CASWIDTH_ENCODE(v)		ARM_REG_VAL_ENCODE(20, SDRC_MCFG_CASWIDTH_MASK, v)
#define SDRC_MCFG_CASWIDTH_DECODE(v)		ARM_REG_VAL_DECODE(20, SDRC_MCFG_CASWIDTH_MASK), v)
#define SDRC_MCFG_CASWIDTH_5_BITS				0x0
#define SDRC_MCFG_CASWIDTH_6_BITS				0x1
#define SDRC_MCFG_CASWIDTH_7_BITS				0x2
#define SDRC_MCFG_CASWIDTH_8_BITS				0x3
#define SDRC_MCFG_CASWIDTH_9_BITS				0x4
#define SDRC_MCFG_CASWIDTH_10_BITS				0x5
#define SDRC_MCFG_CASWIDTH_11_BITS				0x6
#define SDRC_MCFG_CASWIDTH_12_BITS				0x7

#define SDRC_MCFG_ADDRMUX_MASK				ARM_REG_VAL(20, 0x1F)
#define SDRC_MCFG_ADDRMUX_ENCODE(v)			ARM_REG_VAL_ENCODE(20, SDRC_MCFG_ADDRMUX_MASK, v)
#define SDRC_MCFG_ADDRMUX_DECODE(v)			ARM_REG_VAL_DECODE(20, SDRC_MCFG_ADDRMUX_MASK, v)
#define SDRC_MCFG_ADDRMUX_SCHEME_1   			0x0
#define SDRC_MCFG_ADDRMUX_SCHEME_2  			0x1
#define SDRC_MCFG_ADDRMUX_SCHEME_3  			0x2
#define SDRC_MCFG_ADDRMUX_SCHEME_4  			0x3
#define SDRC_MCFG_ADDRMUX_SCHEME_5  			0x4
#define SDRC_MCFG_ADDRMUX_SCHEME_6				0x5
#define SDRC_MCFG_ADDRMUX_SCHEME_7				0x6
#define SDRC_MCFG_ADDRMUX_SCHEME_8				0x7
#define SDRC_MCFG_ADDRMUX_SCHEME_9   			0x8
#define SDRC_MCFG_ADDRMUX_SCHEME_10  			0x9
#define SDRC_MCFG_ADDRMUX_SCHEME_11  			0xA
#define SDRC_MCFG_ADDRMUX_SCHEME_12 			0xB
#define SDRC_MCFG_ADDRMUX_SCHEME_13  			0xC
#define SDRC_MCFG_ADDRMUX_SCHEME_14				0xD
#define SDRC_MCFG_ADDRMUX_SCHEME_15				0xE
#define SDRC_MCFG_ADDRMUX_SCHEME_16				0xF
#define SDRC_MCFG_ADDRMUX_SCHEME_23  			0x16
#define SDRC_MCFG_ADDRMUX_SCHEME_24  			0x17
#define SDRC_MCFG_ADDRMUX_SCHEME_25 			0x18
#define SDRC_MCFG_ADDRMUX_SCHEME_26  			0x19
#define SDRC_MCFG_ADDRMUX_SCHEME_27				0x1A
#define SDRC_MCFG_ADDRMUX_SCHEME_28				0x1B
#define SDRC_MCFG_ADDRMUX_SCHEME_29				0x1C

#define SDRC_MCFG_ADDRMUXLEGACY_FIXED		ARM_REG_VAL(19, 0)
#define SDRC_MCFG_ADDRMUXLEGACY_FLEXIBLE	ARM_REG_VAL(19, 1)

#define SDRC_MCFG_RAMSIZE_MASK				ARM_REG_VAL(8, 0x3FF)
#define SDRC_MCFG_RAMSIZE_ENCODE(v)			ARM_REG_VAL_ENCODE(8, SDRC_MCFG_RAMSIZE_MASK, ((v) / 2))
#define SDRC_MCFG_RAMSIZE_DECODE(v)			(ARM_REG_VAL_DECODE(8, SDRC_MCFG_RAMSIZE_MASK, v) * 2)

#define SDRC_MCFG_BANKALLOCATION_MASK		ARM_REG_VAL(6, 0x3)
#define SDRC_MCFG_BANKALLOCATION_ENCODE(v)	ARM_REG_VAL_ENCODE(6, SDRC_MCFG_BANKALLOCATION_MASK, v)
#define SDRC_MCFG_BANKALLOCATION_DECODE(v)	ARM_REG_VAL_DECODE(6, SDRC_MCFG_BANKALLOCATION_MASK), v)
#define SDRC_MCFG_BANKALLOCATION_B_R_C			0x0
#define SDRC_MCFG_BANKALLOCATION_B1_R_B0_C		0x1
#define SDRC_MCFG_BANKALLOCATION_R_B_C			0x2

#define SDRC_MCFG_B32NOT16_OFF				ARM_REG_VAL(4, 0)
#define SDRC_MCFG_B32NOT16_ON				ARM_REG_VAL(4, 1)

#define SDRC_MCFG_DEEPPD_UNSUPPORTED		ARM_REG_VAL(3, 0)
#define	SDRC_MCFG_DEEPPD_SUPPORTED			ARM_REG_VAL(3, 1)

#define SDRC_MCFG_DDRTYPE_MASK				ARM_REG_VAL(2, 0x1)
#define SDRC_MCFG_DDRTYPE_ENCODE(v)			ARM_REG_VAL_ENCODE(2, SDRC_MCFG_DDRTYPE_MASK, v)
#define SDRC_MCFG_DDRTYPE_DECODE(v)			ARM_REG_VAL_DECODE(2, SDRC_MCFG_DDRTYPE_MASK, v)
#define SDRC_MCFG_DDRTYPE_MOBILE_DDR			0

#define SDRC_MCFG_RAMTYPE_MASK				ARM_REG_VAL(0, 0x3)
#define SDRC_MCFG_RAMTYPE_ENCODE(v)			ARM_REG_VAL_ENCODE(0, SDRC_MCFG_RAMTYPE_MASK, v)
#define SDRC_MCFG_RAMTYPE_DECODE(v)			ARM_REG_VAL_DECODE(0, SDRC_MCFG_RAMTYPE_MASK, v)
#define SDRC_MCFG_RAMTYPE_SDR					0x0
#define SDRC_MCFG_RAMTYPE_DDR					0x1

/*
 * SDRAM Controller DDR Mode Register (Corresponds 1:1 w/ JEDEC Mode
 * Register)
 */

#define SDRC_MR_ZERO_1						ARM_REG_VAL(10, 0)

#define SDRC_MR_WBST_ENABLE					ARM_REG_VAL(9, 0)
#define SDRC_MR_WBST_DISABLE				ARM_REG_VAL(9, 1)

#define SDRC_MR_ZERO_0						ARM_REG_VAL(7, 0)

#define SDRC_MR_CASL_MASK					ARM_REG_VAL(4, 0x7)
#define SDRC_MR_CASL_ENCODE(v)				ARM_REG_VAL_ENCODE(4, SDRC_MR_CASL_MASK, v)
#define SDRC_MR_CASL_DECODE(v)				ARM_REG_VAL_DECODE(4, SDRC_MR_CASL_MASK, v)
#define SDRC_MR_CASL_1							0x1
#define SDRC_MR_CASL_2							0x2
#define SDRC_MR_CASL_3							0x3
#define SDRC_MR_CASL_4							0x4
#define SDRC_MR_CASL_5							0x5

#define SDRC_MR_SIL_SERIAL					ARM_REG_VAL(3, 0)
#define SDRC_MR_SIL_INTERLEAVED				ARM_REG_VAL(3, 1)

#define SDRC_MR_BL_MASK						ARM_REG_VAL(0, 0x7)
#define SDRC_MR_BL_ENCODE(v)				ARM_REG_VAL_ENCODE(0, SDRC_MR_BL_MASK, v)
#define SDRC_MR_BL_DECODE(v)				ARM_REG_VAL_DECODE(0, SDRC_MR_BL_MASK, v)
#define SDRC_MR_BL_1							0x0
#define SDRC_MR_BL_2							0x1
#define SDRC_MR_BL_4							0x2
#define SDRC_MR_BL_8							0x3
#define SDRC_MR_BL_FULL_PAGE					0x7

/*
 * SDRAM Controller DDR Extended Mode Register (Corresponds 1:1 w/
 * JEDEC Mode Register)
 */

/*
 * SDRAM Controller AC Timing Control A
 */
#define SDRC_ACTIM_CTRLA_TRFC_MASK			ARM_REG_VAL(27, 0x1F)
#define SDRC_ACTIM_CTRLA_TRFC_ENCODE(v)		ARM_REG_VAL_ENCODE(27, SDRC_ACTIM_CTRLA_TRFC_MASK, v)
#define SDRC_ACTIM_CTRLA_TRFC_DECODE(v)		ARM_REG_VAL_DECODE(27, SDRC_ACTIM_CTRLA_TRFC_MASK), v)

#define SDRC_ACTIM_CTRLA_TRC_MASK			ARM_REG_VAL(22, 0x1F)
#define SDRC_ACTIM_CTRLA_TRC_ENCODE(v)		ARM_REG_VAL_ENCODE(22, SDRC_ACTIM_CTRLA_TRC_MASK, v)
#define SDRC_ACTIM_CTRLA_TRC_DECODE(v)		ARM_REG_VAL_DECODE(22, SDRC_ACTIM_CTRLA_TRC_MASK), v)

#define SDRC_ACTIM_CTRLA_TRAS_MASK			ARM_REG_VAL(18, 0xF)
#define SDRC_ACTIM_CTRLA_TRAS_ENCODE(v)		ARM_REG_VAL_ENCODE(18, SDRC_ACTIM_CTRLA_TRAS_MASK, v)
#define SDRC_ACTIM_CTRLA_TRAS_DECODE(v)		ARM_REG_VAL_DECODE(18, SDRC_ACTIM_CTRLA_TRAS_MASK), v)

#define SDRC_ACTIM_CTRLA_TRP_MASK			ARM_REG_VAL(15, 0x7)
#define SDRC_ACTIM_CTRLA_TRP_ENCODE(v)		ARM_REG_VAL_ENCODE(15, SDRC_ACTIM_CTRLA_TRP_MASK, v)
#define SDRC_ACTIM_CTRLA_TRP_DECODE(v)		ARM_REG_VAL_DECODE(15, SDRC_ACTIM_CTRLA_TRP_MASK), v)

#define SDRC_ACTIM_CTRLA_TRCD_MASK			ARM_REG_VAL(12, 0x7)
#define SDRC_ACTIM_CTRLA_TRCD_ENCODE(v)		ARM_REG_VAL_ENCODE(12, SDRC_ACTIM_CTRLA_TRCD_MASK, v)
#define SDRC_ACTIM_CTRLA_TRCD_DECODE(v)		ARM_REG_VAL_DECODE(12, SDRC_ACTIM_CTRLA_TRCD_MASK), v)

#define SDRC_ACTIM_CTRLA_TRRD_MASK			ARM_REG_VAL(9, 0x7)
#define SDRC_ACTIM_CTRLA_TRRD_ENCODE(v)		ARM_REG_VAL_ENCODE(9, SDRC_ACTIM_CTRLA_TRRD_MASK, v)
#define SDRC_ACTIM_CTRLA_TRRD_DECODE(v)		ARM_REG_VAL_DECODE(9, SDRC_ACTIM_CTRLA_TRRD_MASK), v)

#define SDRC_ACTIM_CTRLA_TDPL_MASK			ARM_REG_VAL(6, 0x7)
#define SDRC_ACTIM_CTRLA_TDPL_ENCODE(v)		ARM_REG_VAL_ENCODE(6, SDRC_ACTIM_CTRLA_TDPL_MASK, v)
#define SDRC_ACTIM_CTRLA_TDPL_DECODE(v)		ARM_REG_VAL_DECODE(6, SDRC_ACTIM_CTRLA_TDPL_MASK), v)

#define SDRC_ACTIM_CTRLA_TDAL_MASK			ARM_REG_VAL(0, 0x1F)
#define SDRC_ACTIM_CTRLA_TDAL_ENCODE(v)		ARM_REG_VAL_ENCODE(0, SDRC_ACTIM_CTRLA_TDAL_MASK, v)
#define SDRC_ACTIM_CTRLA_TDAL_DECODE(v)		ARM_REG_VAL_DECODE(0, SDRC_ACTIM_CTRLA_TDAL_MASK), v)

/*
 * SDRAM Controller AC Timing Control B
 */
#define SDRC_ACTIM_CTRLB_TWTR_MASK			ARM_REG_VAL(16, 0x3)
#define SDRC_ACTIM_CTRLB_TWTR_ENCODE(v)		ARM_REG_VAL_ENCODE(16, SDRC_ACTIM_CTRLB_TWTR_MASK, v)
#define SDRC_ACTIM_CTRLB_TWTR_DECODE(v)		ARM_REG_VAL_DECODE(16, SDRC_ACTIM_CTRLB_TWTR_MASK), v)

#define SDRC_ACTIM_CTRLB_TCKE_MASK			ARM_REG_VAL(12, 0x7)
#define SDRC_ACTIM_CTRLB_TCKE_ENCODE(v)		ARM_REG_VAL_ENCODE(12, SDRC_ACTIM_CTRLB_TCKE_MASK, v)
#define SDRC_ACTIM_CTRLB_TCKE_DECODE(v)		ARM_REG_VAL_DECODE(12, SDRC_ACTIM_CTRLB_TCKE_MASK), v)

#define SDRC_ACTIM_CTRLB_TXP_MASK			ARM_REG_VAL(8, 0x7)
#define SDRC_ACTIM_CTRLB_TXP_ENCODE(v)		ARM_REG_VAL_ENCODE(8, SDRC_ACTIM_CTRLB_TXP_MASK, v)
#define SDRC_ACTIM_CTRLB_TXP_DECODE(v)		ARM_REG_VAL_DECODE(8, SDRC_ACTIM_CTRLB_TXP_MASK), v)

#define SDRC_ACTIM_CTRLB_TXSR_MASK			ARM_REG_VAL(0, 0xFF)
#define SDRC_ACTIM_CTRLB_TXSR_ENCODE(v)		ARM_REG_VAL_ENCODE(0, SDRC_ACTIM_CTRLB_TXSR_MASK, v)
#define SDRC_ACTIM_CTRLB_TXSR_DECODE(v)		ARM_REG_VAL_DECODE(0, SDRC_ACTIM_CTRLB_TXSR_MASK), v)

/*
 * SDRAM Controller Autorefresh Control
 */
#define SDRC_RFR_CTRL_ARCV_MASK				ARM_REG_VAL(8, 0xFFFF)
#define SDRC_RFR_CTRL_ARCV_ENCODE(v)		ARM_REG_VAL_ENCODE(8, SDRC_RFR_CTRL_ARCV_MASK, v)
#define SDRC_RFR_CTRL_ARCV_DECODE(v)		ARM_REG_VAL_DECODE(8, SDRC_RFR_CTRL_ARCV_MASK), v)

#define SDRC_RFR_CTRL_ARE_MASK				ARM_REG_VAL(0, 0x3)
#define SDRC_RFR_CTRL_ARE_ENCODE(v)			ARM_REG_VAL_ENCODE(0, SDRC_RFR_CTRL_ARE_MASK, v)
#define SDRC_RFR_CTRL_ARE_DECODE(v)			ARM_REG_VAL_DECODE(0, SDRC_RFR_CTRL_ARE_MASK), v)
#define SDRC_RFR_CTRL_ARE_DISABLED				0x0
#define SDRC_RFR_CTRL_ARE_1_ARCV				0x1
#define SDRC_RFR_CTRL_ARE_4_ARCV				0x2
#define SDRC_RFR_CTRL_ARE_8_ARCV				0x3

/*
 * SDRAM Controller Manual Control
 */
#define SDRC_MANUAL_CMDPARAM_MASK			ARM_REG_VAL(16, 0xFFFF)
#define SDRC_MANUAL_CMDPARAM_ENCODE(v)		ARM_REG_VAL_ENCODE(16, SDRC_MANUAL_CMDPARAM_MASK, v)
#define SDRC_MANUAL_CMDPARAM_DECODE(v)		ARM_REG_VAL_DECODE(16, SDRC_MANUAL_CMDPARAM_MASK), v)

#define SDRC_MANUAL_CMDCODE_MASK			ARM_REG_VAL(0, 0x7)
#define SDRC_MANUAL_CMDCODE_ENCODE(v)		ARM_REG_VAL_ENCODE(0, SDRC_MANUAL_CMDCODE_MASK, v)
#define SDRC_MANUAL_CMDCODE_DECODE(v)		ARM_REG_VAL_DECODE(0, SDRC_MANUAL_CMDCODE_MASK), v)
#define SDRC_MANUAL_CMDCODE_NOP					0x0
#define SDRC_MANUAL_CMDCODE_PRECHARGE_ALL		0x1
#define SDRC_MANUAL_CMDCODE_AUTOREFRESH			0x2
#define SDRC_MANUAL_CMDCODE_ENTER_PWD			0x3
#define SDRC_MANUAL_CMDCODE_EXIT_PWD			0x4
#define SDRC_MANUAL_CMDCODE_ENTER_SELFREFRESH	0x5
#define SDRC_MANUAL_CMDCODE_EXIT_SELFREFRESH	0x6
#define SDRC_MANUAL_CMDCODE_SET_CKE_HIGH		0x7
#define SDRC_MANUAL_CMDCODE_SET_CKE_LOW			0x8

#endif /* _OMAP3_SDRC_H */