/*
 * Copyright 2011-2016 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#include "hardware.h"

#define GPC_CNTR		0x000
#define GPC_CNTR_PCIE_PHY_PDU_SHIFT	0x7
#define GPC_CNTR_PCIE_PHY_PDN_SHIFT	0x6
#define PGC_PCIE_PHY_CTRL		0x200
#define PGC_PCIE_PHY_PDN_EN		0x1
#define GPC_IMR1		0x008
#define GPC_ISR1		0x018
#define GPC_PGC_MF_PDN		0x220
#define GPC_PGC_GPU_PDN		0x260
#define GPC_PGC_GPU_PUPSCR	0x264
#define GPC_PGC_GPU_PDNSCR	0x268
#define GPC_PGC_CPU_PDN		0x2a0
#define GPC_PGC_CPU_PUPSCR	0x2a4
#define GPC_PGC_CPU_PDNSCR	0x2a8
#define GPC_PGC_SW2ISO_SHIFT	0x8
#define GPC_PGC_SW_SHIFT	0x0
#define GPC_PGC_DISP_PGCR_OFFSET	0x240
#define GPC_PGC_DISP_PUPSCR_OFFSET	0x244
#define GPC_PGC_DISP_PDNSCR_OFFSET	0x248
#define GPC_PGC_DISP_SR_OFFSET		0x24c
#define GPC_M4_LPSR		0x2c
#define GPC_M4_LPSR_M4_SLEEPING_SHIFT	4
#define GPC_M4_LPSR_M4_SLEEPING_MASK	0x1
#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK	0x1
#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT	0
#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK	0x1
#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT	1

#define GPC_PGC_CPU_SW_SHIFT		0
#define GPC_PGC_CPU_SW_MASK		0x3f
#define GPC_PGC_CPU_SW2ISO_SHIFT	8
#define GPC_PGC_CPU_SW2ISO_MASK		0x3f

#define IMR_NUM			4
#define GPC_MAX_IRQS		(IMR_NUM * 32)

#define GPU_VPU_PUP_REQ		BIT(1)
#define GPU_VPU_PDN_REQ		BIT(0)

#define GPC_CLK_MAX		10
#define DEFAULT_IPG_RATE		66000000
#define GPC_PU_UP_DELAY_MARGIN		2

/* for irq #74 and #75 */
#define GPC_USB_VBUS_WAKEUP_IRQ_MASK		0xc00

#define GPC_IRQS_PER_IMR		32

struct pu_domain {
	struct generic_pm_domain base;
	struct regulator *reg;
	struct clk *clk[GPC_CLK_MAX];
	int num_clks;
};

struct disp_domain {
	struct generic_pm_domain base;
	struct clk *clk[GPC_CLK_MAX];
	int num_clks;
};

struct irq_map_entry {
	u32 hwirq;
	const char *system;
	const char *descr;
};

struct irq_map {
	const struct irq_map_entry *table;
	unsigned int count;
};

static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
static u32 gpc_mf_irqs[IMR_NUM];
static u32 gpc_mf_request_on[IMR_NUM];
static DEFINE_SPINLOCK(gpc_lock);
static struct notifier_block nb_pcie;
static struct pu_domain imx6q_pu_domain;
static bool pu_on;      /* keep always on i.mx6qp */
static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd);
static void _imx6q_pm_pu_power_on(struct generic_pm_domain *genpd);
static struct clk *ipg;
static const struct irq_map *irq_map;

// Data copy-pasted from Table 3-1 of the i.MX 6SoloX Applications Processor Reference Manual
// irq_map_table[0] is the LSB of the ISR/IMR and is IRQ32
static const struct irq_map_entry imx6sx_irq_map_table[] =
{
	{32, "IOMUXC", "General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot."},
	{33, "DAP", "Debug Access Port interrupt request."},
	{34, "SDMA", "SDMA interrupt request from all channels."},
	{35, "Reserved", "Reserved"},
	{36, "SNVS", "PMIC power off request."},
	{37, "LCDIF1", "LCDIF1 Sync Interrupt"},
	{38, "LCDIF2", "LCDIF2 Sync Interrupt"},
	{39, "CSI1", "CMOS Sensor Interface interrupt request"},
	{40, "PXP", "PXP interrupt"},
	{41, "Reserved", "Reserved."},
	{42, "GPU", "GPU general interrupt request."},
	{43, "WDOG3", "WDOG3 timer reset interrupt request."},
	{44, "SEMA4", "SEMA4 CP1 interrupt request."},
	{45, "APBH", "DMA Logical OR of APBH DMA channels 0-3 completion and error interrupts."},
	{46, "EIM", "EIM interrupt request."},
	{47, "BCH", "BCH operation complete interrupt."},
	{48, "GPMI", "GPMI operation timeout error interrupt."},
	{49, "UART6", "UART6 interrupt request."},
	{50, "eCSPI5", "eCSPI5 interrupt request."},
	{51, "SNVS", "SNVS consolidated interrupt."},
	{52, "SNVS", "SNVS security interrupt."},
	{53, "CSU", "CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted."},
	{54, "uSDHC1", "uSDHC1 (Enhanced SDHC) interrupt request."},
	{55, "uSDHC2", "uSDHC2 (Enhanced SDHC) interrupt request."},
	{56, "uSDHC3", "uSDHC3 (Enhanced SDHC) interrupt request."},
	{57, "uSDHC4", "uSDHC4 (Enhanced SDHC) interrupt request."},
	{58, "UART1", "UART1 interrupt request."},
	{59, "UART2", "UART2 interrupt request."},
	{60, "UART3", "UART3 interrupt request."},
	{61, "UART4", "UART4 interrupt request."},
	{62, "UART5", "UART5 interrupt request."},
	{63, "eCSPI1", "eCSPI1 interrupt request."},
	{64, "eCSPI2", "eCSPI2 interrupt request."},
	{65, "eCSPI3", "eCSPI3 interrupt request."},
	{66, "eCSPI4", "eCSPI4 interrupt request."},
	{67, "I2C4", "I2C4 interrupt request"},
	{68, "I2C1", "I2C1 interrupt request."},
	{69, "I2C2", "I2C2 interrupt request."},
	{70, "I2C3", "I2C3 interrupt request."},
	{71, "RDC", "RDC interrupt request."},
	{72, "USB", "USB HISC Host interrupt request."},
	{73, "CSI2", "CSI interrupt"},
	{74, "USB", "USB OTG 2 interrupt request."},
	{75, "USB", "USB OTG 1 interrupt request."},
	{76, "USB_PHY", "UTMI0 interrupt request."},
	{77, "USB_PHY", "UTMI1 interrupt request."},
	{78, "SSI1", "SSI1 interrupt request."},
	{79, "SSI2", "SSI2 interrupt request."},
	{80, "SSI3", "SSI3 interrupt request."},
	{81, "Temperature Monitor", "Temperature Sensor (temp. greater than threshold) interrupt request."},
	{82, "ASRC", "ASRC interrupt request."},
	{83, "ESAI", "ESAI interrupt request."},
	{84, "SPDIF", "SPDIF Rx/Tx interrupt."},
	{85, "MLB", "MLB error interrupt request."},
	{86, "PMU", "Brown-out event on either the 1.1, 2.5 or 3.0 regulators."},
	{87, "GPT", "Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines."},
	{88, "EPIT1", "EPIT1 output compare interrupt."},
	{89, "EPIT2", "EPIT2 output compare interrupt."},
	{90, "GPIO1", "INT7 interrupt request."},
	{91, "GPIO1", "INT6 interrupt request."},
	{92, "GPIO1", "INT5 interrupt request."},
	{93, "GPIO1", "INT4 interrupt request."},
	{94, "GPIO1", "INT3 interrupt request."},
	{95, "GPIO1", "INT2 interrupt request."},
	{96, "GPIO1", "INT1 interrupt request."},
	{97, "GPIO1", "INT0 interrupt request."},
	{98, "GPIO1", "Combined interrupt indication for GPIO1 signals 0 - 15."},
	{99, "GPIO1", "Combined interrupt indication for GPIO1 signals 16 - 31."},
	{100, "GPIO2", "Combined interrupt indication for GPIO2 signals 0 - 15."},
	{101, "GPIO2", "Combined interrupt indication for GPIO2 signals 16 - 31."},
	{102, "GPIO3", "Combined interrupt indication for GPIO3 signals 0 - 15."},
	{103, "GPIO3", "Combined interrupt indication for GPIO3 signals 16 - 31."},
	{104, "GPIO4", "Combined interrupt indication for GPIO4 signals 0 - 15."},
	{105, "GPIO4", "Combined interrupt indication for GPIO4 signals 16 - 31."},
	{106, "GPIO5", "Combined interrupt indication for GPIO5 signals 0 - 15."},
	{107, "GPIO5", "Combined interrupt indication for GPIO5 signals 16 - 31."},
	{108, "GPIO6", "Combined interrupt indication for GPIO6 signals 0 - 15."},
	{109, "GPIO6", "Combined interrupt indication for GPIO6 signals 16 - 31."},
	{110, "GPIO7", "Combined interrupt indication for GPIO7 signals 0 - 15."},
	{111, "GPIO7", "Combined interrupt indication for GPIO7 signals 16 - 31."},
	{112, "WDOG1", "WDOG1 timer reset interrupt request."},
	{113, "WDOG2", "WDOG2 timer reset interrupt request."},
	{114, "KPP", "Key Pad interrupt request."},
	{115, "PWM1/PWM5", "Cumulative interrupt line for PWM1/PWM5. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{116, "PWM2/PWM6", "Cumulative interrupt line for PWM2/PWM6. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{117, "PWM3/PWM7", "Cumulative interrupt line for PWM3/PWM7. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{118, "PWM4/PWM8", "Cumulative interrupt line for PWM4/PWM8. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{119, "CCM", "CCM interrupt request 1."},
	{120, "CCM", "CCM interrupt request 2."},
	{121, "GPC", "GPC interrupt request 1."},
	{122, "MU", "Message unit interrupt to A9 core"},
	{123, "SRC", "SRC interrupt request."},
	{124, "CPU", "L2 interrupt request."},
	{125, "CPU", "Parity Check error interrupt request."},
	{126, "CPU", "Performance Unit interrupt."},
	{127, "CPU", "CTI trigger outputs interrupt."},
	{128, "SRC", "Combined CPU wdog interrupts (4x) out of SRC."},
	{129, "SAI1", "SAI1 interrupt request."},
	{130, "SAI2", "SAI2 interrupt request."},
	{131, "MU", "Message unit Interrupt to M4 core"},
	{132, "ADC1", "ADC1 interrupt request."},
	{133, "ADC2", "ADC2 interrupt request."},
	{134, "ENET2", "ENET2 Interrupt Request."},
	{135, "ENET2", "ENET2 1588 Timer interrupt [synchronous] request."},
	{136, "SJC", "SJC interrupt from General Purpose register."},
	{137, "CAAM", "CAAM job ring 0 interrupt."},
	{138, "CAAM", "CAAM job ring 1 interrupt."},
	{139, "QSPI1", "QSPI1 interrupt request."},
	{140, "TZASC", "TZASC (PL380) interrupt request."},
	{141, "QSPI2", "QSPI2 interrupt request."},
	{142, "FLEXCAN1", "FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein."},
	{143, "FLEXCAN2", "FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein."},
	{144, "Reserved", "Reserved"},
	{145, "Reserved", "Reserved"},
	{146, "Reserved", "Reserved"},
	{147, "Reserved", "Reserved"},
	{148, "SEMA4", "SEMA4 CP0 interrupt request"},
	{149, "MLB", "Interrupt request for channels [31:0]. Interrupt request for channels [63:32] available on IRQ #149 if SMX bit is set in MLB150 AHB control register (ACTL), otherwise interrupt for channels [63:32] interrupt is available on IRQ #158."},
	{150, "ENET1", "ENET1 Interrupt Request."},
	{151, "ENET1", "ENET1 1588 Timer interrupt [synchronous] request."},
	{152, "PCIe", "PCIe interrupt request 1."},
	{153, "PCIe", "PCIe interrupt request 2."},
	{154, "PCIe", "PCIe interrupt request 3."},
	{155, "PCIe", "PCIe interrupt request 4."},
	{156, "DCIC1", "DCIC1 interrupt request."},
	{157, "DCIC2", "DCIC2 interrupt request."},
	{158, "MLB", "Logical OR of channel[63:32] interrupt requests."},
	{159, "PMU", "Brown out of core, gpu, and chip digital regulators occurred."},
};

static const struct irq_map imx6sx_irq_map =
{
    .table = imx6sx_irq_map_table,
    .count = ARRAY_SIZE(imx6sx_irq_map_table),
};

// Data copy-pasted from Table 3-1 of the i.MX 6UltraLight Applications Processor Reference Manual
// irq_map_table[0] is the LSB of the ISR/IMR and is IRQ32
static const struct irq_map_entry imx6ul_irq_map_table[] =
{
	{32, "IOMUXC", "General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot."},
	{33, "DAP", "Debug Access Port interrupt request."},
	{34, "SDMA", "SDMA interrupt request from all channels."},
	{35, "TSC", "TSC interrupt."},
	{36, "SNVS_LP/SNVS_HP", "Logic OR of SNVS_LP and SNVS_HP interrupts."},
	{37, "LCDIF", "LCDIF sync interrupt."},
	{38, "BEE", "BEE interrupt."},
	{39, "CSI", "CMOS Sensor Interface interrupt request."},
	{40, "PXP", "PXP interrupt."},
	{41, "SCTR", "SCTR compare interrupt."},
	{42, "SCTR", "SCTR compare interrupt."},
	{43, "WDOG3", "WDOG3 timer reset interrupt request."},
	{44, "Reserved", "Reserved"},
	{45, "APBH DMA", "Logical OR of APBH DMA channels 0-3 completion and error interrupts."},
	{46, "WEIM", "WEIM interrupt request."},
	{47, "RAWNAND BCH", "operation complete interrupt."},
	{48, "RAWNAND GPMI", "operation timeout error interrupt."},
	{49, "UART6", "UART6 interrupt request."},
	{50, "Reserved", "Reserved"},
	{51, "SNVS", "SRTC consolidated interrupt."},
	{52, "SNVS", "SRTC security interrupt."},
	{53, "CSU", "CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted."},
	{54, "uSDHC1", "uSDHC1 (Enhanced SDHC) interrupt request."},
	{55, "uSDHC2", "uSDHC2 (Enhanced SDHC) interrupt request."},
	{56, "SAI3", "SAI interrupt"},
	{57, "SAI3", "SAI interrupt."},
	{58, "UART1", "UART1 interrupt request."},
	{59, "UART2", "UART2 interrupt request."},
	{60, "UART3", "UART3 interrupt request."},
	{61, "UART4", "UART4 interrupt request."},
	{62, "UART5", "UART5 interrupt request."},
	{63, "eCSPI1", "eCSPI1 interrupt request."},
	{64, "eCSPI2", "eCSPI2 interrupt request."},
	{65, "eCSPI3", "eCSPI3 interrupt request."},
	{66, "eCSPI4", "eCSPI4 interrupt request."},
	{67, "I2C4", "I2C4 interrupt request."},
	{68, "I2C1", "I2C1 interrupt request."},
	{69, "I2C2", "I2C2 interrupt request."},
	{70, "I2C3", "I2C3 interrupt request."},
	{71, "UART7", "UART-7 ORed interrupt."},
	{72, "UART8", "UART-8 ORed interrupt."},
	{73, "Reserved", "Reserved"},
	{74, "USB", "USBO2 USB OTG2"},
	{75, "USB", "USBO2 USB OTG1"},
	{76, "USB_PHY", "UTMI0 interrupt request."},
	{77, "USB_PHY", "UTMI1 interrupt request."},
	{78, "CAAM", "CAAM interrupt queue for JQ2."},
	{79, "CAAM", "CAAM interrupt for recoverable error."},
	{80, "CAAM", "CAAM interrupt for RTIC."},
	{81, "Temperature Monitor", "Temperature Sensor (temperature greater than threshold) interrupt request."},
	{82, "ASRC", "ASRC interrupt request."},
	{83, "Reserved", "Reserved"},
	{84, "SPDIF", "Logic OR of SPDIF Rx/Tx interrupts."},
	{85, "Reserved", "Reserved"},
	{86, "PMU", "Brown-out event on either the 1.1, 2.5 or 3.0 regulators."},
	{87, "GPT1", "Logical OR of GPT1 rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2, and 3 interrupt lines."},
	{88, "EPIT1", "EPIT1 output compare interrupt."},
	{89, "EPIT2", "EPIT2 output compare interrupt."},
	{90, "GPIO1", "INT7 interrupt request."},
	{91, "GPIO1", "INT6 interrupt request."},
	{92, "GPIO1", "INT5 interrupt request."},
	{93, "GPIO1", "INT4 interrupt request."},
	{94, "GPIO1", "INT3 interrupt request."},
	{95, "GPIO1", "INT2 interrupt request."},
	{96, "GPIO1", "INT1 interrupt request."},
	{97, "GPIO1", "INT0 interrupt request."},
	{98, "GPIO1", "Combined interrupt indication for GPIO1 signals 0 - 15."},
	{99, "GPIO1", "Combined interrupt indication for GPIO1 signals 16 - 31."},
	{100, "GPIO2", "Combined interrupt indication for GPIO2 signals 0 - 15."},
	{101, "GPIO2", "Combined interrupt indication for GPIO2 signals 16 - 31."},
	{102, "GPIO3", "Combined interrupt indication for GPIO3 signals 0 - 15."},
	{103, "GPIO3", "Combined interrupt indication for GPIO3 signals 16 - 31."},
	{104, "GPIO4", "Combined interrupt indication for GPIO4 signals 0 - 15."},
	{105, "GPIO4", "Combined interrupt indication for GPIO4 signals 16 - 31."},
	{106, "GPIO5", "Combined interrupt indication for GPIO5 signals 0 - 15."},
	{107, "GPIO5", "Combined interrupt indication for GPIO5 signals 16 - 31."},
	{108, "Reserved", "Reserved"},
	{109, "Reserved", "Reserved"},
	{110, "Reserved", "Reserved"},
	{111, "Reserved", "Reserved"},
	{112, "WDOG1", "WDOG1 timer reset interrupt request."},
	{113, "WDOG2", "WDOG2 timer reset interrupt request."},
	{114, "KPP", "Key Pad interrupt request."},
	{115, "PWM1", "Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{116, "PWM2", "Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{117, "PWM3", "Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{118, "PWM4", "Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts."},
	{119, "CCM", "CCM interrupt request 1."},
	{120, "CCM", "CCM interrupt request 2."},
	{121, "GPC", "GPC interrupt request 1."},
	{122, "Reserved", "Reserved"},
	{123, "SRC", "SRC interrupt request."},
	{124, "Reserved", "Reserved"},
	{125, "Reserved", "Reserved"},
	{126, "CPU", "Performance Unit interrupt."},
	{127, "CPU", "CTI trigger outputs interrupt."},
	{128, "SRC", "Combined CPU wdog interrupts (4x) out of SRC."},
	{129, "SAI1", "SAI1 interrupt request."},
	{130, "SAI2", "SAI2 interrupt request."},
	{131, "Reserved", "Reserved"},
	{132, "ADC1", "ADC1 interrupt request."},
	{133, "ADC2", "ADC2 interrupt request."},
	{134, "Reserved", "Reserved"},
	{135, "Reserved", "Reserved"},
	{136, "SJC", "SJC interrupt from General Purpose register."},
	{137, "CAAM", "CAAM job ring 0 interrupt."},
	{138, "CAAM", "CAAM job ring 1 interrupt."},
	{139, "QSPI", "QSPI interrupt request."},
	{140, "TZASC", "TZASC (PL380) interrupt request."},
	{141, "GPT2", "Logical OR of GPT2 rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines."},
	{142, "CAN1", "Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken"},
	{143, "CAN2", "Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken"},
	{144, "SIM1", "SIM interrupt"},
	{145, "SIM2", "SIM interrupt"},
	{146, "PWM5", "Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line"},
	{147, "PWM6", "Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line"},
	{148, "PWM7", "Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line"},
	{149, "PWM8", "Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line"},
	{150, "ENET1", "ENET1 interrupt"},
	{151, "ENET1", "ENET1 1588 Timer interrupt [synchronous] request."},
	{152, "ENET2", "ENET2 interrupt"},
	{153, "ENET2", "MAC 0 1588 Timer interrupt [synchronous] request."},
	{154, "Reserved", "Reserved"},
	{155, "Reserved", "Reserved"},
	{156, "Reserved", "Reserved"},
	{157, "Reserved", "Reserved"},
	{158, "Reserved", "Reserved"},
	{159, "PMU", "Brown-out event on either core, gpu or soc regulators."},
};

static const struct irq_map imx6ul_irq_map =
{
    .table = imx6ul_irq_map_table,
    .count = ARRAY_SIZE(imx6ul_irq_map_table),
};

void imx_gpc_add_m4_wake_up_irq(u32 hwirq, bool enable)
{
	unsigned int idx = hwirq / 32;
	unsigned long flags;
	u32 mask;

	/* Sanity check for SPI irq */
	if (hwirq < 32)
		return;

	mask = 1 << hwirq % 32;
	spin_lock_irqsave(&gpc_lock, flags);
	gpc_wake_irqs[idx] = enable ? gpc_wake_irqs[idx] | mask :
		gpc_wake_irqs[idx] & ~mask;
	spin_unlock_irqrestore(&gpc_lock, flags);
}

void imx_gpc_hold_m4_in_sleep(void)
{
	int val;
	unsigned long timeout = jiffies + msecs_to_jiffies(500);

	/* wait M4 in wfi before asserting hold request */
	while (!imx_gpc_is_m4_sleeping())
		if (time_after(jiffies, timeout))
			pr_err("M4 is NOT in expected sleep!\n");

	val = readl_relaxed(gpc_base + GPC_M4_LPSR);
	val &= ~(GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK <<
		GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT);
	writel_relaxed(val, gpc_base + GPC_M4_LPSR);

	timeout = jiffies + msecs_to_jiffies(500);
	while (readl_relaxed(gpc_base + GPC_M4_LPSR)
		& (GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK <<
		GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT))
		if (time_after(jiffies, timeout))
			pr_err("Wait M4 hold ack timeout!\n");
}

void imx_gpc_release_m4_in_sleep(void)
{
	int val;

	val = readl_relaxed(gpc_base + GPC_M4_LPSR);
	val |= GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK <<
		GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT;
	writel_relaxed(val, gpc_base + GPC_M4_LPSR);
}

unsigned int imx_gpc_is_m4_sleeping(void)
{
	if (readl_relaxed(gpc_base + GPC_M4_LPSR) &
		(GPC_M4_LPSR_M4_SLEEPING_MASK <<
		GPC_M4_LPSR_M4_SLEEPING_SHIFT))
		return 1;

	return 0;
}

bool imx_gpc_usb_wakeup_enabled(void)
{
	if (!(cpu_is_imx6sx() || cpu_is_imx6ul()))
		return false;

	/*
	 * for SoC later than i.MX6SX, USB vbus wakeup
	 * only needs weak 2P5 on, stop_mode_config is
	 * NOT needed, so we check if is USB vbus wakeup
	 * is enabled(assume irq #74 and #75) to decide
	 * if to keep weak 2P5 on.
	 */
	if (gpc_wake_irqs[1] & GPC_USB_VBUS_WAKEUP_IRQ_MASK)
		return true;

	return false;
}

unsigned int imx_gpc_is_mf_mix_off(void)
{
	return readl_relaxed(gpc_base + GPC_PGC_MF_PDN);
}

static void imx_gpc_mf_mix_off(void)
{
	int i;

	for (i = 0; i < IMR_NUM; i++)
		if (((gpc_wake_irqs[i] | gpc_mf_request_on[i]) &
						gpc_mf_irqs[i]) != 0)
			return;

	pr_info("Turn off M/F mix!\n");
	/* turn off mega/fast mix */
	writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN);
}

void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
}

void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
}

void imx_gpc_set_arm_power_in_lpm(bool power_off)
{
	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
}

void imx_gpc_pre_suspend(bool arm_power_off)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);

	/* power down the mega-fast power domain */
	if ((cpu_is_imx6sx() || cpu_is_imx6ul()) && arm_power_off)
		imx_gpc_mf_mix_off();

	/* Tell GPC to power off ARM core when suspend */
	if (arm_power_off)
		imx_gpc_set_arm_power_in_lpm(arm_power_off);

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	}
}

void imx_gpc_post_resume(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	void __iomem *reg_isr1 = gpc_base + GPC_ISR1;
	int i;

	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
		_imx6q_pm_pu_power_on(&imx6q_pu_domain.base);

	/* Keep ARM core powered on for other low-power modes */
	imx_gpc_set_arm_power_in_lpm(false);
	/* Keep M/F mix powered on for other low-power modes */
	if (cpu_is_imx6sx() || cpu_is_imx6ul())
		writel_relaxed(0x0, gpc_base + GPC_PGC_MF_PDN);

	for (i = 0; i < IMR_NUM; i++) {
		u32 imr, isr, source;
		imr = readl_relaxed(reg_imr1 + i * 4);
		isr = readl_relaxed(reg_isr1 + i * 4);
		source = ~imr & isr;
		pr_info("imr[%d] = 0x%08x, isr[%d] = 0x%08x, source = 0x%08x",
			i, imr, i, isr, source);

		if (irq_map)
		{
			while (source != 0)
			{
				const int bit = fls(source) - 1;
				const int irqoffset = bit + GPC_IRQS_PER_IMR * i;
				if (irqoffset < irq_map->count) {
					const struct irq_map_entry *row = &irq_map->table[irqoffset];
					pr_info("wakeup hwirq %d %s (%s)", row->hwirq, row->system, row->descr);
				} else {
					pr_info("wakeup irqoffset  %d", irqoffset);
				}
				source &= ~(1 << bit);
			}
		}

		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	}
}

static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned int idx = d->hwirq / 32;
	unsigned long flags;
	u32 mask;

	mask = 1 << d->hwirq % 32;
	spin_lock_irqsave(&gpc_lock, flags);
	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
				  gpc_wake_irqs[idx] & ~mask;
	spin_unlock_irqrestore(&gpc_lock, flags);

	/*
	 * Do *not* call into the parent, as the GIC doesn't have any
	 * wake-up facility...
	 */
	return 0;
}

void imx_gpc_mask_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~0, reg_imr1 + i * 4);
	}

}

void imx_gpc_restore_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
	val = readl_relaxed(reg);
	val &= ~(1 << hwirq % 32);
	writel_relaxed(val, reg);
}

void imx_gpc_hwirq_mask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
	val = readl_relaxed(reg);
	val |= 1 << (hwirq % 32);
	writel_relaxed(val, reg);
}

static void imx_gpc_irq_unmask(struct irq_data *d)
{
	imx_gpc_hwirq_unmask(d->hwirq);
	irq_chip_unmask_parent(d);
}

static void imx_gpc_irq_mask(struct irq_data *d)
{
	imx_gpc_hwirq_mask(d->hwirq);
	irq_chip_mask_parent(d);
}

static struct irq_chip imx_gpc_chip = {
	.name			= "GPC",
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_mask		= imx_gpc_irq_mask,
	.irq_unmask		= imx_gpc_irq_unmask,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_wake		= imx_gpc_irq_set_wake,
	.irq_set_type           = irq_chip_set_type_parent,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
};

static int imx_gpc_domain_xlate(struct irq_domain *domain,
				struct device_node *controller,
				const u32 *intspec,
				unsigned int intsize,
				unsigned long *out_hwirq,
				unsigned int *out_type)
{
	if (domain->of_node != controller)
		return -EINVAL;	/* Shouldn't happen, really... */
	if (intsize != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (intspec[0] != 0)
		return -EINVAL;	/* No PPI should point to this domain */

	*out_hwirq = intspec[1];
	*out_type = intspec[2];
	return 0;
}

static int imx_gpc_domain_alloc(struct irq_domain *domain,
				  unsigned int irq,
				  unsigned int nr_irqs, void *data)
{
	struct of_phandle_args *args = data;
	struct of_phandle_args parent_args;
	irq_hw_number_t hwirq;
	int i;

	if (args->args_count != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (args->args[0] != 0)
		return -EINVAL;	/* No PPI should point to this domain */

	hwirq = args->args[1];
	if (hwirq >= GPC_MAX_IRQS)
		return -EINVAL;	/* Can't deal with this */

	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
					      &imx_gpc_chip, NULL);

	parent_args = *args;
	parent_args.np = domain->parent->of_node;
	return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
}

static struct irq_domain_ops imx_gpc_domain_ops = {
	.xlate	= imx_gpc_domain_xlate,
	.alloc	= imx_gpc_domain_alloc,
	.free	= irq_domain_free_irqs_common,
};

int imx_gpc_mf_power_on(unsigned int irq, unsigned int on)
{
	struct irq_desc *d = irq_to_desc(irq);
	unsigned int idx = d->irq_data.hwirq / 32;
	unsigned long flags;
	u32 mask;

	mask = 1 << (d->irq_data.hwirq % 32);
	spin_lock_irqsave(&gpc_lock, flags);
	gpc_mf_request_on[idx] = on ? gpc_mf_request_on[idx] | mask :
				  gpc_mf_request_on[idx] & ~mask;
	spin_unlock_irqrestore(&gpc_lock, flags);

	return 0;
}

int imx_gpc_mf_request_on(unsigned int irq, unsigned int on)
{
	if (cpu_is_imx6sx() || cpu_is_imx6ul())
		return imx_gpc_mf_power_on(irq, on);
	else if (cpu_is_imx7d())
		return imx_gpcv2_mf_power_on(irq, on);
	else
		return 0;
}
EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on);

void imx_gpc_switch_pupscr_clk(bool flag)
{
	static u32 pupscr_sw2iso, pupscr_sw;
	u32 ratio, pupscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR);

	if (flag) {
		/* save the init clock setting IPG/2048 for IPG@66Mhz */
		pupscr_sw2iso = (pupscr >> GPC_PGC_CPU_SW2ISO_SHIFT) &
				    GPC_PGC_CPU_SW2ISO_MASK;
		pupscr_sw = (pupscr >> GPC_PGC_CPU_SW_SHIFT) &
				GPC_PGC_CPU_SW_MASK;
		/*
		 * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source,
		 * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch
		 * clock to IPG/32, enable this bit to speed up the ARM power
		 * up process in low power idle case(IPG@1.5Mhz). So the sw and
		 * sw2iso need to be adjusted as below:
		 * sw_new(sw2iso_new) = (2048 * 1.5 / 66 * 32) * sw(sw2iso)
		 */
		ratio = 3072 / (66 * 32);
		pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT |
			  GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
		pupscr |= (ratio * pupscr_sw + 1) << GPC_PGC_CPU_SW_SHIFT |
			  1 << 5 | (ratio * pupscr_sw2iso + 1) <<
			  GPC_PGC_CPU_SW2ISO_SHIFT;
		writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR);
	} else {
		/* restore back after exit from low power idle */
		pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT |
			  GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
		pupscr |= pupscr_sw << GPC_PGC_CPU_SW_SHIFT |
			  pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT;
		writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR);
	}
}

static int imx_pcie_regulator_notify(struct notifier_block *nb,
					unsigned long event,
					void *ignored)
{
	u32 value = readl_relaxed(gpc_base + GPC_CNTR);

	switch (event) {
	case REGULATOR_EVENT_PRE_DO_ENABLE:
		value |= 1 << GPC_CNTR_PCIE_PHY_PDU_SHIFT;
		writel_relaxed(value, gpc_base + GPC_CNTR);
		break;
	case REGULATOR_EVENT_PRE_DO_DISABLE:
		value |= 1 << GPC_CNTR_PCIE_PHY_PDN_SHIFT;
		writel_relaxed(value, gpc_base + GPC_CNTR);
		writel_relaxed(PGC_PCIE_PHY_PDN_EN,
				gpc_base + PGC_PCIE_PHY_CTRL);
		break;
	default:
		break;
	}

	return NOTIFY_OK;
}

static int __init imx_gpc_init(struct device_node *node,
			       struct device_node *parent)
{
	struct irq_domain *parent_domain, *domain;
	int i;
	u32 val;
	u32 cpu_pupscr_sw2iso, cpu_pupscr_sw;
	u32 cpu_pdnscr_iso2sw, cpu_pdnscr_iso;

	if (!parent) {
		pr_err("%s: no parent, giving up\n", node->full_name);
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%s: unable to obtain parent domain\n", node->full_name);
		return -ENXIO;
	}

	gpc_base = of_iomap(node, 0);
	if (WARN_ON(!gpc_base))
	        return -ENOMEM;

	domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
					  node, &imx_gpc_domain_ops,
					  NULL);
	if (!domain) {
		iounmap(gpc_base);
		return -ENOMEM;
	}

	/* Initially mask all interrupts */
	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);

	/* Read supported wakeup source in M/F domain */
	if (cpu_is_imx6sx() || cpu_is_imx6ul()) {
		of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0,
			&gpc_mf_irqs[0]);
		of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1,
			&gpc_mf_irqs[1]);
		of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2,
			&gpc_mf_irqs[2]);
		of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3,
			&gpc_mf_irqs[3]);
		if (!(gpc_mf_irqs[0] | gpc_mf_irqs[1] |
			gpc_mf_irqs[2] | gpc_mf_irqs[3]))
			pr_info("No wakeup source in Mega/Fast domain found!\n");
	}

	/*
	 * If there are CPU isolation timing settings in dts,
	 * update them according to dts, otherwise, keep them
	 * with default value in registers.
	 */
	cpu_pupscr_sw2iso = cpu_pupscr_sw =
		cpu_pdnscr_iso2sw = cpu_pdnscr_iso = 0;

	/* Read CPU isolation setting for GPC */
	of_property_read_u32(node, "fsl,cpu_pupscr_sw2iso", &cpu_pupscr_sw2iso);
	of_property_read_u32(node, "fsl,cpu_pupscr_sw", &cpu_pupscr_sw);
	of_property_read_u32(node, "fsl,cpu_pdnscr_iso2sw", &cpu_pdnscr_iso2sw);
	of_property_read_u32(node, "fsl,cpu_pdnscr_iso", &cpu_pdnscr_iso);

	/* Return if no property found in dtb */
	if ((cpu_pupscr_sw2iso | cpu_pupscr_sw
		| cpu_pdnscr_iso2sw | cpu_pdnscr_iso) == 0)
		return 0;

	/* Update CPU PUPSCR timing if it is defined in dts */
	val = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR);
	val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
	val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT);
	val |= cpu_pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT;
	val |= cpu_pupscr_sw << GPC_PGC_CPU_SW_SHIFT;
	writel_relaxed(val, gpc_base + GPC_PGC_CPU_PUPSCR);

	/* Update CPU PDNSCR timing if it is defined in dts */
	val = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR);
	val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
	val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT);
	val |= cpu_pdnscr_iso2sw << GPC_PGC_CPU_SW2ISO_SHIFT;
	val |= cpu_pdnscr_iso << GPC_PGC_CPU_SW_SHIFT;
	writel_relaxed(val, gpc_base + GPC_PGC_CPU_PDNSCR);

	return 0;
}

/*
 * We cannot use the IRQCHIP_DECLARE macro that lives in
 * drivers/irqchip, so we're forced to roll our own. Not very nice.
 */
OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);

void __init imx_gpc_check_dt(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	if (WARN_ON(!np))
		return;

	if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
		pr_warn("Outdated DT detected, suspend/resume will NOT work\n");

		/* map GPC, so that at least CPUidle and WARs keep working */
		gpc_base = of_iomap(np, 0);
	}
}

static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	int iso, iso2sw;
	u32 val;

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	iso = val & 0x3f;
	iso2sw = (val >> 8) & 0x3f;

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Request GPC to power down GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PDN_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((iso + iso2sw) * 1000 / 66);
}

static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);

	if (&imx6q_pu_domain == pu && pu_on && cpu_is_imx6q() &&
		imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
		return 0;

	_imx6q_pm_pu_power_off(genpd);

	if (pu->reg)
		regulator_disable(pu->reg);

	return 0;
}

static void _imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	int i, sw, sw2iso;
	u32 val;

	/* Enable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_prepare_enable(pu->clk[i]);

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	sw = val & 0x3f;
	sw2iso = (val >> 8) & 0x3f;

	/* Request GPC to power up GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PUP_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((sw + sw2iso) * 1000 / 66);

	/* Disable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_disable_unprepare(pu->clk[i]);
}

static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	int ret;

	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0
		&& &imx6q_pu_domain == pu) {
		if (!pu_on)
			pu_on = true;
		else
			return 0;
	}

	if (pu->reg)
		ret = regulator_enable(pu->reg);
	if (pu->reg && ret) {
		pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
		return ret;
	}

	_imx6q_pm_pu_power_on(genpd);

	return 0;
}

static int imx_pm_dispmix_on(struct generic_pm_domain *genpd)
{
	struct disp_domain *disp = container_of(genpd, struct disp_domain, base);
	u32 val = readl_relaxed(gpc_base + GPC_CNTR);
	int i;
	u32 ipg_rate = clk_get_rate(ipg);

	if ((cpu_is_imx6sl() &&
		imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) {

		/* Enable reset clocks for all devices in the disp domain */
		for (i = 0; i < disp->num_clks; i++)
			clk_prepare_enable(disp->clk[i]);

		writel_relaxed(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
		writel_relaxed(0x20 | val, gpc_base + GPC_CNTR);
		while (readl_relaxed(gpc_base + GPC_CNTR) & 0x20)
			;

		writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);

		/* Wait power switch done */
		udelay(2 * DEFAULT_IPG_RATE / ipg_rate +
			GPC_PU_UP_DELAY_MARGIN);

		/* Disable reset clocks for all devices in the disp domain */
		for (i = 0; i < disp->num_clks; i++)
			clk_disable_unprepare(disp->clk[i]);
	}
	return 0;
}

static int imx_pm_dispmix_off(struct generic_pm_domain *genpd)
{
	struct disp_domain *disp = container_of(genpd, struct disp_domain, base);
	u32 val = readl_relaxed(gpc_base + GPC_CNTR);
	int i;

	if ((cpu_is_imx6sl() &&
		imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) {

		/* Enable reset clocks for all devices in the disp domain */
		for (i = 0; i < disp->num_clks; i++)
			clk_prepare_enable(disp->clk[i]);

		writel_relaxed(0xFFFFFFFF,
				gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
		writel_relaxed(0xFFFFFFFF,
				gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
		writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
		writel_relaxed(0x10 | val, gpc_base + GPC_CNTR);
		while (readl_relaxed(gpc_base + GPC_CNTR) & 0x10)
			;

		/* Disable reset clocks for all devices in the disp domain */
		for (i = 0; i < disp->num_clks; i++)
			clk_disable_unprepare(disp->clk[i]);
	}
	return 0;
}

static struct generic_pm_domain imx6q_arm_domain = {
	.name = "ARM",
};

static struct pu_domain imx6q_pu_domain = {
	.base = {
		.name = "PU",
		.power_off = imx6q_pm_pu_power_off,
		.power_on = imx6q_pm_pu_power_on,
		.power_off_latency_ns = 25000,
		.power_on_latency_ns = 2000000,
	},
};

static struct disp_domain imx6s_display_domain = {
	.base = {
		.name = "DISPLAY",
		.power_off = imx_pm_dispmix_off,
		.power_on = imx_pm_dispmix_on,
	},
};

static struct generic_pm_domain *imx_gpc_domains[] = {
	&imx6q_arm_domain,
	&imx6q_pu_domain.base,
	&imx6s_display_domain.base,
};

static struct genpd_onecell_data imx_gpc_onecell_data = {
	.domains = imx_gpc_domains,
	.num_domains = ARRAY_SIZE(imx_gpc_domains),
};

static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
	struct clk *clk;
	bool is_off;
	int pu_clks, disp_clks, ipg_clks = 1;
	int i = 0, k = 0;

	imx6q_pu_domain.reg = pu_reg;

	if ((cpu_is_imx6sl() &&
			imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2)) {
		pu_clks = 2 ;
		disp_clks = 5;
	} else if (cpu_is_imx6sx()) {
		pu_clks = 1;
		disp_clks = 7;
	} else {
		pu_clks = 6;
		disp_clks = 0;
	}

	/* Get pu domain clks */
	for (i = 0; i < pu_clks ; i++) {
		clk = of_clk_get(dev->of_node, i);
		if (IS_ERR(clk))
			break;
		imx6q_pu_domain.clk[i] = clk;
	}
	imx6q_pu_domain.num_clks = i;

	ipg = of_clk_get(dev->of_node, pu_clks);

	/* Get disp domain clks */
	for (i = pu_clks + ipg_clks; i < pu_clks + ipg_clks + disp_clks;
		i++) {
		clk = of_clk_get(dev->of_node, i);
		if (IS_ERR(clk))
			break;
		imx6s_display_domain.clk[k++] = clk;
	}
	imx6s_display_domain.num_clks = k;

	is_off = IS_ENABLED(CONFIG_PM);
	if (is_off && !(cpu_is_imx6q() &&
		imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)) {
		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
	} else {
		/*
		 * Enable power if compiled without CONFIG_PM in case the
		 * bootloader disabled it.
		 */
		imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
	}

	pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
	pm_genpd_init(&imx6s_display_domain.base, NULL, is_off);

	return of_genpd_add_provider_onecell(dev->of_node,
					     &imx_gpc_onecell_data);
}

static const struct of_device_id irq_map_dt_ids[] = {
	{ .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_irq_map, },
	{ .compatible = "fsl,imx6ul-gpc", .data = &imx6ul_irq_map, },
	{ }
};

static int imx_gpc_probe(struct platform_device *pdev)
{
	struct regulator *pu_reg;
	int ret;
	u32 bypass = 0;
	const struct of_device_id *irq_map_of_id =
		of_match_node(irq_map_dt_ids, pdev->dev.of_node);

	if (irq_map_of_id) {
		irq_map = irq_map_of_id->data;
	}

	/* bail out if DT too old and doesn't provide the necessary info */
	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
		return 0;

	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
	if (PTR_ERR(pu_reg) == -ENODEV)
		pu_reg = NULL;
	if (IS_ERR(pu_reg)) {
		ret = PTR_ERR(pu_reg);
		dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
		return ret;
	}

	if (of_property_read_u32(pdev->dev.of_node, "fsl,ldo-bypass", &bypass))
		dev_warn(&pdev->dev,
			"no fsl,ldo-bypass found!\n");
	/* We only bypass pu since arm and soc has been set in u-boot */
	if (pu_reg && bypass)
		regulator_allow_bypass(pu_reg, true);

	if (cpu_is_imx6sx()) {
		struct regulator *pcie_reg;

		pcie_reg = devm_regulator_get(&pdev->dev, "pcie-phy");
		if (IS_ERR(pcie_reg)) {
			ret = PTR_ERR(pcie_reg);
			dev_info(&pdev->dev, "pcie regulator not ready.\n");
			return ret;
		}
		nb_pcie.notifier_call = &imx_pcie_regulator_notify;

		ret = regulator_register_notifier(pcie_reg, &nb_pcie);
		if (ret) {
			dev_err(&pdev->dev,
				"pcie regulator notifier request failed\n");
			return ret;
		}
	}

	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
}

static const struct of_device_id imx_gpc_dt_ids[] = {
	{ .compatible = "fsl,imx6q-gpc" },
	{ .compatible = "fsl,imx6sl-gpc" },
	{ }
};

static struct platform_driver imx_gpc_driver = {
	.driver = {
		.name = "imx-gpc",
		.owner = THIS_MODULE,
		.of_match_table = imx_gpc_dt_ids,
	},
	.probe = imx_gpc_probe,
};

static int __init imx_pgc_init(void)
{
	return platform_driver_register(&imx_gpc_driver);
}
subsys_initcall(imx_pgc_init);