/*
 * Copyright 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__

#define CCM_CCOSR		0x020c4060
#define CCM_CCGR0		0x020C4068
#define CCM_CCGR1		0x020C406c
#define CCM_CCGR2		0x020C4070
#define CCM_CCGR3		0x020C4074
#define CCM_CCGR4		0x020C4078
#define CCM_CCGR5		0x020C407c
#define CCM_CCGR6		0x020C4080

#define PMU_MISC2		0x020C8170

#ifndef __ASSEMBLY__
struct mxc_ccm_reg {
	u32 ccr;	/* 0x0000 */
	u32 ccdr;
	u32 csr;
	u32 ccsr;
	u32 cacrr;	/* 0x0010*/
	u32 cbcdr;
	u32 cbcmr;
	u32 cscmr1;
	u32 cscmr2;	/* 0x0020 */
	u32 cscdr1;
	u32 cs1cdr;
	u32 cs2cdr;
	u32 cdcdr;	/* 0x0030 */
	u32 chsccdr;
	u32 cscdr2;
	u32 cscdr3;
	u32 cscdr4;	/* 0x0040 */
	u32 resv0;
	u32 cdhipr;
	u32 cdcr;
	u32 ctor;	/* 0x0050 */
	u32 clpcr;
	u32 cisr;
	u32 cimr;
	u32 ccosr;	/* 0x0060 */
	u32 cgpr;
	u32 CCGR0;
	u32 CCGR1;
	u32 CCGR2;	/* 0x0070 */
	u32 CCGR3;
	u32 CCGR4;
	u32 CCGR5;
	u32 CCGR6;	/* 0x0080 */
	u32 CCGR7;
	u32 cmeor;
	u32 resv[0xfdd];
	u32 analog_pll_sys;			/* 0x4000 */
	u32 analog_pll_sys_set;
	u32 analog_pll_sys_clr;
	u32 analog_pll_sys_tog;
	u32 analog_usb1_pll_480_ctrl;		/* 0x4010 */
	u32 analog_usb1_pll_480_ctrl_set;
	u32 analog_usb1_pll_480_ctrl_clr;
	u32 analog_usb1_pll_480_ctrl_tog;
	u32 analog_usb2_pll_480_ctrl;	/* 0x4020 */
	u32 analog_usb2_pll_480_ctrl_set;
	u32 analog_usb2_pll_480_ctrl_clr;
	u32 analog_usb2_pll_480_ctrl_tog;
	u32 analog_pll_528;			/* 0x4030 */
	u32 analog_pll_528_set;
	u32 analog_pll_528_clr;
	u32 analog_pll_528_tog;
	u32 analog_pll_528_ss;			/* 0x4040 */
	u32 analog_reserved1[3];
	u32 analog_pll_528_num;			/* 0x4050 */
	u32 analog_reserved2[3];
	u32 analog_pll_528_denom;		/* 0x4060 */
	u32 analog_reserved3[3];
	u32 analog_pll_audio;			/* 0x4070 */
	u32 analog_pll_audio_set;
	u32 analog_pll_audio_clr;
	u32 analog_pll_audio_tog;
	u32 analog_pll_audio_num;		/* 0x4080*/
	u32 analog_reserved4[3];
	u32 analog_pll_audio_denom;		/* 0x4090 */
	u32 analog_reserved5[3];
	u32 analog_pll_video;			/* 0x40a0 */
	u32 analog_pll_video_set;
	u32 analog_pll_video_clr;
	u32 analog_pll_video_tog;
	u32 analog_pll_video_num;		/* 0x40b0 */
	u32 analog_reserved6[3];
	u32 analog_pll_video_denom;		/* 0x40c0 */
	u32 analog_reserved7[3];
	u32 analog_pll_mlb;		        /* 0x40d0 */
	u32 analog_pll_mlb_set;
	u32 analog_pll_mlb_clr;
	u32 analog_pll_mlb_tog;
	u32 analog_pll_enet;			/* 0x40e0 */
	u32 analog_pll_enet_set;
	u32 analog_pll_enet_clr;
	u32 analog_pll_enet_tog;
	u32 analog_pfd_480;			/* 0x40f0 */
	u32 analog_pfd_480_set;
	u32 analog_pfd_480_clr;
	u32 analog_pfd_480_tog;
	u32 analog_pfd_528;			/* 0x4100 */
	u32 analog_pfd_528_set;
	u32 analog_pfd_528_clr;
	u32 analog_pfd_528_tog;
	u32 reg_1p1;		/* 0x4110 */
	u32 reg_1p1_set;		/* 0x4114 */
	u32 reg_1p1_clr;		/* 0x4118 */
	u32 reg_1p1_tog;		/* 0x411c */
	u32 reg_3p0;		/* 0x4120 */
	u32 reg_3p0_set;		/* 0x4124 */
	u32 reg_3p0_clr;		/* 0x4128 */
	u32 reg_3p0_tog;		/* 0x412c */
	u32 reg_2p5;		/* 0x4130 */
	u32 reg_2p5_set;		/* 0x4134 */
	u32 reg_2p5_clr;		/* 0x4138 */
	u32 reg_2p5_tog;		/* 0x413c */
	u32 reg_core;		/* 0x4140 */
	u32 reg_core_set;		/* 0x4144 */
	u32 reg_core_clr;		/* 0x4148 */
	u32 reg_core_tog;		/* 0x414c */
	u32 ana_misc0;		/* 0x4150 */
	u32 ana_misc0_set;		/* 0x4154 */
	u32 ana_misc0_clr;		/* 0x4158 */
	u32 ana_misc0_tog;		/* 0x415c */
	u32 ana_misc1;		/* 0x4160 */
	u32 ana_misc1_set;		/* 0x4164 */
	u32 ana_misc1_clr;		/* 0x4168 */
	u32 ana_misc1_tog;		/* 0x416c */
	u32 ana_misc2;		/* 0x4170 */
	u32 ana_misc2_set;		/* 0x4174 */
	u32 ana_misc2_clr;		/* 0x4178 */
	u32 ana_misc2_tog;		/* 0x417c */
	u32 tempsense0;		/* 0x4180 */
	u32 tempsense0_set;		/* 0x4184 */
	u32 tempsense0_clr;		/* 0x4188 */
	u32 tempsense0_tog;		/* 0x418c */
	u32 tempsense1;		/* 0x4190 */
	u32 tempsense1_set;		/* 0x4194 */
	u32 tempsense1_clr;		/* 0x4198 */
	u32 tempsense1_tog;		/* 0x419c */
	u32 usb1_vbus_detect;	/* 0x41a0 */
	u32 usb1_vbus_detect_set;	/* 0x41a4 */
	u32 usb1_vbus_detect_clr;	/* 0x41a8 */
	u32 usb1_vbus_detect_tog;	/* 0x41ac */
	u32 usb1_chrg_detect;	/* 0x41b0 */
	u32 usb1_chrg_detect_set;	/* 0x41b4 */
	u32 usb1_chrg_detect_clr;	/* 0x41b8 */
	u32 usb1_chrg_detect_tog;	/* 0x41bc */
	u32 usb1_vbus_det_stat;	/* 0x41c0 */
	u32 usb1_vbus_det_stat_set;	/* 0x41c4 */
	u32 usb1_vbus_det_stat_clr;	/* 0x41c8 */
	u32 usb1_vbus_det_stat_tog;	/* 0x41cc */
	u32 usb1_chrg_det_stat;	/* 0x41d0 */
	u32 usb1_chrg_det_stat_set;	/* 0x41d4 */
	u32 usb1_chrg_det_stat_clr;	/* 0x41d8 */
	u32 usb1_chrg_det_stat_tog;	/* 0x41dc */
	u32 usb1_loopback;		/* 0x41e0 */
	u32 usb1_loopback_set;	/* 0x41e4 */
	u32 usb1_loopback_clr;	/* 0x41e8 */
	u32 usb1_loopback_tog;	/* 0x41ec */
	u32 usb1_misc;		/* 0x41f0 */
	u32 usb1_misc_set;		/* 0x41f4 */
	u32 usb1_misc_clr;		/* 0x41f8 */
	u32 usb1_misc_tog;		/* 0x41fc */
	u32 usb2_vbus_detect;	/* 0x4200 */
	u32 usb2_vbus_detect_set;	/* 0x4204 */
	u32 usb2_vbus_detect_clr;	/* 0x4208 */
	u32 usb2_vbus_detect_tog;	/* 0x420c */
	u32 usb2_chrg_detect;	/* 0x4210 */
	u32 usb2_chrg_detect_set;	/* 0x4214 */
	u32 usb2_chrg_detect_clr;	/* 0x4218 */
	u32 usb2_chrg_detect_tog;	/* 0x421c */
	u32 usb2_vbus_det_stat;	/* 0x4220 */
	u32 usb2_vbus_det_stat_set;	/* 0x4224 */
	u32 usb2_vbus_det_stat_clr;	/* 0x4228 */
	u32 usb2_vbus_det_stat_tog;	/* 0x422c */
	u32 usb2_chrg_det_stat;	/* 0x4230 */
	u32 usb2_chrg_det_stat_set;	/* 0x4234 */
	u32 usb2_chrg_det_stat_clr;	/* 0x4238 */
	u32 usb2_chrg_det_stat_tog;	/* 0x423c */
	u32 usb2_loopback;		/* 0x4240 */
	u32 usb2_loopback_set;	/* 0x4244 */
	u32 usb2_loopback_clr;	/* 0x4248 */
	u32 usb2_loopback_tog;	/* 0x424c */
	u32 usb2_misc;		/* 0x4250 */
	u32 usb2_misc_set;		/* 0x4254 */
	u32 usb2_misc_clr;		/* 0x4258 */
	u32 usb2_misc_tog;		/* 0x425c */
	u32 digprog;		/* 0x4260 */
	u32 reserved1[7];
	u32 digprog_sololite;	/* 0x4280 */
};
#endif

/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN				(1 << 27)
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK			(0x3F << 21)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET		21
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CCR_WB_COUNT_MASK			0x7
#define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
#endif
#define MXC_CCM_CCR_COSC_EN				(1 << 12)
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP) || defined(CONFIG_MX6UL))
#define MXC_CCM_CCR_OSCNT_MASK				0x7F
#else
#define MXC_CCM_CCR_OSCNT_MASK				0xFF
#endif
#define MXC_CCM_CCR_OSCNT_OFFSET			0

/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
#ifdef CONFIG_MX6QP
#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG	(1 << 18)
#endif

/* Define the bits in register CSR */
#define MXC_CCM_CSR_COSC_READY				(1 << 5)
#define MXC_CCM_CSR_REF_EN_B				(1 << 0)

/* Define the bits in register CCSR */
#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS			(1 << 15)
#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS			(1 << 14)
#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS			(1 << 13)
#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS			(1 << 12)
#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS			(1 << 11)
#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS			(1 << 10)
#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS			(1 << 9)
#define MXC_CCM_CCSR_STEP_SEL				(1 << 8)
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL			(1 << 2)
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL			(1 << 1)
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL			(1 << 0)

#ifdef CONFIG_MX6UL
#define MXC_CCM_CCSR_CA7_SECONDARY_CLK_SEL		(1 << 3)
#endif

/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET			0
#define MXC_CCM_CACRR_ARM_PODF_MASK			0x7

/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK		(0x7 << 27)
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET		27
#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL			(1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(1 << 25)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK		(0x7 << 19)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET		19
#endif
/* To 6SX, 6UL and 6SL OCRAM_PODF is AXI_PODF */
#define MXC_CCM_CBCDR_AXI_PODF_MASK			(0x7 << 16)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET			16
#define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET			10
#define MXC_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET			8
#define MXC_CCM_CBCDR_AXI_ALT_SEL			(1 << 7)
#define MXC_CCM_CBCDR_AXI_SEL				(1 << 6)
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK		(0x7 << 3)
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET		3
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK		(0x7 << 0)
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET		0

/* Define the bits in register CBCMR */
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#ifndef CONFIG_MX6UL
#define MXC_CCM_CBCMR_GPU_CORE_PODF_MASK		(0x7 << 29)
#define MXC_CCM_CBCMR_GPU_CORE_PODF_OFFSET		29
#define MXC_CCM_CBCMR_GPU_AXI_PODF_MASK		(0x7 << 26)
#define MXC_CCM_CBCMR_GPU_AXI_PODF_OFFSET		26
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)
#define MXC_CCM_CBCMR_GPU_AXI_CLK_SEL_MASK		(0x3 << 8)
#define MXC_CCM_CBCMR_GPU_AXI_CLK_SEL_OFFSET		8
#define MXC_CCM_CBCMR_GPU_CORE_CLK_SEL_MASK		(0x3 << 4)
#define MXC_CCM_CBCMR_GPU_CORE_CLK_SEL_OFFSET		4
#endif
#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK		(0x7 << 23)
#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET		23
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		18
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		12
#else
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK		(0x7 << 29)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL		(1 << 20)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		18
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		16
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		12
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL			(1 << 11)
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK		(0x3 << 8)
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
#ifdef CONFIG_MX6QP
#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
#else
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
#endif
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
#endif

/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET		29
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK			(0x7 << 26)
#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET		26
#else
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK			(0x3 << 27)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			27
#endif
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	23
/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
#ifndef CONFIG_MX6UL
#if defined(CONFIG_MX6SX)
#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK		(0x7 << 20)
#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET		20
#else
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
#endif
#endif

#ifdef CONFIG_MX6UL
#define MXC_CCM_CSCMR1_GPMI_CLK_SEL			(1 << 19)
#define MXC_CCM_CSCMR1_BCH_CLK_SEL			(1 << 18)
#else
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL			(1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL			(1 << 18)
#endif
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL			(1 << 17)
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL			(1 << 16)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK		(0x3 << 14)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET		14
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		10
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
#endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || \
	defined(CONFIG_MX6QP) || defined(CONFIG_MX6UL))
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK			(1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
#endif
#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F

/* Define the bits in register CSCMR2 */
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CSCMR2_VID_CLK_PODF_MASK		(0x7 << 26)
#define MXC_CCM_CSCMR2_VID_CLK_PODF_OFFSET		26
#define MXC_CCM_CSCMR2_VID_CLK_PRE_PODF_MASK		(0x3 << 24)
#define MXC_CCM_CSCMR2_VID_CLK_PRE_PODF_OFFSET		24
#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK			(0x7 << 21)
#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET		21
#endif
#ifndef CONFIG_MX6UL
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
#endif
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP) || defined(CONFIG_MX6UL))
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
#endif
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2

/* Define the bits in register CSCDR1 */
#ifndef CONFIG_MX6SX
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		25
#endif
#ifdef CONFIG_MX6UL
#define MXC_CCM_CSCDR1_GPMI_PODF_MASK			(0x7 << 22)
#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET			22
#define MXC_CCM_CSCDR1_BCH_PODF_MASK			(0x7 << 19)
#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET			19
#else
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK			(0x7 << 22)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET		22
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK			(0x7 << 19)
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET		19
#endif
#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK			(0x7 << 16)
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET		16
#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK			(0x7 << 11)
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET		11
#ifndef CONFIG_MX6SX
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
#endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || \
	defined(CONFIG_MX6QP) || defined(CONFIG_MX6UL))
#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
#endif
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0

/* Define the bits in register CS1CDR */
#ifndef CONFIG_MX6UL
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET		25
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK		(0x3 << 9)
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET		9
#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK		(0x7 << 22)
#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET		22
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK		(0x3F << 16)
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET		16
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		6
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		0x3F
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		0
#else
#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK		(0x7 << 22)
#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET		22
#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK		(0x3F << 16)
#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET		16
#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK		(0x7 << 6)
#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET		6
#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK		0x3F
#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET		0
#endif

/* Define the bits in register CS2CDR */
#ifdef CONFIG_MX6SX
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << 21)
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                       (((v) & 0x3f) << 21)
#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK             (0x7 << 18)
#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET           18
#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                       (((v) & 0x7) << 18)
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK              (0x7 << 15)
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET            15
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << 15)
#else
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		21
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)			(((v) & 0x3f) << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)

#if defined(CONFIG_MX6QP) || defined(CONFIG_MX6UL)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x7 << 15)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		15
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x7) << 15)
#else
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
#endif
#endif
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET		9
#ifdef CONFIG_MX6UL
#define MXC_CCM_CS2CDR_SAI2_CLK_PRED_MASK		(0x7 << 6)
#define MXC_CCM_CS2CDR_SAI2_CLK_PRED_OFFSET		6
#define MXC_CCM_CS2CDR_SAI2_CLK_PODF_MASK		0x3F
#define MXC_CCM_CS2CDR_SAI2_CLK_PODF_OFFSET		0
#else
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		6
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK		0x3F
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		0
#endif

/* Define the bits in register CDCDR */
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK			(0x7 << 29)
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET		29
#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL			(1 << 28)
#endif
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		25
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x7 << 22)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		22
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK		(0x3 << 20)
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET		20
#ifndef CONFIG_MX6UL
#ifdef CONFIG_MX6SX
#define MXC_CCM_CDCDR_AUDIO_CLK_PRED_MASK		(0x7 << 12)
#define MXC_CCM_CDCDR_AUDIO_CLK_PRED_OFFSET		12
#define MXC_CCM_CDCDR_AUDIO_CLK_PODF_MASK		(0x7 << 9)
#define MXC_CCM_CDCDR_AUDIO_CLK_PODF_OFFSET		9
#define MXC_CCM_CDCDR_AUDIO_CLK_SEL_MASK		(0x3 << 7)
#define MXC_CCM_CDCDR_AUDIO_CLK_SEL_OFFSET		7
#else
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 12)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		12
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x7 << 9)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		9
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK		(0x3 << 7)
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET		7
#endif
#endif

/* Define the bits in register CHSCCDR */
#ifdef CONFIG_MX6UL
#define MXC_CCM_CHSCCDR_SIM_PRE_CLK_SEL_MASK		(0x7 << 15)
#define MXC_CCM_CHSCCDR_SIM_PRE_CLK_SEL_OFFSET		15
#define MXC_CCM_CHSCCDR_SIM_PODF_MASK			(0x7 << 12)
#define MXC_CCM_CHSCCDR_SIM_PODF_OFFSET			12
#define MXC_CCM_CHSCCDR_SIM_CLK_SEL_MASK		(0x7 << 9)
#define MXC_CCM_CHSCCDR_SIM_CLK_SEL_OFFSET		9
#elif defined(CONFIG_MX6SX)
#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK		(0x7 << 15)
#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET		15
#define MXC_CCM_CHSCCDR_ENET_PODF_MASK			(0x7 << 12)
#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET		12
#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK		(0x7 << 9)
#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET		9
#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK		(0x7 << 6)
#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET		6
#define MXC_CCM_CHSCCDR_M4_PODF_MASK			(0x7 << 3)
#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET			3
#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK			(0x7)
#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET		0
#else
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET	15
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK		(0x7 << 12)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET		12
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK		(0x7 << 9)
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET		9
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET	6
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET		3
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		0
#endif

#define CHSCCDR_CLK_SEL_LDB_DI0				3
#define CHSCCDR_PODF_DIVIDE_BY_3			2
#define CHSCCDR_IPU_PRE_CLK_540M_PFD			5

/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
#if defined(CONFIG_MX6QP) || defined(CONFIG_MX6SX) || \
	defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL)
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET		18
#endif

#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK		(0x7 << 15)
#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET	15
#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK		(0x7 << 12)
#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET	12
#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK		(0x7 << 9)
#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET	9
#endif
#ifdef CONFIG_MX6SX
#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK		(0x7 << 6)
#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET	6
#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK		(0x7 << 3)
#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET	3
#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK		(0x7 << 0)
#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET	0
#endif

#ifdef CONFIG_MX6UL
#define MXC_CCM_CSCDR3_CSI_PODF_MASK		(0x7 << 11)
#define MXC_CCM_CSCDR3_CSI_PODF_OFFSET		11
#define MXC_CCM_CSCDR3_CSI_CLK_SEL_MASK		(0x3 << 9)
#define MXC_CCM_CSCDR3_CSI_CLK_SEL_OFFSET	9
#else
/* All IPU2_DI1 are LCDIF1 on MX6SX */
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK		(0x7 << 12)
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET		12
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET		9
/* All IPU2_DI0 are LCDIF2 on MX6SX */
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET	6
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK		(0x7 << 3)
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		3
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		0x7
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		0

/* Define the bits in register CSCDR3 */
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET		16
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK		(0x3 << 14)
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET		14
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK		(0x7 << 11)
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET		11
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK		(0x3 << 9)
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET		9
#endif

/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY		(1 << 4)
#endif
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		(1 << 3)
#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6SX)
#define MXC_CCM_CDHIPR_MMDC_PODF_BUSY			(1 << 2)
#else
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY		(1 << 2)
#endif
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 1)
#define MXC_CCM_CDHIPR_AXI_PODF_BUSY			1

/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE			(1 << 27)
#define MXC_CCM_CLPCR_MASK_SCU_IDLE			(1 << 26)
#if !defined(CONFIG_MX6SX) || !defined(CONFIG_MX6UL)
#define MXC_CCM_CLPCR_MASK_CORE3_WFI			(1 << 25)
#define MXC_CCM_CLPCR_MASK_CORE2_WFI			(1 << 24)
#define MXC_CCM_CLPCR_MASK_CORE1_WFI			(1 << 23)
#endif
#define MXC_CCM_CLPCR_MASK_CORE0_WFI			(1 << 22)
#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 16)
#endif
#define MXC_CCM_CLPCR_COSC_PWRDOWN			(1 << 11)
#define MXC_CCM_CLPCR_STBY_COUNT_MASK			(0x3 << 9)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET			9
#define MXC_CCM_CLPCR_VSTBY				(1 << 8)
#define MXC_CCM_CLPCR_DIS_REF_OSC			(1 << 7)
#define MXC_CCM_CLPCR_SBYOS				(1 << 6)
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(1 << 5)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK			(0x3 << 3)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		3
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(1 << 2)
#endif
#define MXC_CCM_CLPCR_LPM_MASK				0x3
#define MXC_CCM_CLPCR_LPM_OFFSET			0

/* Define the bits in register CISR */
#define MXC_CCM_CISR_ARM_PODF_LOADED			(1 << 26)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED		(1 << 23)
#endif
#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED		(1 << 22)
#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED		(1 << 21)
#define MXC_CCM_CISR_AHB_PODF_LOADED			(1 << 20)
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED		(1 << 19)
#define MXC_CCM_CISR_AXI_PODF_LOADED			(1 << 17)
#define MXC_CCM_CISR_COSC_READY				(1 << 6)
#define MXC_CCM_CISR_LRF_PLL				1

/* Define the bits in register CIMR */
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(1 << 26)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED		(1 << 23)
#endif
#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED		(1 << 22)
#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED		(1 << 21)
#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED		(1 << 20)
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED	(1 << 19)
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED		(1 << 17)
#define MXC_CCM_CIMR_MASK_COSC_READY			(1 << 6)
#define MXC_CCM_CIMR_MASK_LRF_PLL			1

/* Define the bits in register CCOSR */
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET			(1 << 24)
#define MXC_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			21
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			16
#define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
#define MXC_CCM_CCOSR_CLK_OUT_SEL			(0x1 << 8)
#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			4
#define MXC_CCM_CCOSR_CKOL_SEL_MASK			0xF
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			0

/* Define the bits in registers CGPR */
#ifdef CONFIG_MX6UL
#define MXC_CCM_CGPR_INT_MEM_CLK_LPM			(1 << 17)
#define MXC_CCM_CGPR_SYS_MEM_DS_CTRL_OFFSET		14
#define MXC_CCM_CGPR_SYS_MEM_DS_CTRL_MASK		(3 << 14)
#endif
#define MXC_CCM_CGPR_FAST_PLL_EN			(1 << 16)
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
#define MXC_CCM_CGPR_PMIC_DELAY_SCALER			1

/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK				3

#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			0
#define MXC_CCM_CCGR0_AIPS_TZ1_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			2
#define MXC_CCM_CCGR0_AIPS_TZ2_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
#define MXC_CCM_CCGR0_APBHDMA_OFFSET			4
#define MXC_CCM_CCGR0_APBHDMA_MASK			(3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
#define MXC_CCM_CCGR0_ASRC_OFFSET			6
#define MXC_CCM_CCGR0_ASRC_MASK				(3 << MXC_CCM_CCGR0_ASRC_OFFSET)
#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET		8
#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK		(3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET		10
#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET		12
#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
#define MXC_CCM_CCGR0_CAN1_OFFSET			14
#define MXC_CCM_CCGR0_CAN1_MASK				(3 << MXC_CCM_CCGR0_CAN1_OFFSET)
#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET		16
#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
#define MXC_CCM_CCGR0_CAN2_OFFSET			18
#define MXC_CCM_CCGR0_CAN2_MASK				(3 << MXC_CCM_CCGR0_CAN2_OFFSET)
#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET		20
#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET		22
#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK		(3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
#define MXC_CCM_CCGR0_DCIC1_OFFSET			24
#define MXC_CCM_CCGR0_DCIC1_MASK			(3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR0_GPT2_SERIAL_CLK_OFFSET		26
#define MXC_CCM_CCGR0_GPT2_SERIAL_CLK_MASK		(3 << MXC_CCM_CCGR0_GPT2_SERIAL_CLK_OFFSET)
#define MXC_CCM_CCGR0_UART2_CLK_ENABLE_OFFSET		28
#define MXC_CCM_CCGR0_UART2_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR0_UART2_CLK_ENABLE_OFFSET)
#else
#define MXC_CCM_CCGR0_DCIC2_OFFSET			26
#define MXC_CCM_CCGR0_DCIC2_MASK			(3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
#endif
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET			30
#define MXC_CCM_CCGR0_AIPS_TZ3_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
#else
#define MXC_CCM_CCGR0_DTCP_OFFSET			28
#define MXC_CCM_CCGR0_DTCP_MASK				(3 << MXC_CCM_CCGR0_DTCP_OFFSET)
#endif

#define MXC_CCM_CCGR1_ECSPI1S_OFFSET			0
#define MXC_CCM_CCGR1_ECSPI1S_MASK			(3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI2S_OFFSET			2
#define MXC_CCM_CCGR1_ECSPI2S_MASK			(3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI3S_OFFSET			4
#define MXC_CCM_CCGR1_ECSPI3S_MASK			(3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI4S_OFFSET			6
#define MXC_CCM_CCGR1_ECSPI4S_MASK			(3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR1_ADC2_OFFSET			8
#define MXC_CCM_CCGR1_ADC2_MASK				(3 << MXC_CCM_CCGR1_ADC2_OFFSET)
#else
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET			8
#define MXC_CCM_CCGR1_ECSPI5S_MASK			(3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
#endif
#ifndef CONFIG_MX6SX
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR1_UART3_CLK_ENABLE_OFFSET		10
#define MXC_CCM_CCGR1_UART3_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_UART3_CLK_ENABLE_OFFSET)
#else
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET		10
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
#endif
#endif
#define MXC_CCM_CCGR1_EPIT1S_OFFSET			12
#define MXC_CCM_CCGR1_EPIT1S_MASK			(3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
#define MXC_CCM_CCGR1_EPIT2S_OFFSET			14
#define MXC_CCM_CCGR1_EPIT2S_MASK			(3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
#ifndef CONFIG_MX6UL
#define MXC_CCM_CCGR1_ESAIS_OFFSET			16
#define MXC_CCM_CCGR1_ESAIS_MASK			(3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
#endif
#ifdef CONFIG_MX6SX
#define MXC_CCM_CCGR1_WAKEUP_OFFSET			18
#define MXC_CCM_CCGR1_WAKEUP_MASK			(3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
#elif defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR1_SIM_S_OFFSET			18
#define MXC_CCM_CCGR1_SIM_S_MASK			(3 << MXC_CCM_CCGR1_SIM_S_OFFSET)
#endif
#define MXC_CCM_CCGR1_GPT_BUS_OFFSET			20
#define MXC_CCM_CCGR1_GPT_BUS_MASK			(3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET			22
#define MXC_CCM_CCGR1_GPT_SERIAL_MASK			(3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
#ifndef CONFIG_MX6SX
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR1_UART4_CLK_ENABLE_OFFSET		24
#define MXC_CCM_CCGR1_UART4_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_UART4_CLK_ENABLE_OFFSET)
#else
#define MXC_CCM_CCGR1_GPU2D_OFFSET			24
#define MXC_CCM_CCGR1_GPU2D_MASK			(3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
#endif
#endif
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR1_GPIO1_CLK_ENABLE_OFFSET		26
#define MXC_CCM_CCGR1_GPIO1_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_GPIO1_CLK_ENABLE_OFFSET)
#else
#define MXC_CCM_CCGR1_GPU3D_OFFSET			26
#define MXC_CCM_CCGR1_GPU3D_MASK			(3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
#endif
#ifdef CONFIG_MX6SX
#define MXC_CCM_CCGR1_OCRAM_S_OFFSET			28
#define MXC_CCM_CCGR1_OCRAM_S_MASK			(3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
#define MXC_CCM_CCGR1_CANFD_OFFSET			30
#define MXC_CCM_CCGR1_CANFD_MASK			(3 << MXC_CCM_CCGR1_CANFD_OFFSET)
#elif defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR1_CSU_CLK_ENABLE_OFFSET		28
#define MXC_CCM_CCGR1_CSU_CLK_ENABLE_MASK		3 << (MXC_CCM_CCGR1_CSU_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR1_GPIO5_CLK_ENABLE_OFFSET		30
#define MXC_CCM_CCGR1_GPIO5_CLK_ENABLE_MASK		3 << (MXC_CCM_CCGR1_GPIO5_CLK_ENABLE_OFFSET)
#endif

#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET		0
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
#else
#define MXC_CCM_CCGR2_CSI_OFFSET			2
#define MXC_CCM_CCGR2_CSI_MASK				(3 << MXC_CCM_CCGR2_CSI_OFFSET)
#endif
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET		4
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
#endif
#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET		6
#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET		8
#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET		10
#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET			12
#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
#define MXC_CCM_CCGR2_IPMUX1_OFFSET			16
#define MXC_CCM_CCGR2_IPMUX1_MASK			(3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
#define MXC_CCM_CCGR2_IPMUX2_OFFSET			18
#define MXC_CCM_CCGR2_IPMUX2_MASK			(3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
#define MXC_CCM_CCGR2_IPMUX3_OFFSET			20
#define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR2_GPIO3_CLK_ENABLE_OFFSET		26
#define MXC_CCM_CCGR2_GPIO3_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR2_GPIO3_CLK_ENABLE_OFFSET)
#endif
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR2_LCD_OFFSET			28
#define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
#define MXC_CCM_CCGR2_PXP_OFFSET			30
#define MXC_CCM_CCGR2_PXP_MASK				(3 << MXC_CCM_CCGR2_PXP_OFFSET)
#else
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET	24
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET	26
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
#endif

#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR3_UART5_CLK_ENABLE_OFFSET			2
#define MXC_CCM_CCGR3_UART5_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_UART5_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR3_ENET_CLK_ENABLE_OFFSET			4
#define MXC_CCM_CCGR3_ENET_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_ENET_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR3_UART6_CLK_ENABLE_OFFSET			6
#define MXC_CCM_CCGR3_UART6_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_UART6_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR3_UART6_CLK_ENABLE_OFFSET			6
#define MXC_CCM_CCGR3_UART6_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_UART6_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET				8
#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET				10
#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
#elif defined(CONFIG_MX6SX)
#define MXC_CCM_CCGR3_M4_OFFSET					2
#define MXC_CCM_CCGR3_M4_MASK					(3 << MXC_CCM_CCGR3_M4_OFFSET)
#define MXC_CCM_CCGR3_ENET_OFFSET				4
#define MXC_CCM_CCGR3_ENET_MASK					(3 << MXC_CCM_CCGR3_ENET_OFFSET)
#define MXC_CCM_CCGR3_QSPI_OFFSET				14
#define MXC_CCM_CCGR3_QSPI_MASK					(3 << MXC_CCM_CCGR3_QSPI_OFFSET)
#define MXC_CCM_CCGR3_DISP_AXI_OFFSET			6
#define MXC_CCM_CCGR3_DISP_AXI_MASK				(3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET				8
#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET				10
#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
#else
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
#define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET			2
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET			4
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET				6
#define MXC_CCM_CCGR3_IPU2_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET			8
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET			10
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
#endif
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET				12
#define MXC_CCM_CCGR3_LDB_DI0_MASK				(3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR3_QSPI1_OFFSET				14
#define MXC_CCM_CCGR3_QSPI1_MASK				(3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
#else
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET				14
#define MXC_CCM_CCGR3_LDB_DI1_MASK				(3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET			16
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK			(3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
#endif
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET			16
#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
#endif
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET			18
#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK			(3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
#else
#define MXC_CCM_CCGR3_MLB_OFFSET				18
#define MXC_CCM_CCGR3_MLB_MASK					(3 << MXC_CCM_CCGR3_MLB_OFFSET)
#endif
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET	20
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET	22
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
#endif
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET		24
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR3_AXI_CLK_OFFSET				28
#define MXC_CCM_CCGR3_AXI_CLK_MASK				(3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
#else
#define MXC_CCM_CCGR3_OCRAM_OFFSET				28
#define MXC_CCM_CCGR3_OCRAM_MASK				(3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
#endif
#ifndef CONFIG_MX6SX
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET				30
#define MXC_CCM_CCGR3_GPIO4_CLK_MASK				(3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
#else
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET			30
#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
#endif
#endif

#define MXC_CCM_CCGR4_PCIE_OFFSET				0
#define MXC_CCM_CCGR4_PCIE_MASK					(3 << MXC_CCM_CCGR4_PCIE_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR4_IOMUX_OFFSET				2
#define MXC_CCM_CCGR4_IOMUX_MASK				(3 << MXC_CCM_CCGR4_IOMUX_OFFSET)
#define MXC_CCM_CCGR4_IOMUX_GPR_OFFSET				4
#define MXC_CCM_CCGR4_IOMUX_GPR_MASK				(3 << MXC_CCM_CCGR4_IOMUX_GPR_OFFSET)
#define MXC_CCM_CCGR4_SIM_CPU_OFFSET				6
#define MXC_CCM_CCGR4_SIM_CPU_MASK				(3 << MXC_CCM_CCGR4_SIM_CPU_OFFSET)
#define MXC_CCM_CCGR4_CXAPBSYNCBRIDGE_OFFSET			8
#define MXC_CCM_CCGR4_CXAPBSYNCBRIDGE_MASK			(3 << MXC_CCM_CCGR4_CXAPBSYNCBRIDGE_OFFSET)
#elif defined(CONFIG_MX6SX)
#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET				10
#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK				(3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
#else
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET		8
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
#endif
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET			12
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET	14
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK	(3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR4_PWM1_OFFSET				16
#define MXC_CCM_CCGR4_PWM1_MASK					(3 << MXC_CCM_CCGR4_PWM1_OFFSET)
#define MXC_CCM_CCGR4_PWM2_OFFSET				18
#define MXC_CCM_CCGR4_PWM2_MASK					(3 << MXC_CCM_CCGR4_PWM2_OFFSET)
#define MXC_CCM_CCGR4_PWM3_OFFSET				20
#define MXC_CCM_CCGR4_PWM3_MASK					(3 << MXC_CCM_CCGR4_PWM3_OFFSET)
#define MXC_CCM_CCGR4_PWM4_OFFSET				22
#define MXC_CCM_CCGR4_PWM4_MASK					(3 << MXC_CCM_CCGR4_PWM4_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET		24
#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET	26
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET	28
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK	(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET		30
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)

#define MXC_CCM_CCGR5_ROM_OFFSET			0
#define MXC_CCM_CCGR5_ROM_MASK				(3 << MXC_CCM_CCGR5_ROM_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR5_STCR_OFFSET			2
#define MXC_CCM_CCGR5_STCR_MASK				(3 << MXC_CCM_CCGR5_STCR_OFFSET)
#define MXC_CCM_CCGR5_SNVS_OFFSET			4
#define MXC_CCM_CCGR5_SNVS_MASK				(3 << MXC_CCM_CCGR5_SNVS_OFFSET)
#endif
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6UL)
#define MXC_CCM_CCGR5_SATA_OFFSET			4
#define MXC_CCM_CCGR5_SATA_MASK				(3 << MXC_CCM_CCGR5_SATA_OFFSET)
#endif
#define MXC_CCM_CCGR5_SDMA_OFFSET			6
#define MXC_CCM_CCGR5_SDMA_MASK				(3 << MXC_CCM_CCGR5_SDMA_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR5_KPP_OFFSET			8
#define MXC_CCM_CCGR5_KPP_MASK				(3 << MXC_CCM_CCGR5_KPP_OFFSET)
#define MXC_CCM_CCGR5_WDOG2_OFFSET			10
#define MXC_CCM_CCGR5_WDOG2_MASK			(3 << MXC_CCM_CCGR5_WDOG2_OFFSET)
#endif
#define MXC_CCM_CCGR5_SPBA_OFFSET			12
#define MXC_CCM_CCGR5_SPBA_MASK				(3 << MXC_CCM_CCGR5_SPBA_OFFSET)
#define MXC_CCM_CCGR5_SPDIF_OFFSET			14
#define MXC_CCM_CCGR5_SPDIF_MASK			(3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR5_SIM_MAIN_OFFSET			16
#define MXC_CCM_CCGR5_SIM_MAIN_MASK			(3 << MXC_CCM_CCGR5_SIM_MAIN_OFFSET)
#define MXC_CCM_CCGR5_SNVS_HP_OFFSET			18
#define MXC_CCM_CCGR5_SNVS_HP_MASK			(3 << MXC_CCM_CCGR5_SNVS_HP_OFFSET)
#define MXC_CCM_CCGR5_SNVS_LP_OFFSET			20
#define MXC_CCM_CCGR5_SNVS_LP_MASK			(3 << MXC_CCM_CCGR5_SNVS_LP_OFFSET)
#define MXC_CCM_CCGR5_SAI3_OFFSET			22
#define MXC_CCM_CCGR5_SAI3_MASK				(3 << MXC_CCM_CCGR5_SAI3_OFFSET)
#define MXC_CCM_CCGR5_UART1_OFFSET			24
#define MXC_CCM_CCGR5_UART1_MASK			(3 << MXC_CCM_CCGR5_UART1_OFFSET)
#define MXC_CCM_CCGR5_UART7_OFFSET			26
#define MXC_CCM_CCGR5_UART7_MASK			(3 << MXC_CCM_CCGR5_UART7_OFFSET)
#define MXC_CCM_CCGR5_SAI1_OFFSET			28
#define MXC_CCM_CCGR5_SAI1_MASK				(3 << MXC_CCM_CCGR5_SAI1_OFFSET)
#define MXC_CCM_CCGR5_SAI2_OFFSET			30
#define MXC_CCM_CCGR5_SAI2_MASK				(3 << MXC_CCM_CCGR5_SAI2_OFFSET)
#else
#define MXC_CCM_CCGR5_SSI1_OFFSET			18
#define MXC_CCM_CCGR5_SSI1_MASK				(3 << MXC_CCM_CCGR5_SSI1_OFFSET)
#define MXC_CCM_CCGR5_SSI2_OFFSET			20
#define MXC_CCM_CCGR5_SSI2_MASK				(3 << MXC_CCM_CCGR5_SSI2_OFFSET)
#define MXC_CCM_CCGR5_SSI3_OFFSET			22
#define MXC_CCM_CCGR5_SSI3_MASK				(3 << MXC_CCM_CCGR5_SSI3_OFFSET)
#define MXC_CCM_CCGR5_UART_OFFSET			24
#define MXC_CCM_CCGR5_UART_MASK				(3 << MXC_CCM_CCGR5_UART_OFFSET)
#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET		26
#define MXC_CCM_CCGR5_UART_SERIAL_MASK			(3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
#endif
#ifdef CONFIG_MX6SX
#define MXC_CCM_CCGR5_SAI1_OFFSET			20
#define MXC_CCM_CCGR5_SAI1_MASK				(3 << MXC_CCM_CCGR5_SAI1_OFFSET)
#define MXC_CCM_CCGR5_SAI2_OFFSET			30
#define MXC_CCM_CCGR5_SAI2_MASK				(3 << MXC_CCM_CCGR5_SAI2_OFFSET)
#endif

#define MXC_CCM_CCGR6_USBOH3_OFFSET		0
#define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
#define MXC_CCM_CCGR6_USDHC1_OFFSET		2
#define MXC_CCM_CCGR6_USDHC1_MASK		(3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET		4
#define MXC_CCM_CCGR6_USDHC2_MASK		(3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR6_BCH_OFFSET		6
#define MXC_CCM_CCGR6_BCH_MASK			(3 << MXC_CCM_CCGR6_BCH_OFFSET)
#define MXC_CCM_CCGR6_GPMI_OFFSET		8
#define MXC_CCM_CCGR6_GPMI_MASK			(3 << MXC_CCM_CCGR6_GPMI_OFFSET)
#else
#define MXC_CCM_CCGR6_USDHC3_OFFSET		6
#define MXC_CCM_CCGR6_USDHC3_MASK		(3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
#define MXC_CCM_CCGR6_USDHC4_OFFSET		8
#define MXC_CCM_CCGR6_USDHC4_MASK		(3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
#endif
#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET		10
#define MXC_CCM_CCGR6_EMI_SLOW_MASK		(3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
#ifdef CONFIG_MX6UL
#define MXC_CCM_CCGR6_PWM8_OFFSET		16
#define MXC_CCM_CCGR6_PWM8_MASK			(3 << MXC_CCM_CCGR6_PWM8_OFFSET)
#define MXC_CCM_CCGR6_WDOG3_OFFSET		20
#define MXC_CCM_CCGR6_WDOG3_MASK		(3 << MXC_CCM_CCGR6_WDOG3_OFFSET)
#define MXC_CCM_CCGR6_ANADIG_OFFSET		22
#define MXC_CCM_CCGR6_ANADIG_MASK		(3 << MXC_CCM_CCGR6_ANADIG_OFFSET)
#define MXC_CCM_CCGR6_I2C4_SERIAL_OFFSET	24
#define MXC_CCM_CCGR6_I2C4_SERIAL_MASK		(3 << MXC_CCM_CCGR6_I2C4_SERIAL_OFFSET)
#define MXC_CCM_CCGR6_PWM5_OFFSET		26
#define MXC_CCM_CCGR6_PWM5_MASK			(3 << MXC_CCM_CCGR6_PWM5_OFFSET)
#define MXC_CCM_CCGR6_PWM6_OFFSET		28
#define MXC_CCM_CCGR6_PWM6_MASK			(3 << MXC_CCM_CCGR6_PWM6_OFFSET)
#define MXC_CCM_CCGR6_PWM7_OFFSET		30
#define MXC_CCM_CCGR6_PWM7_MASK			(3 << MXC_CCM_CCGR6_PWM7_OFFSET)
#elif defined(CONFIG_MX6SX)
#define MXC_CCM_CCGR6_PWM8_OFFSET		16
#define MXC_CCM_CCGR6_PWM8_MASK			(3 << MXC_CCM_CCGR6_PWM8_OFFSET)
#define MXC_CCM_CCGR6_VADC_OFFSET		20
#define MXC_CCM_CCGR6_VADC_MASK			(3 << MXC_CCM_CCGR6_VADC_OFFSET)
#define MXC_CCM_CCGR6_GIS_OFFSET		22
#define MXC_CCM_CCGR6_GIS_MASK			(3 << MXC_CCM_CCGR6_GIS_OFFSET)
#define MXC_CCM_CCGR6_I2C4_SERIAL_OFFSET	24
#define MXC_CCM_CCGR6_I2C4_SERIAL_MASK		(3 << MXC_CCM_CCGR6_I2C4_SERIAL_OFFSET)
#define MXC_CCM_CCGR6_PWM5_OFFSET		26
#define MXC_CCM_CCGR6_PWM5_MASK			(3 << MXC_CCM_CCGR6_PWM5_OFFSET)
#define MXC_CCM_CCGR6_PWM6_OFFSET		28
#define MXC_CCM_CCGR6_PWM6_MASK			(3 << MXC_CCM_CCGR6_PWM6_OFFSET)
#define MXC_CCM_CCGR6_PWM7_OFFSET		30
#define MXC_CCM_CCGR6_PWM7_MASK			(3 << MXC_CCM_CCGR6_PWM7_OFFSET)
#else
#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
#define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
#ifdef CONFIG_MX6QP
#define MXC_CCM_CCGR6_VPUCLK_OFFSET		14
#define MXC_CCM_CCGR6_VPUCLK_MASK		(3 << MXC_CCM_CCGR6_VPUCLK_OFFSET)
#define MXC_CCM_CCGR6_PRE_CLK0_OFFSET		16
#define MXC_CCM_CCGR6_PRE_CLK0_MASK		(3 << MXC_CCM_CCGR6_PRE_CLK0_OFFSET)
#define MXC_CCM_CCGR6_PRE_CLK1_OFFSET		18
#define MXC_CCM_CCGR6_PRE_CLK1_MASK		(3 << MXC_CCM_CCGR6_PRE_CLK1_OFFSET)
#define MXC_CCM_CCGR6_PRE_CLK2_OFFSET		20
#define MXC_CCM_CCGR6_PRE_CLK2_MASK		(3 << MXC_CCM_CCGR6_PRE_CLK2_OFFSET)
#define MXC_CCM_CCGR6_PRE_CLK3_OFFSET		22
#define MXC_CCM_CCGR6_PRE_CLK3_MASK		(3 << MXC_CCM_CCGR6_PRE_CLK3_OFFSET)
#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET		24
#define MXC_CCM_CCGR6_PRG_CLK0_MASK		(3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
#define MXC_CCM_CCGR6_PRG_CLK1_OFFSET		26
#define MXC_CCM_CCGR6_PRG_CLK1_MASK		(3 << MXC_CCM_CCGR6_PRG_CLK1_OFFSET)
#endif
#endif

#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
#define BP_ANADIG_PLL_SYS_RSVD0      20
#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
#define BF_ANADIG_PLL_SYS_RSVD0(v)  \
	(((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
#ifndef CONFIG_MX6UL
#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
#endif
#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \
	(((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \
	(((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)

#define HW_ANADIG_USB1_PLL_480_CTRL (0x00000010)
#define HW_ANADIG_USB1_PLL_480_CTRL_SET (0x00000014)
#define HW_ANADIG_USB1_PLL_480_CTRL_CLR (0x00000018)
#define HW_ANADIG_USB1_PLL_480_CTRL_TOG (0x0000001c)

#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1      17
#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \
	(((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \
	(((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \
	(((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \
	(((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)

#define BM_ANADIG_PLL_528_LOCK 0x80000000
#define BP_ANADIG_PLL_528_RSVD1      19
#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
#define BF_ANADIG_PLL_528_RSVD1(v)  \
	(((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_528_BYPASS 0x00010000
#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \
	(((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
#define BM_ANADIG_PLL_528_ENABLE 0x00002000
#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
#define BP_ANADIG_PLL_528_RSVD0      1
#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
#define BF_ANADIG_PLL_528_RSVD0(v)  \
	(((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001

#define BP_ANADIG_PLL_528_SS_STOP      16
#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
#define BF_ANADIG_PLL_528_SS_STOP(v) \
	(((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
#define BP_ANADIG_PLL_528_SS_STEP      0
#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
#define BF_ANADIG_PLL_528_SS_STEP(v)  \
	(((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)

#define BP_ANADIG_PLL_528_NUM_RSVD0      30
#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
	(((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
#define BP_ANADIG_PLL_528_NUM_A      0
#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
#define BF_ANADIG_PLL_528_NUM_A(v)  \
	(((v) << 0) & BM_ANADIG_PLL_528_NUM_A)

#define BP_ANADIG_PLL_528_DENOM_RSVD0      30
#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
	(((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
#define BP_ANADIG_PLL_528_DENOM_B      0
#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
#define BF_ANADIG_PLL_528_DENOM_B(v)  \
	(((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)

#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
#define BP_ANADIG_PLL_AUDIO_RSVD0      22
#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
#define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \
	(((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \
	(((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \
	(((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \
	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)

#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0      30
#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
	(((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
#define BP_ANADIG_PLL_AUDIO_NUM_A      0
#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \
	(((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)

#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0      30
#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
	(((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \
	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)

#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
#define BP_ANADIG_PLL_VIDEO_RSVD0      22
#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
#define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
	(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  \
	(((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \
	(((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \
	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)

#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0      30
#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
	(((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
#define BP_ANADIG_PLL_VIDEO_NUM_A      0
#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \
	(((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)

#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0      30
#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
	(((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \
	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)

#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
#define BP_ANADIG_PLL_ENET_RSVD1      21
#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
#define BF_ANADIG_PLL_ENET_RSVD1(v)  \
	(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \
	(((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
#define BP_ANADIG_PLL_ENET_RSVD0      2
#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
#define BF_ANADIG_PLL_ENET_RSVD0(v)  \
	(((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)

#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
	(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)

#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
#define BP_ANADIG_PFD_480_PFD3_FRAC      24
#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \
	(((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
#define BP_ANADIG_PFD_480_PFD2_FRAC      16
#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \
	(((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
#define BP_ANADIG_PFD_480_PFD1_FRAC      8
#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \
	(((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
#define BP_ANADIG_PFD_480_PFD0_FRAC      0
#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \
	(((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)

#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
#define BP_ANADIG_PFD_528_PFD3_FRAC      24
#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \
	(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
#define BP_ANADIG_PFD_528_PFD2_FRAC      16
#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \
	(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
#define BP_ANADIG_PFD_528_PFD1_FRAC      8
#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \
	(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
#define BP_ANADIG_PFD_528_PFD0_FRAC      0
#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)

#define HW_ANADIG_REG_1P1	(0x00000110)
#define HW_ANADIG_REG_1P1_SET	(0x00000114)
#define HW_ANADIG_REG_1P1_CLR	(0x00000118)
#define HW_ANADIG_REG_1P1_TOG	(0x0000011c)

#define BP_ANADIG_REG_1P1_RSVD2      18
#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC0000
#define BF_ANADIG_REG_1P1_RSVD2(v) \
	(((v) << 18) & BM_ANADIG_REG_1P1_RSVD2)
#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000
#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000
#define BP_ANADIG_REG_1P1_RSVD1      13
#define BM_ANADIG_REG_1P1_RSVD1 0x0000E000
#define BF_ANADIG_REG_1P1_RSVD1(v)  \
	(((v) << 13) & BM_ANADIG_REG_1P1_RSVD1)
#define BP_ANADIG_REG_1P1_OUTPUT_TRG      8
#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00
#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v)  \
	(((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG)
#define BM_ANADIG_REG_1P1_RSVD0 0x00000080
#define BP_ANADIG_REG_1P1_BO_OFFSET      4
#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070
#define BF_ANADIG_REG_1P1_BO_OFFSET(v)  \
	(((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET)
#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008
#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004
#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002
#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001

#define HW_ANADIG_REG_3P0	(0x00000120)
#define HW_ANADIG_REG_3P0_SET	(0x00000124)
#define HW_ANADIG_REG_3P0_CLR	(0x00000128)
#define HW_ANADIG_REG_3P0_TOG	(0x0000012c)

#define BP_ANADIG_REG_3P0_RSVD2      18
#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC0000
#define BF_ANADIG_REG_3P0_RSVD2(v) \
	(((v) << 18) & BM_ANADIG_REG_3P0_RSVD2)
#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000
#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000
#define BP_ANADIG_REG_3P0_RSVD1      13
#define BM_ANADIG_REG_3P0_RSVD1 0x0000E000
#define BF_ANADIG_REG_3P0_RSVD1(v)  \
	(((v) << 13) & BM_ANADIG_REG_3P0_RSVD1)
#define BP_ANADIG_REG_3P0_OUTPUT_TRG      8
#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00
#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v)  \
	(((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG)
#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080
#define BP_ANADIG_REG_3P0_BO_OFFSET      4
#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070
#define BF_ANADIG_REG_3P0_BO_OFFSET(v)  \
	(((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET)
#define BM_ANADIG_REG_3P0_RSVD0 0x00000008
#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004
#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002
#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001

#define HW_ANADIG_REG_2P5	(0x00000130)
#define HW_ANADIG_REG_2P5_SET	(0x00000134)
#define HW_ANADIG_REG_2P5_CLR	(0x00000138)
#define HW_ANADIG_REG_2P5_TOG	(0x0000013c)

#define BP_ANADIG_REG_2P5_RSVD2      19
#define BM_ANADIG_REG_2P5_RSVD2 0xFFF80000
#define BF_ANADIG_REG_2P5_RSVD2(v) \
	(((v) << 19) & BM_ANADIG_REG_2P5_RSVD2)
#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000
#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000
#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000
#define BP_ANADIG_REG_2P5_RSVD1      13
#define BM_ANADIG_REG_2P5_RSVD1 0x0000E000
#define BF_ANADIG_REG_2P5_RSVD1(v)  \
	(((v) << 13) & BM_ANADIG_REG_2P5_RSVD1)
#define BP_ANADIG_REG_2P5_OUTPUT_TRG      8
#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00
#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v)  \
	(((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG)
#define BM_ANADIG_REG_2P5_RSVD0 0x00000080
#define BP_ANADIG_REG_2P5_BO_OFFSET      4
#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070
#define BF_ANADIG_REG_2P5_BO_OFFSET(v)  \
	(((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET)
#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008
#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004
#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002
#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001

#define HW_ANADIG_REG_CORE	(0x00000140)
#define HW_ANADIG_REG_CORE_SET	(0x00000144)
#define HW_ANADIG_REG_CORE_CLR	(0x00000148)
#define HW_ANADIG_REG_CORE_TOG	(0x0000014c)

#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000
#define BM_ANADIG_REG_CORE_RSVD0 0x40000000
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
#define BP_ANADIG_REG_CORE_RAMP_RATE      27
#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000
#define BF_ANADIG_REG_CORE_RAMP_RATE(v)  \
	(((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE)
#define BP_ANADIG_REG_CORE_REG2_ADJ      23
#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000
#define BF_ANADIG_REG_CORE_REG2_ADJ(v)  \
	(((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ)
#define BP_ANADIG_REG_CORE_REG2_TRG      18
#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000
#define BF_ANADIG_REG_CORE_REG2_TRG(v)  \
	(((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG)
#define BP_ANADIG_REG_CORE_REG1_ADJ      14
#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000
#define BF_ANADIG_REG_CORE_REG1_ADJ(v)  \
	(((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ)
#define BP_ANADIG_REG_CORE_REG1_TRG      9
#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00
#define BF_ANADIG_REG_CORE_REG1_TRG(v)  \
	(((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG)
#define BP_ANADIG_REG_CORE_REG0_ADJ      5
#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0
#define BF_ANADIG_REG_CORE_REG0_ADJ(v)  \
	(((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ)
#define BP_ANADIG_REG_CORE_REG0_TRG      0
#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F
#define BF_ANADIG_REG_CORE_REG0_TRG(v)  \
	(((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG)

#define HW_ANADIG_ANA_MISC0	(0x00000150)
#define HW_ANADIG_ANA_MISC0_SET	(0x00000154)
#define HW_ANADIG_ANA_MISC0_CLR	(0x00000158)
#define HW_ANADIG_ANA_MISC0_TOG	(0x0000015c)

#define BP_ANADIG_ANA_MISC0_RSVD2      29
#define BM_ANADIG_ANA_MISC0_RSVD2 0xE0000000
#define BF_ANADIG_ANA_MISC0_RSVD2(v) \
	(((v) << 29) & BM_ANADIG_ANA_MISC0_RSVD2)
#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY      26
#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000
#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)  \
	(((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000
#define BP_ANADIG_ANA_MISC0_ANAMUX      21
#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000
#define BF_ANADIG_ANA_MISC0_ANAMUX(v)  \
	(((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX)
#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000
#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH      18
#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000
#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)  \
	(((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000
#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000
#define BP_ANADIG_ANA_MISC0_OSC_I      14
#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
#define BF_ANADIG_ANA_MISC0_OSC_I(v)  \
	(((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I)
#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000
#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
#define BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS 0x1000
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000
#define BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG 0x00000800
#define BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG 0x00000c00
#define BP_ANADIG_ANA_MISC0_RSVD0      10
#define BM_ANADIG_ANA_MISC0_RSVD0 0x00000C00
#define BF_ANADIG_ANA_MISC0_RSVD0(v)  \
	(((v) << 10) & BM_ANADIG_ANA_MISC0_RSVD0)
#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST      8
#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)  \
	(((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080
#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ      4
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070
#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)  \
	(((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004
#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002
#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001

#define HW_ANADIG_ANA_MISC1	(0x00000160)
#define HW_ANADIG_ANA_MISC1_SET	(0x00000164)
#define HW_ANADIG_ANA_MISC1_CLR	(0x00000168)
#define HW_ANADIG_ANA_MISC1_TOG	(0x0000016c)

#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000
#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
#define BP_ANADIG_ANA_MISC1_RSVD0      14
#define BM_ANADIG_ANA_MISC1_RSVD0 0x1FFFC000
#define BF_ANADIG_ANA_MISC1_RSVD0(v)  \
	(((v) << 14) & BM_ANADIG_ANA_MISC1_RSVD0)
#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000
#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000
#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800
#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400
#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL      5
#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v)  \
	(((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL      0
#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v)  \
	(((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)

#define HW_ANADIG_ANA_MISC2	(0x00000170)
#define HW_ANADIG_ANA_MISC2_SET	(0x00000174)
#define HW_ANADIG_ANA_MISC2_CLR	(0x00000178)
#define HW_ANADIG_ANA_MISC2_TOG	(0x0000017c)

#define BP_ANADIG_ANA_MISC2_CONTROL3      30
#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
	(((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3)
#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME      28
#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v)  \
	(((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME      26
#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v)  \
	(((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME      24
#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v)  \
	(((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000
#define BM_ANADIG_ANA_MISC2_RSVD2 0x00100000
#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000
#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET      16
#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v)  \
	(((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000
#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000
#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000
#define BM_ANADIG_ANA_MISC2_RSVD1 0x00001000
#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800
#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET      8
#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v)  \
	(((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080
#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040
#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020
#define BM_ANADIG_ANA_MISC2_RSVD0 0x00000010
#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008
#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET      0
#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007
#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v)  \
	(((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)

#define HW_ANADIG_TEMPSENSE0	(0x00000180)
#define HW_ANADIG_TEMPSENSE0_SET	(0x00000184)
#define HW_ANADIG_TEMPSENSE0_CLR	(0x00000188)
#define HW_ANADIG_TEMPSENSE0_TOG	(0x0000018c)

#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE      20
#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000
#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
	(((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE      8
#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00
#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v)  \
	(((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
#define BM_ANADIG_TEMPSENSE0_RSVD0 0x00000080
#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040
#define BP_ANADIG_TEMPSENSE0_VBGADJ      3
#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038
#define BF_ANADIG_TEMPSENSE0_VBGADJ(v)  \
	(((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ)
#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004
#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002
#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001

#define HW_ANADIG_TEMPSENSE1	(0x00000190)
#define HW_ANADIG_TEMPSENSE1_SET	(0x00000194)
#define HW_ANADIG_TEMPSENSE1_CLR	(0x00000198)
#define HW_ANADIG_TEMPSENSE1_TOG	(0x0000019c)

#define BP_ANADIG_TEMPSENSE1_RSVD0      16
#define BM_ANADIG_TEMPSENSE1_RSVD0 0xFFFF0000
#define BF_ANADIG_TEMPSENSE1_RSVD0(v) \
	(((v) << 16) & BM_ANADIG_TEMPSENSE1_RSVD0)
#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ      0
#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF
#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)  \
	(((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)

#define HW_ANADIG_USB1_VBUS_DETECT	(0x000001a0)
#define HW_ANADIG_USB1_VBUS_DETECT_SET	(0x000001a4)
#define HW_ANADIG_USB1_VBUS_DETECT_CLR	(0x000001a8)
#define HW_ANADIG_USB1_VBUS_DETECT_TOG	(0x000001ac)

#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
#define BP_ANADIG_USB1_VBUS_DETECT_RSVD2      28
#define BM_ANADIG_USB1_VBUS_DETECT_RSVD2 0x70000000
#define BF_ANADIG_USB1_VBUS_DETECT_RSVD2(v)  \
	(((v) << 28) & BM_ANADIG_USB1_VBUS_DETECT_RSVD2)
#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000
#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
#define BP_ANADIG_USB1_VBUS_DETECT_RSVD1      21
#define BM_ANADIG_USB1_VBUS_DETECT_RSVD1 0x03E00000
#define BF_ANADIG_USB1_VBUS_DETECT_RSVD1(v)  \
	(((v) << 21) & BM_ANADIG_USB1_VBUS_DETECT_RSVD1)
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
#define BP_ANADIG_USB1_VBUS_DETECT_RSVD0      8
#define BM_ANADIG_USB1_VBUS_DETECT_RSVD0 0x0003FF00
#define BF_ANADIG_USB1_VBUS_DETECT_RSVD0(v)  \
	(((v) << 8) & BM_ANADIG_USB1_VBUS_DETECT_RSVD0)
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080
#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040
#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020
#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010
#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008
#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH      0
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v)  \
	(((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH)

#define HW_ANADIG_USB1_CHRG_DETECT	(0x000001b0)
#define HW_ANADIG_USB1_CHRG_DETECT_SET	(0x000001b4)
#define HW_ANADIG_USB1_CHRG_DETECT_CLR	(0x000001b8)
#define HW_ANADIG_USB1_CHRG_DETECT_TOG	(0x000001bc)

#define BP_ANADIG_USB1_CHRG_DETECT_RSVD2      24
#define BM_ANADIG_USB1_CHRG_DETECT_RSVD2 0xFF000000
#define BF_ANADIG_USB1_CHRG_DETECT_RSVD2(v) \
	(((v) << 24) & BM_ANADIG_USB1_CHRG_DETECT_RSVD2)
#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000
#define BP_ANADIG_USB1_CHRG_DETECT_RSVD1      21
#define BM_ANADIG_USB1_CHRG_DETECT_RSVD1 0x00600000
#define BF_ANADIG_USB1_CHRG_DETECT_RSVD1(v)  \
	(((v) << 21) & BM_ANADIG_USB1_CHRG_DETECT_RSVD1)
#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000
#define BP_ANADIG_USB1_CHRG_DETECT_RSVD0      1
#define BM_ANADIG_USB1_CHRG_DETECT_RSVD0 0x0003FFFE
#define BF_ANADIG_USB1_CHRG_DETECT_RSVD0(v)  \
	(((v) << 1) & BM_ANADIG_USB1_CHRG_DETECT_RSVD0)
#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001

#define HW_ANADIG_USB1_VBUS_DET_STAT	(0x000001c0)
#define HW_ANADIG_USB1_VBUS_DET_STAT_SET	(0x000001c4)
#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR	(0x000001c8)
#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG	(0x000001cc)

#define BP_ANADIG_USB1_VBUS_DET_STAT_RSVD0      4
#define BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0 0xFFFFFFF0
#define BF_ANADIG_USB1_VBUS_DET_STAT_RSVD0(v) \
	(((v) << 4) & BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0)
#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008
#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004
#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002
#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001

#define HW_ANADIG_USB1_CHRG_DET_STAT	(0x000001d0)
#define HW_ANADIG_USB1_CHRG_DET_STAT_SET	(0x000001d4)
#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR	(0x000001d8)
#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG	(0x000001dc)

#define BP_ANADIG_USB1_CHRG_DET_STAT_RSVD0      4
#define BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0 0xFFFFFFF0
#define BF_ANADIG_USB1_CHRG_DET_STAT_RSVD0(v) \
	(((v) << 4) & BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0)
#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008
#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004
#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001

#define HW_ANADIG_USB1_LOOPBACK	(0x000001e0)
#define HW_ANADIG_USB1_LOOPBACK_SET	(0x000001e4)
#define HW_ANADIG_USB1_LOOPBACK_CLR	(0x000001e8)
#define HW_ANADIG_USB1_LOOPBACK_TOG	(0x000001ec)

#define BP_ANADIG_USB1_LOOPBACK_RSVD0      9
#define BM_ANADIG_USB1_LOOPBACK_RSVD0 0xFFFFFE00
#define BF_ANADIG_USB1_LOOPBACK_RSVD0(v) \
	(((v) << 9) & BM_ANADIG_USB1_LOOPBACK_RSVD0)
#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100
#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004
#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002
#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001

#define HW_ANADIG_USB1_MISC	(0x000001f0)
#define HW_ANADIG_USB1_MISC_SET	(0x000001f4)
#define HW_ANADIG_USB1_MISC_CLR	(0x000001f8)
#define HW_ANADIG_USB1_MISC_TOG	(0x000001fc)

#define BM_ANADIG_USB1_MISC_RSVD1 0x80000000
#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000
#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000
#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000
#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000
#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000
#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000
#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000
#define BP_ANADIG_USB1_MISC_RSVD0      2
#define BM_ANADIG_USB1_MISC_RSVD0 0x00FFFFFC
#define BF_ANADIG_USB1_MISC_RSVD0(v)  \
	(((v) << 2) & BM_ANADIG_USB1_MISC_RSVD0)
#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002
#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001

#define HW_ANADIG_USB2_VBUS_DETECT	(0x00000200)
#define HW_ANADIG_USB2_VBUS_DETECT_SET	(0x00000204)
#define HW_ANADIG_USB2_VBUS_DETECT_CLR	(0x00000208)
#define HW_ANADIG_USB2_VBUS_DETECT_TOG	(0x0000020c)

#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
#define BP_ANADIG_USB2_VBUS_DETECT_RSVD2      28
#define BM_ANADIG_USB2_VBUS_DETECT_RSVD2 0x70000000
#define BF_ANADIG_USB2_VBUS_DETECT_RSVD2(v)  \
	(((v) << 28) & BM_ANADIG_USB2_VBUS_DETECT_RSVD2)
#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000
#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
#define BP_ANADIG_USB2_VBUS_DETECT_RSVD1      21
#define BM_ANADIG_USB2_VBUS_DETECT_RSVD1 0x03E00000
#define BF_ANADIG_USB2_VBUS_DETECT_RSVD1(v)  \
	(((v) << 21) & BM_ANADIG_USB2_VBUS_DETECT_RSVD1)
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
#define BP_ANADIG_USB2_VBUS_DETECT_RSVD0      3
#define BM_ANADIG_USB2_VBUS_DETECT_RSVD0 0x0003FFF8
#define BF_ANADIG_USB2_VBUS_DETECT_RSVD0(v)  \
	(((v) << 3) & BM_ANADIG_USB2_VBUS_DETECT_RSVD0)
#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH      0
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v)  \
	(((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH)

#define HW_ANADIG_USB2_CHRG_DETECT	(0x00000210)
#define HW_ANADIG_USB2_CHRG_DETECT_SET	(0x00000214)
#define HW_ANADIG_USB2_CHRG_DETECT_CLR	(0x00000218)
#define HW_ANADIG_USB2_CHRG_DETECT_TOG	(0x0000021c)

#define BP_ANADIG_USB2_CHRG_DETECT_RSVD2      24
#define BM_ANADIG_USB2_CHRG_DETECT_RSVD2 0xFF000000
#define BF_ANADIG_USB2_CHRG_DETECT_RSVD2(v) \
	(((v) << 24) & BM_ANADIG_USB2_CHRG_DETECT_RSVD2)
#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000
#define BP_ANADIG_USB2_CHRG_DETECT_RSVD1      21
#define BM_ANADIG_USB2_CHRG_DETECT_RSVD1 0x00600000
#define BF_ANADIG_USB2_CHRG_DETECT_RSVD1(v)  \
	(((v) << 21) & BM_ANADIG_USB2_CHRG_DETECT_RSVD1)
#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000
#define BP_ANADIG_USB2_CHRG_DETECT_RSVD0      1
#define BM_ANADIG_USB2_CHRG_DETECT_RSVD0 0x0003FFFE
#define BF_ANADIG_USB2_CHRG_DETECT_RSVD0(v)  \
	(((v) << 1) & BM_ANADIG_USB2_CHRG_DETECT_RSVD0)
#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001

#define HW_ANADIG_USB2_VBUS_DET_STAT	(0x00000220)
#define HW_ANADIG_USB2_VBUS_DET_STAT_SET	(0x00000224)
#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR	(0x00000228)
#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG	(0x0000022c)

#define BP_ANADIG_USB2_VBUS_DET_STAT_RSVD0      4
#define BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0 0xFFFFFFF0
#define BF_ANADIG_USB2_VBUS_DET_STAT_RSVD0(v) \
	(((v) << 4) & BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0)
#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008
#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004
#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002
#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001

#define HW_ANADIG_USB2_CHRG_DET_STAT	(0x00000230)
#define HW_ANADIG_USB2_CHRG_DET_STAT_SET	(0x00000234)
#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR	(0x00000238)
#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG	(0x0000023c)

#define BP_ANADIG_USB2_CHRG_DET_STAT_RSVD0      4
#define BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0 0xFFFFFFF0
#define BF_ANADIG_USB2_CHRG_DET_STAT_RSVD0(v) \
	(((v) << 4) & BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0)
#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008
#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004
#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001

#define HW_ANADIG_USB2_LOOPBACK	(0x00000240)
#define HW_ANADIG_USB2_LOOPBACK_SET	(0x00000244)
#define HW_ANADIG_USB2_LOOPBACK_CLR	(0x00000248)
#define HW_ANADIG_USB2_LOOPBACK_TOG	(0x0000024c)

#define BP_ANADIG_USB2_LOOPBACK_RSVD0      9
#define BM_ANADIG_USB2_LOOPBACK_RSVD0 0xFFFFFE00
#define BF_ANADIG_USB2_LOOPBACK_RSVD0(v) \
	(((v) << 9) & BM_ANADIG_USB2_LOOPBACK_RSVD0)
#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100
#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004
#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002
#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001

#define HW_ANADIG_USB2_MISC	(0x00000250)
#define HW_ANADIG_USB2_MISC_SET	(0x00000254)
#define HW_ANADIG_USB2_MISC_CLR	(0x00000258)
#define HW_ANADIG_USB2_MISC_TOG	(0x0000025c)

#define BM_ANADIG_USB2_MISC_RSVD1 0x80000000
#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000
#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000
#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000
#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000
#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000
#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000
#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000
#define BP_ANADIG_USB2_MISC_RSVD0      2
#define BM_ANADIG_USB2_MISC_RSVD0 0x00FFFFFC
#define BF_ANADIG_USB2_MISC_RSVD0(v)  \
	(((v) << 2) & BM_ANADIG_USB2_MISC_RSVD0)
#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002
#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001

#define HW_ANADIG_DIGPROG	(0x00000260)

#define BP_ANADIG_DIGPROG_RSVD      24
#define BM_ANADIG_DIGPROG_RSVD 0xFF000000
#define BF_ANADIG_DIGPROG_RSVD(v) \
	(((v) << 24) & BM_ANADIG_DIGPROG_RSVD)
#define BP_ANADIG_DIGPROG_MAJOR      8
#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00
#define BF_ANADIG_DIGPROG_MAJOR(v)  \
	(((v) << 8) & BM_ANADIG_DIGPROG_MAJOR)
#define BP_ANADIG_DIGPROG_MINOR      0
#define BM_ANADIG_DIGPROG_MINOR 0x000000FF
#define BF_ANADIG_DIGPROG_MINOR(v)  \
	(((v) << 0) & BM_ANADIG_DIGPROG_MINOR)

#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */