| /* |
| This file is provided under a dual BSD/GPLv2 license. When using or |
| redistributing this file, you may do so under either license. |
| |
| GPL LICENSE SUMMARY |
| Copyright(c) 2014 Intel Corporation. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of version 2 of the GNU General Public License as |
| published by the Free Software Foundation. |
| |
| This program is distributed in the hope that it will be useful, but |
| WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| General Public License for more details. |
| |
| Contact Information: |
| qat-linux@intel.com |
| |
| BSD LICENSE |
| Copyright(c) 2014 Intel Corporation. |
| Redistribution and use in source and binary forms, with or without |
| modification, are permitted provided that the following conditions |
| are met: |
| |
| * Redistributions of source code must retain the above copyright |
| notice, this list of conditions and the following disclaimer. |
| * Redistributions in binary form must reproduce the above copyright |
| notice, this list of conditions and the following disclaimer in |
| the documentation and/or other materials provided with the |
| distribution. |
| * Neither the name of Intel Corporation nor the names of its |
| contributors may be used to endorse or promote products derived |
| from this software without specific prior written permission. |
| |
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #ifndef ADF_ACCEL_DEVICES_H_ |
| #define ADF_ACCEL_DEVICES_H_ |
| #include <linux/module.h> |
| #include <linux/list.h> |
| #include <linux/proc_fs.h> |
| #include <linux/io.h> |
| #include "adf_cfg_common.h" |
| |
| #define ADF_DH895XCC_DEVICE_NAME "dh895xcc" |
| #define ADF_DH895XCC_PCI_DEVICE_ID 0x435 |
| #define ADF_PCI_MAX_BARS 3 |
| #define ADF_DEVICE_NAME_LENGTH 32 |
| #define ADF_ETR_MAX_RINGS_PER_BANK 16 |
| #define ADF_MAX_MSIX_VECTOR_NAME 16 |
| #define ADF_DEVICE_NAME_PREFIX "qat_" |
| |
| enum adf_accel_capabilities { |
| ADF_ACCEL_CAPABILITIES_NULL = 0, |
| ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1, |
| ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2, |
| ADF_ACCEL_CAPABILITIES_CIPHER = 4, |
| ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8, |
| ADF_ACCEL_CAPABILITIES_COMPRESSION = 32, |
| ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64, |
| ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128 |
| }; |
| |
| struct adf_bar { |
| resource_size_t base_addr; |
| void __iomem *virt_addr; |
| resource_size_t size; |
| } __packed; |
| |
| struct adf_accel_msix { |
| struct msix_entry *entries; |
| char **names; |
| } __packed; |
| |
| struct adf_accel_pci { |
| struct pci_dev *pci_dev; |
| struct adf_accel_msix msix_entries; |
| struct adf_bar pci_bars[ADF_PCI_MAX_BARS]; |
| uint8_t revid; |
| uint8_t sku; |
| } __packed; |
| |
| enum dev_state { |
| DEV_DOWN = 0, |
| DEV_UP |
| }; |
| |
| enum dev_sku_info { |
| DEV_SKU_1 = 0, |
| DEV_SKU_2, |
| DEV_SKU_3, |
| DEV_SKU_4, |
| DEV_SKU_UNKNOWN, |
| }; |
| |
| static inline const char *get_sku_info(enum dev_sku_info info) |
| { |
| switch (info) { |
| case DEV_SKU_1: |
| return "SKU1"; |
| case DEV_SKU_2: |
| return "SKU2"; |
| case DEV_SKU_3: |
| return "SKU3"; |
| case DEV_SKU_4: |
| return "SKU4"; |
| case DEV_SKU_UNKNOWN: |
| default: |
| break; |
| } |
| return "Unknown SKU"; |
| } |
| |
| struct adf_hw_device_class { |
| const char *name; |
| const enum adf_device_type type; |
| uint32_t instances; |
| } __packed; |
| |
| struct adf_cfg_device_data; |
| struct adf_accel_dev; |
| struct adf_etr_data; |
| struct adf_etr_ring_data; |
| |
| struct adf_hw_device_data { |
| struct adf_hw_device_class *dev_class; |
| uint32_t (*get_accel_mask)(uint32_t fuse); |
| uint32_t (*get_ae_mask)(uint32_t fuse); |
| uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self); |
| uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self); |
| uint32_t (*get_num_aes)(struct adf_hw_device_data *self); |
| uint32_t (*get_num_accels)(struct adf_hw_device_data *self); |
| enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self); |
| void (*hw_arb_ring_enable)(struct adf_etr_ring_data *ring); |
| void (*hw_arb_ring_disable)(struct adf_etr_ring_data *ring); |
| int (*alloc_irq)(struct adf_accel_dev *accel_dev); |
| void (*free_irq)(struct adf_accel_dev *accel_dev); |
| void (*enable_error_correction)(struct adf_accel_dev *accel_dev); |
| int (*init_admin_comms)(struct adf_accel_dev *accel_dev); |
| void (*exit_admin_comms)(struct adf_accel_dev *accel_dev); |
| int (*init_arb)(struct adf_accel_dev *accel_dev); |
| void (*exit_arb)(struct adf_accel_dev *accel_dev); |
| void (*enable_ints)(struct adf_accel_dev *accel_dev); |
| const char *fw_name; |
| uint32_t pci_dev_id; |
| uint32_t fuses; |
| uint32_t accel_capabilities_mask; |
| uint16_t accel_mask; |
| uint16_t ae_mask; |
| uint16_t tx_rings_mask; |
| uint8_t tx_rx_gap; |
| uint8_t instance_id; |
| uint8_t num_banks; |
| uint8_t num_accel; |
| uint8_t num_logical_accel; |
| uint8_t num_engines; |
| } __packed; |
| |
| /* CSR write macro */ |
| #define ADF_CSR_WR(csr_base, csr_offset, val) \ |
| __raw_writel(val, csr_base + csr_offset) |
| |
| /* CSR read macro */ |
| #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) |
| |
| #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev) |
| #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars) |
| #define GET_HW_DATA(accel_dev) (accel_dev->hw_device) |
| #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks) |
| #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines) |
| #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev |
| |
| struct adf_admin_comms; |
| struct icp_qat_fw_loader_handle; |
| struct adf_fw_loader_data { |
| struct icp_qat_fw_loader_handle *fw_loader; |
| const struct firmware *uof_fw; |
| }; |
| |
| struct adf_accel_dev { |
| struct adf_etr_data *transport; |
| struct adf_hw_device_data *hw_device; |
| struct adf_cfg_device_data *cfg; |
| struct adf_fw_loader_data *fw_loader; |
| struct adf_admin_comms *admin; |
| struct list_head crypto_list; |
| unsigned long status; |
| atomic_t ref_count; |
| struct dentry *debugfs_dir; |
| struct list_head list; |
| struct module *owner; |
| struct adf_accel_pci accel_pci_dev; |
| uint8_t accel_id; |
| } __packed; |
| #endif |