| #ifndef __ASM_ARCH_MX6UL_DDR_H__ |
| #define __ASM_ARCH_MX6UL_DDR_H__ |
| |
| #ifndef CONFIG_MX6UL |
| #error "wrong CPU" |
| #endif |
| |
| #define MX6_IOM_DRAM_DQM0_OFFSET 0x244 |
| #define MX6_IOM_DRAM_DQM1_OFFSET 0x248 |
| |
| #define MX6_IOM_DRAM_RAS_OFFSET 0x24c |
| #define MX6_IOM_DRAM_CAS_OFFSET 0x250 |
| #define MX6_IOM_DRAM_SDODT0_OFFSET 0x260 |
| #define MX6_IOM_DRAM_SDODT1_OFFSET 0x264 |
| #define MX6_IOM_DRAM_SDCKE0_OFFSET 0x274 |
| #define MX6_IOM_DRAM_SDCKE1_OFFSET 0x278 |
| #define MX6_IOM_DRAM_SDCLK_0_OFFSET 0x27c |
| #define MX6_IOM_DRAM_RESET_OFFSET 0x288 |
| |
| #define MX6_IOM_DRAM_SDQS0_OFFSET 0x280 |
| #define MX6_IOM_DRAM_SDQS1_OFFSET 0x284 |
| |
| #define MX6_IOM_GRP_ADDDS_OFFSET 0x490 |
| #define MX6_IOM_DDRMODE_CTL_OFFSET 0x494 |
| #define MX6_IOM_GRP_DDRMODE_OFFSET 0x4b0 |
| #define MX6_IOM_GRP_B0DS_OFFSET 0x498 |
| #define MX6_IOM_GRP_B1DS_OFFSET 0x4a4 |
| |
| #endif /*__ASM_ARCH_MX6SX_DDR_H__ */ |
