blob: ac97f5e75614d41cc705330e421410bd9f812b68 [file] [log] [blame]
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* SPDX-License-Identifier: GPL-2.0+
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/imx-common/regs-common.h>
#include "../arch-imx/cpu.h"
#define is_soc_rev(rev) ((int)((get_cpu_rev() & 0xFF) - rev))
u32 get_cpu_rev(void);
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12)&0xff)
/* use with MXC_CPU_ constants */
#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_wdog_reset(struct wdog_regs *wdog);
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data);
int arch_auxiliary_core_check_up(u32 core_id);
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);