| /* |
| * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. |
| * |
| * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/io.h> |
| #include <asm/imx-common/mxc_i2c.h> |
| #include <linux/sizes.h> |
| #include <common.h> |
| #include <fsl_esdhc.h> |
| #include <mmc.h> |
| #include <i2c.h> |
| #include <miiphy.h> |
| #include <netdev.h> |
| #include <power/pmic.h> |
| #include <power/pfuze100_pmic.h> |
| #include "../common/pfuze.h" |
| #include <usb.h> |
| #include <usb/ehci-fsl.h> |
| |
| #ifdef CONFIG_MXC_RDC |
| #include <asm/imx-common/rdc-sema.h> |
| #include <asm/arch/imx-rdc.h> |
| #endif |
| |
| #ifdef CONFIG_VIDEO_MXS |
| #include <linux/fb.h> |
| #include <mxsfb.h> |
| #endif |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| #include <fsl_fastboot.h> |
| #ifdef CONFIG_ANDROID_RECOVERY |
| #include <recovery.h> |
| #endif |
| #endif /*CONFIG_FSL_FASTBOOT*/ |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE) |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE) |
| |
| #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) |
| |
| #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm) |
| |
| #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm) |
| |
| #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| int dram_init(void) |
| { |
| gd->ram_size = PHYS_SDRAM_SIZE; |
| |
| return 0; |
| } |
| |
| static iomux_v3_cfg_t const uart1_pads[] = { |
| MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc2_pads[] = { |
| MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc3_pads[] = { |
| MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| |
| /* CD pin */ |
| MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* RST_B, used for power reset cycle */ |
| MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc4_pads[] = { |
| MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc4_emmc_pads[] = { |
| MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const wdog_b_pad = { |
| MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const peri_3v3_pads[] = { |
| MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| } |
| |
| #ifdef CONFIG_FEC_MXC |
| static iomux_v3_cfg_t const fec1_pads[] = { |
| MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const fec2_pads[] = { |
| MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const phy_control_pads[] = { |
| /* 25MHz Ethernet PHY Clock */ |
| MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), |
| |
| /* ENET PHY Power */ |
| MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* AR8031 PHY Reset */ |
| MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static int setup_fec(int fec_id) |
| { |
| struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
| struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs |
| = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; |
| int reg; |
| |
| if (0 == fec_id) |
| /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ |
| clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); |
| else |
| /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ |
| clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); |
| |
| imx_iomux_v3_setup_multiple_pads(phy_control_pads, |
| ARRAY_SIZE(phy_control_pads)); |
| |
| /* Enable the ENET power, active low */ |
| gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); |
| |
| /* Reset AR8031 PHY */ |
| gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); |
| udelay(500); |
| gpio_set_value(IMX_GPIO_NR(2, 7), 1); |
| |
| reg = readl(&anatop->pll_enet); |
| reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; |
| writel(reg, &anatop->pll_enet); |
| |
| return enable_fec_anatop_clock(fec_id, ENET_125MHZ); |
| } |
| |
| int board_eth_init(bd_t *bis) |
| { |
| if (0 == CONFIG_FEC_ENET_DEV) |
| imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
| else |
| imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); |
| |
| setup_fec(CONFIG_FEC_ENET_DEV); |
| |
| return cpu_eth_init(bis); |
| } |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| /* |
| * Enable 1.8V(SEL_1P5_1P8_POS_REG) on |
| * Phy control debug reg 0 |
| */ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); |
| |
| /* rgmii tx clock delay enable */ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_VIDEO_MXS |
| static iomux_v3_cfg_t const lvds_ctrl_pads[] = { |
| /* CABC enable */ |
| MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* Use GPIO for Brightness adjustment, duty cycle = period */ |
| MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const lcd_pads[] = { |
| MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* Use GPIO for Brightness adjustment, duty cycle = period */ |
| MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| |
| struct lcd_panel_info_t { |
| unsigned int lcdif_base_addr; |
| int depth; |
| void (*enable)(struct lcd_panel_info_t const *dev); |
| struct fb_videomode mode; |
| }; |
| |
| void do_enable_lvds(struct lcd_panel_info_t const *dev) |
| { |
| enable_lcdif_clock(dev->lcdif_base_addr); |
| enable_lvds(dev->lcdif_base_addr); |
| |
| imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, |
| ARRAY_SIZE(lvds_ctrl_pads)); |
| |
| /* Enable CABC */ |
| gpio_direction_output(IMX_GPIO_NR(4, 18) , 1); |
| |
| /* Set Brightness to high */ |
| gpio_direction_output(IMX_GPIO_NR(6, 3) , 1); |
| } |
| |
| void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) |
| { |
| enable_lcdif_clock(dev->lcdif_base_addr); |
| |
| imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
| |
| /* Power up the LCD */ |
| gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); |
| |
| /* Set Brightness to high */ |
| gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); |
| } |
| |
| static struct lcd_panel_info_t const displays[] = {{ |
| .lcdif_base_addr = LCDIF2_BASE_ADDR, |
| .depth = 18, |
| .enable = do_enable_lvds, |
| .mode = { |
| .name = "Hannstar-XGA", |
| .xres = 1024, |
| .yres = 768, |
| .pixclock = 15385, |
| .left_margin = 220, |
| .right_margin = 40, |
| .upper_margin = 21, |
| .lower_margin = 7, |
| .hsync_len = 60, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } }, { |
| .lcdif_base_addr = LCDIF1_BASE_ADDR, |
| .depth = 24, |
| .enable = do_enable_parallel_lcd, |
| .mode = { |
| .name = "MCIMX28LCD", |
| .xres = 800, |
| .yres = 480, |
| .pixclock = 29850, |
| .left_margin = 89, |
| .right_margin = 164, |
| .upper_margin = 23, |
| .lower_margin = 10, |
| .hsync_len = 10, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } } }; |
| |
| int board_video_skip(void) |
| { |
| int i; |
| int ret; |
| char const *panel = getenv("panel"); |
| if (!panel) { |
| panel = displays[0].mode.name; |
| printf("No panel detected: default to %s\n", panel); |
| i = 0; |
| } else { |
| for (i = 0; i < ARRAY_SIZE(displays); i++) { |
| if (!strcmp(panel, displays[i].mode.name)) |
| break; |
| } |
| } |
| if (i < ARRAY_SIZE(displays)) { |
| ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, |
| displays[i].lcdif_base_addr); |
| if (!ret) { |
| if (displays[i].enable) |
| displays[i].enable(displays+i); |
| printf("Display: %s (%ux%u)\n", |
| displays[i].mode.name, |
| displays[i].mode.xres, |
| displays[i].mode.yres); |
| } else |
| printf("LCD %s cannot be configured: %d\n", |
| displays[i].mode.name, ret); |
| } else { |
| printf("unsupported panel %s\n", panel); |
| return -EINVAL; |
| } |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_SYS_I2C_MXC |
| #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| /* I2C1 for PMIC */ |
| static struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, |
| .gp = IMX_GPIO_NR(1, 0), |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, |
| .gp = IMX_GPIO_NR(1, 1), |
| }, |
| }; |
| |
| /* I2C2 */ |
| struct i2c_pads_info i2c_pad_info2 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, |
| .gp = IMX_GPIO_NR(1, 2), |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, |
| .gp = IMX_GPIO_NR(1, 3), |
| }, |
| }; |
| |
| static struct pmic *pfuze; |
| int power_init_board(void) |
| { |
| unsigned int reg, ret; |
| |
| pfuze = pfuze_common_init(I2C_PMIC); |
| if (!pfuze) |
| return -ENODEV; |
| |
| ret = pfuze_mode_init(pfuze, APS_PFM); |
| if (ret < 0) |
| return ret; |
| |
| /* set SW1AB standby volatage 1.10V */ |
| pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); |
| reg &= ~0x3f; |
| reg |= PFUZE100_SW1ABC_SETP(11000); |
| pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); |
| |
| /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); |
| reg &= ~0xc0; |
| reg |= 0x40; |
| pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); |
| |
| /* set SW1C standby volatage 1.10V */ |
| pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); |
| reg &= ~0x3f; |
| reg |= PFUZE100_SW1ABC_SETP(11000); |
| pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); |
| |
| /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ |
| pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); |
| reg &= ~0xc0; |
| reg |= 0x40; |
| pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); |
| |
| /* Enable power of VGEN5 3V3, needed for SD3 */ |
| pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); |
| reg &= ~LDO_VOL_MASK; |
| reg |= (LDOB_3_30V | (1 << LDO_EN)); |
| pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_LDO_BYPASS_CHECK |
| void ldo_mode_set(int ldo_bypass) |
| { |
| unsigned int value; |
| int is_400M; |
| u32 vddarm; |
| struct pmic *p = pfuze; |
| |
| if (!p) { |
| printf("No PMIC found!\n"); |
| return; |
| } |
| |
| /* switch to ldo_bypass mode */ |
| if (ldo_bypass) { |
| prep_anatop_bypass(); |
| /* decrease VDDARM to 1.275V */ |
| pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); |
| value &= ~0x3f; |
| value |= PFUZE100_SW1ABC_SETP(12750); |
| pmic_reg_write(p, PFUZE100_SW1ABVOL, value); |
| |
| /* decrease VDDSOC to 1.3V */ |
| pmic_reg_read(p, PFUZE100_SW1CVOL, &value); |
| value &= ~0x3f; |
| value |= PFUZE100_SW1ABC_SETP(13000); |
| pmic_reg_write(p, PFUZE100_SW1CVOL, value); |
| |
| is_400M = set_anatop_bypass(1); |
| if (is_400M) |
| vddarm = PFUZE100_SW1ABC_SETP(10750); |
| else |
| vddarm = PFUZE100_SW1ABC_SETP(11750); |
| |
| pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); |
| value &= ~0x3f; |
| value |= vddarm; |
| pmic_reg_write(p, PFUZE100_SW1ABVOL, value); |
| |
| pmic_reg_read(p, PFUZE100_SW1CVOL, &value); |
| value &= ~0x3f; |
| value |= PFUZE100_SW1ABC_SETP(11750); |
| pmic_reg_write(p, PFUZE100_SW1CVOL, value); |
| |
| finish_anatop_bypass(); |
| printf("switch to ldo_bypass mode!\n"); |
| } |
| |
| } |
| #endif |
| #endif |
| |
| #ifdef CONFIG_MXC_RDC |
| static rdc_peri_cfg_t const shared_resources[] = { |
| (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)), |
| }; |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| #define USB_OTHERREGS_OFFSET 0x800 |
| #define UCTRL_PWR_POL (1 << 9) |
| |
| static iomux_v3_cfg_t const usb_otg_pads[] = { |
| /* OGT1 */ |
| MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), |
| /* OTG2 */ |
| MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) |
| }; |
| |
| static void setup_usb(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| ARRAY_SIZE(usb_otg_pads)); |
| } |
| |
| int board_usb_phy_mode(int port) |
| { |
| if (port == 1) |
| return USB_INIT_HOST; |
| else |
| return usb_phy_mode(port); |
| } |
| |
| int board_ehci_hcd_init(int port) |
| { |
| u32 *usbnc_usb_ctrl; |
| |
| if (port > 1) |
| return -EINVAL; |
| |
| usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
| port * 4); |
| |
| /* Set Power polarity */ |
| setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
| |
| return 0; |
| } |
| #endif |
| |
| int board_early_init_f(void) |
| { |
| #ifdef CONFIG_MXC_RDC |
| imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources)); |
| #endif |
| |
| #ifdef CONFIG_SYS_AUXCORE_FASTUP |
| arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA); |
| #endif |
| |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| static struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| {USDHC2_BASE_ADDR, 0, 4}, |
| {USDHC3_BASE_ADDR}, |
| #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK |
| {USDHC4_BASE_ADDR, 0, 8}, |
| #else |
| {USDHC4_BASE_ADDR}, |
| #endif |
| }; |
| |
| #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) |
| #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) |
| #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) |
| |
| int mmc_get_env_devno(void) |
| { |
| u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); |
| int dev_no; |
| u32 bootsel; |
| |
| bootsel = (soc_sbmr & 0x000000FF) >> 6 ; |
| |
| /* If not boot from sd/mmc, use default value */ |
| if (bootsel != 1) |
| return CONFIG_SYS_MMC_ENV_DEV; |
| |
| /* BOOT_CFG2[3] and BOOT_CFG2[4] */ |
| dev_no = (soc_sbmr & 0x00001800) >> 11; |
| |
| /* need ubstract 1 to map to the mmc device id |
| * see the comments in board_mmc_init function |
| */ |
| |
| dev_no--; |
| |
| return dev_no; |
| } |
| |
| int mmc_map_to_kernel_blk(int dev_no) |
| { |
| return dev_no + 1; |
| } |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC2_BASE_ADDR: |
| ret = 1; /* Assume uSDHC2 is always present */ |
| break; |
| case USDHC3_BASE_ADDR: |
| ret = !gpio_get_value(USDHC3_CD_GPIO); |
| break; |
| case USDHC4_BASE_ADDR: |
| #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK |
| ret = 1; |
| #else |
| ret = !gpio_get_value(USDHC4_CD_GPIO); |
| #endif |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| #ifndef CONFIG_SPL_BUILD |
| int i, ret; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-boot device node) (Physical Port) |
| * mmc0 USDHC2 |
| * mmc1 USDHC3 |
| * mmc2 USDHC4 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| break; |
| case 1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| gpio_direction_input(USDHC3_CD_GPIO); |
| gpio_direction_output(USDHC3_PWR_GPIO, 1); |
| usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| break; |
| case 2: |
| #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); |
| #else |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| gpio_direction_input(USDHC4_CD_GPIO); |
| #endif |
| usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| break; |
| default: |
| printf("Warning: you configured more USDHC controllers" |
| "(%d) than supported by the board\n", i + 1); |
| return -EINVAL; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) { |
| printf("Warning: failed to initialize mmc dev %d\n", i); |
| return ret; |
| } |
| } |
| |
| return 0; |
| #else |
| struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
| u32 val; |
| u32 port; |
| |
| val = readl(&src_regs->sbmr1); |
| |
| if ((val & 0xc0) != 0x40) { |
| printf("Not boot from USDHC!\n"); |
| return -EINVAL; |
| } |
| |
| port = (val >> 11) & 0x3; |
| printf("port %d\n", port); |
| switch (port) { |
| case 1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
| break; |
| case 2: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| gpio_direction_input(USDHC3_CD_GPIO); |
| gpio_direction_output(USDHC3_PWR_GPIO, 1); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
| break; |
| case 3: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| gpio_direction_input(USDHC4_CD_GPIO); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; |
| break; |
| } |
| |
| gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| #endif |
| } |
| |
| int check_mmc_autodetect(void) |
| { |
| char *autodetect_str = getenv("mmcautodetect"); |
| |
| if ((autodetect_str != NULL) && |
| (strcmp(autodetect_str, "yes") == 0)) { |
| return 1; |
| } |
| |
| return 0; |
| } |
| |
| void board_late_mmc_init(void) |
| { |
| char cmd[32]; |
| char mmcblk[32]; |
| u32 dev_no = mmc_get_env_devno(); |
| |
| if (!check_mmc_autodetect()) |
| return; |
| |
| setenv_ulong("mmcdev", dev_no); |
| |
| /* Set mmcblk env */ |
| sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", |
| mmc_map_to_kernel_blk(dev_no)); |
| setenv("mmcroot", mmcblk); |
| |
| sprintf(cmd, "mmc dev %d", dev_no); |
| run_command(cmd, 0); |
| } |
| |
| #ifdef CONFIG_FSL_QSPI |
| |
| #define QSPI_PAD_CTRL1 \ |
| (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) |
| |
| static iomux_v3_cfg_t const quadspi_pads[] = { |
| MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| }; |
| |
| int board_qspi_init(void) |
| { |
| /* Set the iomux */ |
| imx_iomux_v3_setup_multiple_pads(quadspi_pads, |
| ARRAY_SIZE(quadspi_pads)); |
| |
| /* Set the clock */ |
| enable_qspi_clk(1); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| /* 4 bit bus width */ |
| {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, |
| {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| int board_init(void) |
| { |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| /* |
| * Because kernel set WDOG_B mux before pad with the commone pinctrl |
| * framwork now and wdog reset will be triggered once set WDOG_B mux |
| * with default pad setting, we set pad setting here to workaround this. |
| * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set |
| * as GPIO mux firstly here to workaround it. |
| */ |
| imx_iomux_v3_setup_pad(wdog_b_pad); |
| |
| /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ |
| imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, |
| ARRAY_SIZE(peri_3v3_pads)); |
| |
| /* Active high for ncp692 */ |
| gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); |
| |
| #ifdef CONFIG_SYS_I2C_MXC |
| setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| setup_usb(); |
| #endif |
| |
| #ifdef CONFIG_FSL_QSPI |
| board_qspi_init(); |
| #endif |
| |
| return 0; |
| } |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| board_late_mmc_init(); |
| #endif |
| |
| return 0; |
| } |
| |
| u32 get_board_rev(void) |
| { |
| return get_cpu_rev(); |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: MX6SX SABRE SDB\n"); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| |
| void board_fastboot_setup(void) |
| { |
| switch (get_boot_device()) { |
| #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| case SD2_BOOT: |
| case MMC2_BOOT: |
| if (!getenv("fastboot_dev")) |
| setenv("fastboot_dev", "mmc0"); |
| if (!getenv("bootcmd")) |
| setenv("bootcmd", "boota mmc0"); |
| break; |
| case SD3_BOOT: |
| case MMC3_BOOT: |
| if (!getenv("fastboot_dev")) |
| setenv("fastboot_dev", "mmc1"); |
| if (!getenv("bootcmd")) |
| setenv("bootcmd", "boota mmc1"); |
| break; |
| case SD4_BOOT: |
| case MMC4_BOOT: |
| if (!getenv("fastboot_dev")) |
| setenv("fastboot_dev", "mmc2"); |
| if (!getenv("bootcmd")) |
| setenv("bootcmd", "boota mmc2"); |
| break; |
| #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| default: |
| printf("unsupported boot devices\n"); |
| break; |
| } |
| } |
| |
| #ifdef CONFIG_ANDROID_RECOVERY |
| |
| #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 19) |
| iomux_v3_cfg_t const recovery_key_pads[] = { |
| (MX6_PAD_CSI_DATA05__GPIO1_IO_19 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), |
| }; |
| |
| int check_recovery_cmd_file(void) |
| { |
| int button_pressed = 0; |
| int recovery_mode = 0; |
| |
| recovery_mode = recovery_check_and_clean_flag(); |
| |
| /* Check Recovery Combo Button press or not. */ |
| imx_iomux_v3_setup_multiple_pads(recovery_key_pads, |
| ARRAY_SIZE(recovery_key_pads)); |
| |
| gpio_direction_input(GPIO_VOL_DN_KEY); |
| |
| if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ |
| button_pressed = 1; |
| printf("Recovery key pressed\n"); |
| } |
| |
| return recovery_mode || button_pressed; |
| } |
| |
| void board_recovery_setup(void) |
| { |
| int bootdev = get_boot_device(); |
| |
| switch (bootdev) { |
| #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| case SD2_BOOT: |
| case MMC2_BOOT: |
| if (!getenv("bootcmd_android_recovery")) |
| setenv("bootcmd_android_recovery", "boota mmc0 recovery"); |
| break; |
| case SD3_BOOT: |
| case MMC3_BOOT: |
| if (!getenv("bootcmd_android_recovery")) |
| setenv("bootcmd_android_recovery", "boota mmc1 recovery"); |
| break; |
| case SD4_BOOT: |
| case MMC4_BOOT: |
| if (!getenv("bootcmd_android_recovery")) |
| setenv("bootcmd_android_recovery", "boota mmc2 recovery"); |
| break; |
| #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| default: |
| printf("Unsupported bootup device for recovery: dev: %d\n", |
| bootdev); |
| return; |
| } |
| |
| printf("setup env for recovery..\n"); |
| setenv("bootcmd", "run bootcmd_android_recovery"); |
| } |
| #endif /*CONFIG_ANDROID_RECOVERY*/ |
| |
| #endif /*CONFIG_FSL_FASTBOOT*/ |
| |
| #ifdef CONFIG_SPL_BUILD |
| #include <libfdt.h> |
| #include <spl.h> |
| #include <asm/arch/mx6-ddr.h> |
| |
| const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { |
| .dram_dqm0 = 0x00000028, |
| .dram_dqm1 = 0x00000028, |
| .dram_dqm2 = 0x00000028, |
| .dram_dqm3 = 0x00000028, |
| .dram_ras = 0x00000020, |
| .dram_cas = 0x00000020, |
| .dram_odt0 = 0x00000020, |
| .dram_odt1 = 0x00000020, |
| .dram_sdba2 = 0x00000000, |
| .dram_sdcke0 = 0x00003000, |
| .dram_sdcke1 = 0x00003000, |
| .dram_sdclk_0 = 0x00000030, |
| .dram_sdqs0 = 0x00000028, |
| .dram_sdqs1 = 0x00000028, |
| .dram_sdqs2 = 0x00000028, |
| .dram_sdqs3 = 0x00000028, |
| .dram_reset = 0x00000020, |
| }; |
| |
| const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { |
| .grp_addds = 0x00000020, |
| .grp_ddrmode_ctl = 0x00020000, |
| .grp_ddrpke = 0x00000000, |
| .grp_ddrmode = 0x00020000, |
| .grp_b0ds = 0x00000028, |
| .grp_b1ds = 0x00000028, |
| .grp_ctlds = 0x00000020, |
| .grp_ddr_type = 0x000c0000, |
| .grp_b2ds = 0x00000028, |
| .grp_b3ds = 0x00000028, |
| }; |
| |
| const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| .p0_mpwldectrl0 = 0x00290025, |
| .p0_mpwldectrl1 = 0x00220022, |
| .p0_mpdgctrl0 = 0x41480144, |
| .p0_mpdgctrl1 = 0x01340130, |
| .p0_mprddlctl = 0x3C3E4244, |
| .p0_mpwrdlctl = 0x34363638, |
| }; |
| |
| static struct mx6_ddr3_cfg mem_ddr = { |
| .mem_speed = 1600, |
| .density = 4, |
| .width = 32, |
| .banks = 8, |
| .rowaddr = 15, |
| .coladdr = 10, |
| .pagesz = 2, |
| .trcd = 1375, |
| .trcmin = 4875, |
| .trasmin = 3500, |
| }; |
| |
| static void ccgr_init(void) |
| { |
| struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| writel(0xFFFFFFFF, &ccm->CCGR0); |
| writel(0xFFFFFFFF, &ccm->CCGR1); |
| writel(0xFFFFFFFF, &ccm->CCGR2); |
| writel(0xFFFFFFFF, &ccm->CCGR3); |
| writel(0xFFFFFFFF, &ccm->CCGR4); |
| writel(0xFFFFFFFF, &ccm->CCGR5); |
| writel(0xFFFFFFFF, &ccm->CCGR6); |
| writel(0xFFFFFFFF, &ccm->CCGR7); |
| } |
| |
| static void spl_dram_init(void) |
| { |
| struct mx6_ddr_sysinfo sysinfo = { |
| .dsize = mem_ddr.width/32, |
| .cs_density = 24, |
| .ncs = 1, |
| .cs1_mirror = 0, |
| .rtt_wr = 2, |
| .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ |
| .walat = 1, /* Write additional latency */ |
| .ralat = 5, /* Read additional latency */ |
| .mif3_mode = 3, /* Command prediction working mode */ |
| .bi_on = 1, /* Bank interleaving enabled */ |
| .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| }; |
| |
| mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| } |
| |
| void board_init_f(ulong dummy) |
| { |
| /* setup AIPS and disable watchdog */ |
| arch_cpu_init(); |
| |
| ccgr_init(); |
| |
| /* iomux and setup of i2c */ |
| board_early_init_f(); |
| |
| /* setup GP timer */ |
| timer_init(); |
| |
| /* UART clocks enabled and gd valid - init serial console */ |
| preloader_console_init(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| /* load/boot image from boot device */ |
| board_init_r(NULL, 0); |
| } |
| |
| void reset_cpu(ulong addr) |
| { |
| } |
| #endif |