/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"

/ {
	model = "Freescale i.MX6 SXSCM EVB Board";
	compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";

	chosen {
	stdout-path = &uart3;
	};

	memory {
		reg = <0x80000000 0x40000000>;
	};

	backlight1 {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		fb-names = "mxs-lcdif0";
	};

	backlight2 {
		compatible = "pwm-backlight";
		pwms = <&pwm4 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		fb-names = "mxs-lcdif1";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		volume-up {
			label = "Volume Up";
			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEUP>;
		};

		volume-down {
			label = "Volume Down";
			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEDOWN>;
		};
	};

	hannstar_cabc {
		compatible = "hannstar,cabc";

		lvds0 {
			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
		};
	};

	pxp_v4l2_out {
		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
		status = "okay";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		vcc_sd3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_vcc_sd3>;
			regulator-name = "VCC_SD3";
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
			off-on-delay = <20000>;
			enable-active-high;
		};

		reg_usb_otg1_vbus: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb_otg1>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg2_vbus: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb_otg2>;
			regulator-name = "usb_otg2_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
		};

		reg_psu_5v: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "PSU-5V0";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
		};

		reg_lcd_3v3: regulator@4 {
			compatible = "regulator-fixed";
			reg = <4>;
			regulator-name = "lcd-3v3";
			gpio = <&gpio3 27 0>;
			enable-active-high;
			status = "disabled";
		};

		reg_peri_3v3: regulator@5 {
			compatible = "regulator-fixed";
			reg = <5>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_peri_3v3>;
			regulator-name = "peri_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			regulator-always-on;
		};

		reg_enet_3v3: regulator@6 {
			compatible = "regulator-fixed";
			reg = <6>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_enet_3v3>;
			regulator-name = "enet_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpios = <&gpio4 25 GPIO_ACTIVE_LOW>,
				<&gpio4 26 GPIO_ACTIVE_HIGH>;
		};

		reg_vref_3v3: regulator@7 {
			compatible = "regulator-fixed";
			reg = <7>;
			regulator-name = "vref-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_pcie: regulator@8 {
			compatible = "regulator-fixed";
			reg = <8>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_pcie_reg>;
			regulator-name = "MPCIE_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 1 0>;
			regulator-always-on;
			enable-active-high;
		};

		reg_can_en: regulator@9 {
			compatible = "regulator-fixed";
			reg = <9>;
			regulator-name = "can-en";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_can_stby: regulator@10 {
			compatible = "regulator-fixed";
			reg = <10>;
			regulator-name = "can-stby";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
		};
	};

	sound {
		compatible = "fsl,imx6sxscm-evb-wm8962", "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		cpu-dai = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
		mux-int-port = <2>;
		mux-ext-port = <6>;
		codec-master;
		hp-det-gpios = <&gpio1 17 1>;
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif",
			   "fsl,imx6sx-sdb-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-out;
	};

	sii902x_reset: sii902x-reset {
		compatible = "gpio-reset";
		reset-gpios = <&gpio3 27 1>;
		reset-delay-us = <100000>;
		#reset-cells = <0>;
		status = "disabled";
	};
};

&adc1 {
	vref-supply = <&reg_vref_3v3>;
	status = "okay";
};

&adc2 {
	vref-supply = <&reg_vref_3v3>;
	status = "okay";
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&gpc {
	fsl,ldo-bypass = <1>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-supply = <&reg_enet_3v3>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio4 26 0>;
	fsl,magic-packet;
	status = "okay";
};

&csi1 {
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&ov5640_ep>;
		};
	};
};

&csi2 {
	status = "okay";
	port {
		csi2_ep: endpoint {
			remote-endpoint = <&vadc_ep>;
		};
	};
};

&dcic1 {
	dcic_id = <0>;
	dcic_mux = "dcic-lcdif1";
	status = "okay";
};

&dcic2 {
	dcic_id = <1>;
	dcic_mux = "dcic-lvds";
	status = "okay";
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_stby>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic: pfuze100@08 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1200000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};

	egalax_ts@04 {
		compatible = "eeti,egalax_ts";
		reg = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_egalax_int>;
		interrupt-parent = <&gpio4>;
		interrupts = <19 2>;
		wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	mma8451@1c {
		compatible = "fsl,mma8451";
		reg = <0x1c>;
		position = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <17 8>;
		interrupt-route = <2>;
	};

	mag3110@0e {
		compatible = "fsl,mag3110";
		reg = <0x0e>;
		position = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <22 1>;
		shared-interrupt;
	};

	isl29023@44 {
		compatible = "fsl,isl29023";
		reg = <0x44>;
		rext = <499>;
		interrupt-parent = <&gpio4>;
		interrupts = <22 1>;
		shared-interrupt;
	};
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: wm8962@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clks IMX6SX_CLK_AUDIO>;
		DCVDD-supply = <&vgen4_reg>;
		DBVDD-supply = <&vgen4_reg>;
		AVDD-supply = <&vgen4_reg>;
		CPVDD-supply = <&vgen4_reg>;
		MICVDD-supply = <&vgen3_reg>;
		PLLVDD-supply = <&vgen4_reg>;
		SPKVDD1-supply = <&reg_psu_5v>;
		SPKVDD2-supply = <&reg_psu_5v>;
		amic-mono;
	};
	ov5640: ov5640@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi_0>;
		clocks = <&clks IMX6SX_CLK_CSI>;
		clock-names = "csi_mclk";
		AVDD-supply = <&vgen3_reg>;
		DVDD-supply = <&vgen2_reg>;
		pwn-gpios = <&gpio3 28 1>;
		rst-gpios = <&gpio3 27 0>;
		csi_id = <0>;
		mclk = <24000000>;
		mclk_source = <0>;
		port {
			ov5640_ep: endpoint {
			remote-endpoint = <&csi1_ep>;
			};
		};
	};

	sii902x: sii902x@39 {
		compatible = "SiI,sii902x";
		interrupt-parent = <&gpio4>;
		interrupts = <21 2>;
		mode_str ="1280x720M@60";
		bits-per-pixel = <16>;
		resets = <&sii902x_reset>;
		reg = <0x39>;
		status = "disabled";
	};
};

&cpu0 {
	operating-points = <
		/* kHz    uV */
		996000	1250000
		792000	1175000
		396000	1175000
		198000	1175000
	>;
	fsl,soc-operating-points = <
		/* ARM kHz      SOC uV */
		996000	1250000
		792000	1175000
		396000	1175000
		198000	1175000
	>;
	fsl,arm-soc-shared = <1>;
};

&reg_arm {
	vin-supply = <&sw1a_reg>;
	regulator-allow-bypass;
};

&reg_soc {
	vin-supply = <&sw1a_reg>;
	regulator-allow-bypass;
};


&qspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi2_1>;
	status = "okay";

#ifndef SPANSIONFLASH
	ddrsmp=<0>;

	flash0: n25q256a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <0>;
	};

	flash1: n25q256a@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <1>;
	};
#endif
};

&lcdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	lcd-supply = <&reg_lcd_3v3>;
	display = <&display0>;
	status = "disabled";

	display0: display@0 {
		bits-per-pixel = <16>;
		bus-width = <24>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <33500000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <89>;
				hfront-porch = <164>;
				vback-porch = <23>;
				vfront-porch = <10>;
				hsync-len = <10>;
				vsync-len = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

&lcdif2 {
	display = <&display1>;
	disp-dev = "ldb";
	status = "okay";

	display1: display@1 {
		bits-per-pixel = <16>;
		bus-width = <18>;
	};
};

&ldb {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		crtc = "lcdif2";
		status = "okay";

		display-timings {
			native-mode = <&timing1>;
			timing1: hsd100pxn1 {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <220>;
				hfront-porch = <40>;
				vback-porch = <21>;
				vfront-porch = <7>;
				hsync-len = <60>;
				vsync-len = <10>;
			};
		};
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
};

&pxp {
	status = "okay";
};

&snvs_poweroff {
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "disabled";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&ssi2 {
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	wifi-host;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	cd-gpios = <>;
	wp-gpios = <>;
	keep-power-in-suspend;
	wakeup-source;
	pm-ignore-notify;
	vmmc-supply = <>;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;

	imx6x-sdb {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17	0x17059
				MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22	0xb000
				MX6SX_PAD_CSI_DATA03__GPIO1_IO_17	0x17059
				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY	0x30b0
				MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21	0x17059
			>;
		};

		pinctrl_can_gpios: can-gpios {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
			>;
		};

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
				MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
				MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
				MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
			>;
		};

		pinctrl_canfd1: canfd1grp-1 {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_DQS__CANFD_TX1         0x1b0b0
				MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1       0x1b0b0
			>;
		};

		pinctrl_canfd2: canfd2grp-1 {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2       0x1b0b0
				MX6SX_PAD_QSPI1A_DQS__CANFD_TX2         0x1b0b0
			>;
		};

		pinctrl_csi_0: csigrp-0 {
			fsl,pins = <
				MX6SX_PAD_LCD1_DATA07__CSI1_MCLK	0x110b0
				MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK	0x110b0
				MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC	0x110b0
				MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC	0x110b0
				MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0	0x110b0
				MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1	0x110b0
				MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2	0x110b0
				MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3	0x110b0
				MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4	0x110b0
				MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5	0x110b0
				MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6	0x110b0
				MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7	0x110b0
				MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8	0x110b0
				MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9	0x110b0
				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27    0x80000000
				MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28    0x80000000
			>;
		};

		pinctrl_egalax_int: egalax_intgrp {
			fsl,pins = <
				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
			>;
		};

		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO05__ENET1_MDIO	0xa0b1
				MX6SX_PAD_GPIO1_IO04__ENET1_MDC		0xa0b1
				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0xa0b9
				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0xa0b1
				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0xa0b1
				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0xa0b1
				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK	0x3081
				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
			>;
		};

		pinctrl_enet_3v3: enet3v3grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25  0x80000000
				MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26  0x80000000
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
			>;
		};

		pinctrl_flexcan1: flexcan1grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_DQS__CAN1_TX		0x1b020
				MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX		0x1b020
			>;
		};

		pinctrl_flexcan2: flexcan2grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX		0x1b020
				MX6SX_PAD_QSPI1A_DQS__CAN2_TX		0x1b020
			>;
		};

		pinctrl_gpio_keys: gpio_keysgrp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
				MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
				MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
				MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
				MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
				MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
			>;
		};

		pinctrl_lcd: lcdgrp {
			fsl,pins = <
				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0  0x4001b0b0
				MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1  0x4001b0b0
				MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2  0x4001b0b0
				MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3  0x4001b0b0
				MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4  0x4001b0b0
				MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5  0x4001b0b0
				MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6  0x4001b0b0
				MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7  0x4001b0b0
				MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8  0x4001b0b0
				MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9  0x4001b0b0
				MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
				MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
				MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
				MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
				MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
				MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
				MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
				MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
				MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
				MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
				MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
				MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
				MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
				MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
				MX6SX_PAD_LCD1_CLK__LCDIF1_CLK        0x4001b0b0
				MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE  0x4001b0b0
				MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC    0x4001b0b0
				MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC    0x4001b0b0
				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27     0x4001b0b0
			>;
		};

		pinctrl_mqs: mqsgrp {
			fsl,pins = <
				MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
				MX6SX_PAD_SD2_CMD__MQS_LEFT  0x120b0
			>;
		};

		pinctrl_pcie: pciegrp {
			fsl,pins = <
				MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
			>;
		};

		pinctrl_pcie_reg: pciereggrp {
			fsl,pins = <
				MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
			>;
		};

		pinctrl_peri_3v3: peri3v3grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16  0x80000000
			>;
		};
		pinctrl_pwm3: pwm3grp {
			fsl,pins = <
				MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x110b0
			>;
		};

		pinctrl_pwm4: pwm4grp {
			fsl,pins = <
				MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x110b0
			>;
		};

		pinctrl_qspi2_1: qspi2grp_1 {
			fsl,pins = <
				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
				MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
				MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
				MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
				MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
				MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
				MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
				MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
				MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
				MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
				MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
				MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
			>;
		};

		pinctrl_sai1: sai1grp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130b0
				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130b0
				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120b0
				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130b0
				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130b0
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6SX_PAD_SD4_DATA4__SPDIF_OUT          0x1b0b0
			>;
		};

		pinctrl_vcc_sd3: vccsd3grp {
			fsl,pins = <
				MX6SX_PAD_KEY_COL1__GPIO2_IO_11	0x17059
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
				MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW3__UART5_RX		0x1b0b1
				MX6SX_PAD_KEY_COL3__UART5_TX		0x1b0b1
				MX6SX_PAD_KEY_ROW2__UART5_CTS_B		0x1b0b1
				MX6SX_PAD_KEY_COL2__UART5_RTS_B		0x1b0b1
			>;
		};

		pinctrl_uart5dte_1: uart5dtegrp-1 {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW3__UART5_TX		0x1b0b1
				MX6SX_PAD_KEY_COL3__UART5_RX		0x1b0b1
				MX6SX_PAD_KEY_ROW2__UART5_RTS_B		0x1b0b1
				MX6SX_PAD_KEY_COL2__UART5_CTS_B		0x1b0b1
			>;
		};

		pinctrl_usb_otg1: usbotg1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9	0x10b0
			>;
		};

		pinctrl_usb_otg1_id: usbotg1idgrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID	0x17059
			>;
		};

		pinctrl_usb_otg2: usbot2ggrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12	0x10b0
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6SX_PAD_SD2_CMD__USDHC2_CMD		0x17059
				MX6SX_PAD_SD2_CLK__USDHC2_CLK		0x10059
				MX6SX_PAD_SD2_DATA0__USDHC2_DATA0	0x17059
				MX6SX_PAD_SD2_DATA1__USDHC2_DATA1	0x17059
				MX6SX_PAD_SD2_DATA2__USDHC2_DATA2	0x17059
				MX6SX_PAD_SD2_DATA3__USDHC2_DATA3	0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17069
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x10071
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x17069
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x17069
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x17069
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x17069
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x17069
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x17069
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x17069
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x17069
				MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x17059
				MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x17059
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170b9
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100b9
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170b9
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170b9
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170b9
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170b9
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170b9
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170b9
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170b9
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170f9
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100f9
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170f9
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170f9
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170f9
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170f9
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170f9
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170f9
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170f9
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170f9
			>;
		};

		pinctrl_usdhc4: usdhc4grp {
			fsl,pins = <
				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
				MX6SX_PAD_SD4_DATA7__GPIO6_IO_21	0x17059
				MX6SX_PAD_SD4_DATA6__GPIO6_IO_20	0x17059
			>;
		};

		pinctrl_usdhc4_1: usdhc4grp-1 {
			fsl,pins = <
				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
				MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x17059
				MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x17059
				MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x17059
				MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x17059
			>;
		};

		pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
			fsl,pins = <
				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170b9
				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100b9
				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170b9
				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170b9
				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170b9
				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170b9
				MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170b9
				MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170b9
				MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170b9
				MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170b9
			>;
		};

		pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
			fsl,pins = <
				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170f9
				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100f9
				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170f9
				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170f9
				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170f9
				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170f9
				MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170f9
				MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170f9
				MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170f9
				MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170f9
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1B_SS0_B__UART3_TX	0x1b0b1
				MX6SX_PAD_QSPI1B_SCLK__UART3_RX		0x1b0b1
			>;
		};
	};
};

&vadc {
	vadc_in = <0>;
	csi_id = <1>;
	status = "disabled";
	port {
		vadc_ep: endpoint {
			remote-endpoint = <&csi2_ep>;
		};
	};
};