/*
 * P1021 MDS Device Tree Source
 *
 * Copyright 2010,2012 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

/include/ "p1021si-pre.dtsi"
/ {
	model = "fsl,P1021";
	compatible = "fsl,P1021MDS";

	aliases {
		ethernet3 = &enet3;
		ethernet4 = &enet4;
	};

	memory {
		device_type = "memory";
	};

	lbc: localbus@ffe05000 {
		reg = <0x0 0xffe05000 0x0 0x1000>;

		/* NAND Flash, BCSR, PMC0/1*/
		ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
			  0x1 0x0 0x0 0xf8000000 0x00008000
			  0x2 0x0 0x0 0xf8010000 0x00020000
			  0x3 0x0 0x0 0xf8020000 0x00020000>;

		nand@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1021-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <0x0 0x0 0x40000>;

			partition@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				label = "NAND (RO) U-Boot Image";
				read-only;
			};

			partition@100000 {
				/* 1MB for DTB Image */
				reg = <0x00100000 0x00100000>;
				label = "NAND (RO) DTB Image";
				read-only;
			};

			partition@200000 {
				/* 4MB for Linux Kernel Image */
				reg = <0x00200000 0x00400000>;
				label = "NAND (RO) Linux Kernel Image";
				read-only;
			};

			partition@600000 {
				/* 5MB for Compressed Root file System Image */
				reg = <0x00600000 0x00500000>;
				label = "NAND (RO) Compressed RFS Image";
				read-only;
			};

			partition@b00000 {
				/* 6MB for JFFS2 based Root file System */
				reg = <0x00a00000 0x00600000>;
				label = "NAND (RW) JFFS2 Root File System";
			};

			partition@1100000 {
				/* 14MB for JFFS2 based Root file System */
				reg = <0x01100000 0x00e00000>;
				label = "NAND (RW) Writable User area";
			};

			partition@1f00000 {
				/* 1MB for microcode */
				reg = <0x01f00000 0x00100000>;
				label = "NAND (RO) QE Ucode";
				read-only;
			};
		};

		bcsr@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1021mds-bcsr";
			reg = <1 0 0x8000>;
			ranges = <0 1 0 0x8000>;
		};

		pib@2,0 {
			compatible = "fsl,p1021mds-pib";
			reg = <2 0 0x10000>;
		};

		pib@3,0 {
			compatible = "fsl,p1021mds-pib";
			reg = <3 0 0x10000>;
		};
	};

	soc: soc@ffe00000 {
		compatible = "fsl,p1021-immr", "simple-bus";
		ranges = <0x0 0x0 0xffe00000 0x100000>;

		i2c@3000 {
			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <0x68>;
			};
		};

		spi@7000 {

			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,s25sl12801", "jedec,spi-nor";
				reg = <0>;
				spi-max-frequency = <40000000>; /* input clock */

				partition@u-boot {
					label = "u-boot-spi";
					reg = <0x00000000 0x00100000>;
					read-only;
				};
				partition@kernel {
					label = "kernel-spi";
					reg = <0x00100000 0x00500000>;
					read-only;
				};
				partition@dtb {
					label = "dtb-spi";
					reg = <0x00600000 0x00100000>;
					read-only;
				};
				partition@fs {
					label = "file system-spi";
					reg = <0x00700000 0x00900000>;
				};
			};
		};

		usb@22000 {
			phy_type = "ulpi";
			dr_mode = "host";
		};

		mdio@24000 {
			phy0: ethernet-phy@0 {
				interrupts = <1 1 0 0>;
				reg = <0x0>;
			};
			phy1: ethernet-phy@1 {
				interrupts = <2 1 0 0>;
				reg = <0x1>;
			};
			phy4: ethernet-phy@4 {
				reg = <0x4>;
			};
			tbi-phy@5 {
				device_type = "tbi-phy";
				reg = <0x5>;
			};
		};

		mdio@25000 {
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		ethernet@b0000 {
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		ethernet@b1000 {
			phy-handle = <&phy4>;
			tbi-handle = <&tbi0>;
			phy-connection-type = "sgmii";
		};

		ethernet@b2000 {
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		par_io@e0100 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xe0100 0x60>;
			ranges = <0x0 0xe0100 0x60>;
			device_type = "par_io";
			num-ports = <3>;
			pio1: ucc_pin@01 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
					0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
					0x0  0x17 0x2  0x0  0x2  0x0    /* CLK12 */
					0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9 */
					0x0  0x7  0x1  0x0  0x2  0x0    /* ENET1_TXD0_SER1_TXD0 */
					0x0  0x9  0x1  0x0  0x2  0x0    /* ENET1_TXD1_SER1_TXD1 */
					0x0  0xb  0x1  0x0  0x2  0x0    /* ENET1_TXD2_SER1_TXD2 */
					0x0  0xc  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
					0x0  0x6  0x2  0x0  0x2  0x0    /* ENET1_RXD0_SER1_RXD0 */
					0x0  0xa  0x2  0x0  0x2  0x0    /* ENET1_RXD1_SER1_RXD1 */
					0x0  0xe  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
					0x0  0xf  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
					0x0  0x5  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
					0x0  0xd  0x1  0x0  0x2  0x0    /* ENET1_TX_ER */
					0x0  0x4  0x2  0x0  0x2  0x0    /* ENET1_RX_DV_SER1_CTS_B */
					0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RX_ER_SER1_CD_B */
					0x0  0x11 0x2  0x0  0x2  0x0    /* ENET1_CRS */
					0x0  0x10 0x2  0x0  0x2  0x0>;    /* ENET1_COL */
			};

			pio2: ucc_pin@02 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
					0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
					0x1  0xb  0x2  0x0  0x1  0x0    /* CLK13 */
					0x1  0x7  0x1  0x0  0x2  0x0    /* ENET5_TXD0_SER5_TXD0 */
					0x1  0xa  0x1  0x0  0x2  0x0    /* ENET5_TXD1_SER5_TXD1 */
					0x1  0x6  0x2  0x0  0x2  0x0    /* ENET5_RXD0_SER5_RXD0 */
					0x1  0x9  0x2  0x0  0x2  0x0    /* ENET5_RXD1_SER5_RXD1 */
					0x1  0x5  0x1  0x0  0x2  0x0    /* ENET5_TX_EN_SER5_RTS_B */
					0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
					0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
			};
		};
	};

	pci0: pcie@ffe09000 {
		reg = <0 0xffe09000 0 0x1000>;
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		reg = <0 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xc0000000
				  0x2000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	qe: qe@ffe80000 {
		ranges = <0x0 0x0 0xffe80000 0x40000>;
		reg = <0 0xffe80000 0 0x480>;
		brg-frequency = <0>;
		bus-frequency = <0>;
		status = "disabled"; /* no firmware loaded */

		enet3: ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "clk12";
			tx-clock-name = "clk9";
			pio-handle = <&pio1>;
			phy-handle = <&qe_phy0>;
			phy-connection-type = "mii";
		};

		mdio@2120 {
			qe_phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <4 1 0 0>;
				reg = <0x0>;
			};
			qe_phy1: ethernet-phy@03 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1 0 0>;
				reg = <0x3>;
			};
			tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet4: ucc@2400 {
			device_type = "network";
			compatible = "ucc_geth";
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk13";
			pio-handle = <&pio2>;
			phy-handle = <&qe_phy1>;
			phy-connection-type = "rmii";
		};
	};
};

/include/ "p1021si-post.dtsi"