/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/*==========================================================================*/
/*!
 * @file
 *
 * Header file used to configure SoC pin list.
 */
/*==========================================================================*/

/* DO NOT EDIT - This file auto generated by bin/pins_h.pl */

#ifndef _SC_PINS_H
#define _SC_PINS_H

/* Includes */

/* Defines */

#define SC_P_ALL            UINT16_MAX      //!< All pins

/*!
 * @name Pin Definitions
 */
/*@{*/
#define SC_P_PCIE_CTRL0_CLKREQ_B                 0    //!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO0.IO08
#define SC_P_PCIE_CTRL0_WAKE_B                   1    //!< HSIO.PCIE0.WAKE_B, LSIO.GPIO0.IO09
#define SC_P_PCIE_CTRL0_PERST_B                  2    //!< HSIO.PCIE0.PERST_B, LSIO.GPIO0.IO10
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3    //!<
#define SC_P_EMMC0_CLK                           4    //!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO0.IO21
#define SC_P_EMMC0_CMD                           5    //!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO0.IO22
#define SC_P_EMMC0_DATA0                         6    //!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO0.IO23
#define SC_P_EMMC0_DATA1                         7    //!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO0.IO24
#define SC_P_EMMC0_DATA2                         8    //!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO0.IO25
#define SC_P_EMMC0_DATA3                         9    //!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO0.IO26
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       10   //!<
#define SC_P_EMMC0_DATA4                         11   //!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO0.IO27
#define SC_P_EMMC0_DATA5                         12   //!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO0.IO28
#define SC_P_EMMC0_DATA6                         13   //!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO0.IO29
#define SC_P_EMMC0_DATA7                         14   //!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO0.IO30
#define SC_P_EMMC0_STROBE                        15   //!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO0.IO31
#define SC_P_EMMC0_RESET_B                       16   //!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO1.IO00
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1       17   //!<
#define SC_P_USDHC1_RESET_B                      18   //!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO0.IO11
#define SC_P_USDHC1_VSELECT                      19   //!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO0.IO12
#define SC_P_CTL_NAND_RE_P_N                     20   //!<
#define SC_P_USDHC1_WP                           21   //!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO0.IO13
#define SC_P_USDHC1_CD_B                         22   //!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO0.IO14
#define SC_P_CTL_NAND_DQS_P_N                    23   //!<
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       24   //!<
#define SC_P_USDHC1_CLK                          25   //!< CONN.USDHC1.CLK, ADMA.UART4.RX, LSIO.GPIO0.IO15
#define SC_P_USDHC1_CMD                          26   //!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO0.IO16
#define SC_P_USDHC1_DATA0                        27   //!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO0.IO17
#define SC_P_USDHC1_DATA1                        28   //!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART4.TX, LSIO.GPIO0.IO18
#define SC_P_USDHC1_DATA2                        29   //!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART4.CTS_B, LSIO.GPIO0.IO19
#define SC_P_USDHC1_DATA3                        30   //!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART4.RTS_B, LSIO.GPIO0.IO20
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         31   //!<
#define SC_P_ENET0_RGMII_TXC                     32   //!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO1.IO01
#define SC_P_ENET0_RGMII_TX_CTL                  33   //!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO1.IO02
#define SC_P_ENET0_RGMII_TXD0                    34   //!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO1.IO03
#define SC_P_ENET0_RGMII_TXD1                    35   //!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO1.IO04
#define SC_P_ENET0_RGMII_TXD2                    36   //!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO1.IO05
#define SC_P_ENET0_RGMII_TXD3                    37   //!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO1.IO06
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   38   //!<
#define SC_P_ENET0_RGMII_RXC                     39   //!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO1.IO07
#define SC_P_ENET0_RGMII_RX_CTL                  40   //!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO1.IO08
#define SC_P_ENET0_RGMII_RXD0                    41   //!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO1.IO09
#define SC_P_ENET0_RGMII_RXD1                    42   //!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO1.IO10
#define SC_P_ENET0_RGMII_RXD2                    43   //!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO1.IO11
#define SC_P_ENET0_RGMII_RXD3                    44   //!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO1.IO12
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   45   //!<
#define SC_P_USB_SS3_TC0                         46   //!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO0.IO00
#define SC_P_USB_SS3_TC1                         47   //!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO0.IO01
#define SC_P_USB_SS3_TC2                         48   //!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO0.IO02
#define SC_P_USB_SS3_TC3                         49   //!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO0.IO03
#define SC_P_UART1_TX                            50   //!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO04
#define SC_P_UART1_RX                            51   //!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO05
#define SC_P_UART1_RTS_B                         52   //!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK, LSIO.GPIO0.IO06
#define SC_P_UART1_CTS_B                         53   //!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO07
#define SC_P_COMP_CTL_GPIO_1V8_3V3_USB3IO        54   //!<
#define SC_P_ENET0_REFCLK_125M_25M               55   //!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO2.IO02
#define SC_P_ENET0_MDIO                          56   //!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO2.IO00
#define SC_P_ENET0_MDC                           57   //!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO2.IO01
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        58   //!<
#define SC_P_ESAI0_FSR                           59   //!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN
#define SC_P_ESAI0_FST                           60   //!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D04, CONN.ENET1.RGMII_TXD2, LSIO.GPIO2.IO07
#define SC_P_ESAI0_SCKR                          61   //!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO2.IO04
#define SC_P_ESAI0_SCKT                          62   //!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D05, CONN.ENET1.RGMII_TXD3, LSIO.GPIO2.IO08
#define SC_P_ESAI0_TX0                           63   //!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXC, LSIO.GPIO2.IO09
#define SC_P_ESAI0_TX1                           64   //!< ADMA.ESAI0.TX1, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD3, LSIO.GPIO2.IO10
#define SC_P_ESAI0_TX2_RX3                       65   //!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D08, CONN.ENET1.RGMII_RXD2, LSIO.GPIO2.IO11
#define SC_P_ESAI0_TX3_RX2                       66   //!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D09, CONN.ENET1.RGMII_RXD1, LSIO.GPIO2.IO12
#define SC_P_ESAI0_TX4_RX1                       67   //!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TXD0, LSIO.GPIO2.IO05
#define SC_P_ESAI0_TX5_RX0                       68   //!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD1, LSIO.GPIO2.IO06
#define SC_P_SPDIF0_RX                           69   //!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO2.IO13
#define SC_P_SPDIF0_TX                           70   //!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO2.IO14
#define SC_P_SPDIF0_EXT_CLK                      71   //!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO2.IO15
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       72   //!<
#define SC_P_SPI3_SCK                            73   //!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO2.IO16
#define SC_P_SPI3_SDO                            74   //!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO2.IO17
#define SC_P_SPI3_SDI                            75   //!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO2.IO18
#define SC_P_SPI3_CS0                            76   //!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO2.IO19
#define SC_P_SPI3_CS1                            77   //!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16
#define SC_P_MCLK_IN0                            78   //!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO2.IO21
#define SC_P_MCLK_OUT0                           79   //!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO2.IO22
#define SC_P_MCLK_IN1                            80   //!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       81   //!<
#define SC_P_SAI0_TXD                            82   //!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO3.IO02
#define SC_P_SAI0_TXC                            83   //!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO3.IO03
#define SC_P_SAI0_RXD                            84   //!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO3.IO04
#define SC_P_SAI0_TXFS                           85   //!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO3.IO01
#define SC_P_SAI1_RXD                            86   //!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D22, LSIO.GPIO3.IO06
#define SC_P_SAI1_RXC                            87   //!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D21, LSIO.GPIO3.IO05
#define SC_P_SAI1_RXFS                           88   //!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO3.IO07
#define SC_P_SPI2_CS0                            89   //!< ADMA.SPI2.CS0, LSIO.GPIO3.IO00
#define SC_P_SPI2_SDO                            90   //!< ADMA.SPI2.SDO, LSIO.GPIO2.IO30
#define SC_P_SPI2_SDI                            91   //!< ADMA.SPI2.SDI, LSIO.GPIO2.IO31
#define SC_P_SPI2_SCK                            92   //!< ADMA.SPI2.SCK, LSIO.GPIO2.IO29
#define SC_P_SPI0_SCK                            93   //!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO2.IO24
#define SC_P_SPI0_SDI                            94   //!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO2.IO26
#define SC_P_SPI0_SDO                            95   //!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO2.IO25
#define SC_P_SPI0_CS1                            96   //!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO2.IO28
#define SC_P_SPI0_CS0                            97   //!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO2.IO27
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       98   //!<
#define SC_P_FLEXCAN0_RX                         99   //!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO3.IO14
#define SC_P_FLEXCAN0_TX                         100  //!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO3.IO15
#define SC_P_FLEXCAN1_RX                         101  //!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH1, ADMA.SAI1.TXD, LSIO.GPIO3.IO16
#define SC_P_FLEXCAN1_TX                         102  //!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO3.IO17
#define SC_P_FLEXCAN2_RX                         103  //!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO3.IO18
#define SC_P_FLEXCAN2_TX                         104  //!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO3.IO19
#define SC_P_UART0_RX                            105  //!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, LSIO.GPIO3.IO20
#define SC_P_UART0_TX                            106  //!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, LSIO.GPIO3.IO21
#define SC_P_UART2_TX                            107  //!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO3.IO23
#define SC_P_UART2_RX                            108  //!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO3.IO22
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        109  //!<
#define SC_P_ADC_IN1                             110  //!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO3.IO09
#define SC_P_ADC_IN0                             111  //!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO3.IO08
#define SC_P_ADC_IN3                             112  //!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO3.IO11
#define SC_P_ADC_IN2                             113  //!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO3.IO10
#define SC_P_ADC_IN5                             114  //!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO3.IO13
#define SC_P_ADC_IN4                             115  //!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO3.IO12
#define SC_P_MIPI_DSI0_I2C0_SCL                  116  //!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO5.IO04
#define SC_P_MIPI_DSI0_I2C0_SDA                  117  //!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO5.IO05
#define SC_P_MIPI_DSI0_GPIO0_00                  118  //!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO5.IO06
#define SC_P_MIPI_DSI0_GPIO0_01                  119  //!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO5.IO07
#define SC_P_MIPI_DSI1_I2C0_SCL                  120  //!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO5.IO08
#define SC_P_MIPI_DSI1_I2C0_SDA                  121  //!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO5.IO09
#define SC_P_MIPI_DSI1_GPIO0_00                  122  //!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO5.IO10
#define SC_P_MIPI_DSI1_GPIO0_01                  123  //!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO5.IO11
#define SC_P_PMIC_I2C_SCL                        124  //!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO3.IO31
#define SC_P_PMIC_I2C_SDA                        125  //!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO3.IO30
#define SC_P_JTAG_TDO                            126  //!< SCU.JTAG.TDO, SCU.WDOG0.WDOG_OUT
#define SC_P_JTAG_TDI                            127  //!< SCU.JTAG.TDI, SCU.DSC.RTC_CLOCK_OUTPUT_32K
#define SC_P_PMIC_INT_B                          128  //!< SCU.DSC.PMIC_INT_B
#define SC_P_SCU_GPIO0_00                        129  //!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART4.RX, LSIO.GPIO3.IO28
#define SC_P_SCU_GPIO0_01                        130  //!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART4.TX, LSIO.GPIO3.IO29
#define SC_P_SCU_PMIC_STANDBY                    131  //!< SCU.DSC.PMIC_STANDBY
#define SC_P_SCU_BOOT_MODE0                      132  //!< SCU.DSC.BOOT_MODE0
#define SC_P_SCU_BOOT_MODE1                      133  //!< SCU.DSC.BOOT_MODE1
#define SC_P_SCU_BOOT_MODE2                      134  //!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA
#define SC_P_SCU_BOOT_MODE3                      135  //!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K
#define SC_P_CSI_D02                             136  //!< CI_PI.D02, ADMA.SAI0.RXC, SNVS.TAMPER_OUT0
#define SC_P_CSI_D03                             137  //!< CI_PI.D03, ADMA.SAI0.RXD, SNVS.TAMPER_OUT1
#define SC_P_CSI_D04                             138  //!< CI_PI.D04, ADMA.SAI0.RXFS, SNVS.TAMPER_OUT2
#define SC_P_CSI_D05                             139  //!< CI_PI.D05, ADMA.SAI2.RXC, SNVS.TAMPER_OUT3
#define SC_P_CSI_D06                             140  //!< CI_PI.D06, ADMA.SAI2.RXD, SNVS.TAMPER_OUT4
#define SC_P_CSI_D07                             141  //!< CI_PI.D07, ADMA.SAI2.RXFS, SNVS.TAMPER_IN0
#define SC_P_CSI_D08                             142  //!< CI_PI.D08, ADMA.SAI3.RXC, SNVS.TAMPER_IN1
#define SC_P_CSI_D09                             143  //!< CI_PI.D09, ADMA.SAI3.RXD, SNVS.TAMPER_IN2
#define SC_P_CSI_HSYNC                           144  //!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS, SNVS.TAMPER_IN3
#define SC_P_CSI_VSYNC                           145  //!< CI_PI.VSYNC, CI_PI.D01, SNVS.TAMPER_IN4
#define SC_P_CSI_PCLK                            146  //!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO5.IO00
#define SC_P_CSI_MCLK                            147  //!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO5.IO01
#define SC_P_CSI_EN                              148  //!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO5.IO02
#define SC_P_CSI_RESET                           149  //!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO5.IO03
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       150  //!<
#define SC_P_MIPI_CSI0_MCLK_OUT                  151  //!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO5.IO12
#define SC_P_MIPI_CSI0_I2C0_SCL                  152  //!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO5.IO13
#define SC_P_MIPI_CSI0_I2C0_SDA                  153  //!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO5.IO14
#define SC_P_MIPI_CSI0_GPIO0_00                  154  //!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO5.IO15
#define SC_P_MIPI_CSI0_GPIO0_01                  155  //!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO5.IO16
#define SC_P_QSPI0A_DATA0                        156  //!< LSIO.QSPI0A.DATA0, LSIO.GPIO5.IO17
#define SC_P_QSPI0A_DATA1                        157  //!< LSIO.QSPI0A.DATA1, LSIO.GPIO5.IO18
#define SC_P_QSPI0A_DATA2                        158  //!< LSIO.QSPI0A.DATA2, LSIO.GPIO5.IO19
#define SC_P_QSPI0A_DATA3                        159  //!< LSIO.QSPI0A.DATA3, LSIO.GPIO5.IO20
#define SC_P_QSPI0A_DQS                          160  //!< LSIO.QSPI0A.DQS, LSIO.GPIO5.IO21
#define SC_P_QSPI0A_SS0_B                        161  //!< LSIO.QSPI0A.SS0_B, LSIO.GPIO5.IO22
#define SC_P_QSPI0A_SS1_B                        162  //!< LSIO.QSPI0A.SS1_B, LSIO.GPIO5.IO23
#define SC_P_QSPI0A_SCLK                         163  //!< LSIO.QSPI0A.SCLK, LSIO.GPIO5.IO24
#define SC_P_QSPI0B_SCLK                         164  //!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO5.IO25
#define SC_P_QSPI0B_DATA0                        165  //!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO5.IO26
#define SC_P_QSPI0B_DATA1                        166  //!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO5.IO27
#define SC_P_QSPI0B_DATA2                        167  //!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO5.IO28
#define SC_P_QSPI0B_DATA3                        168  //!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO5.IO29
#define SC_P_QSPI0B_DQS                          169  //!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO5.IO30
#define SC_P_QSPI0B_SS0_B                        170  //!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO5.IO31
#define SC_P_QSPI0B_SS1_B                        171  //!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO6.IO00
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         172  //!<
#define SC_P_XTALI                               173  //!< SCU.DSC.XTALI
#define SC_P_XTALO                               174  //!< SCU.DSC.XTALO
#define SC_P_ANA_TEST_OUT_P                      175  //!< SCU.DSC.TEST_OUT_P
#define SC_P_ANA_TEST_OUT_N                      176  //!< SCU.DSC.TEST_OUT_N
#define SC_P_RTC_XTALI                           177  //!< SNVS.RTC_XTALI
#define SC_P_RTC_XTALO                           178  //!< SNVS.RTC_XTALO
#define SC_P_PMIC_ON_REQ                         179  //!< SNVS.PMIC_ON_REQ
#define SC_P_ON_OFF_BUTTON                       180  //!< SNVS.ON_OFF_BUTTON
/*@}*/

#endif /* _SC_PINS_H */