| #include <dt-bindings/clock/tegra210-car.h> |
| #include <dt-bindings/gpio/tegra-gpio.h> |
| #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> |
| |
| #include "skeleton.dtsi" |
| |
| / { |
| compatible = "nvidia,tegra210"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| pcie-controller@0,01003000 { |
| compatible = "nvidia,tegra210-pcie"; |
| device_type = "pci"; |
| reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ |
| 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ |
| 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ |
| reg-names = "pads", "afi", "cs"; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| interrupt-names = "intr", "msi"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| |
| bus-range = <0x00 0xff>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ |
| 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ |
| 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ |
| 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ |
| 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ |
| |
| clocks = <&tegra_car TEGRA210_CLK_PCIE>, |
| <&tegra_car TEGRA210_CLK_AFI>, |
| <&tegra_car TEGRA210_CLK_PLL_E>, |
| <&tegra_car TEGRA210_CLK_CML0>; |
| clock-names = "pex", "afi", "pll_e", "cml"; |
| resets = <&tegra_car 70>, |
| <&tegra_car 72>, |
| <&tegra_car 74>; |
| reset-names = "pex", "afi", "pcie_x"; |
| status = "disabled"; |
| |
| phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; |
| phy-names = "pcie"; |
| |
| pci@1,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; |
| reg = <0x000800 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <4>; |
| }; |
| |
| pci@2,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; |
| reg = <0x001000 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <1>; |
| }; |
| }; |
| |
| gic: interrupt-controller@0,50041000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x50041000 0x0 0x1000>, |
| <0x0 0x50042000 0x0 0x2000>, |
| <0x0 0x50044000 0x0 0x2000>, |
| <0x0 0x50046000 0x0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| tegra_car: clock@0,60006000 { |
| compatible = "nvidia,tegra210-car"; |
| reg = <0x0 0x60006000 0x0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| gpio: gpio@0,6000d000 { |
| compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; |
| reg = <0x0 0x6000d000 0x0 0x1000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| }; |
| |
| i2c@0,7000c000 { |
| compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x7000c000 0x0 0x100>; |
| interrupts = <0 38 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 12>; |
| status = "disabled"; |
| }; |
| |
| i2c@0,7000c400 { |
| compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x7000c400 0x0 0x100>; |
| interrupts = <0 84 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 54>; |
| status = "disabled"; |
| }; |
| |
| i2c@0,7000c500 { |
| compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x7000c500 0x0 0x100>; |
| interrupts = <0 92 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 67>; |
| status = "disabled"; |
| }; |
| |
| i2c@0,7000c700 { |
| compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x7000c700 0x0 0x100>; |
| interrupts = <0 120 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 103>; |
| status = "disabled"; |
| }; |
| |
| i2c@0,7000d000 { |
| compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x7000d000 0x0 0x100>; |
| interrupts = <0 53 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 47>; |
| status = "disabled"; |
| }; |
| |
| i2c@0,7000d100 { |
| compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x7000d100 0x0 0x100>; |
| interrupts = <0 53 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 47>; |
| status = "disabled"; |
| }; |
| |
| uarta: serial@0,70006000 { |
| compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x70006000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA210_CLK_UARTA>; |
| resets = <&tegra_car 6>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartb: serial@0,70006040 { |
| compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x70006040 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA210_CLK_UARTB>; |
| resets = <&tegra_car 7>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartc: serial@0,70006200 { |
| compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x70006200 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA210_CLK_UARTC>; |
| resets = <&tegra_car 55>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartd: serial@0,70006300 { |
| compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x70006300 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA210_CLK_UARTD>; |
| resets = <&tegra_car 65>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| spi@0,7000d400 { |
| compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
| reg = <0x0 0x7000d400 0x0 0x200>; |
| interrupts = <0 59 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car TEGRA210_CLK_SBC1>; |
| resets = <&tegra_car 41>; |
| reset-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@0,7000d600 { |
| compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
| reg = <0x0 0x7000d600 0x0 0x200>; |
| interrupts = <0 82 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car TEGRA210_CLK_SBC2>; |
| resets = <&tegra_car 44>; |
| reset-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@0,7000d800 { |
| compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
| reg = <0x0 0x7000d800 0x0 0x200>; |
| interrupts = <0 83 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car TEGRA210_CLK_SBC3>; |
| resets = <&tegra_car 46>; |
| reset-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@0,7000da00 { |
| compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
| reg = <0x0 0x7000da00 0x0 0x200>; |
| interrupts = <0 93 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car TEGRA210_CLK_SBC4>; |
| resets = <&tegra_car 68>; |
| reset-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@0,70410000 { |
| compatible = "nvidia,tegra210-qspi"; |
| reg = <0x0 0x70410000 0x0 0x1000>; |
| interrupts = <0 10 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 211>; |
| status = "disabled"; |
| }; |
| |
| padctl: padctl@0,7009f000 { |
| compatible = "nvidia,tegra210-xusb-padctl"; |
| reg = <0x0 0x7009f000 0x0 0x1000>; |
| resets = <&tegra_car 142>; |
| reset-names = "padctl"; |
| #phy-cells = <1>; |
| }; |
| |
| sdhci@0,700b0000 { |
| compatible = "nvidia,tegra210-sdhci"; |
| reg = <0x0 0x700b0000 0x0 0x200>; |
| interrupts = <0 14 0x04>; |
| clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; |
| resets = <&tegra_car 14>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| sdhci@0,700b0200 { |
| compatible = "nvidia,tegra210-sdhci"; |
| reg = <0x0 0x700b0200 0x0 0x200>; |
| interrupts = <0 15 0x04>; |
| clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; |
| resets = <&tegra_car 9>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| sdhci@0,700b0400 { |
| compatible = "nvidia,tegra210-sdhci"; |
| reg = <0x0 0x700b0400 0x0 0x200>; |
| interrupts = <0 19 0x04>; |
| clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; |
| resets = <&tegra_car 69>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| sdhci@0,700b0600 { |
| compatible = "nvidia,tegra210-sdhci"; |
| reg = <0x0 0x700b0600 0x0 0x200>; |
| interrupts = <0 31 0x04>; |
| clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; |
| resets = <&tegra_car 15>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| usb@0,7d000000 { |
| compatible = "nvidia,tegra210-ehci"; |
| reg = <0x0 0x7d000000 0x0 0x4000>; |
| interrupts = <0 20 0x04>; |
| phy_type = "utmi"; |
| clocks = <&tegra_car TEGRA210_CLK_USBD>; |
| resets = <&tegra_car 22>; |
| reset-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| usb@0,7d004000 { |
| compatible = "nvidia,tegra210-ehci"; |
| reg = <0x0 0x7d004000 0x0 0x4000>; |
| interrupts = < 53 >; |
| phy_type = "utmi"; |
| clocks = <&tegra_car TEGRA210_CLK_USB2>; |
| resets = <&tegra_car 58>; |
| reset-names = "usb"; |
| status = "disabled"; |
| }; |
| }; |
