| /* |
| * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef _IPQ5018_H |
| #define _IPQ5018_H |
| |
| #ifndef DO_DEPS_ONLY |
| #include <generated/asm-offsets.h> |
| #endif |
| |
| #define CONFIG_IPQ5018 |
| #undef CONFIG_QCA_DISABLE_SCM |
| #define CONFIG_SPI_FLASH_CYPRESS |
| #define CONFIG_SYS_NO_FLASH |
| #define CONFIG_SYS_CACHELINE_SIZE 64 |
| #define CONFIG_IPQ_NO_RELOC |
| |
| #define CONFIG_SYS_VSNPRINTF |
| |
| /* |
| * Enable Early and Late init |
| * This config needs for secondary boot and to set BADOFF5E |
| * This config also need for spi-nor boot, |
| * set size and offset of hlos and rootfs |
| */ |
| #define CONFIG_BOARD_EARLY_INIT_F |
| #define CONFIG_BOARD_LATE_INIT |
| |
| #define CONFIG_IPQ5018_UART |
| #define CONFIG_NR_DRAM_BANKS 1 |
| #define CONFIG_SKIP_LOWLEVEL_INIT |
| |
| #define CONFIG_SYS_BOOTM_LEN 0x4000000 |
| |
| #define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */ |
| |
| /* |
| * PSCI Calls enable |
| */ |
| #define CONFIG_ARMV7_PSCI |
| |
| /* |
| * Enable Flashwrite command |
| */ |
| #define CONFIG_CMD_FLASHWRITE |
| |
| /* |
| * Enable Env overwrite support |
| */ |
| #define CONFIG_ENV_OVERWRITE |
| |
| /* |
| * select serial console configuration |
| */ |
| #define CONFIG_CONS_INDEX 1 |
| #define CONFIG_SYS_DEVICE_NULLDEV |
| |
| /* allow to overwrite serial and ethaddr */ |
| #define CONFIG_BAUDRATE 115200 |
| #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 115200} |
| |
| #define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */ |
| /* |
| |
| svc_sp --> -------------- |
| irq_sp --> | | |
| fiq_sp --> | | |
| bd --> | | |
| gd --> | | |
| pgt --> | | |
| malloc --> | | |
| text_base --> |------------| |
| */ |
| |
| #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\ |
| CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\ |
| GENERATED_BD_INFO_SIZE) |
| |
| #define CONFIG_SYS_MAXARGS 16 |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| sizeof(CONFIG_SYS_PROMPT) + 16) |
| |
| #define TLMM_BASE 0x01000000 |
| #define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000) |
| #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000) |
| |
| #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| #define CONFIG_SYS_TEXT_BASE 0x4A920000 |
| #define CONFIG_SYS_SDRAM_SIZE 0x10000000 |
| #define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE |
| #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 28)) |
| |
| #define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE |
| #define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE |
| #define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100) |
| |
| /*#define CONFIG_OF_COMBINE 1*/ |
| |
| |
| #define CONFIG_QCA_SMEM_BASE 0x4AB00000 |
| |
| #define CONFIG_IPQ_FDT_HIGH 0x4A400000 |
| #define CONFIG_ENV_IS_IN_SPI_FLASH 1 |
| #define CONFIG_ENV_SECT_SIZE (64 * 1024) |
| |
| #define CONFIG_QCA_UBOOT_OFFSET 0xA800000 |
| #define CONFIG_UBOOT_END_ADDR 0x4AA00000 |
| #define CONFIG_SMEM_END_ADDR 0x4AC00000 |
| |
| /* |
| * IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region. |
| * CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting |
| * address of WLAN Area. |
| * TFTP file can only be written in Linux HLOS region and WLAN AREA. |
| */ |
| #define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20)) |
| #define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21)) |
| #define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size) |
| |
| #ifndef __ASSEMBLY__ |
| #include <compiler.h> |
| extern loff_t board_env_offset; |
| extern loff_t board_env_range; |
| extern loff_t board_env_size; |
| #endif |
| |
| #define CONFIG_IPQ5018_ENV 1 |
| #define CONFIG_ENV_OFFSET board_env_offset |
| #define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX |
| #define CONFIG_ENV_RANGE board_env_range |
| #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (500 << 10)) |
| |
| /* |
| * NAND Flash Configs |
| */ |
| |
| /* CONFIG_QPIC_NAND: QPIC NAND in BAM mode |
| * CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode. |
| * BAM is enabled by default. |
| */ |
| #define CONFIG_CMD_MTDPARTS |
| #define CONFIG_SYS_NAND_SELF_INIT |
| |
| #ifdef CONFIG_NAND_FLASH |
| #define CONFIG_CMD_NAND |
| #define CONFIG_ENV_IS_IN_NAND 1 |
| #define CONFIG_QPIC_NAND |
| #define CONFIG_SYS_NAND_ONFI_DETECTION |
| #define CONFIG_CMD_NAND_YAFFS |
| #define CONFIG_MTD_DEVICE |
| #define CONFIG_MTD_PARTITIONS |
| #endif |
| |
| #ifdef CONFIG_QPIC_SERIAL |
| #ifdef QSPI_SERIAL_DEBUG /* QSPI DEBUG */ |
| #define qspi_debug(fmt,args...) printf (fmt ,##args) |
| #else |
| #define qspi_debug(fmt,args...) |
| #endif /* QSPI DEBUG */ |
| #define CONFIG_PAGE_SCOPE_MULTI_PAGE_READ |
| #define CONFIG_QSPI_SERIAL_TRAINING |
| #endif |
| |
| /* |
| * SPI Flash Configs |
| */ |
| #define CONFIG_QCA_SPI |
| #define CONFIG_SPI_FLASH |
| #define CONFIG_CMD_SF |
| #define CONFIG_SPI_FLASH_STMICRO |
| #define CONFIG_SPI_FLASH_WINBOND |
| #define CONFIG_SPI_FLASH_MACRONIX |
| #define CONFIG_SPI_FLASH_GIGADEVICE |
| #define CONFIG_SPI_FLASH_SPANSION |
| #define CONFIG_SF_DEFAULT_BUS 0 |
| #define CONFIG_SF_DEFAULT_CS 0 |
| #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
| #define CONFIG_SF_DEFAULT_SPEED (48 * 1000 * 1000) |
| #define CONFIG_SPI_FLASH_BAR 1 |
| #define CONFIG_SPI_FLASH_USE_4K_SECTORS |
| #define CONFIG_IPQ_4B_ADDR_SWITCH_REQD |
| |
| #define CONFIG_QUP_SPI_USE_DMA 1 |
| #define CONFIG_QCA_BAM 1 |
| |
| /* |
| * MMC configs |
| */ |
| #ifdef CONFIG_MMC_FLASH |
| #define CONFIG_QCA_MMC |
| #define CONFIG_MMC |
| #define CONFIG_CMD_MMC |
| #define CONFIG_GENERIC_MMC |
| #define CONFIG_SDHCI |
| #define CONFIG_SDHCI_QCA |
| #define CONFIG_ENV_IS_IN_MMC |
| #define CONFIG_SYS_MMC_ENV_DEV 0 |
| #define CONFIG_SDHCI_SUPPORT |
| #define CONFIG_MMC_ADMA |
| #define CONFIG_EFI_PARTITION |
| #define CONFIG_MMC_VENDOR_SECURE_ERASE |
| /* |
| * eMMC controller support only 4-bit |
| * force SDHC driver to 4-bit mode |
| */ |
| #define CONFIG_MMC_FORCE_CAP_4BIT_BUSWIDTH |
| #endif |
| |
| /* |
| * Andoid A/B boot support |
| */ |
| #define CONFIG_ANDROID_AB_BOOT |
| |
| /* |
| * I2C Enable |
| */ |
| #ifdef CONFIG_IPQ5018_I2C |
| #define CONFIG_SYS_I2C_QUP |
| #define CONFIG_CMD_I2C |
| #define CONFIG_DM_I2C |
| #endif |
| |
| /* |
| * GMAC Enable |
| */ |
| |
| #define CONFIG_IPQ5018_GMAC |
| #define CONFIG_IPQ5018_MDIO |
| |
| #define CONFIG_NET_RETRY_COUNT 5 |
| #define CONFIG_SYS_RX_ETH_BUFFER 16 |
| #define CONFIG_CMD_PING |
| #define CONFIG_CMD_DHCP |
| #define CONFIG_MII |
| #define CONFIG_IPADDR 192.168.10.10 |
| #define CONFIG_NETMASK 255.255.255.0 |
| #define CONFIG_SERVERIP 192.168.10.19 |
| #define CONFIG_CMD_TFTPPUT |
| #define CONFIG_IPQ_MDIO 1 |
| #define CONFIG_IPQ_ETH_INIT_DEFER |
| #define CONFIG_IPQ_NO_MACS 2 |
| |
| /* |
| * GEPHY |
| */ |
| #define CONFIG_GEPHY |
| |
| /* |
| * USB Support |
| */ |
| #ifdef CONFIG_USB_XHCI_IPQ |
| #define CONFIG_USB_XHCI |
| #define CONFIG_USB_XHCI_DWC3 |
| #define CONFIG_CMD_USB |
| #define CONFIG_USB_STORAGE |
| #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
| #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| |
| /* |
| * USB crashdump collection |
| */ |
| #define CONFIG_FS_FAT |
| #define CONFIG_FAT_WRITE |
| #define CONFIG_CMD_FAT |
| |
| /* |
| * Block Device & Disk Partition Config |
| */ |
| #define HAVE_BLOCK_DEVICE |
| #define CONFIG_DOS_PARTITION |
| |
| /* |
| * USB device mode suppport |
| */ |
| #define CONFIG_USB_GADGET |
| #define CONFIG_USB_FUNCTION_MASS_STORAGE |
| #define CONFIG_USB_DWC3_GADGET |
| #define CONFIG_USB_DWC3 |
| #define CONFIG_USB_GADGET_DOWNLOAD |
| #define CONFIG_USB_GADGET_VBUS_DRAW 2 |
| #define CONFIG_USB_GADGET_DUALSPEED |
| |
| /* Fastboot */ |
| #define CONFIG_USB_FUNCTION_FASTBOOT |
| #define CONFIG_CMD_FASTBOOT |
| #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR |
| #define CONFIG_FASTBOOT_BUF_SIZE 0x8000000 |
| #define CONFIG_FASTBOOT_FLASH |
| #define CONFIG_FASTBOOT_FLASH_MMC_DEV CONFIG_SYS_MMC_ENV_DEV |
| #define FASTBOOT_MMC_SKIP_ERASE_GROUP |
| #define FASTBOOT_SKIP_ERROR |
| |
| #define CONFIG_G_DNL_VENDOR_NUM 0x18d1 |
| #define CONFIG_G_DNL_PRODUCT_NUM 0xD00D |
| #define CONFIG_G_DNL_MANUFACTURER "Google" |
| |
| /* skip proto header file */ |
| #define _SYS_PROTO_H_ |
| #define SKIP_MULTI_DEF |
| #endif |
| |
| /* |
| * PCIE Enable |
| */ |
| #define PCI_MAX_DEVICES 2 |
| #if defined(CONFIG_PCI_IPQ) |
| #define CONFIG_PCI |
| #define CONFIG_CMD_PCI |
| #define CONFIG_PCI_SCAN_SHOW |
| #endif |
| |
| /* |
| * Expose SPI driver as a pseudo NAND driver to make use |
| * of U-Boot's MTD framework. |
| */ |
| #define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \ |
| CONFIG_IPQ_MAX_SPI_DEVICE |
| |
| #define CONFIG_IPQ_MAX_NAND_DEVICE 1 |
| #define CONFIG_IPQ_MAX_SPI_DEVICE 1 |
| |
| #define CONFIG_QPIC_NAND_NAND_INFO_IDX 0 |
| #define CONFIG_IPQ_SPI_NOR_INFO_IDX 1 |
| |
| #define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX |
| #define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX |
| |
| #define QCA_SPI_NOR_DEVICE "spi0.0" |
| |
| /* |
| * U-Boot Env Configs |
| */ |
| #define CONFIG_OF_LIBFDT 1 |
| #define CONFIG_SYS_HUSH_PARSER |
| #define CONFIG_CMD_XIMG |
| |
| /* MTEST */ |
| #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x1300000 |
| #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + 0x100 |
| |
| /* NSS firmware loaded using bootm */ |
| #define CONFIG_BOOTCOMMAND "bootipq" |
| #define CONFIG_BOOTARGS "androidboot.hardware="BOARD_NAME |
| #define QCA_ROOT_FS_PART_NAME "rootfs" |
| |
| #define CONFIG_BOOTDELAY 0 |
| |
| #define NUM_ALT_PARTITION 16 |
| |
| #ifdef CONFIG_IPQ_TINY |
| /* undef gzip lib */ |
| #undef CONFIG_GZIP |
| #undef CONFIG_ZLIB |
| |
| #else |
| #define CONFIG_CMD_BOOTZ |
| |
| /* Multicore CPU support */ |
| #define CONFIG_SMP_CMD_SUPPORT |
| |
| /* Mii command support */ |
| #define CONFIG_CMD_MII |
| |
| /* compress crash dump support */ |
| #define CONFIG_CMD_ZIP |
| #define CONFIG_GZIP_COMPRESSED |
| |
| /* Enable DTB compress */ |
| #if 0 |
| #define CONFIG_COMPRESSED_DTB_MAX_SIZE 0x40000 |
| #define CONFIG_COMPRESSED_DTB_BASE CONFIG_SYS_TEXT_BASE -\ |
| CONFIG_COMPRESSED_DTB_MAX_SIZE |
| #endif |
| #endif |
| |
| #define CONFIG_FDT_FIXUP_PARTITIONS |
| |
| #define CONFIG_IPQ_FDT_FIXUP |
| /* |
| * Below Configs need to be updated after enabling reset_crashdump |
| * Included now to avoid build failure |
| */ |
| #define CONFIG_OF_BOARD_SETUP |
| |
| #ifdef CONFIG_OF_BOARD_SETUP |
| #define DLOAD_DISABLE 0x1 |
| #define SET_MAGIC 0x1 |
| #define CLEAR_MAGIC 0x0 |
| #define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9 |
| #define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10 |
| #define SCM_CMD_TZ_PSHOLD 0x16 |
| #define BOOT_VERSION 0 |
| #define TZ_VERSION 1 |
| #endif |
| |
| |
| #define CONFIG_IPQ5018_TZ_WONCE_4_ADDR 0x193d010 |
| /* |
| * CRASH DUMP ENABLE |
| */ |
| #define CONFIG_QCA_APPSBL_DLOAD |
| #define CONFIG_IPQ5018_DMAGIC_ADDR 0x193D100 |
| #ifdef CONFIG_QCA_APPSBL_DLOAD |
| |
| #undef CONFIG_NET_RETRY_COUNT |
| #define CONFIG_NET_RETRY_COUNT 500 |
| |
| #define IPQ_TEMP_DUMP_ADDR 0x44000000 |
| #endif |
| |
| #define CONFIG_QCA_KERNEL_CRASHDUMP_ADDRESS *((unsigned int *)0x08600658) |
| #define CONFIG_CPU_CONTEXT_DUMP_SIZE 4096 |
| #define TLV_BUF_OFFSET 1012 * 1024 |
| #define CONFIG_TLV_DUMP_SIZE 12 * 1024 |
| |
| /* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes |
| * Cache flush and invalidation based on L1 cache, so the cache line |
| * size is configured to 64 */ |
| #define CONFIG_SYS_CACHELINE_SIZE 64 |
| |
| /* |
| * UBI write command |
| */ |
| #ifdef CONFIG_UBI_WRITE |
| #define CONFIG_CMD_UBI |
| #define CONFIG_RBTREE |
| #define IPQ_UBI_VOL_WRITE_SUPPORT |
| #endif |
| |
| #undef CONFIG_BOOTM_NETBSD |
| #undef CONFIG_BOOTM_PLAN9 |
| #undef CONFIG_BOOTM_RTEMS |
| #undef CONFIG_BOOTM_VXWORKS |
| |
| #ifdef CONFIG_ART_COMPRESSED |
| /* |
| * This location use to keep comprssed data for |
| * uncompress process. |
| * default location is CONFIG_SYS_LOAD_ADDR if not defined. |
| */ |
| #define CONFIG_COMPRESSED_LOAD_ADDR (CONFIG_SYS_LOAD_ADDR + (1 << 22)) |
| #endif |
| |
| #ifdef CONFIG_SMP_CMD_SUPPORT |
| #define NR_CPUS 2 |
| #endif |
| |
| /* |
| * 96 MHz |
| */ |
| |
| #define INTERNAL_96MHZ |
| |
| /* INITRD_HIGH */ |
| #define CONFIG_INITRD_HIGH 0x46000000 |
| |
| /*#define CONFIG_IPQ_BT_SUPPORT*/ |
| |
| #define CONFIG_CRASHDUMP_TO_MMC_FLASH |
| #ifdef CONFIG_CRASHDUMP_TO_MMC_FLASH |
| #define CRASH_DUMP_PARTITION_NAME "crash" |
| #define CONFIG_CMD_EXT4 |
| #define CONFIG_CMD_EXT4_WRITE |
| |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| "dump_compressed=1\0" \ |
| "ext4_on_mmc=1\0" |
| #endif |
| |
| /* maximum boot image size */ |
| #define CONFIG_BOOGIMG_SIZE_MAX (64 << 20) /* 64MB */ |
| |
| #endif /* _IPQ5018_H */ |
