| /******************************************************************************* |
| * 2017 Synaptics Incorporated. All Rights Reserved * |
| * THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF Synaptics. * |
| * NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * |
| * OF Synaptics OR ANY THIRD PARTY. Synaptics RESERVES THE RIGHT AT ITS SOLE * |
| * DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO Synaptics. * |
| * THIS CODE IS PROVIDED "AS IS". Synaptics MAKES NO WARRANTIES, EXPRESSED, * |
| * IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * |
| * * |
| *******************************************************************************/ |
| #ifndef _DIAG_PLL_H_ |
| #define _DIAG_PLL_H_ |
| |
| #include "Galois_memmap.h" |
| #include "global.h" |
| #include "cpu_wrp.h" |
| #include "MC6Ctrl.h" |
| #include "nand_drv.h" |
| |
| #define DOWN 1 |
| #define UP 0 |
| |
| #define ENABLE 1 |
| #define DISABLE 0 |
| |
| #define BYPASS 1 |
| #define UNBYPASS 0 |
| |
| #define INT 0 |
| #define FRACTION 1 |
| |
| #define DPONLY 1 |
| #define ALL 0 |
| |
| // REF CLOCK divider, recommended value from ASIC Vinson as 1. |
| // FREF=25Mhz, FREF/Mint [1:100], FREF/Mfrac [10:100] ==> M [1:2] |
| // 1 is recommended by ASIC. |
| #define M1 1 |
| #define M5 5 |
| #define FREF 25 |
| |
| enum PLLMODE { |
| INT_MODE = 0, |
| FRAC_MODE, |
| SSC_MODE, |
| RSVD, |
| }; |
| |
| enum E_PLL_SRC { |
| DIAG_SYSPLL = 0, |
| DIAG_MEMPLL, |
| DIAG_CPUPLL, |
| DIAG_APLL0, |
| DIAG_APLL1, |
| }; |
| |
| enum divider_index { |
| DIVIDED_BY_2 = 1, |
| DIVIDED_BY_4, |
| DIVIDED_BY_6, |
| DIVIDED_BY_8, |
| DIVIDED_BY_12, |
| }; |
| |
| #define PLL_REG_SET(tmpstr, field123, val123) tmpstr.uctrl_##field123 = val123 |
| #define PLL_REG_GET(tmpstr, field123, val123) val123 = tmpstr.uctrl_##field123 |
| |
| #define PLL_REG_READ(baseaddr, offset, val123) \ |
| do { \ |
| val123 = hal_read32((baseaddr + offset * 4)); \ |
| } while (0) |
| |
| #define PLL_REG_WRITE(baseaddr, offset, val123) \ |
| do { \ |
| hal_write32((baseaddr + offset * 4), val123); \ |
| } while (0) |
| |
| |
| typedef struct { |
| int clocko; |
| int clocko1; |
| } CLOCKO_t; |
| |
| typedef struct { |
| unsigned int dm; |
| unsigned int dn; |
| unsigned int frac; |
| unsigned int dp; |
| } APLLCFG_t; |
| |
| typedef struct { |
| unsigned int ssc; |
| unsigned int freq; |
| unsigned int amp; |
| } SSC_t; |
| |
| |
| CLOCKO_t diag_get_cpupll(); |
| |
| #endif //_DIAG_PLL_H_ |