| // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| /* |
| * hw.h - DesignWare HS OTG Controller hardware definitions |
| * |
| * Copyright 2004-2013 Synopsys, Inc. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * 1. Redistributions of source code must retain the above copyright |
| * notice, this list of conditions, and the following disclaimer, |
| * without modification. |
| * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * 3. The names of the above-listed copyright holders may not be used |
| * to endorse or promote products derived from this software without |
| * specific prior written permission. |
| * |
| * ALTERNATIVELY, this software may be distributed under the terms of the |
| * GNU General Public License ("GPL") as published by the Free Software |
| * Foundation; either version 2 of the License, or (at your option) any |
| * later version. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #ifndef __DWC2_HW_H__ |
| #define __DWC2_HW_H__ |
| |
| #ifndef BIT |
| #define BIT(x) (1UL << (x)) |
| #endif |
| #define HSOTG_REG(x) (x) |
| #define GENMASK(h, l) \ |
| (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (64 - 1 - (h)))) |
| |
| |
| #define GOTGCTL HSOTG_REG(0x000) |
| #define GOTGCTL_CHIRPEN BIT(27) |
| #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) |
| #define GOTGCTL_MULT_VALID_BC_SHIFT 22 |
| #define GOTGCTL_OTGVER BIT(20) |
| #define GOTGCTL_BSESVLD BIT(19) |
| #define GOTGCTL_ASESVLD BIT(18) |
| #define GOTGCTL_DBNC_SHORT BIT(17) |
| #define GOTGCTL_CONID_B BIT(16) |
| #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15) |
| #define GOTGCTL_DEVHNPEN BIT(11) |
| #define GOTGCTL_HSTSETHNPEN BIT(10) |
| #define GOTGCTL_HNPREQ BIT(9) |
| #define GOTGCTL_HSTNEGSCS BIT(8) |
| #define GOTGCTL_SESREQ BIT(1) |
| #define GOTGCTL_SESREQSCS BIT(0) |
| #define DWC2_GOTGCTL_SESREQSCS (1 << 0) |
| #define DWC2_GOTGCTL_SESREQSCS_OFFSET 0 |
| #define DWC2_GOTGCTL_SESREQ (1 << 1) |
| #define DWC2_GOTGCTL_SESREQ_OFFSET 1 |
| #define DWC2_GOTGCTL_HSTNEGSCS (1 << 8) |
| #define DWC2_GOTGCTL_HSTNEGSCS_OFFSET 8 |
| #define DWC2_GOTGCTL_HNPREQ (1 << 9) |
| #define DWC2_GOTGCTL_HNPREQ_OFFSET 9 |
| #define DWC2_GOTGCTL_HSTSETHNPEN (1 << 10) |
| #define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET 10 |
| #define DWC2_GOTGCTL_DEVHNPEN (1 << 11) |
| #define DWC2_GOTGCTL_DEVHNPEN_OFFSET 11 |
| #define DWC2_GOTGCTL_CONIDSTS (1 << 16) |
| #define DWC2_GOTGCTL_CONIDSTS_OFFSET 16 |
| #define DWC2_GOTGCTL_DBNCTIME (1 << 17) |
| #define DWC2_GOTGCTL_DBNCTIME_OFFSET 17 |
| #define DWC2_GOTGCTL_ASESVLD (1 << 18) |
| #define DWC2_GOTGCTL_ASESVLD_OFFSET 18 |
| #define DWC2_GOTGCTL_BSESVLD (1 << 19) |
| #define DWC2_GOTGCTL_BSESVLD_OFFSET 19 |
| #define DWC2_GOTGCTL_OTGVER (1 << 20) |
| #define DWC2_GOTGCTL_OTGVER_OFFSET 20 |
| |
| #define GOTGINT HSOTG_REG(0x004) |
| #define GOTGINT_DBNCE_DONE BIT(19) |
| #define GOTGINT_A_DEV_TOUT_CHG BIT(18) |
| #define GOTGINT_HST_NEG_DET BIT(17) |
| #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9) |
| #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8) |
| #define GOTGINT_SES_END_DET BIT(2) |
| #define DWC2_GOTGINT_SESENDDET (1 << 2) |
| #define DWC2_GOTGINT_SESENDDET_OFFSET 2 |
| #define DWC2_GOTGINT_SESREQSUCSTSCHNG (1 << 8) |
| #define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET 8 |
| #define DWC2_GOTGINT_HSTNEGSUCSTSCHNG (1 << 9) |
| #define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 9 |
| #define DWC2_GOTGINT_RESERVER10_16_MASK (0x7F << 10) |
| #define DWC2_GOTGINT_RESERVER10_16_OFFSET 10 |
| #define DWC2_GOTGINT_HSTNEGDET (1 << 17) |
| #define DWC2_GOTGINT_HSTNEGDET_OFFSET 17 |
| #define DWC2_GOTGINT_ADEVTOUTCHNG (1 << 18) |
| #define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET 18 |
| #define DWC2_GOTGINT_DEBDONE (1 << 19) |
| #define DWC2_GOTGINT_DEBDONE_OFFSET 19 |
| |
| #define GAHBCFG HSOTG_REG(0x008) |
| #define GAHBCFG_AHB_SINGLE BIT(23) |
| #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22) |
| #define GAHBCFG_REM_MEM_SUPP BIT(21) |
| #define GAHBCFG_P_TXF_EMP_LVL BIT(8) |
| #define GAHBCFG_NP_TXF_EMP_LVL BIT(7) |
| #define GAHBCFG_DMA_EN BIT(5) |
| #define GAHBCFG_HBSTLEN_MASK (0xf << 1) |
| #define GAHBCFG_HBSTLEN_SHIFT 1 |
| #define GAHBCFG_HBSTLEN_SINGLE 0 |
| #define GAHBCFG_HBSTLEN_INCR 1 |
| #define GAHBCFG_HBSTLEN_INCR4 3 |
| #define GAHBCFG_HBSTLEN_INCR8 5 |
| #define GAHBCFG_HBSTLEN_INCR16 7 |
| #define GAHBCFG_GLBL_INTR_EN BIT(0) |
| #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ |
| GAHBCFG_NP_TXF_EMP_LVL | \ |
| GAHBCFG_DMA_EN | \ |
| GAHBCFG_GLBL_INTR_EN) |
| #define DWC2_GAHBCFG_GLBLINTRMSK (1 << 0) |
| #define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET 0 |
| #define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1) |
| #define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1) |
| #define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1) |
| #define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1) |
| #define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1) |
| #define DWC2_GAHBCFG_HBURSTLEN_MASK (0xF << 1) |
| #define DWC2_GAHBCFG_HBURSTLEN_OFFSET 1 |
| #define DWC2_GAHBCFG_DMAENABLE (1 << 5) |
| #define DWC2_GAHBCFG_DMAENABLE_OFFSET 5 |
| #define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL (1 << 7) |
| #define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET 7 |
| #define DWC2_GAHBCFG_PTXFEMPLVL (1 << 8) |
| #define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET 8 |
| |
| |
| #define GUSBCFG HSOTG_REG(0x00C) |
| #define GUSBCFG_FORCEDEVMODE BIT(30) |
| #define GUSBCFG_FORCEHOSTMODE BIT(29) |
| #define GUSBCFG_TXENDDELAY BIT(28) |
| #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27) |
| #define GUSBCFG_ICUSBCAP BIT(26) |
| #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) |
| #define GUSBCFG_INDICATORPASSTHROUGH BIT(24) |
| #define GUSBCFG_INDICATORCOMPLEMENT BIT(23) |
| #define GUSBCFG_TERMSELDLPULSE BIT(22) |
| #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21) |
| #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) |
| #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19) |
| #define GUSBCFG_ULPI_AUTO_RES BIT(18) |
| #define GUSBCFG_ULPI_FS_LS BIT(17) |
| #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16) |
| #define GUSBCFG_PHY_LP_CLK_SEL BIT(15) |
| #define GUSBCFG_USBTRDTIM_MASK (0xf << 10) |
| #define GUSBCFG_USBTRDTIM_SHIFT 10 |
| #define GUSBCFG_HNPCAP BIT(9) |
| #define GUSBCFG_SRPCAP BIT(8) |
| #define GUSBCFG_DDRSEL BIT(7) |
| #define GUSBCFG_PHYSEL BIT(6) |
| #define GUSBCFG_FSINTF BIT(5) |
| #define GUSBCFG_ULPI_UTMI_SEL BIT(4) |
| #define GUSBCFG_PHYIF16 BIT(3) |
| #define GUSBCFG_PHYIF8 (0 << 3) |
| #define GUSBCFG_TOUTCAL_MASK (0x7 << 0) |
| #define GUSBCFG_TOUTCAL_SHIFT 0 |
| #define GUSBCFG_TOUTCAL_LIMIT 0x7 |
| #define GUSBCFG_TOUTCAL(_x) ((_x) << 0) |
| #define DWC2_GUSBCFG_TOUTCAL_MASK (0x7 << 0) |
| #define DWC2_GUSBCFG_TOUTCAL_OFFSET 0 |
| #define DWC2_GUSBCFG_PHYIF (1 << 3) |
| #define DWC2_GUSBCFG_PHYIF_OFFSET 3 |
| #define DWC2_GUSBCFG_ULPI_UTMI_SEL (1 << 4) |
| #define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET 4 |
| #define DWC2_GUSBCFG_FSINTF (1 << 5) |
| #define DWC2_GUSBCFG_FSINTF_OFFSET 5 |
| #define DWC2_GUSBCFG_PHYSEL (1 << 6) |
| #define DWC2_GUSBCFG_PHYSEL_OFFSET 6 |
| #define DWC2_GUSBCFG_DDRSEL (1 << 7) |
| #define DWC2_GUSBCFG_DDRSEL_OFFSET 7 |
| #define DWC2_GUSBCFG_SRPCAP (1 << 8) |
| #define DWC2_GUSBCFG_SRPCAP_OFFSET 8 |
| #define DWC2_GUSBCFG_HNPCAP (1 << 9) |
| #define DWC2_GUSBCFG_HNPCAP_OFFSET 9 |
| #define DWC2_GUSBCFG_USBTRDTIM_MASK (0xF << 10) |
| #define DWC2_GUSBCFG_USBTRDTIM_OFFSET 10 |
| #define DWC2_GUSBCFG_NPTXFRWNDEN (1 << 14) |
| #define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET 14 |
| #define DWC2_GUSBCFG_PHYLPWRCLKSEL (1 << 15) |
| #define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET 15 |
| #define DWC2_GUSBCFG_OTGUTMIFSSEL (1 << 16) |
| #define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET 16 |
| #define DWC2_GUSBCFG_ULPI_FSLS (1 << 17) |
| #define DWC2_GUSBCFG_ULPI_FSLS_OFFSET 17 |
| #define DWC2_GUSBCFG_ULPI_AUTO_RES (1 << 18) |
| #define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET 18 |
| #define DWC2_GUSBCFG_ULPI_CLK_SUS_M (1 << 19) |
| #define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET 19 |
| #define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) |
| #define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET 20 |
| #define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR (1 << 21) |
| #define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21 |
| #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22) |
| #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22 |
| #define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH (1 << 24) |
| #define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH_OFFSET 24 |
| #define DWC2_GUSBCFG_IC_USB_CAP (1 << 26) |
| #define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26 |
| #define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27) |
| #define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET 27 |
| #define DWC2_GUSBCFG_TX_END_DELAY (1 << 28) |
| #define DWC2_GUSBCFG_TX_END_DELAY_OFFSET 28 |
| #define DWC2_GUSBCFG_FORCEHOSTMODE (1 << 29) |
| #define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET 29 |
| #define DWC2_GUSBCFG_FORCEDEVMODE (1 << 30) |
| #define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET 30 |
| |
| |
| #define GRSTCTL HSOTG_REG(0x010) |
| #define GRSTCTL_AHBIDLE BIT(31) |
| #define GRSTCTL_DMAREQ BIT(30) |
| #define GRSTCTL_TXFNUM_MASK (0x1f << 6) |
| #define GRSTCTL_TXFNUM_SHIFT 6 |
| #define GRSTCTL_TXFNUM_LIMIT 0x1f |
| #define GRSTCTL_TXFNUM(_x) ((_x) << 6) |
| #define GRSTCTL_TXFFLSH BIT(5) |
| #define GRSTCTL_RXFFLSH BIT(4) |
| #define GRSTCTL_IN_TKNQ_FLSH BIT(3) |
| #define GRSTCTL_FRMCNTRRST BIT(2) |
| #define GRSTCTL_HSFTRST BIT(1) |
| #define GRSTCTL_CSFTRST BIT(0) |
| #define DWC2_GRSTCTL_CSFTRST (1 << 0) |
| #define DWC2_GRSTCTL_CSFTRST_OFFSET 0 |
| #define DWC2_GRSTCTL_HSFTRST (1 << 1) |
| #define DWC2_GRSTCTL_HSFTRST_OFFSET 1 |
| #define DWC2_GRSTCTL_HSTFRM (1 << 2) |
| #define DWC2_GRSTCTL_HSTFRM_OFFSET 2 |
| #define DWC2_GRSTCTL_INTKNQFLSH (1 << 3) |
| #define DWC2_GRSTCTL_INTKNQFLSH_OFFSET 3 |
| #define DWC2_GRSTCTL_RXFFLSH (1 << 4) |
| #define DWC2_GRSTCTL_RXFFLSH_OFFSET 4 |
| #define DWC2_GRSTCTL_TXFFLSH (1 << 5) |
| #define DWC2_GRSTCTL_TXFFLSH_OFFSET 5 |
| #define DWC2_GRSTCTL_TXFNUM_MASK (0x1F << 6) |
| #define DWC2_GRSTCTL_TXFNUM_OFFSET 6 |
| #define DWC2_GRSTCTL_DMAREQ (1 << 30) |
| #define DWC2_GRSTCTL_DMAREQ_OFFSET 30 |
| #define DWC2_GRSTCTL_AHBIDLE (1 << 31) |
| #define DWC2_GRSTCTL_AHBIDLE_OFFSET 31 |
| |
| #define GINTSTS HSOTG_REG(0x014) |
| #define GINTMSK HSOTG_REG(0x018) |
| #define DWC2_GINTMSK_MODEMISMATCH (1 << 1) |
| #define DWC2_GINTMSK_MODEMISMATCH_OFFSET 1 |
| #define DWC2_GINTMSK_OTGINTR (1 << 2) |
| #define DWC2_GINTMSK_OTGINTR_OFFSET 2 |
| #define DWC2_GINTMSK_SOFINTR (1 << 3) |
| #define DWC2_GINTMSK_SOFINTR_OFFSET 3 |
| #define DWC2_GINTMSK_RXSTSQLVL (1 << 4) |
| #define DWC2_GINTMSK_RXSTSQLVL_OFFSET 4 |
| #define DWC2_GINTMSK_NPTXFEMPTY (1 << 5) |
| #define DWC2_GINTMSK_NPTXFEMPTY_OFFSET 5 |
| #define DWC2_GINTMSK_GINNAKEFF (1 << 6) |
| #define DWC2_GINTMSK_GINNAKEFF_OFFSET 6 |
| #define DWC2_GINTMSK_GOUTNAKEFF (1 << 7) |
| #define DWC2_GINTMSK_GOUTNAKEFF_OFFSET 7 |
| #define DWC2_GINTMSK_I2CINTR (1 << 9) |
| #define DWC2_GINTMSK_I2CINTR_OFFSET 9 |
| #define DWC2_GINTMSK_ERLYSUSPEND (1 << 10) |
| #define DWC2_GINTMSK_ERLYSUSPEND_OFFSET 10 |
| #define DWC2_GINTMSK_USBSUSPEND (1 << 11) |
| #define DWC2_GINTMSK_USBSUSPEND_OFFSET 11 |
| #define DWC2_GINTMSK_USBRESET (1 << 12) |
| #define DWC2_GINTMSK_USBRESET_OFFSET 12 |
| #define DWC2_GINTMSK_ENUMDONE (1 << 13) |
| #define DWC2_GINTMSK_ENUMDONE_OFFSET 13 |
| #define DWC2_GINTMSK_ISOOUTDROP (1 << 14) |
| #define DWC2_GINTMSK_ISOOUTDROP_OFFSET 14 |
| #define DWC2_GINTMSK_EOPFRAME (1 << 15) |
| #define DWC2_GINTMSK_EOPFRAME_OFFSET 15 |
| #define DWC2_GINTMSK_EPMISMATCH (1 << 17) |
| #define DWC2_GINTMSK_EPMISMATCH_OFFSET 17 |
| #define DWC2_GINTMSK_INEPINTR (1 << 18) |
| #define DWC2_GINTMSK_INEPINTR_OFFSET 18 |
| #define DWC2_GINTMSK_OUTEPINTR (1 << 19) |
| #define DWC2_GINTMSK_OUTEPINTR_OFFSET 19 |
| #define DWC2_GINTMSK_INCOMPLISOIN (1 << 20) |
| #define DWC2_GINTMSK_INCOMPLISOIN_OFFSET 20 |
| #define DWC2_GINTMSK_INCOMPLISOOUT (1 << 21) |
| #define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET 21 |
| #define DWC2_GINTMSK_PORTINTR (1 << 24) |
| #define DWC2_GINTMSK_PORTINTR_OFFSET 24 |
| #define DWC2_GINTMSK_HCINTR (1 << 25) |
| #define DWC2_GINTMSK_HCINTR_OFFSET 25 |
| #define DWC2_GINTMSK_PTXFEMPTY (1 << 26) |
| #define DWC2_GINTMSK_PTXFEMPTY_OFFSET 26 |
| #define DWC2_GINTMSK_LPMTRANRCVD (1 << 27) |
| #define DWC2_GINTMSK_LPMTRANRCVD_OFFSET 27 |
| #define DWC2_GINTMSK_CONIDSTSCHNG (1 << 28) |
| #define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET 28 |
| #define DWC2_GINTMSK_DISCONNECT (1 << 29) |
| #define DWC2_GINTMSK_DISCONNECT_OFFSET 29 |
| #define DWC2_GINTMSK_SESSREQINTR (1 << 30) |
| #define DWC2_GINTMSK_SESSREQINTR_OFFSET 30 |
| #define DWC2_GINTMSK_WKUPINTR (1 << 31) |
| #define DWC2_GINTMSK_WKUPINTR_OFFSET 31 |
| |
| |
| |
| #define GINTSTS_WKUPINT BIT(31) |
| #define GINTSTS_SESSREQINT BIT(30) |
| #define GINTSTS_DISCONNINT BIT(29) |
| #define GINTSTS_CONIDSTSCHNG BIT(28) |
| #define GINTSTS_LPMTRANRCVD BIT(27) |
| #define GINTSTS_PTXFEMP BIT(26) |
| #define GINTSTS_HCHINT BIT(25) |
| #define GINTSTS_PRTINT BIT(24) |
| #define GINTSTS_RESETDET BIT(23) |
| #define GINTSTS_FET_SUSP BIT(22) |
| #define GINTSTS_INCOMPL_IP BIT(21) |
| #define GINTSTS_INCOMPL_SOOUT BIT(21) |
| #define GINTSTS_INCOMPL_SOIN BIT(20) |
| #define GINTSTS_OEPINT BIT(19) |
| #define GINTSTS_IEPINT BIT(18) |
| #define GINTSTS_EPMIS BIT(17) |
| #define GINTSTS_RESTOREDONE BIT(16) |
| #define GINTSTS_EOPF BIT(15) |
| #define GINTSTS_ISOUTDROP BIT(14) |
| #define GINTSTS_ENUMDONE BIT(13) |
| #define GINTSTS_USBRST BIT(12) |
| #define GINTSTS_USBSUSP BIT(11) |
| #define GINTSTS_ERLYSUSP BIT(10) |
| #define GINTSTS_I2CINT BIT(9) |
| #define GINTSTS_ULPI_CK_INT BIT(8) |
| #define GINTSTS_GOUTNAKEFF BIT(7) |
| #define GINTSTS_GINNAKEFF BIT(6) |
| #define GINTSTS_NPTXFEMP BIT(5) |
| #define GINTSTS_RXFLVL BIT(4) |
| #define GINTSTS_SOF BIT(3) |
| #define GINTSTS_OTGINT BIT(2) |
| #define GINTSTS_MODEMIS BIT(1) |
| #define GINTSTS_CURMODE_HOST BIT(0) |
| #define DWC2_GINTSTS_CURMODE_DEVICE (0 << 0) |
| #define DWC2_GINTSTS_CURMODE_HOST (1 << 0) |
| #define DWC2_GINTSTS_CURMODE (1 << 0) |
| #define DWC2_GINTSTS_CURMODE_OFFSET 0 |
| #define DWC2_GINTSTS_MODEMISMATCH (1 << 1) |
| #define DWC2_GINTSTS_MODEMISMATCH_OFFSET 1 |
| #define DWC2_GINTSTS_OTGINTR (1 << 2) |
| #define DWC2_GINTSTS_OTGINTR_OFFSET 2 |
| #define DWC2_GINTSTS_SOFINTR (1 << 3) |
| #define DWC2_GINTSTS_SOFINTR_OFFSET 3 |
| #define DWC2_GINTSTS_RXSTSQLVL (1 << 4) |
| #define DWC2_GINTSTS_RXSTSQLVL_OFFSET 4 |
| #define DWC2_GINTSTS_NPTXFEMPTY (1 << 5) |
| #define DWC2_GINTSTS_NPTXFEMPTY_OFFSET 5 |
| #define DWC2_GINTSTS_GINNAKEFF (1 << 6) |
| #define DWC2_GINTSTS_GINNAKEFF_OFFSET 6 |
| #define DWC2_GINTSTS_GOUTNAKEFF (1 << 7) |
| #define DWC2_GINTSTS_GOUTNAKEFF_OFFSET 7 |
| #define DWC2_GINTSTS_I2CINTR (1 << 9) |
| #define DWC2_GINTSTS_I2CINTR_OFFSET 9 |
| #define DWC2_GINTSTS_ERLYSUSPEND (1 << 10) |
| #define DWC2_GINTSTS_ERLYSUSPEND_OFFSET 10 |
| #define DWC2_GINTSTS_USBSUSPEND (1 << 11) |
| #define DWC2_GINTSTS_USBSUSPEND_OFFSET 11 |
| #define DWC2_GINTSTS_USBRESET (1 << 12) |
| #define DWC2_GINTSTS_USBRESET_OFFSET 12 |
| #define DWC2_GINTSTS_ENUMDONE (1 << 13) |
| #define DWC2_GINTSTS_ENUMDONE_OFFSET 13 |
| #define DWC2_GINTSTS_ISOOUTDROP (1 << 14) |
| #define DWC2_GINTSTS_ISOOUTDROP_OFFSET 14 |
| #define DWC2_GINTSTS_EOPFRAME (1 << 15) |
| #define DWC2_GINTSTS_EOPFRAME_OFFSET 15 |
| #define DWC2_GINTSTS_INTOKENRX (1 << 16) |
| #define DWC2_GINTSTS_INTOKENRX_OFFSET 16 |
| #define DWC2_GINTSTS_EPMISMATCH (1 << 17) |
| #define DWC2_GINTSTS_EPMISMATCH_OFFSET 17 |
| #define DWC2_GINTSTS_INEPINT (1 << 18) |
| #define DWC2_GINTSTS_INEPINT_OFFSET 18 |
| #define DWC2_GINTSTS_OUTEPINTR (1 << 19) |
| #define DWC2_GINTSTS_OUTEPINTR_OFFSET 19 |
| #define DWC2_GINTSTS_INCOMPLISOIN (1 << 20) |
| #define DWC2_GINTSTS_INCOMPLISOIN_OFFSET 20 |
| #define DWC2_GINTSTS_INCOMPLISOOUT (1 << 21) |
| #define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET 21 |
| #define DWC2_GINTSTS_PORTINTR (1 << 24) |
| #define DWC2_GINTSTS_PORTINTR_OFFSET 24 |
| #define DWC2_GINTSTS_HCINTR (1 << 25) |
| #define DWC2_GINTSTS_HCINTR_OFFSET 25 |
| #define DWC2_GINTSTS_PTXFEMPTY (1 << 26) |
| #define DWC2_GINTSTS_PTXFEMPTY_OFFSET 26 |
| #define DWC2_GINTSTS_LPMTRANRCVD (1 << 27) |
| #define DWC2_GINTSTS_LPMTRANRCVD_OFFSET 27 |
| #define DWC2_GINTSTS_CONIDSTSCHNG (1 << 28) |
| #define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET 28 |
| #define DWC2_GINTSTS_DISCONNECT (1 << 29) |
| #define DWC2_GINTSTS_DISCONNECT_OFFSET 29 |
| #define DWC2_GINTSTS_SESSREQINTR (1 << 30) |
| #define DWC2_GINTSTS_SESSREQINTR_OFFSET 30 |
| #define DWC2_GINTSTS_WKUPINTR (1 << 31) |
| #define DWC2_GINTSTS_WKUPINTR_OFFSET 31 |
| |
| #define GRXSTSR HSOTG_REG(0x01C) |
| #define DWC2_GRXSTS_EPNUM_MASK (0xF << 0) |
| #define DWC2_GRXSTS_EPNUM_OFFSET 0 |
| #define DWC2_GRXSTS_BCNT_MASK (0x7FF << 4) |
| #define DWC2_GRXSTS_BCNT_OFFSET 4 |
| #define DWC2_GRXSTS_DPID_MASK (0x3 << 15) |
| #define DWC2_GRXSTS_DPID_OFFSET 15 |
| #define DWC2_GRXSTS_PKTSTS_MASK (0xF << 17) |
| #define DWC2_GRXSTS_PKTSTS_OFFSET 17 |
| #define DWC2_GRXSTS_FN_MASK (0xF << 21) |
| #define DWC2_GRXSTS_FN_OFFSET 21 |
| |
| #define GRXSTSP HSOTG_REG(0x020) |
| #define GRXSTS_FN_MASK (0x7f << 25) |
| #define GRXSTS_FN_SHIFT 25 |
| #define GRXSTS_PKTSTS_MASK (0xf << 17) |
| #define GRXSTS_PKTSTS_SHIFT 17 |
| #define GRXSTS_PKTSTS_GLOBALOUTNAK 1 |
| #define GRXSTS_PKTSTS_OUTRX 2 |
| #define GRXSTS_PKTSTS_HCHIN 2 |
| #define GRXSTS_PKTSTS_OUTDONE 3 |
| #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 |
| #define GRXSTS_PKTSTS_SETUPDONE 4 |
| #define GRXSTS_PKTSTS_DATATOGGLEERR 5 |
| #define GRXSTS_PKTSTS_SETUPRX 6 |
| #define GRXSTS_PKTSTS_HCHHALTED 7 |
| #define GRXSTS_HCHNUM_MASK (0xf << 0) |
| #define GRXSTS_HCHNUM_SHIFT 0 |
| #define GRXSTS_DPID_MASK (0x3 << 15) |
| #define GRXSTS_DPID_SHIFT 15 |
| #define GRXSTS_BYTECNT_MASK (0x7ff << 4) |
| #define GRXSTS_BYTECNT_SHIFT 4 |
| #define GRXSTS_EPNUM_MASK (0xf << 0) |
| #define GRXSTS_EPNUM_SHIFT 0 |
| |
| #define GRXFSIZ HSOTG_REG(0x024) |
| #define GRXFSIZ_DEPTH_MASK (0xffff << 0) |
| #define GRXFSIZ_DEPTH_SHIFT 0 |
| |
| #define GNPTXFSIZ HSOTG_REG(0x028) |
| /* Use FIFOSIZE_* constants to access this register */ |
| #define DWC2_FIFOSIZE_STARTADDR_MASK (0xFFFF << 0) |
| #define DWC2_FIFOSIZE_STARTADDR_OFFSET 0 |
| #define DWC2_FIFOSIZE_DEPTH_MASK (0xFFFF << 16) |
| #define DWC2_FIFOSIZE_DEPTH_OFFSET 16 |
| |
| #define GNPTXSTS HSOTG_REG(0x02C) |
| #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) |
| #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 |
| #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) |
| #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 |
| #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) |
| #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) |
| #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 |
| #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) |
| #define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK (0xFFFF << 0) |
| #define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET 0 |
| #define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK (0xFF << 16) |
| #define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET 16 |
| #define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE (1 << 24) |
| #define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET 24 |
| #define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK (0x3 << 25) |
| #define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET 25 |
| #define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK (0xF << 27) |
| #define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET 27 |
| |
| #define GI2CCTL HSOTG_REG(0x0030) |
| #define GI2CCTL_BSYDNE BIT(31) |
| #define GI2CCTL_RW BIT(30) |
| #define GI2CCTL_I2CDATSE0 BIT(28) |
| #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) |
| #define GI2CCTL_I2CDEVADDR_SHIFT 26 |
| #define GI2CCTL_I2CSUSPCTL BIT(25) |
| #define GI2CCTL_ACK BIT(24) |
| #define GI2CCTL_I2CEN BIT(23) |
| #define GI2CCTL_ADDR_MASK (0x7f << 16) |
| #define GI2CCTL_ADDR_SHIFT 16 |
| #define GI2CCTL_REGADDR_MASK (0xff << 8) |
| #define GI2CCTL_REGADDR_SHIFT 8 |
| #define GI2CCTL_RWDATA_MASK (0xff << 0) |
| #define GI2CCTL_RWDATA_SHIFT 0 |
| #define DWC2_GI2CCTL_RWDATA_MASK (0xFF << 0) |
| #define DWC2_GI2CCTL_RWDATA_OFFSET 0 |
| #define DWC2_GI2CCTL_REGADDR_MASK (0xFF << 8) |
| #define DWC2_GI2CCTL_REGADDR_OFFSET 8 |
| #define DWC2_GI2CCTL_ADDR_MASK (0x7F << 16) |
| #define DWC2_GI2CCTL_ADDR_OFFSET 16 |
| #define DWC2_GI2CCTL_I2CEN (1 << 23) |
| #define DWC2_GI2CCTL_I2CEN_OFFSET 23 |
| #define DWC2_GI2CCTL_ACK (1 << 24) |
| #define DWC2_GI2CCTL_ACK_OFFSET 24 |
| #define DWC2_GI2CCTL_I2CSUSPCTL (1 << 25) |
| #define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET 25 |
| #define DWC2_GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) |
| #define DWC2_GI2CCTL_I2CDEVADDR_OFFSET 26 |
| #define DWC2_GI2CCTL_RW (1 << 30) |
| #define DWC2_GI2CCTL_RW_OFFSET 30 |
| #define DWC2_GI2CCTL_BSYDNE (1 << 31) |
| #define DWC2_GI2CCTL_BSYDNE_OFFSET 31 |
| |
| |
| #define GPVNDCTL HSOTG_REG(0x0034) |
| #define GGPIO HSOTG_REG(0x0038) |
| #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16) |
| |
| #define GUID HSOTG_REG(0x003c) |
| #define GSNPSID HSOTG_REG(0x0040) |
| #define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12) |
| #define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12) |
| #define DWC2_SNPSID_DEVID_VER_4xx (0x4f544 << 12) |
| #define DWC2_SNPSID_DEVID_MASK (0xfffff << 12) |
| #define DWC2_SNPSID_DEVID_OFFSET 12 |
| |
| #define GHWCFG1 HSOTG_REG(0x0044) |
| #define DWC2_HWCFG1_EP_DIR0_MASK (0x3 << 0) |
| #define DWC2_HWCFG1_EP_DIR0_OFFSET 0 |
| #define DWC2_HWCFG1_EP_DIR1_MASK (0x3 << 2) |
| #define DWC2_HWCFG1_EP_DIR1_OFFSET 2 |
| #define DWC2_HWCFG1_EP_DIR2_MASK (0x3 << 4) |
| #define DWC2_HWCFG1_EP_DIR2_OFFSET 4 |
| #define DWC2_HWCFG1_EP_DIR3_MASK (0x3 << 6) |
| #define DWC2_HWCFG1_EP_DIR3_OFFSET 6 |
| #define DWC2_HWCFG1_EP_DIR4_MASK (0x3 << 8) |
| #define DWC2_HWCFG1_EP_DIR4_OFFSET 8 |
| #define DWC2_HWCFG1_EP_DIR5_MASK (0x3 << 10) |
| #define DWC2_HWCFG1_EP_DIR5_OFFSET 10 |
| #define DWC2_HWCFG1_EP_DIR6_MASK (0x3 << 12) |
| #define DWC2_HWCFG1_EP_DIR6_OFFSET 12 |
| #define DWC2_HWCFG1_EP_DIR7_MASK (0x3 << 14) |
| #define DWC2_HWCFG1_EP_DIR7_OFFSET 14 |
| #define DWC2_HWCFG1_EP_DIR8_MASK (0x3 << 16) |
| #define DWC2_HWCFG1_EP_DIR8_OFFSET 16 |
| #define DWC2_HWCFG1_EP_DIR9_MASK (0x3 << 18) |
| #define DWC2_HWCFG1_EP_DIR9_OFFSET 18 |
| #define DWC2_HWCFG1_EP_DIR10_MASK (0x3 << 20) |
| #define DWC2_HWCFG1_EP_DIR10_OFFSET 20 |
| #define DWC2_HWCFG1_EP_DIR11_MASK (0x3 << 22) |
| #define DWC2_HWCFG1_EP_DIR11_OFFSET 22 |
| #define DWC2_HWCFG1_EP_DIR12_MASK (0x3 << 24) |
| #define DWC2_HWCFG1_EP_DIR12_OFFSET 24 |
| #define DWC2_HWCFG1_EP_DIR13_MASK (0x3 << 26) |
| #define DWC2_HWCFG1_EP_DIR13_OFFSET 26 |
| #define DWC2_HWCFG1_EP_DIR14_MASK (0x3 << 28) |
| #define DWC2_HWCFG1_EP_DIR14_OFFSET 28 |
| #define DWC2_HWCFG1_EP_DIR15_MASK (0x3 << 30) |
| #define DWC2_HWCFG1_EP_DIR15_OFFSET 30 |
| |
| #define GSNPSID_ID_MASK GENMASK(31, 16) |
| |
| #define GHWCFG2 HSOTG_REG(0x0048) |
| #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31) |
| #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) |
| #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 |
| #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) |
| #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 |
| #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) |
| #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 |
| #define GHWCFG2_MULTI_PROC_INT BIT(20) |
| #define GHWCFG2_DYNAMIC_FIFO BIT(19) |
| #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18) |
| #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) |
| #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 |
| #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) |
| #define GHWCFG2_NUM_DEV_EP_SHIFT 10 |
| #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) |
| #define GHWCFG2_FS_PHY_TYPE_SHIFT 8 |
| #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 |
| #define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 |
| #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 |
| #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 |
| #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) |
| #define GHWCFG2_HS_PHY_TYPE_SHIFT 6 |
| #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 |
| #define GHWCFG2_HS_PHY_TYPE_UTMI 1 |
| #define GHWCFG2_HS_PHY_TYPE_ULPI 2 |
| #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 |
| #define GHWCFG2_POINT2POINT BIT(5) |
| #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) |
| #define GHWCFG2_ARCHITECTURE_SHIFT 3 |
| #define GHWCFG2_SLAVE_ONLY_ARCH 0 |
| #define GHWCFG2_EXT_DMA_ARCH 1 |
| #define GHWCFG2_INT_DMA_ARCH 2 |
| #define GHWCFG2_OP_MODE_MASK (0x7 << 0) |
| #define GHWCFG2_OP_MODE_SHIFT 0 |
| #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 |
| #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 |
| #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 |
| #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 |
| #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 |
| #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 |
| #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 |
| #define GHWCFG2_OP_MODE_UNDEFINED 7 |
| #define DWC2_HWCFG2_OP_MODE_MASK (0x7 << 0) |
| #define DWC2_HWCFG2_OP_MODE_OFFSET 0 |
| #define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3) |
| #define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3) |
| #define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3) |
| #define DWC2_HWCFG2_ARCHITECTURE_MASK (0x3 << 3) |
| #define DWC2_HWCFG2_ARCHITECTURE_OFFSET 3 |
| #define DWC2_HWCFG2_POINT2POINT (1 << 5) |
| #define DWC2_HWCFG2_POINT2POINT_OFFSET 5 |
| #define DWC2_HWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) |
| #define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET 6 |
| #define DWC2_HWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) |
| #define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET 8 |
| #define DWC2_HWCFG2_NUM_DEV_EP_MASK (0xF << 10) |
| #define DWC2_HWCFG2_NUM_DEV_EP_OFFSET 10 |
| #define DWC2_HWCFG2_NUM_HOST_CHAN_MASK (0xF << 14) |
| #define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET 14 |
| #define DWC2_HWCFG2_PERIO_EP_SUPPORTED (1 << 18) |
| #define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET 18 |
| #define DWC2_HWCFG2_DYNAMIC_FIFO (1 << 19) |
| #define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET 19 |
| #define DWC2_HWCFG2_MULTI_PROC_INT (1 << 20) |
| #define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET 20 |
| #define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) |
| #define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET 22 |
| #define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) |
| #define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET 24 |
| #define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1F << 26) |
| #define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET 26 |
| |
| #define GHWCFG3 HSOTG_REG(0x004c) |
| #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) |
| #define GHWCFG3_DFIFO_DEPTH_SHIFT 16 |
| #define GHWCFG3_OTG_LPM_EN BIT(15) |
| #define GHWCFG3_BC_SUPPORT BIT(14) |
| #define GHWCFG3_OTG_ENABLE_HSIC BIT(13) |
| #define GHWCFG3_ADP_SUPP BIT(12) |
| #define GHWCFG3_SYNCH_RESET_TYPE BIT(11) |
| #define GHWCFG3_OPTIONAL_FEATURES BIT(10) |
| #define GHWCFG3_VENDOR_CTRL_IF BIT(9) |
| #define GHWCFG3_I2C BIT(8) |
| #define GHWCFG3_OTG_FUNC BIT(7) |
| #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) |
| #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 |
| #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) |
| #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 |
| #define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xF << 0) |
| #define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET 0 |
| #define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) |
| #define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET 4 |
| #define DWC2_HWCFG3_OTG_FUNC (1 << 7) |
| #define DWC2_HWCFG3_OTG_FUNC_OFFSET 7 |
| #define DWC2_HWCFG3_I2C (1 << 8) |
| #define DWC2_HWCFG3_I2C_OFFSET 8 |
| #define DWC2_HWCFG3_VENDOR_CTRL_IF (1 << 9) |
| #define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET 9 |
| #define DWC2_HWCFG3_OPTIONAL_FEATURES (1 << 10) |
| #define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET 10 |
| #define DWC2_HWCFG3_SYNCH_RESET_TYPE (1 << 11) |
| #define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET 11 |
| #define DWC2_HWCFG3_OTG_ENABLE_IC_USB (1 << 12) |
| #define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET 12 |
| #define DWC2_HWCFG3_OTG_ENABLE_HSIC (1 << 13) |
| #define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET 13 |
| #define DWC2_HWCFG3_OTG_LPM_EN (1 << 15) |
| #define DWC2_HWCFG3_OTG_LPM_EN_OFFSET 15 |
| #define DWC2_HWCFG3_DFIFO_DEPTH_MASK (0xFFFF << 16) |
| #define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET 16 |
| |
| #define GHWCFG4 HSOTG_REG(0x0050) |
| #define GHWCFG4_DESC_DMA_DYN BIT(31) |
| #define GHWCFG4_DESC_DMA BIT(30) |
| #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) |
| #define GHWCFG4_NUM_IN_EPS_SHIFT 26 |
| #define GHWCFG4_DED_FIFO_EN BIT(25) |
| #define GHWCFG4_DED_FIFO_SHIFT 25 |
| #define GHWCFG4_SESSION_END_FILT_EN BIT(24) |
| #define GHWCFG4_B_VALID_FILT_EN BIT(23) |
| #define GHWCFG4_A_VALID_FILT_EN BIT(22) |
| #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) |
| #define GHWCFG4_IDDIG_FILT_EN BIT(20) |
| #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) |
| #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 |
| #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) |
| #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 |
| #define GHWCFG4_ACG_SUPPORTED BIT(12) |
| #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) |
| #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 |
| #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 |
| #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 |
| #define GHWCFG4_XHIBER BIT(7) |
| #define GHWCFG4_HIBER BIT(6) |
| #define GHWCFG4_MIN_AHB_FREQ BIT(5) |
| #define GHWCFG4_POWER_OPTIMIZ BIT(4) |
| #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) |
| #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 |
| #define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xF << 0) |
| #define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET 0 |
| #define DWC2_HWCFG4_POWER_OPTIMIZ (1 << 4) |
| #define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET 4 |
| #define DWC2_HWCFG4_MIN_AHB_FREQ_MASK (0x1FF << 5) |
| #define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET 5 |
| #define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) |
| #define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET 14 |
| #define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xF << 16) |
| #define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET 16 |
| #define DWC2_HWCFG4_IDDIG_FILT_EN (1 << 20) |
| #define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET 20 |
| #define DWC2_HWCFG4_VBUS_VALID_FILT_EN (1 << 21) |
| #define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET 21 |
| #define DWC2_HWCFG4_A_VALID_FILT_EN (1 << 22) |
| #define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET 22 |
| #define DWC2_HWCFG4_B_VALID_FILT_EN (1 << 23) |
| #define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET 23 |
| #define DWC2_HWCFG4_SESSION_END_FILT_EN (1 << 24) |
| #define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET 24 |
| #define DWC2_HWCFG4_DED_FIFO_EN (1 << 25) |
| #define DWC2_HWCFG4_DED_FIFO_EN_OFFSET 25 |
| #define DWC2_HWCFG4_NUM_IN_EPS_MASK (0xF << 26) |
| #define DWC2_HWCFG4_NUM_IN_EPS_OFFSET 26 |
| #define DWC2_HWCFG4_DESC_DMA (1 << 30) |
| #define DWC2_HWCFG4_DESC_DMA_OFFSET 30 |
| #define DWC2_HWCFG4_DESC_DMA_DYN (1 << 31) |
| #define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET 31 |
| |
| #define GLPMCFG HSOTG_REG(0x0054) |
| #define GLPMCFG_INVSELHSIC BIT(31) |
| #define GLPMCFG_HSICCON BIT(30) |
| #define GLPMCFG_RSTRSLPSTS BIT(29) |
| #define GLPMCFG_ENBESL BIT(28) |
| #define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25) |
| #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25 |
| #define GLPMCFG_SNDLPM BIT(24) |
| #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21) |
| #define GLPMCFG_RETRY_CNT_SHIFT 21 |
| #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17) |
| #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17 |
| #define GLPMCFG_L1RESUMEOK BIT(16) |
| #define GLPMCFG_SLPSTS BIT(15) |
| #define GLPMCFG_COREL1RES_MASK (0x3 << 13) |
| #define GLPMCFG_COREL1RES_SHIFT 13 |
| #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) |
| #define GLPMCFG_HIRD_THRES_SHIFT 8 |
| #define GLPMCFG_HIRD_THRES_EN (0x10 << 8) |
| #define GLPMCFG_ENBLSLPM BIT(7) |
| #define GLPMCFG_BREMOTEWAKE BIT(6) |
| #define GLPMCFG_HIRD_MASK (0xf << 2) |
| #define GLPMCFG_HIRD_SHIFT 2 |
| #define GLPMCFG_APPL1RES BIT(1) |
| #define GLPMCFG_LPMCAP BIT(0) |
| |
| #define GPWRDN HSOTG_REG(0x0058) |
| #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) |
| #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 |
| #define GPWRDN_ADP_INT BIT(23) |
| #define GPWRDN_BSESSVLD BIT(22) |
| #define GPWRDN_IDSTS BIT(21) |
| #define GPWRDN_LINESTATE_MASK (0x3 << 19) |
| #define GPWRDN_LINESTATE_SHIFT 19 |
| #define GPWRDN_STS_CHGINT_MSK BIT(18) |
| #define GPWRDN_STS_CHGINT BIT(17) |
| #define GPWRDN_SRP_DET_MSK BIT(16) |
| #define GPWRDN_SRP_DET BIT(15) |
| #define GPWRDN_CONNECT_DET_MSK BIT(14) |
| #define GPWRDN_CONNECT_DET BIT(13) |
| #define GPWRDN_DISCONN_DET_MSK BIT(12) |
| #define GPWRDN_DISCONN_DET BIT(11) |
| #define GPWRDN_RST_DET_MSK BIT(10) |
| #define GPWRDN_RST_DET BIT(9) |
| #define GPWRDN_LNSTSCHG_MSK BIT(8) |
| #define GPWRDN_LNSTSCHG BIT(7) |
| #define GPWRDN_DIS_VBUS BIT(6) |
| #define GPWRDN_PWRDNSWTCH BIT(5) |
| #define GPWRDN_PWRDNRSTN BIT(4) |
| #define GPWRDN_PWRDNCLMP BIT(3) |
| #define GPWRDN_RESTORE BIT(2) |
| #define GPWRDN_PMUACTV BIT(1) |
| #define GPWRDN_PMUINTSEL BIT(0) |
| |
| #define GDFIFOCFG HSOTG_REG(0x005c) |
| #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) |
| #define GDFIFOCFG_EPINFOBASE_SHIFT 16 |
| #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) |
| #define GDFIFOCFG_GDFIFOCFG_SHIFT 0 |
| |
| #define ADPCTL HSOTG_REG(0x0060) |
| #define ADPCTL_AR_MASK (0x3 << 27) |
| #define ADPCTL_AR_SHIFT 27 |
| #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26) |
| #define ADPCTL_ADP_SNS_INT_MSK BIT(25) |
| #define ADPCTL_ADP_PRB_INT_MSK BIT(24) |
| #define ADPCTL_ADP_TMOUT_INT BIT(23) |
| #define ADPCTL_ADP_SNS_INT BIT(22) |
| #define ADPCTL_ADP_PRB_INT BIT(21) |
| #define ADPCTL_ADPENA BIT(20) |
| #define ADPCTL_ADPRES BIT(19) |
| #define ADPCTL_ENASNS BIT(18) |
| #define ADPCTL_ENAPRB BIT(17) |
| #define ADPCTL_RTIM_MASK (0x7ff << 6) |
| #define ADPCTL_RTIM_SHIFT 6 |
| #define ADPCTL_PRB_PER_MASK (0x3 << 4) |
| #define ADPCTL_PRB_PER_SHIFT 4 |
| #define ADPCTL_PRB_DELTA_MASK (0x3 << 2) |
| #define ADPCTL_PRB_DELTA_SHIFT 2 |
| #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) |
| #define ADPCTL_PRB_DSCHRG_SHIFT 0 |
| |
| #define HPTXFSIZ HSOTG_REG(0x100) |
| /* Use FIFOSIZE_* constants to access this register */ |
| |
| #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) |
| /* Use FIFOSIZE_* constants to access this register */ |
| |
| /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ |
| #define FIFOSIZE_DEPTH_MASK (0xffff << 16) |
| #define FIFOSIZE_DEPTH_SHIFT 16 |
| #define FIFOSIZE_STARTADDR_MASK (0xffff << 0) |
| #define FIFOSIZE_STARTADDR_SHIFT 0 |
| #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) |
| |
| /* Device mode registers */ |
| |
| #define DCFG HSOTG_REG(0x800) |
| #define DCFG_DESCDMA_EN BIT(23) |
| #define DCFG_EPMISCNT_MASK (0x1f << 18) |
| #define DCFG_EPMISCNT_SHIFT 18 |
| #define DCFG_EPMISCNT_LIMIT 0x1f |
| #define DCFG_EPMISCNT(_x) ((_x) << 18) |
| #define DCFG_IPG_ISOC_SUPPORDED BIT(17) |
| #define DCFG_PERFRINT_MASK (0x3 << 11) |
| #define DCFG_PERFRINT_SHIFT 11 |
| #define DCFG_PERFRINT_LIMIT 0x3 |
| #define DCFG_PERFRINT(_x) ((_x) << 11) |
| #define DCFG_DEVADDR_MASK (0x7f << 4) |
| #define DCFG_DEVADDR_SHIFT 4 |
| #define DCFG_DEVADDR_LIMIT 0x7f |
| #define DCFG_DEVADDR(_x) ((_x) << 4) |
| #define DCFG_NZ_STS_OUT_HSHK BIT(2) |
| #define DCFG_DEVSPD_MASK (0x3 << 0) |
| #define DCFG_DEVSPD_SHIFT 0 |
| #define DCFG_DEVSPD_HS 0 |
| #define DCFG_DEVSPD_FS 1 |
| #define DCFG_DEVSPD_LS 2 |
| #define DCFG_DEVSPD_FS48 3 |
| |
| #define DCTL HSOTG_REG(0x804) |
| #define DCTL_PWRONPRGDONE BIT(11) |
| #define DCTL_CGOUTNAK BIT(10) |
| #define DCTL_SGOUTNAK BIT(9) |
| #define DCTL_CGNPINNAK BIT(8) |
| #define DCTL_SGNPINNAK BIT(7) |
| #define DCTL_TSTCTL_MASK (0x7 << 4) |
| #define DCTL_TSTCTL_SHIFT 4 |
| #define DCTL_GOUTNAKSTS BIT(3) |
| #define DCTL_GNPINNAKSTS BIT(2) |
| #define DCTL_SFTDISCON BIT(1) |
| #define DCTL_RMTWKUPSIG BIT(0) |
| |
| #define DSTS HSOTG_REG(0x808) |
| #define DSTS_SOFFN_MASK (0x3fff << 8) |
| #define DSTS_SOFFN_SHIFT 8 |
| #define DSTS_SOFFN_LIMIT 0x3fff |
| #define DSTS_SOFFN(_x) ((_x) << 8) |
| #define DSTS_ERRATICERR BIT(3) |
| #define DSTS_ENUMSPD_MASK (0x3 << 1) |
| #define DSTS_ENUMSPD_SHIFT 1 |
| #define DSTS_ENUMSPD_HS 0 |
| #define DSTS_ENUMSPD_FS 1 |
| #define DSTS_ENUMSPD_LS 2 |
| #define DSTS_ENUMSPD_FS48 3 |
| #define DSTS_SUSPSTS BIT(0) |
| |
| #define DIEPMSK HSOTG_REG(0x810) |
| #define DIEPMSK_NAKMSK BIT(13) |
| #define DIEPMSK_BNAININTRMSK BIT(9) |
| #define DIEPMSK_TXFIFOUNDRNMSK BIT(8) |
| #define DIEPMSK_TXFIFOEMPTY BIT(7) |
| #define DIEPMSK_INEPNAKEFFMSK BIT(6) |
| #define DIEPMSK_INTKNEPMISMSK BIT(5) |
| #define DIEPMSK_INTKNTXFEMPMSK BIT(4) |
| #define DIEPMSK_TIMEOUTMSK BIT(3) |
| #define DIEPMSK_AHBERRMSK BIT(2) |
| #define DIEPMSK_EPDISBLDMSK BIT(1) |
| #define DIEPMSK_XFERCOMPLMSK BIT(0) |
| |
| #define DOEPMSK HSOTG_REG(0x814) |
| #define DOEPMSK_BNAMSK BIT(9) |
| #define DOEPMSK_BACK2BACKSETUP BIT(6) |
| #define DOEPMSK_STSPHSERCVDMSK BIT(5) |
| #define DOEPMSK_OUTTKNEPDISMSK BIT(4) |
| #define DOEPMSK_SETUPMSK BIT(3) |
| #define DOEPMSK_AHBERRMSK BIT(2) |
| #define DOEPMSK_EPDISBLDMSK BIT(1) |
| #define DOEPMSK_XFERCOMPLMSK BIT(0) |
| |
| #define DAINT HSOTG_REG(0x818) |
| #define DAINTMSK HSOTG_REG(0x81C) |
| #define DAINT_OUTEP_SHIFT 16 |
| #define DAINT_OUTEP(_x) (1 << ((_x) + 16)) |
| #define DAINT_INEP(_x) (1 << (_x)) |
| |
| #define DTKNQR1 HSOTG_REG(0x820) |
| #define DTKNQR2 HSOTG_REG(0x824) |
| #define DTKNQR3 HSOTG_REG(0x830) |
| #define DTKNQR4 HSOTG_REG(0x834) |
| #define DIEPEMPMSK HSOTG_REG(0x834) |
| |
| #define DVBUSDIS HSOTG_REG(0x828) |
| #define DVBUSPULSE HSOTG_REG(0x82C) |
| |
| #define DIEPCTL0 HSOTG_REG(0x900) |
| #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) |
| |
| #define DOEPCTL0 HSOTG_REG(0xB00) |
| #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) |
| |
| /* EP0 specialness: |
| * bits[29..28] - reserved (no SetD0PID, SetD1PID) |
| * bits[25..22] - should always be zero, this isn't a periodic endpoint |
| * bits[10..0] - MPS setting different for EP0 |
| */ |
| #define D0EPCTL_MPS_MASK (0x3 << 0) |
| #define D0EPCTL_MPS_SHIFT 0 |
| #define D0EPCTL_MPS_64 0 |
| #define D0EPCTL_MPS_32 1 |
| #define D0EPCTL_MPS_16 2 |
| #define D0EPCTL_MPS_8 3 |
| |
| #define DXEPCTL_EPENA BIT(31) |
| #define DXEPCTL_EPDIS BIT(30) |
| #define DXEPCTL_SETD1PID BIT(29) |
| #define DXEPCTL_SETODDFR BIT(29) |
| #define DXEPCTL_SETD0PID BIT(28) |
| #define DXEPCTL_SETEVENFR BIT(28) |
| #define DXEPCTL_SNAK BIT(27) |
| #define DXEPCTL_CNAK BIT(26) |
| #define DXEPCTL_TXFNUM_MASK (0xf << 22) |
| #define DXEPCTL_TXFNUM_SHIFT 22 |
| #define DXEPCTL_TXFNUM_LIMIT 0xf |
| #define DXEPCTL_TXFNUM(_x) ((_x) << 22) |
| #define DXEPCTL_STALL BIT(21) |
| #define DXEPCTL_SNP BIT(20) |
| #define DXEPCTL_EPTYPE_MASK (0x3 << 18) |
| #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) |
| #define DXEPCTL_EPTYPE_ISO (0x1 << 18) |
| #define DXEPCTL_EPTYPE_BULK (0x2 << 18) |
| #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) |
| |
| #define DXEPCTL_NAKSTS BIT(17) |
| #define DXEPCTL_DPID BIT(16) |
| #define DXEPCTL_EOFRNUM BIT(16) |
| #define DXEPCTL_USBACTEP BIT(15) |
| #define DXEPCTL_NEXTEP_MASK (0xf << 11) |
| #define DXEPCTL_NEXTEP_SHIFT 11 |
| #define DXEPCTL_NEXTEP_LIMIT 0xf |
| #define DXEPCTL_NEXTEP(_x) ((_x) << 11) |
| #define DXEPCTL_MPS_MASK (0x7ff << 0) |
| #define DXEPCTL_MPS_SHIFT 0 |
| #define DXEPCTL_MPS_LIMIT 0x7ff |
| #define DXEPCTL_MPS(_x) ((_x) << 0) |
| |
| #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) |
| #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) |
| #define DXEPINT_SETUP_RCVD BIT(15) |
| #define DXEPINT_NYETINTRPT BIT(14) |
| #define DXEPINT_NAKINTRPT BIT(13) |
| #define DXEPINT_BBLEERRINTRPT BIT(12) |
| #define DXEPINT_PKTDRPSTS BIT(11) |
| #define DXEPINT_BNAINTR BIT(9) |
| #define DXEPINT_TXFIFOUNDRN BIT(8) |
| #define DXEPINT_OUTPKTERR BIT(8) |
| #define DXEPINT_TXFEMP BIT(7) |
| #define DXEPINT_INEPNAKEFF BIT(6) |
| #define DXEPINT_BACK2BACKSETUP BIT(6) |
| #define DXEPINT_INTKNEPMIS BIT(5) |
| #define DXEPINT_STSPHSERCVD BIT(5) |
| #define DXEPINT_INTKNTXFEMP BIT(4) |
| #define DXEPINT_OUTTKNEPDIS BIT(4) |
| #define DXEPINT_TIMEOUT BIT(3) |
| #define DXEPINT_SETUP BIT(3) |
| #define DXEPINT_AHBERR BIT(2) |
| #define DXEPINT_EPDISBLD BIT(1) |
| #define DXEPINT_XFERCOMPL BIT(0) |
| |
| #define DIEPTSIZ0 HSOTG_REG(0x910) |
| #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) |
| #define DIEPTSIZ0_PKTCNT_SHIFT 19 |
| #define DIEPTSIZ0_PKTCNT_LIMIT 0x3 |
| #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) |
| #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) |
| #define DIEPTSIZ0_XFERSIZE_SHIFT 0 |
| #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f |
| #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) |
| |
| #define DOEPTSIZ0 HSOTG_REG(0xB10) |
| #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) |
| #define DOEPTSIZ0_SUPCNT_SHIFT 29 |
| #define DOEPTSIZ0_SUPCNT_LIMIT 0x3 |
| #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) |
| #define DOEPTSIZ0_PKTCNT BIT(19) |
| #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) |
| #define DOEPTSIZ0_XFERSIZE_SHIFT 0 |
| |
| #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) |
| #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) |
| #define DXEPTSIZ_MC_MASK (0x3 << 29) |
| #define DXEPTSIZ_MC_SHIFT 29 |
| #define DXEPTSIZ_MC_LIMIT 0x3 |
| #define DXEPTSIZ_MC(_x) ((_x) << 29) |
| #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) |
| #define DXEPTSIZ_PKTCNT_SHIFT 19 |
| #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff |
| #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) |
| #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) |
| #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) |
| #define DXEPTSIZ_XFERSIZE_SHIFT 0 |
| #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff |
| #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) |
| #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) |
| |
| #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) |
| #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) |
| |
| #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) |
| #define DWC2_DTXFSTS_TXFSPCAVAIL_MASK (0xFFFF << 0) |
| #define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET 0 |
| |
| #define PCGCTL HSOTG_REG(0x0e00) |
| #define PCGCTL_IF_DEV_MODE BIT(31) |
| #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) |
| #define PCGCTL_P2HD_PRT_SPD_SHIFT 29 |
| #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) |
| #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 |
| #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) |
| #define PCGCTL_MAC_DEV_ADDR_SHIFT 20 |
| #define PCGCTL_MAX_TERMSEL BIT(19) |
| #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) |
| #define PCGCTL_MAX_XCVRSELECT_SHIFT 17 |
| #define PCGCTL_PORT_POWER BIT(16) |
| #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) |
| #define PCGCTL_PRT_CLK_SEL_SHIFT 14 |
| #define PCGCTL_ESS_REG_RESTORED BIT(13) |
| #define PCGCTL_EXTND_HIBER_SWITCH BIT(12) |
| #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11) |
| #define PCGCTL_ENBL_EXTND_HIBER BIT(10) |
| #define PCGCTL_RESTOREMODE BIT(9) |
| #define PCGCTL_RESETAFTSUSP BIT(8) |
| #define PCGCTL_DEEP_SLEEP BIT(7) |
| #define PCGCTL_PHY_IN_SLEEP BIT(6) |
| #define PCGCTL_ENBL_SLEEP_GATING BIT(5) |
| #define PCGCTL_RSTPDWNMODULE BIT(3) |
| #define PCGCTL_PWRCLMP BIT(2) |
| #define PCGCTL_GATEHCLK BIT(1) |
| #define PCGCTL_STOPPCLK BIT(0) |
| |
| #define PCGCCTL1 HSOTG_REG(0xe04) |
| #define DWC2_PCGCCTL_STOPPCLK (1 << 0) |
| #define DWC2_PCGCCTL_STOPPCLK_OFFSET 0 |
| #define DWC2_PCGCCTL_GATEHCLK (1 << 1) |
| #define DWC2_PCGCCTL_GATEHCLK_OFFSET 1 |
| #define DWC2_PCGCCTL_PWRCLMP (1 << 2) |
| #define DWC2_PCGCCTL_PWRCLMP_OFFSET 2 |
| #define DWC2_PCGCCTL_RSTPDWNMODULE (1 << 3) |
| #define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET 3 |
| #define DWC2_PCGCCTL_PHYSUSPENDED (1 << 4) |
| #define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET 4 |
| #define DWC2_PCGCCTL_ENBL_SLEEP_GATING (1 << 5) |
| #define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET 5 |
| #define DWC2_PCGCCTL_PHY_IN_SLEEP (1 << 6) |
| #define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET 6 |
| #define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7) |
| #define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7 |
| |
| #define PCGCCTL1_TIMER (0x3 << 1) |
| #define PCGCCTL1_GATEEN BIT(0) |
| |
| #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) |
| |
| /* Host Mode Registers */ |
| struct dwc2_host_regs { |
| u32 hcfg; /* 0x00 */ |
| u32 hfir; |
| u32 hfnum; |
| u32 _pad_0x40c; |
| u32 hptxsts; /* 0x10 */ |
| u32 haint; |
| u32 haintmsk; |
| u32 hflbaddr; |
| }; |
| #define HCFG HSOTG_REG(0x0400) |
| #define HCFG_MODECHTIMEN BIT(31) |
| #define HCFG_PERSCHEDENA BIT(26) |
| #define HCFG_FRLISTEN_MASK (0x3 << 24) |
| #define HCFG_FRLISTEN_SHIFT 24 |
| #define HCFG_FRLISTEN_8 (0 << 24) |
| #define FRLISTEN_8_SIZE 8 |
| #define HCFG_FRLISTEN_16 BIT(24) |
| #define FRLISTEN_16_SIZE 16 |
| #define HCFG_FRLISTEN_32 (2 << 24) |
| #define FRLISTEN_32_SIZE 32 |
| #define HCFG_FRLISTEN_64 (3 << 24) |
| #define FRLISTEN_64_SIZE 64 |
| #define HCFG_DESCDMA BIT(23) |
| #define HCFG_RESVALID_MASK (0xff << 8) |
| #define HCFG_RESVALID_SHIFT 8 |
| #define HCFG_ENA32KHZ BIT(7) |
| #define HCFG_FSLSSUPP BIT(2) |
| #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) |
| #define HCFG_FSLSPCLKSEL_SHIFT 0 |
| #define HCFG_FSLSPCLKSEL_30_60_MHZ 0 |
| #define HCFG_FSLSPCLKSEL_48_MHZ 1 |
| #define HCFG_FSLSPCLKSEL_6_MHZ 2 |
| #define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0 |
| #define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1 |
| #define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2 |
| #define DWC2_HCFG_FSLSPCLKSEL_MASK (0x3 << 0) |
| #define DWC2_HCFG_FSLSPCLKSEL_OFFSET 0 |
| #define DWC2_HCFG_FSLSSUPP (1 << 2) |
| #define DWC2_HCFG_FSLSSUPP_OFFSET 2 |
| #define DWC2_HCFG_DESCDMA (1 << 23) |
| #define DWC2_HCFG_DESCDMA_OFFSET 23 |
| #define DWC2_HCFG_FRLISTEN_MASK (0x3 << 24) |
| #define DWC2_HCFG_FRLISTEN_OFFSET 24 |
| #define DWC2_HCFG_PERSCHEDENA (1 << 26) |
| #define DWC2_HCFG_PERSCHEDENA_OFFSET 26 |
| #define DWC2_HCFG_PERSCHEDSTAT (1 << 27) |
| #define DWC2_HCFG_PERSCHEDSTAT_OFFSET 27 |
| |
| #define HFIR HSOTG_REG(0x0404) |
| #define HFIR_FRINT_MASK (0xffff << 0) |
| #define HFIR_FRINT_SHIFT 0 |
| #define HFIR_RLDCTRL BIT(16) |
| #define DWC2_HFIR_FRINT_MASK (0xFFFF << 0) |
| #define DWC2_HFIR_FRINT_OFFSET 0 |
| |
| #define HFNUM HSOTG_REG(0x0408) |
| #define HFNUM_FRREM_MASK (0xffff << 16) |
| #define HFNUM_FRREM_SHIFT 16 |
| #define HFNUM_FRNUM_MASK (0xffff << 0) |
| #define HFNUM_FRNUM_SHIFT 0 |
| #define HFNUM_MAX_FRNUM 0x3fff |
| #define DWC2_HFNUM_FRNUM_MASK (0xFFFF << 0) |
| #define DWC2_HFNUM_FRNUM_OFFSET 0 |
| #define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16) |
| #define DWC2_HFNUM_FRREM_OFFSET 16 |
| #define DWC2_HFNUM_MAX_FRNUM 0x3FFF |
| |
| #define HPTXSTS HSOTG_REG(0x0410) |
| #define TXSTS_QTOP_ODD BIT(31) |
| #define TXSTS_QTOP_CHNEP_MASK (0xf << 27) |
| #define TXSTS_QTOP_CHNEP_SHIFT 27 |
| #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) |
| #define TXSTS_QTOP_TOKEN_SHIFT 25 |
| #define TXSTS_QTOP_TERMINATE BIT(24) |
| #define TXSTS_QSPCAVAIL_MASK (0xff << 16) |
| #define TXSTS_QSPCAVAIL_SHIFT 16 |
| #define TXSTS_FSPCAVAIL_MASK (0xffff << 0) |
| #define TXSTS_FSPCAVAIL_SHIFT 0 |
| #define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0) |
| #define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0 |
| #define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16) |
| #define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET 16 |
| #define DWC2_HPTXSTS_PTXQTOP_TERMINATE (1 << 24) |
| #define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET 24 |
| #define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK (0x3 << 25) |
| #define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET 25 |
| #define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK (0xF << 27) |
| #define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET 27 |
| #define DWC2_HPTXSTS_PTXQTOP_ODD (1 << 31) |
| #define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET 31 |
| |
| #define HAINT HSOTG_REG(0x0414) |
| #define DWC2_HAINT_CH0 (1 << 0) |
| #define DWC2_HAINT_CH0_OFFSET 0 |
| #define DWC2_HAINT_CH1 (1 << 1) |
| #define DWC2_HAINT_CH1_OFFSET 1 |
| #define DWC2_HAINT_CH2 (1 << 2) |
| #define DWC2_HAINT_CH2_OFFSET 2 |
| #define DWC2_HAINT_CH3 (1 << 3) |
| #define DWC2_HAINT_CH3_OFFSET 3 |
| #define DWC2_HAINT_CH4 (1 << 4) |
| #define DWC2_HAINT_CH4_OFFSET 4 |
| #define DWC2_HAINT_CH5 (1 << 5) |
| #define DWC2_HAINT_CH5_OFFSET 5 |
| #define DWC2_HAINT_CH6 (1 << 6) |
| #define DWC2_HAINT_CH6_OFFSET 6 |
| #define DWC2_HAINT_CH7 (1 << 7) |
| #define DWC2_HAINT_CH7_OFFSET 7 |
| #define DWC2_HAINT_CH8 (1 << 8) |
| #define DWC2_HAINT_CH8_OFFSET 8 |
| #define DWC2_HAINT_CH9 (1 << 9) |
| #define DWC2_HAINT_CH9_OFFSET 9 |
| #define DWC2_HAINT_CH10 (1 << 10) |
| #define DWC2_HAINT_CH10_OFFSET 10 |
| #define DWC2_HAINT_CH11 (1 << 11) |
| #define DWC2_HAINT_CH11_OFFSET 11 |
| #define DWC2_HAINT_CH12 (1 << 12) |
| #define DWC2_HAINT_CH12_OFFSET 12 |
| #define DWC2_HAINT_CH13 (1 << 13) |
| #define DWC2_HAINT_CH13_OFFSET 13 |
| #define DWC2_HAINT_CH14 (1 << 14) |
| #define DWC2_HAINT_CH14_OFFSET 14 |
| #define DWC2_HAINT_CH15 (1 << 15) |
| #define DWC2_HAINT_CH15_OFFSET 15 |
| #define DWC2_HAINT_CHINT_MASK 0xffff |
| #define DWC2_HAINT_CHINT_OFFSET 0 |
| |
| #define HAINTMSK HSOTG_REG(0x0418) |
| #define DWC2_HAINTMSK_CH0 (1 << 0) |
| #define DWC2_HAINTMSK_CH0_OFFSET 0 |
| #define DWC2_HAINTMSK_CH1 (1 << 1) |
| #define DWC2_HAINTMSK_CH1_OFFSET 1 |
| #define DWC2_HAINTMSK_CH2 (1 << 2) |
| #define DWC2_HAINTMSK_CH2_OFFSET 2 |
| #define DWC2_HAINTMSK_CH3 (1 << 3) |
| #define DWC2_HAINTMSK_CH3_OFFSET 3 |
| #define DWC2_HAINTMSK_CH4 (1 << 4) |
| #define DWC2_HAINTMSK_CH4_OFFSET 4 |
| #define DWC2_HAINTMSK_CH5 (1 << 5) |
| #define DWC2_HAINTMSK_CH5_OFFSET 5 |
| #define DWC2_HAINTMSK_CH6 (1 << 6) |
| #define DWC2_HAINTMSK_CH6_OFFSET 6 |
| #define DWC2_HAINTMSK_CH7 (1 << 7) |
| #define DWC2_HAINTMSK_CH7_OFFSET 7 |
| #define DWC2_HAINTMSK_CH8 (1 << 8) |
| #define DWC2_HAINTMSK_CH8_OFFSET 8 |
| #define DWC2_HAINTMSK_CH9 (1 << 9) |
| #define DWC2_HAINTMSK_CH9_OFFSET 9 |
| #define DWC2_HAINTMSK_CH10 (1 << 10) |
| #define DWC2_HAINTMSK_CH10_OFFSET 10 |
| #define DWC2_HAINTMSK_CH11 (1 << 11) |
| #define DWC2_HAINTMSK_CH11_OFFSET 11 |
| #define DWC2_HAINTMSK_CH12 (1 << 12) |
| #define DWC2_HAINTMSK_CH12_OFFSET 12 |
| #define DWC2_HAINTMSK_CH13 (1 << 13) |
| #define DWC2_HAINTMSK_CH13_OFFSET 13 |
| #define DWC2_HAINTMSK_CH14 (1 << 14) |
| #define DWC2_HAINTMSK_CH14_OFFSET 14 |
| #define DWC2_HAINTMSK_CH15 (1 << 15) |
| #define DWC2_HAINTMSK_CH15_OFFSET 15 |
| #define DWC2_HAINTMSK_CHINT_MASK 0xffff |
| #define DWC2_HAINTMSK_CHINT_OFFSET 0 |
| |
| #define HFLBADDR HSOTG_REG(0x041c) |
| |
| struct dwc2_hc_regs { |
| u32 hcchar; /* 0x00 */ |
| u32 hcsplt; |
| u32 hcint; |
| u32 hcintmsk; |
| u32 hctsiz; /* 0x10 */ |
| u32 hcdma; |
| u32 reserved; |
| u32 hcdmab; |
| }; |
| #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) |
| #define DWC2_HCCHAR_MPS_MASK (0x7FF << 0) |
| #define DWC2_HCCHAR_MPS_OFFSET 0 |
| #define DWC2_HCCHAR_EPNUM_MASK (0xF << 11) |
| #define DWC2_HCCHAR_EPNUM_OFFSET 11 |
| #define DWC2_HCCHAR_EPDIR (1 << 15) |
| #define DWC2_HCCHAR_EPDIR_OFFSET 15 |
| #define DWC2_HCCHAR_LSPDDEV (1 << 17) |
| #define DWC2_HCCHAR_LSPDDEV_OFFSET 17 |
| #define DWC2_HCCHAR_EPTYPE_CONTROL 0 |
| #define DWC2_HCCHAR_EPTYPE_ISOC 1 |
| #define DWC2_HCCHAR_EPTYPE_BULK 2 |
| #define DWC2_HCCHAR_EPTYPE_INTR 3 |
| #define DWC2_HCCHAR_EPTYPE_MASK (0x3 << 18) |
| #define DWC2_HCCHAR_EPTYPE_OFFSET 18 |
| #define DWC2_HCCHAR_MULTICNT_MASK (0x3 << 20) |
| #define DWC2_HCCHAR_MULTICNT_OFFSET 20 |
| #define DWC2_HCCHAR_DEVADDR_MASK (0x7F << 22) |
| #define DWC2_HCCHAR_DEVADDR_OFFSET 22 |
| #define DWC2_HCCHAR_ODDFRM (1 << 29) |
| #define DWC2_HCCHAR_ODDFRM_OFFSET 29 |
| #define DWC2_HCCHAR_CHDIS (1 << 30) |
| #define DWC2_HCCHAR_CHDIS_OFFSET 30 |
| #define DWC2_HCCHAR_CHEN (1 << 31) |
| #define DWC2_HCCHAR_CHEN_OFFSET 31 |
| |
| #define HCCHAR_CHENA BIT(31) |
| #define HCCHAR_CHDIS BIT(30) |
| #define HCCHAR_ODDFRM BIT(29) |
| #define HCCHAR_DEVADDR_MASK (0x7f << 22) |
| #define HCCHAR_DEVADDR_SHIFT 22 |
| #define HCCHAR_MULTICNT_MASK (0x3 << 20) |
| #define HCCHAR_MULTICNT_SHIFT 20 |
| #define HCCHAR_EPTYPE_MASK (0x3 << 18) |
| #define HCCHAR_EPTYPE_SHIFT 18 |
| #define HCCHAR_LSPDDEV BIT(17) |
| #define HCCHAR_EPDIR BIT(15) |
| #define HCCHAR_EPNUM_MASK (0xf << 11) |
| #define HCCHAR_EPNUM_SHIFT 11 |
| #define HCCHAR_MPS_MASK (0x7ff << 0) |
| #define HCCHAR_MPS_SHIFT 0 |
| |
| #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) |
| #define HCSPLT_SPLTENA BIT(31) |
| #define HCSPLT_COMPSPLT BIT(16) |
| #define HCSPLT_XACTPOS_MASK (0x3 << 14) |
| #define HCSPLT_XACTPOS_SHIFT 14 |
| #define HCSPLT_XACTPOS_MID 0 |
| #define HCSPLT_XACTPOS_END 1 |
| #define HCSPLT_XACTPOS_BEGIN 2 |
| #define HCSPLT_XACTPOS_ALL 3 |
| #define HCSPLT_HUBADDR_MASK (0x7f << 7) |
| #define HCSPLT_HUBADDR_SHIFT 7 |
| #define HCSPLT_PRTADDR_MASK (0x7f << 0) |
| #define HCSPLT_PRTADDR_SHIFT 0 |
| #define DWC2_HCSPLT_PRTADDR_MASK (0x7F << 0) |
| #define DWC2_HCSPLT_PRTADDR_OFFSET 0 |
| #define DWC2_HCSPLT_HUBADDR_MASK (0x7F << 7) |
| #define DWC2_HCSPLT_HUBADDR_OFFSET 7 |
| #define DWC2_HCSPLT_XACTPOS_MASK (0x3 << 14) |
| #define DWC2_HCSPLT_XACTPOS_OFFSET 14 |
| #define DWC2_HCSPLT_COMPSPLT (1 << 16) |
| #define DWC2_HCSPLT_COMPSPLT_OFFSET 16 |
| #define DWC2_HCSPLT_SPLTENA (1 << 31) |
| #define DWC2_HCSPLT_SPLTENA_OFFSET 31 |
| |
| #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) |
| #define DWC2_HCINT_XFERCOMP (1 << 0) |
| #define DWC2_HCINT_XFERCOMP_OFFSET 0 |
| #define DWC2_HCINT_CHHLTD (1 << 1) |
| #define DWC2_HCINT_CHHLTD_OFFSET 1 |
| #define DWC2_HCINT_AHBERR (1 << 2) |
| #define DWC2_HCINT_AHBERR_OFFSET 2 |
| #define DWC2_HCINT_STALL (1 << 3) |
| #define DWC2_HCINT_STALL_OFFSET 3 |
| #define DWC2_HCINT_NAK (1 << 4) |
| #define DWC2_HCINT_NAK_OFFSET 4 |
| #define DWC2_HCINT_ACK (1 << 5) |
| #define DWC2_HCINT_ACK_OFFSET 5 |
| #define DWC2_HCINT_NYET (1 << 6) |
| #define DWC2_HCINT_NYET_OFFSET 6 |
| #define DWC2_HCINT_XACTERR (1 << 7) |
| #define DWC2_HCINT_XACTERR_OFFSET 7 |
| #define DWC2_HCINT_BBLERR (1 << 8) |
| #define DWC2_HCINT_BBLERR_OFFSET 8 |
| #define DWC2_HCINT_FRMOVRUN (1 << 9) |
| #define DWC2_HCINT_FRMOVRUN_OFFSET 9 |
| #define DWC2_HCINT_DATATGLERR (1 << 10) |
| #define DWC2_HCINT_DATATGLERR_OFFSET 10 |
| #define DWC2_HCINT_BNA (1 << 11) |
| #define DWC2_HCINT_BNA_OFFSET 11 |
| #define DWC2_HCINT_XCS_XACT (1 << 12) |
| #define DWC2_HCINT_XCS_XACT_OFFSET 12 |
| #define DWC2_HCINT_FRM_LIST_ROLL (1 << 13) |
| #define DWC2_HCINT_FRM_LIST_ROLL_OFFSET 13 |
| |
| #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) |
| #define DWC2_HCINTMSK_XFERCOMPL (1 << 0) |
| #define DWC2_HCINTMSK_XFERCOMPL_OFFSET 0 |
| #define DWC2_HCINTMSK_CHHLTD (1 << 1) |
| #define DWC2_HCINTMSK_CHHLTD_OFFSET 1 |
| #define DWC2_HCINTMSK_AHBERR (1 << 2) |
| #define DWC2_HCINTMSK_AHBERR_OFFSET 2 |
| #define DWC2_HCINTMSK_STALL (1 << 3) |
| #define DWC2_HCINTMSK_STALL_OFFSET 3 |
| #define DWC2_HCINTMSK_NAK (1 << 4) |
| #define DWC2_HCINTMSK_NAK_OFFSET 4 |
| #define DWC2_HCINTMSK_ACK (1 << 5) |
| #define DWC2_HCINTMSK_ACK_OFFSET 5 |
| #define DWC2_HCINTMSK_NYET (1 << 6) |
| #define DWC2_HCINTMSK_NYET_OFFSET 6 |
| #define DWC2_HCINTMSK_XACTERR (1 << 7) |
| #define DWC2_HCINTMSK_XACTERR_OFFSET 7 |
| #define DWC2_HCINTMSK_BBLERR (1 << 8) |
| #define DWC2_HCINTMSK_BBLERR_OFFSET 8 |
| #define DWC2_HCINTMSK_FRMOVRUN (1 << 9) |
| #define DWC2_HCINTMSK_FRMOVRUN_OFFSET 9 |
| #define DWC2_HCINTMSK_DATATGLERR (1 << 10) |
| #define DWC2_HCINTMSK_DATATGLERR_OFFSET 10 |
| #define DWC2_HCINTMSK_BNA (1 << 11) |
| #define DWC2_HCINTMSK_BNA_OFFSET 11 |
| #define DWC2_HCINTMSK_XCS_XACT (1 << 12) |
| #define DWC2_HCINTMSK_XCS_XACT_OFFSET 12 |
| #define DWC2_HCINTMSK_FRM_LIST_ROLL (1 << 13) |
| #define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET 13 |
| |
| #define HCINTMSK_RESERVED14_31 (0x3ffff << 14) |
| #define HCINTMSK_FRM_LIST_ROLL BIT(13) |
| #define HCINTMSK_XCS_XACT BIT(12) |
| #define HCINTMSK_BNA BIT(11) |
| #define HCINTMSK_DATATGLERR BIT(10) |
| #define HCINTMSK_FRMOVRUN BIT(9) |
| #define HCINTMSK_BBLERR BIT(8) |
| #define HCINTMSK_XACTERR BIT(7) |
| #define HCINTMSK_NYET BIT(6) |
| #define HCINTMSK_ACK BIT(5) |
| #define HCINTMSK_NAK BIT(4) |
| #define HCINTMSK_STALL BIT(3) |
| #define HCINTMSK_AHBERR BIT(2) |
| #define HCINTMSK_CHHLTD BIT(1) |
| #define HCINTMSK_XFERCOMPL BIT(0) |
| |
| #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) |
| #define TSIZ_DOPNG BIT(31) |
| #define TSIZ_SC_MC_PID_MASK (0x3 << 29) |
| #define TSIZ_SC_MC_PID_SHIFT 29 |
| #define TSIZ_SC_MC_PID_DATA0 0 |
| #define TSIZ_SC_MC_PID_DATA2 1 |
| #define TSIZ_SC_MC_PID_DATA1 2 |
| #define TSIZ_SC_MC_PID_MDATA 3 |
| #define TSIZ_SC_MC_PID_SETUP 3 |
| #define TSIZ_PKTCNT_MASK (0x3ff << 19) |
| #define TSIZ_PKTCNT_SHIFT 19 |
| #define TSIZ_NTD_MASK (0xff << 8) |
| #define TSIZ_NTD_SHIFT 8 |
| #define TSIZ_SCHINFO_MASK (0xff << 0) |
| #define TSIZ_SCHINFO_SHIFT 0 |
| #define TSIZ_XFERSIZE_MASK (0x7ffff << 0) |
| #define TSIZ_XFERSIZE_SHIFT 0 |
| #define DWC2_HCTSIZ_XFERSIZE_MASK 0x7ffff |
| #define DWC2_HCTSIZ_XFERSIZE_OFFSET 0 |
| #define DWC2_HCTSIZ_SCHINFO_MASK 0xff |
| #define DWC2_HCTSIZ_SCHINFO_OFFSET 0 |
| #define DWC2_HCTSIZ_NTD_MASK (0xff << 8) |
| #define DWC2_HCTSIZ_NTD_OFFSET 8 |
| #define DWC2_HCTSIZ_PKTCNT_MASK (0x3ff << 19) |
| #define DWC2_HCTSIZ_PKTCNT_OFFSET 19 |
| #define DWC2_HCTSIZ_PID_MASK (0x3 << 29) |
| #define DWC2_HCTSIZ_PID_OFFSET 29 |
| #define DWC2_HCTSIZ_DOPNG (1 << 31) |
| #define DWC2_HCTSIZ_DOPNG_OFFSET 31 |
| |
| #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) |
| #define DWC2_HCDMA_CTD_MASK (0xFF << 3) |
| #define DWC2_HCDMA_CTD_OFFSET 3 |
| #define DWC2_HCDMA_DMA_ADDR_MASK (0x1FFFFF << 11) |
| #define DWC2_HCDMA_DMA_ADDR_OFFSET 11 |
| |
| #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) |
| |
| struct dwc2_core_regs { |
| u32 gotgctl; /* 0x000 */ |
| u32 gotgint; |
| u32 gahbcfg; |
| u32 gusbcfg; |
| u32 grstctl; /* 0x010 */ |
| u32 gintsts; |
| u32 gintmsk; |
| u32 grxstsr; |
| u32 grxstsp; /* 0x020 */ |
| u32 grxfsiz; |
| u32 gnptxfsiz; |
| u32 gnptxsts; |
| u32 gi2cctl; /* 0x030 */ |
| u32 gpvndctl; |
| u32 ggpio; |
| u32 guid; |
| u32 gsnpsid; /* 0x040 */ |
| u32 ghwcfg1; |
| u32 ghwcfg2; |
| u32 ghwcfg3; |
| u32 ghwcfg4; /* 0x050 */ |
| u32 glpmcfg; |
| u32 _pad_0x58_0x9c[42]; |
| u32 hptxfsiz; /* 0x100 */ |
| u32 dptxfsiz_dieptxf[15]; |
| u32 _pad_0x140_0x3fc[176]; |
| struct dwc2_host_regs host_regs; /* 0x400 */ |
| u32 _pad_0x420_0x43c[8]; |
| u32 hprt0; /* 0x440 */ |
| u32 _pad_0x444_0x4fc[47]; |
| struct dwc2_hc_regs hc_regs[16]; /* 0x500 */ |
| u32 _pad_0x700_0xe00[448]; |
| u32 pcgcctl; /* 0xe00 */ |
| }; |
| |
| #define HPRT0 HSOTG_REG(0x0440) |
| #define DWC2_HPRT0_PRTCONNSTS (1 << 0) |
| #define DWC2_HPRT0_PRTCONNSTS_OFFSET 0 |
| #define DWC2_HPRT0_PRTCONNDET (1 << 1) |
| #define DWC2_HPRT0_PRTCONNDET_OFFSET 1 |
| #define DWC2_HPRT0_PRTENA (1 << 2) |
| #define DWC2_HPRT0_PRTENA_OFFSET 2 |
| #define DWC2_HPRT0_PRTENCHNG (1 << 3) |
| #define DWC2_HPRT0_PRTENCHNG_OFFSET 3 |
| #define DWC2_HPRT0_PRTOVRCURRACT (1 << 4) |
| #define DWC2_HPRT0_PRTOVRCURRACT_OFFSET 4 |
| #define DWC2_HPRT0_PRTOVRCURRCHNG (1 << 5) |
| #define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET 5 |
| #define DWC2_HPRT0_PRTRES (1 << 6) |
| #define DWC2_HPRT0_PRTRES_OFFSET 6 |
| #define DWC2_HPRT0_PRTSUSP (1 << 7) |
| #define DWC2_HPRT0_PRTSUSP_OFFSET 7 |
| #define DWC2_HPRT0_PRTRST (1 << 8) |
| #define DWC2_HPRT0_PRTRST_OFFSET 8 |
| #define DWC2_HPRT0_PRTLNSTS_MASK (0x3 << 10) |
| #define DWC2_HPRT0_PRTLNSTS_OFFSET 10 |
| #define DWC2_HPRT0_PRTPWR (1 << 12) |
| #define DWC2_HPRT0_PRTPWR_OFFSET 12 |
| #define DWC2_HPRT0_PRTTSTCTL_MASK (0xF << 13) |
| #define DWC2_HPRT0_PRTTSTCTL_OFFSET 13 |
| #define DWC2_HPRT0_PRTSPD_HIGH (0 << 17) |
| #define DWC2_HPRT0_PRTSPD_FULL (1 << 17) |
| #define DWC2_HPRT0_PRTSPD_LOW (2 << 17) |
| #define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17) |
| #define DWC2_HPRT0_PRTSPD_OFFSET 17 |
| |
| #define HPRT0_SPD_MASK (0x3 << 17) |
| #define HPRT0_SPD_SHIFT 17 |
| #define HPRT0_SPD_HIGH_SPEED 0 |
| #define HPRT0_SPD_FULL_SPEED 1 |
| #define HPRT0_SPD_LOW_SPEED 2 |
| #define HPRT0_TSTCTL_MASK (0xf << 13) |
| #define HPRT0_TSTCTL_SHIFT 13 |
| #define HPRT0_PWR BIT(12) |
| #define HPRT0_LNSTS_MASK (0x3 << 10) |
| #define HPRT0_LNSTS_SHIFT 10 |
| #define HPRT0_RST BIT(8) |
| #define HPRT0_SUSP BIT(7) |
| #define HPRT0_RES BIT(6) |
| #define HPRT0_OVRCURRCHG BIT(5) |
| #define HPRT0_OVRCURRACT BIT(4) |
| #define HPRT0_ENACHG BIT(3) |
| #define HPRT0_ENA BIT(2) |
| #define HPRT0_CONNDET BIT(1) |
| #define HPRT0_CONNSTS BIT(0) |
| |
| |
| #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) |
| |
| |
| /* Host Mode DMA descriptor status quadlet */ |
| |
| #define HOST_DMA_A BIT(31) |
| #define HOST_DMA_STS_MASK (0x3 << 28) |
| #define HOST_DMA_STS_SHIFT 28 |
| #define HOST_DMA_STS_PKTERR BIT(28) |
| #define HOST_DMA_EOL BIT(26) |
| #define HOST_DMA_IOC BIT(25) |
| #define HOST_DMA_SUP BIT(24) |
| #define HOST_DMA_ALT_QTD BIT(23) |
| #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) |
| #define HOST_DMA_QTD_OFFSET_SHIFT 17 |
| #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) |
| #define HOST_DMA_ISOC_NBYTES_SHIFT 0 |
| #define HOST_DMA_NBYTES_MASK (0x1ffff << 0) |
| #define HOST_DMA_NBYTES_SHIFT 0 |
| #define HOST_DMA_NBYTES_LIMIT 131071 |
| |
| /* Device Mode DMA descriptor status quadlet */ |
| |
| #define DEV_DMA_BUFF_STS_MASK (0x3 << 30) |
| #define DEV_DMA_BUFF_STS_SHIFT 30 |
| #define DEV_DMA_BUFF_STS_HREADY 0 |
| #define DEV_DMA_BUFF_STS_DMABUSY 1 |
| #define DEV_DMA_BUFF_STS_DMADONE 2 |
| #define DEV_DMA_BUFF_STS_HBUSY 3 |
| #define DEV_DMA_STS_MASK (0x3 << 28) |
| #define DEV_DMA_STS_SHIFT 28 |
| #define DEV_DMA_STS_SUCC 0 |
| #define DEV_DMA_STS_BUFF_FLUSH 1 |
| #define DEV_DMA_STS_BUFF_ERR 3 |
| #define DEV_DMA_L BIT(27) |
| #define DEV_DMA_SHORT BIT(26) |
| #define DEV_DMA_IOC BIT(25) |
| #define DEV_DMA_SR BIT(24) |
| #define DEV_DMA_MTRF BIT(23) |
| #define DEV_DMA_ISOC_PID_MASK (0x3 << 23) |
| #define DEV_DMA_ISOC_PID_SHIFT 23 |
| #define DEV_DMA_ISOC_PID_DATA0 0 |
| #define DEV_DMA_ISOC_PID_DATA2 1 |
| #define DEV_DMA_ISOC_PID_DATA1 2 |
| #define DEV_DMA_ISOC_PID_MDATA 3 |
| #define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12) |
| #define DEV_DMA_ISOC_FRNUM_SHIFT 12 |
| #define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0) |
| #define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff |
| #define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0) |
| #define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff |
| #define DEV_DMA_ISOC_NBYTES_SHIFT 0 |
| #define DEV_DMA_NBYTES_MASK (0xffff << 0) |
| #define DEV_DMA_NBYTES_SHIFT 0 |
| #define DEV_DMA_NBYTES_LIMIT 0xffff |
| |
| #define MAX_DMA_DESC_NUM_GENERIC 64 |
| #define MAX_DMA_DESC_NUM_HS_ISOC 256 |
| |
| |
| |
| /* Host controller specific */ |
| #define DWC2_HC_PID_DATA0 0 |
| #define DWC2_HC_PID_DATA2 1 |
| #define DWC2_HC_PID_DATA1 2 |
| #define DWC2_HC_PID_MDATA 3 |
| #define DWC2_HC_PID_SETUP 3 |
| |
| /* roothub.a masks */ |
| #define RH_A_NDP (0xff << 0) /* number of downstream ports */ |
| #define RH_A_PSM (1 << 8) /* power switching mode */ |
| #define RH_A_NPS (1 << 9) /* no power switching */ |
| #define RH_A_DT (1 << 10) /* device type (mbz) */ |
| #define RH_A_OCPM (1 << 11) /* over current protection mode */ |
| #define RH_A_NOCP (1 << 12) /* no over current protection */ |
| #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ |
| |
| /* roothub.b masks */ |
| #define RH_B_DR 0x0000ffff /* device removable flags */ |
| #define RH_B_PPCM 0xffff0000 /* port power control mask */ |
| |
| /* Default driver configuration */ |
| #define CONFIG_DWC2_DMA_ENABLE |
| #define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ |
| #undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ |
| #define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ |
| #define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ |
| #define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) |
| #define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ |
| #define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ |
| #define CONFIG_DWC2_MAX_TRANSFER_SIZE ((512*1024)-1) // max dma xfer size |
| #define CONFIG_DWC2_MAX_PACKET_COUNT (CONFIG_DWC2_MAX_TRANSFER_SIZE/512) // max dma xfer size / hs packet size |
| |
| #define DWC2_PHY_TYPE_FS 0 |
| #define DWC2_PHY_TYPE_UTMI 1 |
| #define DWC2_PHY_TYPE_ULPI 2 |
| #define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ |
| #define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ |
| |
| #undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ |
| #define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ |
| #undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ |
| #undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ |
| #undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ |
| #undef CONFIG_DWC2_THR_CTL /* Threshold control */ |
| #define CONFIG_DWC2_TX_THR_LENGTH 64 |
| #undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ |
| |
| /* Scatter / Gather defines */ |
| |
| #define DESC_ACTIVE (1<<31) |
| #define DESC_EOL (1<<26) |
| #define DESC_IOC (1<<25) |
| #define DESC_STS_OFFSET 28 |
| #define DESC_STS_OK 0x0 |
| #define DESC_STS_PKTERR 0x1 |
| #define DESC_STS_RESERVED 0x2 |
| #define DESC_STS_BUFFER 0x3 |
| #define DESC_STS_MASK 0x3 |
| #define DESC_SETUP (1<<24) |
| #define DESC_XFER_SIZE_MASK 0x1FFFF |
| #define MAKE_DESC( desc ,flags, xfer_sz, buff) { desc->header =((flags) | ((xfer_sz)&DESC_XFER_SIZE_MASK)); desc->addr = (u64)(buff);} |
| |
| #define DESC_DEFAULT_DMA_XFER_SIZE (4*1024) |
| |
| /* Use only HC channel x. */ |
| #define DWC2_HC_CHANNEL g_dwc2_host_channel |
| #define DWC2_STATUS_BUF_SIZE 64 |
| #define DWC2_DATA_BUF_SIZE (512 * 1024) |
| |
| |
| #endif /* __DWC2_HW_H__ */ |
