| /* |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * Register address mapping configure file for rom testing code. |
| */ |
| |
| #ifndef __avioGbl_H__ |
| #define __avioGbl_H__ |
| |
| #define RA_avpllCh_ctrl 0x0000 |
| #define BA_avpllCh_ctrl_POSTDIV 0x0000 |
| #define B16avpllCh_ctrl_POSTDIV 0x0000 |
| #define LSb32avpllCh_ctrl_POSTDIV 0 |
| #define LSb16avpllCh_ctrl_POSTDIV 0 |
| #define bavpllCh_ctrl_POSTDIV 13 |
| #define MSK32avpllCh_ctrl_POSTDIV 0x00001FFF |
| #define BA_avpllCh_ctrl_POSTDIV_0P5 0x0001 |
| #define B16avpllCh_ctrl_POSTDIV_0P5 0x0000 |
| #define LSb32avpllCh_ctrl_POSTDIV_0P5 13 |
| #define LSb16avpllCh_ctrl_POSTDIV_0P5 13 |
| #define bavpllCh_ctrl_POSTDIV_0P5 1 |
| #define MSK32avpllCh_ctrl_POSTDIV_0P5 0x00002000 |
| #define BA_avpllCh_ctrl_EN_DPLL 0x0001 |
| #define B16avpllCh_ctrl_EN_DPLL 0x0000 |
| #define LSb32avpllCh_ctrl_EN_DPLL 14 |
| #define LSb16avpllCh_ctrl_EN_DPLL 14 |
| #define bavpllCh_ctrl_EN_DPLL 1 |
| #define MSK32avpllCh_ctrl_EN_DPLL 0x00004000 |
| #define BA_avpllCh_ctrl_EN_LP 0x0001 |
| #define B16avpllCh_ctrl_EN_LP 0x0000 |
| #define LSb32avpllCh_ctrl_EN_LP 15 |
| #define LSb16avpllCh_ctrl_EN_LP 15 |
| #define bavpllCh_ctrl_EN_LP 2 |
| #define MSK32avpllCh_ctrl_EN_LP 0x00018000 |
| #define RA_avpllCh_ctrl1 0x0004 |
| #define BA_avpllCh_ctrl_FREQ_OFFSET 0x0004 |
| #define B16avpllCh_ctrl_FREQ_OFFSET 0x0004 |
| #define LSb32avpllCh_ctrl_FREQ_OFFSET 0 |
| #define LSb16avpllCh_ctrl_FREQ_OFFSET 0 |
| #define bavpllCh_ctrl_FREQ_OFFSET 19 |
| #define MSK32avpllCh_ctrl_FREQ_OFFSET 0x0007FFFF |
| #define BA_avpllCh_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define B16avpllCh_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define LSb32avpllCh_ctrl_FREQ_OFFSET_READY 19 |
| #define LSb16avpllCh_ctrl_FREQ_OFFSET_READY 3 |
| #define bavpllCh_ctrl_FREQ_OFFSET_READY 1 |
| #define MSK32avpllCh_ctrl_FREQ_OFFSET_READY 0x00080000 |
| #define BA_avpllCh_ctrl_PU 0x0006 |
| #define B16avpllCh_ctrl_PU 0x0006 |
| #define LSb32avpllCh_ctrl_PU 20 |
| #define LSb16avpllCh_ctrl_PU 4 |
| #define bavpllCh_ctrl_PU 1 |
| #define MSK32avpllCh_ctrl_PU 0x00100000 |
| #define BA_avpllCh_ctrl_PU_OFST_CTRL 0x0006 |
| #define B16avpllCh_ctrl_PU_OFST_CTRL 0x0006 |
| #define LSb32avpllCh_ctrl_PU_OFST_CTRL 21 |
| #define LSb16avpllCh_ctrl_PU_OFST_CTRL 5 |
| #define bavpllCh_ctrl_PU_OFST_CTRL 1 |
| #define MSK32avpllCh_ctrl_PU_OFST_CTRL 0x00200000 |
| #define RA_avpllCh_ctrl2 0x0008 |
| #define BA_avpllCh_ctrl_P_SYNC1 0x0008 |
| #define B16avpllCh_ctrl_P_SYNC1 0x0008 |
| #define LSb32avpllCh_ctrl_P_SYNC1 0 |
| #define LSb16avpllCh_ctrl_P_SYNC1 0 |
| #define bavpllCh_ctrl_P_SYNC1 20 |
| #define MSK32avpllCh_ctrl_P_SYNC1 0x000FFFFF |
| #define RA_avpllCh_ctrl3 0x000C |
| #define BA_avpllCh_ctrl_P_SYNC2 0x000C |
| #define B16avpllCh_ctrl_P_SYNC2 0x000C |
| #define LSb32avpllCh_ctrl_P_SYNC2 0 |
| #define LSb16avpllCh_ctrl_P_SYNC2 0 |
| #define bavpllCh_ctrl_P_SYNC2 20 |
| #define MSK32avpllCh_ctrl_P_SYNC2 0x000FFFFF |
| #define BA_avpllCh_ctrl_RESET 0x000E |
| #define B16avpllCh_ctrl_RESET 0x000E |
| #define LSb32avpllCh_ctrl_RESET 20 |
| #define LSb16avpllCh_ctrl_RESET 4 |
| #define bavpllCh_ctrl_RESET 1 |
| #define MSK32avpllCh_ctrl_RESET 0x00100000 |
| #define BA_avpllCh_ctrl_RESERVE_IN 0x000E |
| #define B16avpllCh_ctrl_RESERVE_IN 0x000E |
| #define LSb32avpllCh_ctrl_RESERVE_IN 21 |
| #define LSb16avpllCh_ctrl_RESERVE_IN 5 |
| #define bavpllCh_ctrl_RESERVE_IN 2 |
| #define MSK32avpllCh_ctrl_RESERVE_IN 0x00600000 |
| #define RA_avpllCh8_ctrl 0x0000 |
| #define BA_avpllCh8_ctrl_POSTDIV 0x0000 |
| #define B16avpllCh8_ctrl_POSTDIV 0x0000 |
| #define LSb32avpllCh8_ctrl_POSTDIV 0 |
| #define LSb16avpllCh8_ctrl_POSTDIV 0 |
| #define bavpllCh8_ctrl_POSTDIV 13 |
| #define MSK32avpllCh8_ctrl_POSTDIV 0x00001FFF |
| #define BA_avpllCh8_ctrl_POSTDIV_0P5 0x0001 |
| #define B16avpllCh8_ctrl_POSTDIV_0P5 0x0000 |
| #define LSb32avpllCh8_ctrl_POSTDIV_0P5 13 |
| #define LSb16avpllCh8_ctrl_POSTDIV_0P5 13 |
| #define bavpllCh8_ctrl_POSTDIV_0P5 1 |
| #define MSK32avpllCh8_ctrl_POSTDIV_0P5 0x00002000 |
| #define BA_avpllCh8_ctrl_EN_DPLL 0x0001 |
| #define B16avpllCh8_ctrl_EN_DPLL 0x0000 |
| #define LSb32avpllCh8_ctrl_EN_DPLL 14 |
| #define LSb16avpllCh8_ctrl_EN_DPLL 14 |
| #define bavpllCh8_ctrl_EN_DPLL 1 |
| #define MSK32avpllCh8_ctrl_EN_DPLL 0x00004000 |
| #define BA_avpllCh8_ctrl_EN_LP 0x0001 |
| #define B16avpllCh8_ctrl_EN_LP 0x0000 |
| #define LSb32avpllCh8_ctrl_EN_LP 15 |
| #define LSb16avpllCh8_ctrl_EN_LP 15 |
| #define bavpllCh8_ctrl_EN_LP 2 |
| #define MSK32avpllCh8_ctrl_EN_LP 0x00018000 |
| #define RA_avpllCh8_ctrl1 0x0004 |
| #define BA_avpllCh8_ctrl_FREQ_OFFSET 0x0004 |
| #define B16avpllCh8_ctrl_FREQ_OFFSET 0x0004 |
| #define LSb32avpllCh8_ctrl_FREQ_OFFSET 0 |
| #define LSb16avpllCh8_ctrl_FREQ_OFFSET 0 |
| #define bavpllCh8_ctrl_FREQ_OFFSET 19 |
| #define MSK32avpllCh8_ctrl_FREQ_OFFSET 0x0007FFFF |
| #define BA_avpllCh8_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define B16avpllCh8_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define LSb32avpllCh8_ctrl_FREQ_OFFSET_READY 19 |
| #define LSb16avpllCh8_ctrl_FREQ_OFFSET_READY 3 |
| #define bavpllCh8_ctrl_FREQ_OFFSET_READY 1 |
| #define MSK32avpllCh8_ctrl_FREQ_OFFSET_READY 0x00080000 |
| #define BA_avpllCh8_ctrl_PU 0x0006 |
| #define B16avpllCh8_ctrl_PU 0x0006 |
| #define LSb32avpllCh8_ctrl_PU 20 |
| #define LSb16avpllCh8_ctrl_PU 4 |
| #define bavpllCh8_ctrl_PU 1 |
| #define MSK32avpllCh8_ctrl_PU 0x00100000 |
| #define BA_avpllCh8_ctrl_PU_OFST_CTRL 0x0006 |
| #define B16avpllCh8_ctrl_PU_OFST_CTRL 0x0006 |
| #define LSb32avpllCh8_ctrl_PU_OFST_CTRL 21 |
| #define LSb16avpllCh8_ctrl_PU_OFST_CTRL 5 |
| #define bavpllCh8_ctrl_PU_OFST_CTRL 1 |
| #define MSK32avpllCh8_ctrl_PU_OFST_CTRL 0x00200000 |
| #define RA_avpllCh8_ctrl2 0x0008 |
| #define BA_avpllCh8_ctrl_P_SYNC1 0x0008 |
| #define B16avpllCh8_ctrl_P_SYNC1 0x0008 |
| #define LSb32avpllCh8_ctrl_P_SYNC1 0 |
| #define LSb16avpllCh8_ctrl_P_SYNC1 0 |
| #define bavpllCh8_ctrl_P_SYNC1 20 |
| #define MSK32avpllCh8_ctrl_P_SYNC1 0x000FFFFF |
| #define RA_avpllCh8_ctrl3 0x000C |
| #define BA_avpllCh8_ctrl_P_SYNC2 0x000C |
| #define B16avpllCh8_ctrl_P_SYNC2 0x000C |
| #define LSb32avpllCh8_ctrl_P_SYNC2 0 |
| #define LSb16avpllCh8_ctrl_P_SYNC2 0 |
| #define bavpllCh8_ctrl_P_SYNC2 20 |
| #define MSK32avpllCh8_ctrl_P_SYNC2 0x000FFFFF |
| #define BA_avpllCh8_ctrl_RESET 0x000E |
| #define B16avpllCh8_ctrl_RESET 0x000E |
| #define LSb32avpllCh8_ctrl_RESET 20 |
| #define LSb16avpllCh8_ctrl_RESET 4 |
| #define bavpllCh8_ctrl_RESET 1 |
| #define MSK32avpllCh8_ctrl_RESET 0x00100000 |
| #define BA_avpllCh8_ctrl_RESERVE_IN 0x000E |
| #define B16avpllCh8_ctrl_RESERVE_IN 0x000E |
| #define LSb32avpllCh8_ctrl_RESERVE_IN 21 |
| #define LSb16avpllCh8_ctrl_RESERVE_IN 5 |
| #define bavpllCh8_ctrl_RESERVE_IN 2 |
| #define MSK32avpllCh8_ctrl_RESERVE_IN 0x00600000 |
| #define RA_avPll_ctrlPLL 0x0000 |
| #define BA_avPll_ctrlPLL_RESET 0x0000 |
| #define B16avPll_ctrlPLL_RESET 0x0000 |
| #define LSb32avPll_ctrlPLL_RESET 0 |
| #define LSb16avPll_ctrlPLL_RESET 0 |
| #define bavPll_ctrlPLL_RESET 1 |
| #define MSK32avPll_ctrlPLL_RESET 0x00000001 |
| #define BA_avPll_ctrlPLL_PU 0x0000 |
| #define B16avPll_ctrlPLL_PU 0x0000 |
| #define LSb32avPll_ctrlPLL_PU 1 |
| #define LSb16avPll_ctrlPLL_PU 1 |
| #define bavPll_ctrlPLL_PU 1 |
| #define MSK32avPll_ctrlPLL_PU 0x00000002 |
| #define BA_avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000 |
| #define B16avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000 |
| #define LSb32avPll_ctrlPLL_PLL_VDDRA_SEL 2 |
| #define LSb16avPll_ctrlPLL_PLL_VDDRA_SEL 2 |
| #define bavPll_ctrlPLL_PLL_VDDRA_SEL 3 |
| #define MSK32avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000001C |
| #define BA_avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x0000 |
| #define B16avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x0000 |
| #define LSb32avPll_ctrlPLL_REG_RING_EXTRA_I_EN 5 |
| #define LSb16avPll_ctrlPLL_REG_RING_EXTRA_I_EN 5 |
| #define bavPll_ctrlPLL_REG_RING_EXTRA_I_EN 1 |
| #define MSK32avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x00000020 |
| #define BA_avPll_ctrlPLL_VCO_REF1P45_SEL 0x0000 |
| #define B16avPll_ctrlPLL_VCO_REF1P45_SEL 0x0000 |
| #define LSb32avPll_ctrlPLL_VCO_REF1P45_SEL 6 |
| #define LSb16avPll_ctrlPLL_VCO_REF1P45_SEL 6 |
| #define bavPll_ctrlPLL_VCO_REF1P45_SEL 2 |
| #define MSK32avPll_ctrlPLL_VCO_REF1P45_SEL 0x000000C0 |
| #define BA_avPll_ctrlPLL_VDDA23_PUMP_SEL 0x0001 |
| #define B16avPll_ctrlPLL_VDDA23_PUMP_SEL 0x0000 |
| #define LSb32avPll_ctrlPLL_VDDA23_PUMP_SEL 8 |
| #define LSb16avPll_ctrlPLL_VDDA23_PUMP_SEL 8 |
| #define bavPll_ctrlPLL_VDDA23_PUMP_SEL 2 |
| #define MSK32avPll_ctrlPLL_VDDA23_PUMP_SEL 0x00000300 |
| #define BA_avPll_ctrlPLL_VDDBUF_ADJ 0x0001 |
| #define B16avPll_ctrlPLL_VDDBUF_ADJ 0x0000 |
| #define LSb32avPll_ctrlPLL_VDDBUF_ADJ 10 |
| #define LSb16avPll_ctrlPLL_VDDBUF_ADJ 10 |
| #define bavPll_ctrlPLL_VDDBUF_ADJ 3 |
| #define MSK32avPll_ctrlPLL_VDDBUF_ADJ 0x00001C00 |
| #define BA_avPll_ctrlPLL_VDDL 0x0001 |
| #define B16avPll_ctrlPLL_VDDL 0x0000 |
| #define LSb32avPll_ctrlPLL_VDDL 13 |
| #define LSb16avPll_ctrlPLL_VDDL 13 |
| #define bavPll_ctrlPLL_VDDL 4 |
| #define MSK32avPll_ctrlPLL_VDDL 0x0001E000 |
| #define BA_avPll_ctrlPLL_FBDIV 0x0002 |
| #define B16avPll_ctrlPLL_FBDIV 0x0002 |
| #define LSb32avPll_ctrlPLL_FBDIV 17 |
| #define LSb16avPll_ctrlPLL_FBDIV 1 |
| #define bavPll_ctrlPLL_FBDIV 9 |
| #define MSK32avPll_ctrlPLL_FBDIV 0x03FE0000 |
| #define BA_avPll_ctrlPLL_ICP 0x0003 |
| #define B16avPll_ctrlPLL_ICP 0x0002 |
| #define LSb32avPll_ctrlPLL_ICP 26 |
| #define LSb16avPll_ctrlPLL_ICP 10 |
| #define bavPll_ctrlPLL_ICP 4 |
| #define MSK32avPll_ctrlPLL_ICP 0x3C000000 |
| #define BA_avPll_ctrlPLL_PLL_LPFC2_LESS 0x0003 |
| #define B16avPll_ctrlPLL_PLL_LPFC2_LESS 0x0002 |
| #define LSb32avPll_ctrlPLL_PLL_LPFC2_LESS 30 |
| #define LSb16avPll_ctrlPLL_PLL_LPFC2_LESS 14 |
| #define bavPll_ctrlPLL_PLL_LPFC2_LESS 1 |
| #define MSK32avPll_ctrlPLL_PLL_LPFC2_LESS 0x40000000 |
| #define RA_avPll_ctrlPLL1 0x0004 |
| #define BA_avPll_ctrlPLL_REFDIV 0x0004 |
| #define B16avPll_ctrlPLL_REFDIV 0x0004 |
| #define LSb32avPll_ctrlPLL_REFDIV 0 |
| #define LSb16avPll_ctrlPLL_REFDIV 0 |
| #define bavPll_ctrlPLL_REFDIV 7 |
| #define MSK32avPll_ctrlPLL_REFDIV 0x0000007F |
| #define BA_avPll_ctrlPLL_RESERVE_PLL_IN 0x0004 |
| #define B16avPll_ctrlPLL_RESERVE_PLL_IN 0x0004 |
| #define LSb32avPll_ctrlPLL_RESERVE_PLL_IN 7 |
| #define LSb16avPll_ctrlPLL_RESERVE_PLL_IN 7 |
| #define bavPll_ctrlPLL_RESERVE_PLL_IN 6 |
| #define MSK32avPll_ctrlPLL_RESERVE_PLL_IN 0x00001F80 |
| #define BA_avPll_ctrlPLL_EXT_SPEED 0x0005 |
| #define B16avPll_ctrlPLL_EXT_SPEED 0x0004 |
| #define LSb32avPll_ctrlPLL_EXT_SPEED 13 |
| #define LSb16avPll_ctrlPLL_EXT_SPEED 13 |
| #define bavPll_ctrlPLL_EXT_SPEED 4 |
| #define MSK32avPll_ctrlPLL_EXT_SPEED 0x0001E000 |
| #define BA_avPll_ctrlPLL_SPEED_FBRES 0x0006 |
| #define B16avPll_ctrlPLL_SPEED_FBRES 0x0006 |
| #define LSb32avPll_ctrlPLL_SPEED_FBRES 17 |
| #define LSb16avPll_ctrlPLL_SPEED_FBRES 1 |
| #define bavPll_ctrlPLL_SPEED_FBRES 4 |
| #define MSK32avPll_ctrlPLL_SPEED_FBRES 0x001E0000 |
| #define BA_avPll_ctrlPLL_UPDATE_SEL 0x0006 |
| #define B16avPll_ctrlPLL_UPDATE_SEL 0x0006 |
| #define LSb32avPll_ctrlPLL_UPDATE_SEL 21 |
| #define LSb16avPll_ctrlPLL_UPDATE_SEL 5 |
| #define bavPll_ctrlPLL_UPDATE_SEL 1 |
| #define MSK32avPll_ctrlPLL_UPDATE_SEL 0x00200000 |
| #define RA_avPll_ctrlCAL 0x0008 |
| #define BA_avPll_ctrlCAL_CAL_FBDIV 0x0008 |
| #define B16avPll_ctrlCAL_CAL_FBDIV 0x0008 |
| #define LSb32avPll_ctrlCAL_CAL_FBDIV 0 |
| #define LSb16avPll_ctrlCAL_CAL_FBDIV 0 |
| #define bavPll_ctrlCAL_CAL_FBDIV 9 |
| #define MSK32avPll_ctrlCAL_CAL_FBDIV 0x000001FF |
| #define BA_avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x0009 |
| #define B16avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x0008 |
| #define LSb32avPll_ctrlCAL_EXT_SLLP_DAC_EN 9 |
| #define LSb16avPll_ctrlCAL_EXT_SLLP_DAC_EN 9 |
| #define bavPll_ctrlCAL_EXT_SLLP_DAC_EN 1 |
| #define MSK32avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x00000200 |
| #define BA_avPll_ctrlCAL_EXT_SPEED_EN 0x0009 |
| #define B16avPll_ctrlCAL_EXT_SPEED_EN 0x0008 |
| #define LSb32avPll_ctrlCAL_EXT_SPEED_EN 10 |
| #define LSb16avPll_ctrlCAL_EXT_SPEED_EN 10 |
| #define bavPll_ctrlCAL_EXT_SPEED_EN 1 |
| #define MSK32avPll_ctrlCAL_EXT_SPEED_EN 0x00000400 |
| #define BA_avPll_ctrlCAL_EXT_SP_FBRES_EN 0x0009 |
| #define B16avPll_ctrlCAL_EXT_SP_FBRES_EN 0x0008 |
| #define LSb32avPll_ctrlCAL_EXT_SP_FBRES_EN 11 |
| #define LSb16avPll_ctrlCAL_EXT_SP_FBRES_EN 11 |
| #define bavPll_ctrlCAL_EXT_SP_FBRES_EN 1 |
| #define MSK32avPll_ctrlCAL_EXT_SP_FBRES_EN 0x00000800 |
| #define BA_avPll_ctrlCAL_PLL_CALCLK_DIV 0x0009 |
| #define B16avPll_ctrlCAL_PLL_CALCLK_DIV 0x0008 |
| #define LSb32avPll_ctrlCAL_PLL_CALCLK_DIV 12 |
| #define LSb16avPll_ctrlCAL_PLL_CALCLK_DIV 12 |
| #define bavPll_ctrlCAL_PLL_CALCLK_DIV 5 |
| #define MSK32avPll_ctrlCAL_PLL_CALCLK_DIV 0x0001F000 |
| #define BA_avPll_ctrlCAL_PLL_CAL_START 0x000A |
| #define B16avPll_ctrlCAL_PLL_CAL_START 0x000A |
| #define LSb32avPll_ctrlCAL_PLL_CAL_START 17 |
| #define LSb16avPll_ctrlCAL_PLL_CAL_START 1 |
| #define bavPll_ctrlCAL_PLL_CAL_START 1 |
| #define MSK32avPll_ctrlCAL_PLL_CAL_START 0x00020000 |
| #define BA_avPll_ctrlCAL_REG_SETTLE_LIMIT 0x000A |
| #define B16avPll_ctrlCAL_REG_SETTLE_LIMIT 0x000A |
| #define LSb32avPll_ctrlCAL_REG_SETTLE_LIMIT 18 |
| #define LSb16avPll_ctrlCAL_REG_SETTLE_LIMIT 2 |
| #define bavPll_ctrlCAL_REG_SETTLE_LIMIT 4 |
| #define MSK32avPll_ctrlCAL_REG_SETTLE_LIMIT 0x003C0000 |
| #define BA_avPll_ctrlCAL_SEL_VTHVCOCONT 0x000A |
| #define B16avPll_ctrlCAL_SEL_VTHVCOCONT 0x000A |
| #define LSb32avPll_ctrlCAL_SEL_VTHVCOCONT 22 |
| #define LSb16avPll_ctrlCAL_SEL_VTHVCOCONT 6 |
| #define bavPll_ctrlCAL_SEL_VTHVCOCONT 1 |
| #define MSK32avPll_ctrlCAL_SEL_VTHVCOCONT 0x00400000 |
| #define BA_avPll_ctrlCAL_SPEED_THRESH 0x000A |
| #define B16avPll_ctrlCAL_SPEED_THRESH 0x000A |
| #define LSb32avPll_ctrlCAL_SPEED_THRESH 23 |
| #define LSb16avPll_ctrlCAL_SPEED_THRESH 7 |
| #define bavPll_ctrlCAL_SPEED_THRESH 6 |
| #define MSK32avPll_ctrlCAL_SPEED_THRESH 0x1F800000 |
| #define BA_avPll_ctrlCAL_VCON_SEL 0x000B |
| #define B16avPll_ctrlCAL_VCON_SEL 0x000A |
| #define LSb32avPll_ctrlCAL_VCON_SEL 29 |
| #define LSb16avPll_ctrlCAL_VCON_SEL 13 |
| #define bavPll_ctrlCAL_VCON_SEL 2 |
| #define MSK32avPll_ctrlCAL_VCON_SEL 0x60000000 |
| #define RA_avPll_ctrlCAL1 0x000C |
| #define BA_avPll_ctrlCAL_EXT_SLLP_DAC 0x000C |
| #define B16avPll_ctrlCAL_EXT_SLLP_DAC 0x000C |
| #define LSb32avPll_ctrlCAL_EXT_SLLP_DAC 0 |
| #define LSb16avPll_ctrlCAL_EXT_SLLP_DAC 0 |
| #define bavPll_ctrlCAL_EXT_SLLP_DAC 7 |
| #define MSK32avPll_ctrlCAL_EXT_SLLP_DAC 0x0000007F |
| #define BA_avPll_ctrlCAL_VTH_VCO_CAL 0x000C |
| #define B16avPll_ctrlCAL_VTH_VCO_CAL 0x000C |
| #define LSb32avPll_ctrlCAL_VTH_VCO_CAL 7 |
| #define LSb16avPll_ctrlCAL_VTH_VCO_CAL 7 |
| #define bavPll_ctrlCAL_VTH_VCO_CAL 2 |
| #define MSK32avPll_ctrlCAL_VTH_VCO_CAL 0x00000180 |
| #define BA_avPll_ctrlCAL_VTH_VCO_PTAT 0x000D |
| #define B16avPll_ctrlCAL_VTH_VCO_PTAT 0x000C |
| #define LSb32avPll_ctrlCAL_VTH_VCO_PTAT 9 |
| #define LSb16avPll_ctrlCAL_VTH_VCO_PTAT 9 |
| #define bavPll_ctrlCAL_VTH_VCO_PTAT 2 |
| #define MSK32avPll_ctrlCAL_VTH_VCO_PTAT 0x00000600 |
| #define RA_avPll_ctrlSlowLoop 0x0010 |
| #define BA_avPll_ctrlSlowLoop_PW_SLLP 0x0010 |
| #define B16avPll_ctrlSlowLoop_PW_SLLP 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_PW_SLLP 0 |
| #define LSb16avPll_ctrlSlowLoop_PW_SLLP 0 |
| #define bavPll_ctrlSlowLoop_PW_SLLP 3 |
| #define MSK32avPll_ctrlSlowLoop_PW_SLLP 0x00000007 |
| #define BA_avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x0010 |
| #define B16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 3 |
| #define LSb16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 3 |
| #define bavPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 1 |
| #define MSK32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x00000008 |
| #define BA_avPll_ctrlSlowLoop_SLLP_EN_DIS 0x0010 |
| #define B16avPll_ctrlSlowLoop_SLLP_EN_DIS 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_SLLP_EN_DIS 4 |
| #define LSb16avPll_ctrlSlowLoop_SLLP_EN_DIS 4 |
| #define bavPll_ctrlSlowLoop_SLLP_EN_DIS 1 |
| #define MSK32avPll_ctrlSlowLoop_SLLP_EN_DIS 0x00000010 |
| #define BA_avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x0010 |
| #define B16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 5 |
| #define LSb16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 5 |
| #define bavPll_ctrlSlowLoop_SLLP_PSF_LEVEL 3 |
| #define MSK32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x000000E0 |
| #define RA_avPll_ctrlINTP 0x0014 |
| #define BA_avPll_ctrlINTP_CLK_DET_EN 0x0014 |
| #define B16avPll_ctrlINTP_CLK_DET_EN 0x0014 |
| #define LSb32avPll_ctrlINTP_CLK_DET_EN 0 |
| #define LSb16avPll_ctrlINTP_CLK_DET_EN 0 |
| #define bavPll_ctrlINTP_CLK_DET_EN 1 |
| #define MSK32avPll_ctrlINTP_CLK_DET_EN 0x00000001 |
| #define BA_avPll_ctrlINTP_DPHER_DLY_SEL 0x0014 |
| #define B16avPll_ctrlINTP_DPHER_DLY_SEL 0x0014 |
| #define LSb32avPll_ctrlINTP_DPHER_DLY_SEL 1 |
| #define LSb16avPll_ctrlINTP_DPHER_DLY_SEL 1 |
| #define bavPll_ctrlINTP_DPHER_DLY_SEL 2 |
| #define MSK32avPll_ctrlINTP_DPHER_DLY_SEL 0x00000006 |
| #define BA_avPll_ctrlINTP_INTPI 0x0014 |
| #define B16avPll_ctrlINTP_INTPI 0x0014 |
| #define LSb32avPll_ctrlINTP_INTPI 3 |
| #define LSb16avPll_ctrlINTP_INTPI 3 |
| #define bavPll_ctrlINTP_INTPI 4 |
| #define MSK32avPll_ctrlINTP_INTPI 0x00000078 |
| #define BA_avPll_ctrlINTP_INTPR 0x0014 |
| #define B16avPll_ctrlINTP_INTPR 0x0014 |
| #define LSb32avPll_ctrlINTP_INTPR 7 |
| #define LSb16avPll_ctrlINTP_INTPR 7 |
| #define bavPll_ctrlINTP_INTPR 3 |
| #define MSK32avPll_ctrlINTP_INTPR 0x00000380 |
| #define RA_avPll_ctrlC8AddOn 0x0018 |
| #define BA_avPll_ctrlC8AddOn_MASTER_SLAVEB 0x0018 |
| #define B16avPll_ctrlC8AddOn_MASTER_SLAVEB 0x0018 |
| #define LSb32avPll_ctrlC8AddOn_MASTER_SLAVEB 0 |
| #define LSb16avPll_ctrlC8AddOn_MASTER_SLAVEB 0 |
| #define bavPll_ctrlC8AddOn_MASTER_SLAVEB 1 |
| #define MSK32avPll_ctrlC8AddOn_MASTER_SLAVEB 0x00000001 |
| #define BA_avPll_ctrlC8AddOn_MODE 0x0018 |
| #define B16avPll_ctrlC8AddOn_MODE 0x0018 |
| #define LSb32avPll_ctrlC8AddOn_MODE 1 |
| #define LSb16avPll_ctrlC8AddOn_MODE 1 |
| #define bavPll_ctrlC8AddOn_MODE 2 |
| #define MSK32avPll_ctrlC8AddOn_MODE 0x00000006 |
| #define RA_avPll_C1 0x001C |
| #define RA_avPll_C2 0x002C |
| #define RA_avPll_C3 0x003C |
| #define RA_avPll_C4 0x004C |
| #define RA_avPll_C5 0x005C |
| #define RA_avPll_C6 0x006C |
| #define RA_avPll_C7 0x007C |
| #define RA_avPll_C8 0x008C |
| #define RA_avPll_ctrlTest 0x009C |
| #define BA_avPll_ctrlTest_CLKOUT_TST_EN 0x009C |
| #define B16avPll_ctrlTest_CLKOUT_TST_EN 0x009C |
| #define LSb32avPll_ctrlTest_CLKOUT_TST_EN 0 |
| #define LSb16avPll_ctrlTest_CLKOUT_TST_EN 0 |
| #define bavPll_ctrlTest_CLKOUT_TST_EN 1 |
| #define MSK32avPll_ctrlTest_CLKOUT_TST_EN 0x00000001 |
| #define BA_avPll_ctrlTest_TEST_MON 0x009C |
| #define B16avPll_ctrlTest_TEST_MON 0x009C |
| #define LSb32avPll_ctrlTest_TEST_MON 1 |
| #define LSb16avPll_ctrlTest_TEST_MON 1 |
| #define bavPll_ctrlTest_TEST_MON 6 |
| #define MSK32avPll_ctrlTest_TEST_MON 0x0000007E |
| #define RA_avPll_status 0x00A0 |
| #define BA_avPll_status_PLL_LOCK 0x00A0 |
| #define B16avPll_status_PLL_LOCK 0x00A0 |
| #define LSb32avPll_status_PLL_LOCK 0 |
| #define LSb16avPll_status_PLL_LOCK 0 |
| #define bavPll_status_PLL_LOCK 1 |
| #define MSK32avPll_status_PLL_LOCK 0x00000001 |
| #define BA_avPll_status_RESERVE_PLL_OUT 0x00A0 |
| #define B16avPll_status_RESERVE_PLL_OUT 0x00A0 |
| #define LSb32avPll_status_RESERVE_PLL_OUT 1 |
| #define LSb16avPll_status_RESERVE_PLL_OUT 1 |
| #define bavPll_status_RESERVE_PLL_OUT 6 |
| #define MSK32avPll_status_RESERVE_PLL_OUT 0x0000007E |
| #define BA_avPll_status_FBDIV_RD 0x00A0 |
| #define B16avPll_status_FBDIV_RD 0x00A0 |
| #define LSb32avPll_status_FBDIV_RD 7 |
| #define LSb16avPll_status_FBDIV_RD 7 |
| #define bavPll_status_FBDIV_RD 9 |
| #define MSK32avPll_status_FBDIV_RD 0x0000FF80 |
| #define BA_avPll_status_PLL_CAL_DONE 0x00A2 |
| #define B16avPll_status_PLL_CAL_DONE 0x00A2 |
| #define LSb32avPll_status_PLL_CAL_DONE 16 |
| #define LSb16avPll_status_PLL_CAL_DONE 0 |
| #define bavPll_status_PLL_CAL_DONE 1 |
| #define MSK32avPll_status_PLL_CAL_DONE 0x00010000 |
| #define BA_avPll_status_SPEED_CNT 0x00A2 |
| #define B16avPll_status_SPEED_CNT 0x00A2 |
| #define LSb32avPll_status_SPEED_CNT 17 |
| #define LSb16avPll_status_SPEED_CNT 1 |
| #define bavPll_status_SPEED_CNT 6 |
| #define MSK32avPll_status_SPEED_CNT 0x007E0000 |
| #define BA_avPll_status_SPEED_RD 0x00A2 |
| #define B16avPll_status_SPEED_RD 0x00A2 |
| #define LSb32avPll_status_SPEED_RD 23 |
| #define LSb16avPll_status_SPEED_RD 7 |
| #define bavPll_status_SPEED_RD 4 |
| #define MSK32avPll_status_SPEED_RD 0x07800000 |
| #define RA_avPll_status1 0x00A4 |
| #define BA_avPll_status_SLLP_DAC_RD 0x00A4 |
| #define B16avPll_status_SLLP_DAC_RD 0x00A4 |
| #define LSb32avPll_status_SLLP_DAC_RD 0 |
| #define LSb16avPll_status_SLLP_DAC_RD 0 |
| #define bavPll_status_SLLP_DAC_RD 7 |
| #define MSK32avPll_status_SLLP_DAC_RD 0x0000007F |
| #define BA_WIDTH32_entry 0x0000 |
| #define B16WIDTH32_entry 0x0000 |
| #define LSb32WIDTH32_entry 0 |
| #define LSb16WIDTH32_entry 0 |
| #define bWIDTH32_entry 32 |
| #define MSK32WIDTH32_entry 0xFFFFFFFF |
| #define RA_HISTLUT_array 0x0000 |
| #define RA_axiLMeter_rLUT 0x0000 |
| #define RA_axiLMeter_wLUT 0x0100 |
| #define RA_axiLMeter_CTRL 0x0200 |
| #define BA_axiLMeter_CTRL_enable 0x0200 |
| #define B16axiLMeter_CTRL_enable 0x0200 |
| #define LSb32axiLMeter_CTRL_enable 0 |
| #define LSb16axiLMeter_CTRL_enable 0 |
| #define baxiLMeter_CTRL_enable 1 |
| #define MSK32axiLMeter_CTRL_enable 0x00000001 |
| #define BA_axiLMeter_CTRL_timerSel 0x0200 |
| #define B16axiLMeter_CTRL_timerSel 0x0200 |
| #define LSb32axiLMeter_CTRL_timerSel 1 |
| #define LSb16axiLMeter_CTRL_timerSel 1 |
| #define baxiLMeter_CTRL_timerSel 1 |
| #define MSK32axiLMeter_CTRL_timerSel 0x00000002 |
| #define RA_axiLMeter_TIMER 0x0204 |
| #define BA_axiLMeter_TIMER_capTimer 0x0204 |
| #define B16axiLMeter_TIMER_capTimer 0x0204 |
| #define LSb32axiLMeter_TIMER_capTimer 0 |
| #define LSb16axiLMeter_TIMER_capTimer 0 |
| #define baxiLMeter_TIMER_capTimer 32 |
| #define MSK32axiLMeter_TIMER_capTimer 0xFFFFFFFF |
| #define RA_axiLMeter_WBIN 0x0208 |
| #define BA_axiLMeter_WBIN_wbin0Hi 0x0208 |
| #define B16axiLMeter_WBIN_wbin0Hi 0x0208 |
| #define LSb32axiLMeter_WBIN_wbin0Hi 0 |
| #define LSb16axiLMeter_WBIN_wbin0Hi 0 |
| #define baxiLMeter_WBIN_wbin0Hi 16 |
| #define MSK32axiLMeter_WBIN_wbin0Hi 0x0000FFFF |
| #define BA_axiLMeter_WBIN_wbinSize 0x020A |
| #define B16axiLMeter_WBIN_wbinSize 0x020A |
| #define LSb32axiLMeter_WBIN_wbinSize 16 |
| #define LSb16axiLMeter_WBIN_wbinSize 0 |
| #define baxiLMeter_WBIN_wbinSize 16 |
| #define MSK32axiLMeter_WBIN_wbinSize 0xFFFF0000 |
| #define RA_axiLMeter_RBIN 0x020C |
| #define BA_axiLMeter_RBIN_rbin0Hi 0x020C |
| #define B16axiLMeter_RBIN_rbin0Hi 0x020C |
| #define LSb32axiLMeter_RBIN_rbin0Hi 0 |
| #define LSb16axiLMeter_RBIN_rbin0Hi 0 |
| #define baxiLMeter_RBIN_rbin0Hi 16 |
| #define MSK32axiLMeter_RBIN_rbin0Hi 0x0000FFFF |
| #define BA_axiLMeter_RBIN_rbinSize 0x020E |
| #define B16axiLMeter_RBIN_rbinSize 0x020E |
| #define LSb32axiLMeter_RBIN_rbinSize 16 |
| #define LSb16axiLMeter_RBIN_rbinSize 0 |
| #define baxiLMeter_RBIN_rbinSize 16 |
| #define MSK32axiLMeter_RBIN_rbinSize 0xFFFF0000 |
| #define RA_axiLMeter_STATUS 0x0210 |
| #define BA_axiLMeter_STATUS_done 0x0210 |
| #define B16axiLMeter_STATUS_done 0x0210 |
| #define LSb32axiLMeter_STATUS_done 0 |
| #define LSb16axiLMeter_STATUS_done 0 |
| #define baxiLMeter_STATUS_done 1 |
| #define MSK32axiLMeter_STATUS_done 0x00000001 |
| #define BA_axiLMeter_STATUS_rError 0x0210 |
| #define B16axiLMeter_STATUS_rError 0x0210 |
| #define LSb32axiLMeter_STATUS_rError 1 |
| #define LSb16axiLMeter_STATUS_rError 1 |
| #define baxiLMeter_STATUS_rError 1 |
| #define MSK32axiLMeter_STATUS_rError 0x00000002 |
| #define BA_axiLMeter_STATUS_wError 0x0210 |
| #define B16axiLMeter_STATUS_wError 0x0210 |
| #define LSb32axiLMeter_STATUS_wError 2 |
| #define LSb16axiLMeter_STATUS_wError 2 |
| #define baxiLMeter_STATUS_wError 1 |
| #define MSK32axiLMeter_STATUS_wError 0x00000004 |
| #define RA_axiLMeter_ID 0x0214 |
| #define BA_axiLMeter_ID_RID 0x0214 |
| #define B16axiLMeter_ID_RID 0x0214 |
| #define LSb32axiLMeter_ID_RID 0 |
| #define LSb16axiLMeter_ID_RID 0 |
| #define baxiLMeter_ID_RID 16 |
| #define MSK32axiLMeter_ID_RID 0x0000FFFF |
| #define BA_axiLMeter_ID_WID 0x0216 |
| #define B16axiLMeter_ID_WID 0x0216 |
| #define LSb32axiLMeter_ID_WID 16 |
| #define LSb16axiLMeter_ID_WID 0 |
| #define baxiLMeter_ID_WID 16 |
| #define MSK32axiLMeter_ID_WID 0xFFFF0000 |
| #define RA_ALM_almIP 0x0000 |
| #define RA_DAC_ctrl_ctrl0 0x0000 |
| #define BA_DAC_ctrl_ctrl0_gain_c 0x0000 |
| #define B16DAC_ctrl_ctrl0_gain_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_gain_c 0 |
| #define LSb16DAC_ctrl_ctrl0_gain_c 0 |
| #define bDAC_ctrl_ctrl0_gain_c 8 |
| #define MSK32DAC_ctrl_ctrl0_gain_c 0x000000FF |
| #define BA_DAC_ctrl_ctrl0_pu_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_pu_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_pu_c 8 |
| #define LSb16DAC_ctrl_ctrl0_pu_c 8 |
| #define bDAC_ctrl_ctrl0_pu_c 1 |
| #define MSK32DAC_ctrl_ctrl0_pu_c 0x00000100 |
| #define BA_DAC_ctrl_ctrl0_rst_ovl_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_rst_ovl_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_rst_ovl_c 9 |
| #define LSb16DAC_ctrl_ctrl0_rst_ovl_c 9 |
| #define bDAC_ctrl_ctrl0_rst_ovl_c 1 |
| #define MSK32DAC_ctrl_ctrl0_rst_ovl_c 0x00000200 |
| #define BA_DAC_ctrl_ctrl0_cal_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_cal_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_cal_c 10 |
| #define LSb16DAC_ctrl_ctrl0_cal_c 10 |
| #define bDAC_ctrl_ctrl0_cal_c 2 |
| #define MSK32DAC_ctrl_ctrl0_cal_c 0x00000C00 |
| #define BA_DAC_ctrl_ctrl0_cal_en_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_cal_en_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_cal_en_c 12 |
| #define LSb16DAC_ctrl_ctrl0_cal_en_c 12 |
| #define bDAC_ctrl_ctrl0_cal_en_c 1 |
| #define MSK32DAC_ctrl_ctrl0_cal_en_c 0x00001000 |
| #define BA_DAC_ctrl_ctrl0_cal_spare_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_cal_spare_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_cal_spare_c 13 |
| #define LSb16DAC_ctrl_ctrl0_cal_spare_c 13 |
| #define bDAC_ctrl_ctrl0_cal_spare_c 1 |
| #define MSK32DAC_ctrl_ctrl0_cal_spare_c 0x00002000 |
| #define BA_DAC_ctrl_ctrl0_calmode_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_calmode_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_calmode_c 14 |
| #define LSb16DAC_ctrl_ctrl0_calmode_c 14 |
| #define bDAC_ctrl_ctrl0_calmode_c 1 |
| #define MSK32DAC_ctrl_ctrl0_calmode_c 0x00004000 |
| #define BA_DAC_ctrl_ctrl0_en_cable_detect_c 0x0001 |
| #define B16DAC_ctrl_ctrl0_en_cable_detect_c 0x0000 |
| #define LSb32DAC_ctrl_ctrl0_en_cable_detect_c 15 |
| #define LSb16DAC_ctrl_ctrl0_en_cable_detect_c 15 |
| #define bDAC_ctrl_ctrl0_en_cable_detect_c 1 |
| #define MSK32DAC_ctrl_ctrl0_en_cable_detect_c 0x00008000 |
| #define BA_DAC_ctrl_ctrl0_en_fullscale_cal_c 0x0002 |
| #define B16DAC_ctrl_ctrl0_en_fullscale_cal_c 0x0002 |
| #define LSb32DAC_ctrl_ctrl0_en_fullscale_cal_c 16 |
| #define LSb16DAC_ctrl_ctrl0_en_fullscale_cal_c 0 |
| #define bDAC_ctrl_ctrl0_en_fullscale_cal_c 1 |
| #define MSK32DAC_ctrl_ctrl0_en_fullscale_cal_c 0x00010000 |
| #define BA_DAC_ctrl_ctrl0_en_open_detect_c 0x0002 |
| #define B16DAC_ctrl_ctrl0_en_open_detect_c 0x0002 |
| #define LSb32DAC_ctrl_ctrl0_en_open_detect_c 17 |
| #define LSb16DAC_ctrl_ctrl0_en_open_detect_c 1 |
| #define bDAC_ctrl_ctrl0_en_open_detect_c 1 |
| #define MSK32DAC_ctrl_ctrl0_en_open_detect_c 0x00020000 |
| #define BA_DAC_ctrl_ctrl0_le_x_c 0x0002 |
| #define B16DAC_ctrl_ctrl0_le_x_c 0x0002 |
| #define LSb32DAC_ctrl_ctrl0_le_x_c 18 |
| #define LSb16DAC_ctrl_ctrl0_le_x_c 2 |
| #define bDAC_ctrl_ctrl0_le_x_c 8 |
| #define MSK32DAC_ctrl_ctrl0_le_x_c 0x03FC0000 |
| #define RA_DAC_ctrl_ctrl01 0x0004 |
| #define BA_DAC_ctrl_ctrl0_le_y_c 0x0004 |
| #define B16DAC_ctrl_ctrl0_le_y_c 0x0004 |
| #define LSb32DAC_ctrl_ctrl0_le_y_c 0 |
| #define LSb16DAC_ctrl_ctrl0_le_y_c 0 |
| #define bDAC_ctrl_ctrl0_le_y_c 8 |
| #define MSK32DAC_ctrl_ctrl0_le_y_c 0x000000FF |
| #define BA_DAC_ctrl_ctrl0_off_c 0x0005 |
| #define B16DAC_ctrl_ctrl0_off_c 0x0004 |
| #define LSb32DAC_ctrl_ctrl0_off_c 8 |
| #define LSb16DAC_ctrl_ctrl0_off_c 8 |
| #define bDAC_ctrl_ctrl0_off_c 6 |
| #define MSK32DAC_ctrl_ctrl0_off_c 0x00003F00 |
| #define BA_DAC_ctrl_ctrl0_pu_refgen 0x0005 |
| #define B16DAC_ctrl_ctrl0_pu_refgen 0x0004 |
| #define LSb32DAC_ctrl_ctrl0_pu_refgen 14 |
| #define LSb16DAC_ctrl_ctrl0_pu_refgen 14 |
| #define bDAC_ctrl_ctrl0_pu_refgen 1 |
| #define MSK32DAC_ctrl_ctrl0_pu_refgen 0x00004000 |
| #define BA_DAC_ctrl_ctrl0_tst 0x0005 |
| #define B16DAC_ctrl_ctrl0_tst 0x0004 |
| #define LSb32DAC_ctrl_ctrl0_tst 15 |
| #define LSb16DAC_ctrl_ctrl0_tst 15 |
| #define bDAC_ctrl_ctrl0_tst 9 |
| #define MSK32DAC_ctrl_ctrl0_tst 0x00FF8000 |
| #define BA_DAC_ctrl_ctrl0_vbg_val 0x0007 |
| #define B16DAC_ctrl_ctrl0_vbg_val 0x0006 |
| #define LSb32DAC_ctrl_ctrl0_vbg_val 24 |
| #define LSb16DAC_ctrl_ctrl0_vbg_val 8 |
| #define bDAC_ctrl_ctrl0_vbg_val 4 |
| #define MSK32DAC_ctrl_ctrl0_vbg_val 0x0F000000 |
| #define RA_DAC_ctrl_ctrl1 0x0008 |
| #define BA_DAC_ctrl_ctrl1_Reserved 0x0008 |
| #define B16DAC_ctrl_ctrl1_Reserved 0x0008 |
| #define LSb32DAC_ctrl_ctrl1_Reserved 0 |
| #define LSb16DAC_ctrl_ctrl1_Reserved 0 |
| #define bDAC_ctrl_ctrl1_Reserved 32 |
| #define MSK32DAC_ctrl_ctrl1_Reserved 0xFFFFFFFF |
| #define BA_DAC_sts_cable_cmp_out_c 0x0000 |
| #define B16DAC_sts_cable_cmp_out_c 0x0000 |
| #define LSb32DAC_sts_cable_cmp_out_c 0 |
| #define LSb16DAC_sts_cable_cmp_out_c 0 |
| #define bDAC_sts_cable_cmp_out_c 1 |
| #define MSK32DAC_sts_cable_cmp_out_c 0x00000001 |
| #define BA_DAC_sts_ovl_flag_c 0x0000 |
| #define B16DAC_sts_ovl_flag_c 0x0000 |
| #define LSb32DAC_sts_ovl_flag_c 1 |
| #define LSb16DAC_sts_ovl_flag_c 1 |
| #define bDAC_sts_ovl_flag_c 1 |
| #define MSK32DAC_sts_ovl_flag_c 0x00000002 |
| #define BA_DAC_sts_open_c 0x0000 |
| #define B16DAC_sts_open_c 0x0000 |
| #define LSb32DAC_sts_open_c 2 |
| #define LSb16DAC_sts_open_c 2 |
| #define bDAC_sts_open_c 1 |
| #define MSK32DAC_sts_open_c 0x00000004 |
| #define RA_VDAC_ctrl_a 0x0000 |
| #define RA_VDAC_ctrl_clk 0x000C |
| #define BA_VDAC_ctrl_clk_N 0x000C |
| #define B16VDAC_ctrl_clk_N 0x000C |
| #define LSb32VDAC_ctrl_clk_N 0 |
| #define LSb16VDAC_ctrl_clk_N 0 |
| #define bVDAC_ctrl_clk_N 3 |
| #define MSK32VDAC_ctrl_clk_N 0x00000007 |
| #define BA_VDAC_ctrl_clk_En 0x000C |
| #define B16VDAC_ctrl_clk_En 0x000C |
| #define LSb32VDAC_ctrl_clk_En 3 |
| #define LSb16VDAC_ctrl_clk_En 3 |
| #define bVDAC_ctrl_clk_En 1 |
| #define MSK32VDAC_ctrl_clk_En 0x00000008 |
| #define BA_VDAC_ctrl_clk_Switch 0x000C |
| #define B16VDAC_ctrl_clk_Switch 0x000C |
| #define LSb32VDAC_ctrl_clk_Switch 4 |
| #define LSb16VDAC_ctrl_clk_Switch 4 |
| #define bVDAC_ctrl_clk_Switch 1 |
| #define MSK32VDAC_ctrl_clk_Switch 0x00000010 |
| #define RA_VDAC_sts_rd 0x0000 |
| #define BA_HDMI_ctrl_PU_IREF 0x0000 |
| #define B16HDMI_ctrl_PU_IREF 0x0000 |
| #define LSb32HDMI_ctrl_PU_IREF 0 |
| #define LSb16HDMI_ctrl_PU_IREF 0 |
| #define bHDMI_ctrl_PU_IREF 1 |
| #define MSK32HDMI_ctrl_PU_IREF 0x00000001 |
| #define BA_HDMI_ctrl_RST_TX 0x0000 |
| #define B16HDMI_ctrl_RST_TX 0x0000 |
| #define LSb32HDMI_ctrl_RST_TX 1 |
| #define LSb16HDMI_ctrl_RST_TX 1 |
| #define bHDMI_ctrl_RST_TX 1 |
| #define MSK32HDMI_ctrl_RST_TX 0x00000002 |
| #define BA_HDMI_ctrl_PU_TX 0x0000 |
| #define B16HDMI_ctrl_PU_TX 0x0000 |
| #define LSb32HDMI_ctrl_PU_TX 2 |
| #define LSb16HDMI_ctrl_PU_TX 2 |
| #define bHDMI_ctrl_PU_TX 4 |
| #define MSK32HDMI_ctrl_PU_TX 0x0000003C |
| #define BA_HDMI_ctrl_POLSWAP_TX 0x0000 |
| #define B16HDMI_ctrl_POLSWAP_TX 0x0000 |
| #define LSb32HDMI_ctrl_POLSWAP_TX 6 |
| #define LSb16HDMI_ctrl_POLSWAP_TX 6 |
| #define bHDMI_ctrl_POLSWAP_TX 4 |
| #define MSK32HDMI_ctrl_POLSWAP_TX 0x000003C0 |
| #define BA_HDMI_ctrl_INV_CK10T 0x0001 |
| #define B16HDMI_ctrl_INV_CK10T 0x0000 |
| #define LSb32HDMI_ctrl_INV_CK10T 10 |
| #define LSb16HDMI_ctrl_INV_CK10T 10 |
| #define bHDMI_ctrl_INV_CK10T 1 |
| #define MSK32HDMI_ctrl_INV_CK10T 0x00000400 |
| #define BA_HDMI_ctrl_DAMP 0x0001 |
| #define B16HDMI_ctrl_DAMP 0x0000 |
| #define LSb32HDMI_ctrl_DAMP 11 |
| #define LSb16HDMI_ctrl_DAMP 11 |
| #define bHDMI_ctrl_DAMP 12 |
| #define MSK32HDMI_ctrl_DAMP 0x007FF800 |
| #define BA_HDMI_ctrl_EAMP 0x0004 |
| #define B16HDMI_ctrl_EAMP 0x0004 |
| #define LSb32HDMI_ctrl_EAMP 0 |
| #define LSb16HDMI_ctrl_EAMP 0 |
| #define bHDMI_ctrl_EAMP 12 |
| #define MSK32HDMI_ctrl_EAMP 0x00000FFF |
| #define BA_HDMI_ctrl_IDRV 0x0005 |
| #define B16HDMI_ctrl_IDRV 0x0004 |
| #define LSb32HDMI_ctrl_IDRV 12 |
| #define LSb16HDMI_ctrl_IDRV 12 |
| #define bHDMI_ctrl_IDRV 16 |
| #define MSK32HDMI_ctrl_IDRV 0x0FFFF000 |
| #define BA_HDMI_ctrl_TXDRVX2 0x0007 |
| #define B16HDMI_ctrl_TXDRVX2 0x0006 |
| #define LSb32HDMI_ctrl_TXDRVX2 28 |
| #define LSb16HDMI_ctrl_TXDRVX2 12 |
| #define bHDMI_ctrl_TXDRVX2 1 |
| #define MSK32HDMI_ctrl_TXDRVX2 0x10000000 |
| #define BA_HDMI_ctrl_SVTX 0x0007 |
| #define B16HDMI_ctrl_SVTX 0x0006 |
| #define LSb32HDMI_ctrl_SVTX 29 |
| #define LSb16HDMI_ctrl_SVTX 13 |
| #define bHDMI_ctrl_SVTX 3 |
| #define MSK32HDMI_ctrl_SVTX 0xE0000000 |
| #define BA_HDMI_ctrl_CP 0x0008 |
| #define B16HDMI_ctrl_CP 0x0008 |
| #define LSb32HDMI_ctrl_CP 0 |
| #define LSb16HDMI_ctrl_CP 0 |
| #define bHDMI_ctrl_CP 8 |
| #define MSK32HDMI_ctrl_CP 0x000000FF |
| #define BA_HDMI_ctrl_AJ_D 0x0009 |
| #define B16HDMI_ctrl_AJ_D 0x0008 |
| #define LSb32HDMI_ctrl_AJ_D 8 |
| #define LSb16HDMI_ctrl_AJ_D 8 |
| #define bHDMI_ctrl_AJ_D 4 |
| #define MSK32HDMI_ctrl_AJ_D 0x00000F00 |
| #define BA_HDMI_ctrl_AJ_EN 0x0009 |
| #define B16HDMI_ctrl_AJ_EN 0x0008 |
| #define LSb32HDMI_ctrl_AJ_EN 12 |
| #define LSb16HDMI_ctrl_AJ_EN 12 |
| #define bHDMI_ctrl_AJ_EN 4 |
| #define MSK32HDMI_ctrl_AJ_EN 0x0000F000 |
| #define BA_HDMI_ctrl_TP_EN 0x000A |
| #define B16HDMI_ctrl_TP_EN 0x000A |
| #define LSb32HDMI_ctrl_TP_EN 16 |
| #define LSb16HDMI_ctrl_TP_EN 0 |
| #define bHDMI_ctrl_TP_EN 6 |
| #define MSK32HDMI_ctrl_TP_EN 0x003F0000 |
| #define BA_HDMI_ctrl_TPC 0x000A |
| #define B16HDMI_ctrl_TPC 0x000A |
| #define LSb32HDMI_ctrl_TPC 22 |
| #define LSb16HDMI_ctrl_TPC 6 |
| #define bHDMI_ctrl_TPC 4 |
| #define MSK32HDMI_ctrl_TPC 0x03C00000 |
| #define BA_HDMI_ctrl_AUX_CTRL0 0x000C |
| #define B16HDMI_ctrl_AUX_CTRL0 0x000C |
| #define LSb32HDMI_ctrl_AUX_CTRL0 0 |
| #define LSb16HDMI_ctrl_AUX_CTRL0 0 |
| #define bHDMI_ctrl_AUX_CTRL0 8 |
| #define MSK32HDMI_ctrl_AUX_CTRL0 0x000000FF |
| #define BA_HDMI_ctrl_AUX_CTRL_1 0x000D |
| #define B16HDMI_ctrl_AUX_CTRL_1 0x000C |
| #define LSb32HDMI_ctrl_AUX_CTRL_1 8 |
| #define LSb16HDMI_ctrl_AUX_CTRL_1 8 |
| #define bHDMI_ctrl_AUX_CTRL_1 8 |
| #define MSK32HDMI_ctrl_AUX_CTRL_1 0x0000FF00 |
| #define BA_HDMI_ctrl_PU_ARC 0x000E |
| #define B16HDMI_ctrl_PU_ARC 0x000E |
| #define LSb32HDMI_ctrl_PU_ARC 16 |
| #define LSb16HDMI_ctrl_PU_ARC 0 |
| #define bHDMI_ctrl_PU_ARC 1 |
| #define MSK32HDMI_ctrl_PU_ARC 0x00010000 |
| #define BA_HDMI_ctrl_ENABLE_ARC 0x000E |
| #define B16HDMI_ctrl_ENABLE_ARC 0x000E |
| #define LSb32HDMI_ctrl_ENABLE_ARC 17 |
| #define LSb16HDMI_ctrl_ENABLE_ARC 1 |
| #define bHDMI_ctrl_ENABLE_ARC 1 |
| #define MSK32HDMI_ctrl_ENABLE_ARC 0x00020000 |
| #define BA_HDMI_ctrl_HYST0_ARC 0x000E |
| #define B16HDMI_ctrl_HYST0_ARC 0x000E |
| #define LSb32HDMI_ctrl_HYST0_ARC 18 |
| #define LSb16HDMI_ctrl_HYST0_ARC 2 |
| #define bHDMI_ctrl_HYST0_ARC 1 |
| #define MSK32HDMI_ctrl_HYST0_ARC 0x00040000 |
| #define BA_HDMI_ctrl_HYST1_ARC 0x000E |
| #define B16HDMI_ctrl_HYST1_ARC 0x000E |
| #define LSb32HDMI_ctrl_HYST1_ARC 19 |
| #define LSb16HDMI_ctrl_HYST1_ARC 3 |
| #define bHDMI_ctrl_HYST1_ARC 1 |
| #define MSK32HDMI_ctrl_HYST1_ARC 0x00080000 |
| #define BA_HDMI_ctrl_M_EN_ARC 0x000E |
| #define B16HDMI_ctrl_M_EN_ARC 0x000E |
| #define LSb32HDMI_ctrl_M_EN_ARC 20 |
| #define LSb16HDMI_ctrl_M_EN_ARC 4 |
| #define bHDMI_ctrl_M_EN_ARC 1 |
| #define MSK32HDMI_ctrl_M_EN_ARC 0x00100000 |
| #define BA_HDMI_ctrl_P_EN_ARC 0x000E |
| #define B16HDMI_ctrl_P_EN_ARC 0x000E |
| #define LSb32HDMI_ctrl_P_EN_ARC 21 |
| #define LSb16HDMI_ctrl_P_EN_ARC 5 |
| #define bHDMI_ctrl_P_EN_ARC 1 |
| #define MSK32HDMI_ctrl_P_EN_ARC 0x00200000 |
| #define BA_HDMI_ctrl_POLSWAP_ARC 0x000E |
| #define B16HDMI_ctrl_POLSWAP_ARC 0x000E |
| #define LSb32HDMI_ctrl_POLSWAP_ARC 22 |
| #define LSb16HDMI_ctrl_POLSWAP_ARC 6 |
| #define bHDMI_ctrl_POLSWAP_ARC 1 |
| #define MSK32HDMI_ctrl_POLSWAP_ARC 0x00400000 |
| #define BA_HDMI_ctrl_TM_EN_ARC 0x000E |
| #define B16HDMI_ctrl_TM_EN_ARC 0x000E |
| #define LSb32HDMI_ctrl_TM_EN_ARC 23 |
| #define LSb16HDMI_ctrl_TM_EN_ARC 7 |
| #define bHDMI_ctrl_TM_EN_ARC 1 |
| #define MSK32HDMI_ctrl_TM_EN_ARC 0x00800000 |
| #define BA_HDMI_ctrl_IPP_CTL 0x000F |
| #define B16HDMI_ctrl_IPP_CTL 0x000E |
| #define LSb32HDMI_ctrl_IPP_CTL 24 |
| #define LSb16HDMI_ctrl_IPP_CTL 8 |
| #define bHDMI_ctrl_IPP_CTL 3 |
| #define MSK32HDMI_ctrl_IPP_CTL 0x07000000 |
| #define BA_HDMI_ctrl_SEL_CK2T 0x000F |
| #define B16HDMI_ctrl_SEL_CK2T 0x000E |
| #define LSb32HDMI_ctrl_SEL_CK2T 27 |
| #define LSb16HDMI_ctrl_SEL_CK2T 11 |
| #define bHDMI_ctrl_SEL_CK2T 2 |
| #define MSK32HDMI_ctrl_SEL_CK2T 0x18000000 |
| #define BA_HDMI_ctrl_RTERM_CTRL 0x0010 |
| #define B16HDMI_ctrl_RTERM_CTRL 0x0010 |
| #define LSb32HDMI_ctrl_RTERM_CTRL 0 |
| #define LSb16HDMI_ctrl_RTERM_CTRL 0 |
| #define bHDMI_ctrl_RTERM_CTRL 16 |
| #define MSK32HDMI_ctrl_RTERM_CTRL 0x0000FFFF |
| #define BA_HDMI_ctrl_PU_PLL 0x0012 |
| #define B16HDMI_ctrl_PU_PLL 0x0012 |
| #define LSb32HDMI_ctrl_PU_PLL 16 |
| #define LSb16HDMI_ctrl_PU_PLL 0 |
| #define bHDMI_ctrl_PU_PLL 1 |
| #define MSK32HDMI_ctrl_PU_PLL 0x00010000 |
| #define BA_HDMI_ctrl_PLL_LOCK_TH 0x0012 |
| #define B16HDMI_ctrl_PLL_LOCK_TH 0x0012 |
| #define LSb32HDMI_ctrl_PLL_LOCK_TH 17 |
| #define LSb16HDMI_ctrl_PLL_LOCK_TH 1 |
| #define bHDMI_ctrl_PLL_LOCK_TH 4 |
| #define MSK32HDMI_ctrl_PLL_LOCK_TH 0x001E0000 |
| #define BA_HDMI_ctrl_RESET_PLL 0x0012 |
| #define B16HDMI_ctrl_RESET_PLL 0x0012 |
| #define LSb32HDMI_ctrl_RESET_PLL 21 |
| #define LSb16HDMI_ctrl_RESET_PLL 5 |
| #define bHDMI_ctrl_RESET_PLL 1 |
| #define MSK32HDMI_ctrl_RESET_PLL 0x00200000 |
| #define BA_HDMI_ctrl_SEL_420 0x0012 |
| #define B16HDMI_ctrl_SEL_420 0x0012 |
| #define LSb32HDMI_ctrl_SEL_420 22 |
| #define LSb16HDMI_ctrl_SEL_420 6 |
| #define bHDMI_ctrl_SEL_420 1 |
| #define MSK32HDMI_ctrl_SEL_420 0x00400000 |
| #define BA_HDMI_ctrl_SEL_DC 0x0012 |
| #define B16HDMI_ctrl_SEL_DC 0x0012 |
| #define LSb32HDMI_ctrl_SEL_DC 23 |
| #define LSb16HDMI_ctrl_SEL_DC 7 |
| #define bHDMI_ctrl_SEL_DC 2 |
| #define MSK32HDMI_ctrl_SEL_DC 0x01800000 |
| #define BA_HDMI_ctrl_SEL_DIVA 0x0013 |
| #define B16HDMI_ctrl_SEL_DIVA 0x0012 |
| #define LSb32HDMI_ctrl_SEL_DIVA 25 |
| #define LSb16HDMI_ctrl_SEL_DIVA 9 |
| #define bHDMI_ctrl_SEL_DIVA 3 |
| #define MSK32HDMI_ctrl_SEL_DIVA 0x0E000000 |
| #define BA_HDMI_ctrl_SEL_DIVX 0x0013 |
| #define B16HDMI_ctrl_SEL_DIVX 0x0012 |
| #define LSb32HDMI_ctrl_SEL_DIVX 28 |
| #define LSb16HDMI_ctrl_SEL_DIVX 12 |
| #define bHDMI_ctrl_SEL_DIVX 3 |
| #define MSK32HDMI_ctrl_SEL_DIVX 0x70000000 |
| #define BA_HDMI_ctrl_SEL_HF 0x0013 |
| #define B16HDMI_ctrl_SEL_HF 0x0012 |
| #define LSb32HDMI_ctrl_SEL_HF 31 |
| #define LSb16HDMI_ctrl_SEL_HF 15 |
| #define bHDMI_ctrl_SEL_HF 1 |
| #define MSK32HDMI_ctrl_SEL_HF 0x80000000 |
| #define BA_HDMI_ctrl_SICP 0x0014 |
| #define B16HDMI_ctrl_SICP 0x0014 |
| #define LSb32HDMI_ctrl_SICP 0 |
| #define LSb16HDMI_ctrl_SICP 0 |
| #define bHDMI_ctrl_SICP 5 |
| #define MSK32HDMI_ctrl_SICP 0x0000001F |
| #define BA_HDMI_ctrl_SIKVCO 0x0014 |
| #define B16HDMI_ctrl_SIKVCO 0x0014 |
| #define LSb32HDMI_ctrl_SIKVCO 5 |
| #define LSb16HDMI_ctrl_SIKVCO 5 |
| #define bHDMI_ctrl_SIKVCO 5 |
| #define MSK32HDMI_ctrl_SIKVCO 0x000003E0 |
| #define BA_HDMI_ctrl_SVPLL 0x0015 |
| #define B16HDMI_ctrl_SVPLL 0x0014 |
| #define LSb32HDMI_ctrl_SVPLL 10 |
| #define LSb16HDMI_ctrl_SVPLL 10 |
| #define bHDMI_ctrl_SVPLL 2 |
| #define MSK32HDMI_ctrl_SVPLL 0x00000C00 |
| #define BA_HDMI_ctrl_SVPLLH 0x0015 |
| #define B16HDMI_ctrl_SVPLLH 0x0014 |
| #define LSb32HDMI_ctrl_SVPLLH 12 |
| #define LSb16HDMI_ctrl_SVPLLH 12 |
| #define bHDMI_ctrl_SVPLLH 2 |
| #define MSK32HDMI_ctrl_SVPLLH 0x00003000 |
| #define BA_HDMI_ctrl_VRHI 0x0015 |
| #define B16HDMI_ctrl_VRHI 0x0014 |
| #define LSb32HDMI_ctrl_VRHI 14 |
| #define LSb16HDMI_ctrl_VRHI 14 |
| #define bHDMI_ctrl_VRHI 1 |
| #define MSK32HDMI_ctrl_VRHI 0x00004000 |
| #define BA_HDMI_ctrl_VCOCAL_EN 0x0015 |
| #define B16HDMI_ctrl_VCOCAL_EN 0x0014 |
| #define LSb32HDMI_ctrl_VCOCAL_EN 15 |
| #define LSb16HDMI_ctrl_VCOCAL_EN 15 |
| #define bHDMI_ctrl_VCOCAL_EN 1 |
| #define MSK32HDMI_ctrl_VCOCAL_EN 0x00008000 |
| #define BA_HDMI_ctrl_V2I_FILT_R_ADJ 0x0016 |
| #define B16HDMI_ctrl_V2I_FILT_R_ADJ 0x0016 |
| #define LSb32HDMI_ctrl_V2I_FILT_R_ADJ 16 |
| #define LSb16HDMI_ctrl_V2I_FILT_R_ADJ 0 |
| #define bHDMI_ctrl_V2I_FILT_R_ADJ 2 |
| #define MSK32HDMI_ctrl_V2I_FILT_R_ADJ 0x00030000 |
| #define BA_HDMI_ctrl_VCOCAL_VCON_ADJ 0x0016 |
| #define B16HDMI_ctrl_VCOCAL_VCON_ADJ 0x0016 |
| #define LSb32HDMI_ctrl_VCOCAL_VCON_ADJ 18 |
| #define LSb16HDMI_ctrl_VCOCAL_VCON_ADJ 2 |
| #define bHDMI_ctrl_VCOCAL_VCON_ADJ 2 |
| #define MSK32HDMI_ctrl_VCOCAL_VCON_ADJ 0x000C0000 |
| #define BA_HDMI_ctrl_VCOCAL_DIV_CTRL 0x0016 |
| #define B16HDMI_ctrl_VCOCAL_DIV_CTRL 0x0016 |
| #define LSb32HDMI_ctrl_VCOCAL_DIV_CTRL 20 |
| #define LSb16HDMI_ctrl_VCOCAL_DIV_CTRL 4 |
| #define bHDMI_ctrl_VCOCAL_DIV_CTRL 2 |
| #define MSK32HDMI_ctrl_VCOCAL_DIV_CTRL 0x00300000 |
| #define BA_HDMI_ctrl_VCOCAL_TIMER_CTRL 0x0016 |
| #define B16HDMI_ctrl_VCOCAL_TIMER_CTRL 0x0016 |
| #define LSb32HDMI_ctrl_VCOCAL_TIMER_CTRL 22 |
| #define LSb16HDMI_ctrl_VCOCAL_TIMER_CTRL 6 |
| #define bHDMI_ctrl_VCOCAL_TIMER_CTRL 2 |
| #define MSK32HDMI_ctrl_VCOCAL_TIMER_CTRL 0x00C00000 |
| #define BA_HDMI_ctrl_VCOCAL_OVRWEN 0x0017 |
| #define B16HDMI_ctrl_VCOCAL_OVRWEN 0x0016 |
| #define LSb32HDMI_ctrl_VCOCAL_OVRWEN 24 |
| #define LSb16HDMI_ctrl_VCOCAL_OVRWEN 8 |
| #define bHDMI_ctrl_VCOCAL_OVRWEN 1 |
| #define MSK32HDMI_ctrl_VCOCAL_OVRWEN 0x01000000 |
| #define BA_HDMI_ctrl_VCOCAL_OVRW 0x0017 |
| #define B16HDMI_ctrl_VCOCAL_OVRW 0x0016 |
| #define LSb32HDMI_ctrl_VCOCAL_OVRW 25 |
| #define LSb16HDMI_ctrl_VCOCAL_OVRW 9 |
| #define bHDMI_ctrl_VCOCAL_OVRW 4 |
| #define MSK32HDMI_ctrl_VCOCAL_OVRW 0x1E000000 |
| #define BA_HDMI_ctrl_ICP_SCALE_OVRWEN 0x0017 |
| #define B16HDMI_ctrl_ICP_SCALE_OVRWEN 0x0016 |
| #define LSb32HDMI_ctrl_ICP_SCALE_OVRWEN 29 |
| #define LSb16HDMI_ctrl_ICP_SCALE_OVRWEN 13 |
| #define bHDMI_ctrl_ICP_SCALE_OVRWEN 1 |
| #define MSK32HDMI_ctrl_ICP_SCALE_OVRWEN 0x20000000 |
| #define BA_HDMI_ctrl_V2I_FILT_BYP_OVRWEN 0x0017 |
| #define B16HDMI_ctrl_V2I_FILT_BYP_OVRWEN 0x0016 |
| #define LSb32HDMI_ctrl_V2I_FILT_BYP_OVRWEN 30 |
| #define LSb16HDMI_ctrl_V2I_FILT_BYP_OVRWEN 14 |
| #define bHDMI_ctrl_V2I_FILT_BYP_OVRWEN 1 |
| #define MSK32HDMI_ctrl_V2I_FILT_BYP_OVRWEN 0x40000000 |
| #define BA_HDMI_ctrl_V2I_FILT_BYP_OVRW 0x0017 |
| #define B16HDMI_ctrl_V2I_FILT_BYP_OVRW 0x0016 |
| #define LSb32HDMI_ctrl_V2I_FILT_BYP_OVRW 31 |
| #define LSb16HDMI_ctrl_V2I_FILT_BYP_OVRW 15 |
| #define bHDMI_ctrl_V2I_FILT_BYP_OVRW 1 |
| #define MSK32HDMI_ctrl_V2I_FILT_BYP_OVRW 0x80000000 |
| #define BA_HDMI_ctrl_ICP_SCALE_OVRW 0x0018 |
| #define B16HDMI_ctrl_ICP_SCALE_OVRW 0x0018 |
| #define LSb32HDMI_ctrl_ICP_SCALE_OVRW 0 |
| #define LSb16HDMI_ctrl_ICP_SCALE_OVRW 0 |
| #define bHDMI_ctrl_ICP_SCALE_OVRW 4 |
| #define MSK32HDMI_ctrl_ICP_SCALE_OVRW 0x0000000F |
| #define BA_HDMI_ctrl_PLL_CP_OPT 0x0018 |
| #define B16HDMI_ctrl_PLL_CP_OPT 0x0018 |
| #define LSb32HDMI_ctrl_PLL_CP_OPT 4 |
| #define LSb16HDMI_ctrl_PLL_CP_OPT 4 |
| #define bHDMI_ctrl_PLL_CP_OPT 1 |
| #define MSK32HDMI_ctrl_PLL_CP_OPT 0x00000010 |
| #define BA_HDMI_ctrl_LB_CH 0x0018 |
| #define B16HDMI_ctrl_LB_CH 0x0018 |
| #define LSb32HDMI_ctrl_LB_CH 5 |
| #define LSb16HDMI_ctrl_LB_CH 5 |
| #define bHDMI_ctrl_LB_CH 2 |
| #define MSK32HDMI_ctrl_LB_CH 0x00000060 |
| #define BA_HDMI_ctrl_LB_EN 0x0018 |
| #define B16HDMI_ctrl_LB_EN 0x0018 |
| #define LSb32HDMI_ctrl_LB_EN 7 |
| #define LSb16HDMI_ctrl_LB_EN 7 |
| #define bHDMI_ctrl_LB_EN 1 |
| #define MSK32HDMI_ctrl_LB_EN 0x00000080 |
| #define BA_HDMI_ctrl_LB_CTRL 0x0019 |
| #define B16HDMI_ctrl_LB_CTRL 0x0018 |
| #define LSb32HDMI_ctrl_LB_CTRL 8 |
| #define LSb16HDMI_ctrl_LB_CTRL 8 |
| #define bHDMI_ctrl_LB_CTRL 8 |
| #define MSK32HDMI_ctrl_LB_CTRL 0x0000FF00 |
| #define BA_HDMI_sts_AUX_STATUS_0 0x0000 |
| #define B16HDMI_sts_AUX_STATUS_0 0x0000 |
| #define LSb32HDMI_sts_AUX_STATUS_0 0 |
| #define LSb16HDMI_sts_AUX_STATUS_0 0 |
| #define bHDMI_sts_AUX_STATUS_0 8 |
| #define MSK32HDMI_sts_AUX_STATUS_0 0x000000FF |
| #define BA_HDMI_sts_PLL_LOCK 0x0001 |
| #define B16HDMI_sts_PLL_LOCK 0x0000 |
| #define LSb32HDMI_sts_PLL_LOCK 8 |
| #define LSb16HDMI_sts_PLL_LOCK 8 |
| #define bHDMI_sts_PLL_LOCK 1 |
| #define MSK32HDMI_sts_PLL_LOCK 0x00000100 |
| #define BA_HDMI_sts_VCOCAL_BUSY 0x0001 |
| #define B16HDMI_sts_VCOCAL_BUSY 0x0000 |
| #define LSb32HDMI_sts_VCOCAL_BUSY 9 |
| #define LSb16HDMI_sts_VCOCAL_BUSY 9 |
| #define bHDMI_sts_VCOCAL_BUSY 1 |
| #define MSK32HDMI_sts_VCOCAL_BUSY 0x00000200 |
| #define BA_HDMI_sts_VCOCAL_VAL 0x0001 |
| #define B16HDMI_sts_VCOCAL_VAL 0x0000 |
| #define LSb32HDMI_sts_VCOCAL_VAL 10 |
| #define LSb16HDMI_sts_VCOCAL_VAL 10 |
| #define bHDMI_sts_VCOCAL_VAL 4 |
| #define MSK32HDMI_sts_VCOCAL_VAL 0x00003C00 |
| #define BA_HDMI_sts_VCOCAL_FAIL 0x0001 |
| #define B16HDMI_sts_VCOCAL_FAIL 0x0000 |
| #define LSb32HDMI_sts_VCOCAL_FAIL 14 |
| #define LSb16HDMI_sts_VCOCAL_FAIL 14 |
| #define bHDMI_sts_VCOCAL_FAIL 1 |
| #define MSK32HDMI_sts_VCOCAL_FAIL 0x00004000 |
| #define BA_HDMI_sts_PLL_AUX0 0x0001 |
| #define B16HDMI_sts_PLL_AUX0 0x0000 |
| #define LSb32HDMI_sts_PLL_AUX0 15 |
| #define LSb16HDMI_sts_PLL_AUX0 15 |
| #define bHDMI_sts_PLL_AUX0 4 |
| #define MSK32HDMI_sts_PLL_AUX0 0x00078000 |
| #define BA_HDMI_sts_LB_STATUS 0x0002 |
| #define B16HDMI_sts_LB_STATUS 0x0002 |
| #define LSb32HDMI_sts_LB_STATUS 19 |
| #define LSb16HDMI_sts_LB_STATUS 3 |
| #define bHDMI_sts_LB_STATUS 8 |
| #define MSK32HDMI_sts_LB_STATUS 0x07F80000 |
| #define BA_ADAC_ctrl_DAC_EN 0x0000 |
| #define B16ADAC_ctrl_DAC_EN 0x0000 |
| #define LSb32ADAC_ctrl_DAC_EN 0 |
| #define LSb16ADAC_ctrl_DAC_EN 0 |
| #define bADAC_ctrl_DAC_EN 1 |
| #define MSK32ADAC_ctrl_DAC_EN 0x00000001 |
| #define BA_ADAC_ctrl_MODE_SEL 0x0000 |
| #define B16ADAC_ctrl_MODE_SEL 0x0000 |
| #define LSb32ADAC_ctrl_MODE_SEL 1 |
| #define LSb16ADAC_ctrl_MODE_SEL 1 |
| #define bADAC_ctrl_MODE_SEL 1 |
| #define MSK32ADAC_ctrl_MODE_SEL 0x00000002 |
| #define BA_ADAC_ctrl_RESET 0x0000 |
| #define B16ADAC_ctrl_RESET 0x0000 |
| #define LSb32ADAC_ctrl_RESET 2 |
| #define LSb16ADAC_ctrl_RESET 2 |
| #define bADAC_ctrl_RESET 1 |
| #define MSK32ADAC_ctrl_RESET 0x00000004 |
| #define BA_ADAC_ctrl_SE_EN 0x0000 |
| #define B16ADAC_ctrl_SE_EN 0x0000 |
| #define LSb32ADAC_ctrl_SE_EN 3 |
| #define LSb16ADAC_ctrl_SE_EN 3 |
| #define bADAC_ctrl_SE_EN 1 |
| #define MSK32ADAC_ctrl_SE_EN 0x00000008 |
| #define BA_ADAC_ctrl_CP_EN 0x0000 |
| #define B16ADAC_ctrl_CP_EN 0x0000 |
| #define LSb32ADAC_ctrl_CP_EN 4 |
| #define LSb16ADAC_ctrl_CP_EN 4 |
| #define bADAC_ctrl_CP_EN 1 |
| #define MSK32ADAC_ctrl_CP_EN 0x00000010 |
| #define BA_ADAC_ctrl_OSR 0x0000 |
| #define B16ADAC_ctrl_OSR 0x0000 |
| #define LSb32ADAC_ctrl_OSR 5 |
| #define LSb16ADAC_ctrl_OSR 5 |
| #define bADAC_ctrl_OSR 2 |
| #define MSK32ADAC_ctrl_OSR 0x00000060 |
| #define BA_ADAC_ctrl_TEST_SEL 0x0000 |
| #define B16ADAC_ctrl_TEST_SEL 0x0000 |
| #define LSb32ADAC_ctrl_TEST_SEL 7 |
| #define LSb16ADAC_ctrl_TEST_SEL 7 |
| #define bADAC_ctrl_TEST_SEL 3 |
| #define MSK32ADAC_ctrl_TEST_SEL 0x00000380 |
| #define BA_ADAC_ctrl_TEST_EN 0x0001 |
| #define B16ADAC_ctrl_TEST_EN 0x0000 |
| #define LSb32ADAC_ctrl_TEST_EN 10 |
| #define LSb16ADAC_ctrl_TEST_EN 10 |
| #define bADAC_ctrl_TEST_EN 1 |
| #define MSK32ADAC_ctrl_TEST_EN 0x00000400 |
| #define BA_ADAC_ctrl_EN_TEST_ADAC 0x0001 |
| #define B16ADAC_ctrl_EN_TEST_ADAC 0x0000 |
| #define LSb32ADAC_ctrl_EN_TEST_ADAC 11 |
| #define LSb16ADAC_ctrl_EN_TEST_ADAC 11 |
| #define bADAC_ctrl_EN_TEST_ADAC 1 |
| #define MSK32ADAC_ctrl_EN_TEST_ADAC 0x00000800 |
| #define BA_ADAC_ctrl_CP_FREQ_SEL 0x0001 |
| #define B16ADAC_ctrl_CP_FREQ_SEL 0x0000 |
| #define LSb32ADAC_ctrl_CP_FREQ_SEL 12 |
| #define LSb16ADAC_ctrl_CP_FREQ_SEL 12 |
| #define bADAC_ctrl_CP_FREQ_SEL 2 |
| #define MSK32ADAC_ctrl_CP_FREQ_SEL 0x00003000 |
| #define BA_ADAC_ctrl_CHOP_FREQ_SEL 0x0001 |
| #define B16ADAC_ctrl_CHOP_FREQ_SEL 0x0000 |
| #define LSb32ADAC_ctrl_CHOP_FREQ_SEL 14 |
| #define LSb16ADAC_ctrl_CHOP_FREQ_SEL 14 |
| #define bADAC_ctrl_CHOP_FREQ_SEL 2 |
| #define MSK32ADAC_ctrl_CHOP_FREQ_SEL 0x0000C000 |
| #define BA_ADAC_ctrl_DAC_RSVD_IN 0x0004 |
| #define B16ADAC_ctrl_DAC_RSVD_IN 0x0004 |
| #define LSb32ADAC_ctrl_DAC_RSVD_IN 0 |
| #define LSb16ADAC_ctrl_DAC_RSVD_IN 0 |
| #define bADAC_ctrl_DAC_RSVD_IN 20 |
| #define MSK32ADAC_ctrl_DAC_RSVD_IN 0x000FFFFF |
| #define BA_ADAC_ctrl_TEST_MODE 0x0006 |
| #define B16ADAC_ctrl_TEST_MODE 0x0006 |
| #define LSb32ADAC_ctrl_TEST_MODE 20 |
| #define LSb16ADAC_ctrl_TEST_MODE 4 |
| #define bADAC_ctrl_TEST_MODE 1 |
| #define MSK32ADAC_ctrl_TEST_MODE 0x00100000 |
| #define RA_ADAC_sts_status 0x0000 |
| #define BA_ADAC_sts_status_DAC_RSVD_OUT 0x0000 |
| #define B16ADAC_sts_status_DAC_RSVD_OUT 0x0000 |
| #define LSb32ADAC_sts_status_DAC_RSVD_OUT 0 |
| #define LSb16ADAC_sts_status_DAC_RSVD_OUT 0 |
| #define bADAC_sts_status_DAC_RSVD_OUT 12 |
| #define MSK32ADAC_sts_status_DAC_RSVD_OUT 0x00000FFF |
| #define RA_AVIO_debug_ctrl_Ctrl0 0x0000 |
| #define BA_AVIO_debug_ctrl_Ctrl0_debug_ctrl0 0x0000 |
| #define B16AVIO_debug_ctrl_Ctrl0_debug_ctrl0 0x0000 |
| #define LSb32AVIO_debug_ctrl_Ctrl0_debug_ctrl0 0 |
| #define LSb16AVIO_debug_ctrl_Ctrl0_debug_ctrl0 0 |
| #define bAVIO_debug_ctrl_Ctrl0_debug_ctrl0 4 |
| #define MSK32AVIO_debug_ctrl_Ctrl0_debug_ctrl0 0x0000000F |
| #define RA_avioGbl_AVPLLA 0x0000 |
| #define RA_avioGbl_alm0_IP 0x0100 |
| #define RA_avioGbl_VDAC_ctrl 0x0400 |
| #define RA_avioGbl_VDAC_sts 0x0410 |
| #define RA_avioGbl_ADAC_ctrl 0x0414 |
| #define RA_avioGbl_ADAC_sts 0x041C |
| #define RA_avioGbl_HDMI_ctrl 0x0420 |
| #define RA_avioGbl_HDMI_sts 0x043C |
| #define RA_avioGbl_AVIO_debug_ctrl 0x0440 |
| #define RA_avioGbl_AVPLLA_CLK_EN 0x0444 |
| #define BA_avioGbl_AVPLLA_CLK_EN_ctrl 0x0444 |
| #define B16avioGbl_AVPLLA_CLK_EN_ctrl 0x0444 |
| #define LSb32avioGbl_AVPLLA_CLK_EN_ctrl 0 |
| #define LSb16avioGbl_AVPLLA_CLK_EN_ctrl 0 |
| #define bavioGbl_AVPLLA_CLK_EN_ctrl 6 |
| #define MSK32avioGbl_AVPLLA_CLK_EN_ctrl 0x0000003F |
| #define BA_avioGbl_AVPLLA_CLK_EN_dbg_mux_sel 0x0444 |
| #define B16avioGbl_AVPLLA_CLK_EN_dbg_mux_sel 0x0444 |
| #define LSb32avioGbl_AVPLLA_CLK_EN_dbg_mux_sel 6 |
| #define LSb16avioGbl_AVPLLA_CLK_EN_dbg_mux_sel 6 |
| #define bavioGbl_AVPLLA_CLK_EN_dbg_mux_sel 1 |
| #define MSK32avioGbl_AVPLLA_CLK_EN_dbg_mux_sel 0x00000040 |
| #define RA_avioGbl_VCLK0_CTRL 0x0448 |
| #define BA_avioGbl_VCLK0_CTRL_extClkSel 0x0448 |
| #define B16avioGbl_VCLK0_CTRL_extClkSel 0x0448 |
| #define LSb32avioGbl_VCLK0_CTRL_extClkSel 0 |
| #define LSb16avioGbl_VCLK0_CTRL_extClkSel 0 |
| #define bavioGbl_VCLK0_CTRL_extClkSel 1 |
| #define MSK32avioGbl_VCLK0_CTRL_extClkSel 0x00000001 |
| #define RA_avioGbl_VCLK1_CTRL 0x044C |
| #define BA_avioGbl_VCLK1_CTRL_extClkSel 0x044C |
| #define B16avioGbl_VCLK1_CTRL_extClkSel 0x044C |
| #define LSb32avioGbl_VCLK1_CTRL_extClkSel 0 |
| #define LSb16avioGbl_VCLK1_CTRL_extClkSel 0 |
| #define bavioGbl_VCLK1_CTRL_extClkSel 1 |
| #define MSK32avioGbl_VCLK1_CTRL_extClkSel 0x00000001 |
| #define BA_avioGbl_VCLK1_CTRL_pllSel 0x044C |
| #define B16avioGbl_VCLK1_CTRL_pllSel 0x044C |
| #define LSb32avioGbl_VCLK1_CTRL_pllSel 1 |
| #define LSb16avioGbl_VCLK1_CTRL_pllSel 1 |
| #define bavioGbl_VCLK1_CTRL_pllSel 1 |
| #define MSK32avioGbl_VCLK1_CTRL_pllSel 0x00000002 |
| #define RA_avioGbl_VCLK2_CTRL 0x0450 |
| #define BA_avioGbl_VCLK2_CTRL_extClkSel 0x0450 |
| #define B16avioGbl_VCLK2_CTRL_extClkSel 0x0450 |
| #define LSb32avioGbl_VCLK2_CTRL_extClkSel 0 |
| #define LSb16avioGbl_VCLK2_CTRL_extClkSel 0 |
| #define bavioGbl_VCLK2_CTRL_extClkSel 1 |
| #define MSK32avioGbl_VCLK2_CTRL_extClkSel 0x00000001 |
| #define BA_avioGbl_VCLK2_CTRL_pllSel 0x0450 |
| #define B16avioGbl_VCLK2_CTRL_pllSel 0x0450 |
| #define LSb32avioGbl_VCLK2_CTRL_pllSel 1 |
| #define LSb16avioGbl_VCLK2_CTRL_pllSel 1 |
| #define bavioGbl_VCLK2_CTRL_pllSel 1 |
| #define MSK32avioGbl_VCLK2_CTRL_pllSel 0x00000002 |
| #define RA_avioGbl_ACLK0_CTRL 0x0454 |
| #define BA_avioGbl_ACLK0_CTRL_clkSwitch 0x0454 |
| #define B16avioGbl_ACLK0_CTRL_clkSwitch 0x0454 |
| #define LSb32avioGbl_ACLK0_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_ACLK0_CTRL_clkSwitch 0 |
| #define bavioGbl_ACLK0_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_ACLK0_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_ACLK0_CTRL_clkD3Switch 0x0454 |
| #define B16avioGbl_ACLK0_CTRL_clkD3Switch 0x0454 |
| #define LSb32avioGbl_ACLK0_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_ACLK0_CTRL_clkD3Switch 1 |
| #define bavioGbl_ACLK0_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_ACLK0_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_ACLK0_CTRL_clkSel 0x0454 |
| #define B16avioGbl_ACLK0_CTRL_clkSel 0x0454 |
| #define LSb32avioGbl_ACLK0_CTRL_clkSel 2 |
| #define LSb16avioGbl_ACLK0_CTRL_clkSel 2 |
| #define bavioGbl_ACLK0_CTRL_clkSel 3 |
| #define MSK32avioGbl_ACLK0_CTRL_clkSel 0x0000001C |
| #define avioGbl_ACLK0_CTRL_clkSel_d2 0x1 |
| #define avioGbl_ACLK0_CTRL_clkSel_d4 0x2 |
| #define avioGbl_ACLK0_CTRL_clkSel_d6 0x3 |
| #define avioGbl_ACLK0_CTRL_clkSel_d8 0x4 |
| #define avioGbl_ACLK0_CTRL_clkSel_d12 0x5 |
| #define BA_avioGbl_ACLK0_CTRL_srcSel 0x0454 |
| #define B16avioGbl_ACLK0_CTRL_srcSel 0x0454 |
| #define LSb32avioGbl_ACLK0_CTRL_srcSel 5 |
| #define LSb16avioGbl_ACLK0_CTRL_srcSel 5 |
| #define bavioGbl_ACLK0_CTRL_srcSel 1 |
| #define MSK32avioGbl_ACLK0_CTRL_srcSel 0x00000020 |
| #define RA_avioGbl_ACLK1_CTRL 0x0458 |
| #define BA_avioGbl_ACLK1_CTRL_clkSwitch 0x0458 |
| #define B16avioGbl_ACLK1_CTRL_clkSwitch 0x0458 |
| #define LSb32avioGbl_ACLK1_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_ACLK1_CTRL_clkSwitch 0 |
| #define bavioGbl_ACLK1_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_ACLK1_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_ACLK1_CTRL_clkD3Switch 0x0458 |
| #define B16avioGbl_ACLK1_CTRL_clkD3Switch 0x0458 |
| #define LSb32avioGbl_ACLK1_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_ACLK1_CTRL_clkD3Switch 1 |
| #define bavioGbl_ACLK1_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_ACLK1_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_ACLK1_CTRL_clkSel 0x0458 |
| #define B16avioGbl_ACLK1_CTRL_clkSel 0x0458 |
| #define LSb32avioGbl_ACLK1_CTRL_clkSel 2 |
| #define LSb16avioGbl_ACLK1_CTRL_clkSel 2 |
| #define bavioGbl_ACLK1_CTRL_clkSel 3 |
| #define MSK32avioGbl_ACLK1_CTRL_clkSel 0x0000001C |
| #define avioGbl_ACLK1_CTRL_clkSel_d2 0x1 |
| #define avioGbl_ACLK1_CTRL_clkSel_d4 0x2 |
| #define avioGbl_ACLK1_CTRL_clkSel_d6 0x3 |
| #define avioGbl_ACLK1_CTRL_clkSel_d8 0x4 |
| #define avioGbl_ACLK1_CTRL_clkSel_d12 0x5 |
| #define BA_avioGbl_ACLK1_CTRL_pllSel 0x0458 |
| #define B16avioGbl_ACLK1_CTRL_pllSel 0x0458 |
| #define LSb32avioGbl_ACLK1_CTRL_pllSel 5 |
| #define LSb16avioGbl_ACLK1_CTRL_pllSel 5 |
| #define bavioGbl_ACLK1_CTRL_pllSel 1 |
| #define MSK32avioGbl_ACLK1_CTRL_pllSel 0x00000020 |
| #define RA_avioGbl_ACLK2_CTRL 0x045C |
| #define BA_avioGbl_ACLK2_CTRL_clkSwitch 0x045C |
| #define B16avioGbl_ACLK2_CTRL_clkSwitch 0x045C |
| #define LSb32avioGbl_ACLK2_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_ACLK2_CTRL_clkSwitch 0 |
| #define bavioGbl_ACLK2_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_ACLK2_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_ACLK2_CTRL_clkD3Switch 0x045C |
| #define B16avioGbl_ACLK2_CTRL_clkD3Switch 0x045C |
| #define LSb32avioGbl_ACLK2_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_ACLK2_CTRL_clkD3Switch 1 |
| #define bavioGbl_ACLK2_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_ACLK2_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_ACLK2_CTRL_clkSel 0x045C |
| #define B16avioGbl_ACLK2_CTRL_clkSel 0x045C |
| #define LSb32avioGbl_ACLK2_CTRL_clkSel 2 |
| #define LSb16avioGbl_ACLK2_CTRL_clkSel 2 |
| #define bavioGbl_ACLK2_CTRL_clkSel 3 |
| #define MSK32avioGbl_ACLK2_CTRL_clkSel 0x0000001C |
| #define avioGbl_ACLK2_CTRL_clkSel_d2 0x1 |
| #define avioGbl_ACLK2_CTRL_clkSel_d4 0x2 |
| #define avioGbl_ACLK2_CTRL_clkSel_d6 0x3 |
| #define avioGbl_ACLK2_CTRL_clkSel_d8 0x4 |
| #define avioGbl_ACLK2_CTRL_clkSel_d12 0x5 |
| #define RA_avioGbl_ACLK3_CTRL 0x0460 |
| #define BA_avioGbl_ACLK3_CTRL_clkSwitch 0x0460 |
| #define B16avioGbl_ACLK3_CTRL_clkSwitch 0x0460 |
| #define LSb32avioGbl_ACLK3_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_ACLK3_CTRL_clkSwitch 0 |
| #define bavioGbl_ACLK3_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_ACLK3_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_ACLK3_CTRL_clkD3Switch 0x0460 |
| #define B16avioGbl_ACLK3_CTRL_clkD3Switch 0x0460 |
| #define LSb32avioGbl_ACLK3_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_ACLK3_CTRL_clkD3Switch 1 |
| #define bavioGbl_ACLK3_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_ACLK3_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_ACLK3_CTRL_clkSel 0x0460 |
| #define B16avioGbl_ACLK3_CTRL_clkSel 0x0460 |
| #define LSb32avioGbl_ACLK3_CTRL_clkSel 2 |
| #define LSb16avioGbl_ACLK3_CTRL_clkSel 2 |
| #define bavioGbl_ACLK3_CTRL_clkSel 3 |
| #define MSK32avioGbl_ACLK3_CTRL_clkSel 0x0000001C |
| #define avioGbl_ACLK3_CTRL_clkSel_d2 0x1 |
| #define avioGbl_ACLK3_CTRL_clkSel_d4 0x2 |
| #define avioGbl_ACLK3_CTRL_clkSel_d6 0x3 |
| #define avioGbl_ACLK3_CTRL_clkSel_d8 0x4 |
| #define avioGbl_ACLK3_CTRL_clkSel_d12 0x5 |
| #define RA_avioGbl_ACLK4_CTRL 0x0464 |
| #define BA_avioGbl_ACLK4_CTRL_clkSwitch 0x0464 |
| #define B16avioGbl_ACLK4_CTRL_clkSwitch 0x0464 |
| #define LSb32avioGbl_ACLK4_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_ACLK4_CTRL_clkSwitch 0 |
| #define bavioGbl_ACLK4_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_ACLK4_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_ACLK4_CTRL_clkD3Switch 0x0464 |
| #define B16avioGbl_ACLK4_CTRL_clkD3Switch 0x0464 |
| #define LSb32avioGbl_ACLK4_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_ACLK4_CTRL_clkD3Switch 1 |
| #define bavioGbl_ACLK4_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_ACLK4_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_ACLK4_CTRL_clkSel 0x0464 |
| #define B16avioGbl_ACLK4_CTRL_clkSel 0x0464 |
| #define LSb32avioGbl_ACLK4_CTRL_clkSel 2 |
| #define LSb16avioGbl_ACLK4_CTRL_clkSel 2 |
| #define bavioGbl_ACLK4_CTRL_clkSel 3 |
| #define MSK32avioGbl_ACLK4_CTRL_clkSel 0x0000001C |
| #define avioGbl_ACLK4_CTRL_clkSel_d2 0x1 |
| #define avioGbl_ACLK4_CTRL_clkSel_d4 0x2 |
| #define avioGbl_ACLK4_CTRL_clkSel_d6 0x3 |
| #define avioGbl_ACLK4_CTRL_clkSel_d8 0x4 |
| #define avioGbl_ACLK4_CTRL_clkSel_d12 0x5 |
| #define RA_avioGbl_DRM_VCLK_CTRL 0x0468 |
| #define BA_avioGbl_DRM_VCLK_CTRL_clkSwitch 0x0468 |
| #define B16avioGbl_DRM_VCLK_CTRL_clkSwitch 0x0468 |
| #define LSb32avioGbl_DRM_VCLK_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_DRM_VCLK_CTRL_clkSwitch 0 |
| #define bavioGbl_DRM_VCLK_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_DRM_VCLK_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_DRM_VCLK_CTRL_clkD3Switch 0x0468 |
| #define B16avioGbl_DRM_VCLK_CTRL_clkD3Switch 0x0468 |
| #define LSb32avioGbl_DRM_VCLK_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_DRM_VCLK_CTRL_clkD3Switch 1 |
| #define bavioGbl_DRM_VCLK_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_DRM_VCLK_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_DRM_VCLK_CTRL_clkSel 0x0468 |
| #define B16avioGbl_DRM_VCLK_CTRL_clkSel 0x0468 |
| #define LSb32avioGbl_DRM_VCLK_CTRL_clkSel 2 |
| #define LSb16avioGbl_DRM_VCLK_CTRL_clkSel 2 |
| #define bavioGbl_DRM_VCLK_CTRL_clkSel 3 |
| #define MSK32avioGbl_DRM_VCLK_CTRL_clkSel 0x0000001C |
| #define avioGbl_DRM_VCLK_CTRL_clkSel_d2 0x1 |
| #define avioGbl_DRM_VCLK_CTRL_clkSel_d4 0x2 |
| #define avioGbl_DRM_VCLK_CTRL_clkSel_d6 0x3 |
| #define avioGbl_DRM_VCLK_CTRL_clkSel_d8 0x4 |
| #define avioGbl_DRM_VCLK_CTRL_clkSel_d12 0x5 |
| #define BA_avioGbl_DRM_VCLK_CTRL_clkEn 0x0468 |
| #define B16avioGbl_DRM_VCLK_CTRL_clkEn 0x0468 |
| #define LSb32avioGbl_DRM_VCLK_CTRL_clkEn 5 |
| #define LSb16avioGbl_DRM_VCLK_CTRL_clkEn 5 |
| #define bavioGbl_DRM_VCLK_CTRL_clkEn 1 |
| #define MSK32avioGbl_DRM_VCLK_CTRL_clkEn 0x00000020 |
| #define RA_avioGbl_HDMIRX_VCLK_CTRL 0x046C |
| #define BA_avioGbl_HDMIRX_VCLK_CTRL_clkSwitch 0x046C |
| #define B16avioGbl_HDMIRX_VCLK_CTRL_clkSwitch 0x046C |
| #define LSb32avioGbl_HDMIRX_VCLK_CTRL_clkSwitch 0 |
| #define LSb16avioGbl_HDMIRX_VCLK_CTRL_clkSwitch 0 |
| #define bavioGbl_HDMIRX_VCLK_CTRL_clkSwitch 1 |
| #define MSK32avioGbl_HDMIRX_VCLK_CTRL_clkSwitch 0x00000001 |
| #define BA_avioGbl_HDMIRX_VCLK_CTRL_clkD3Switch 0x046C |
| #define B16avioGbl_HDMIRX_VCLK_CTRL_clkD3Switch 0x046C |
| #define LSb32avioGbl_HDMIRX_VCLK_CTRL_clkD3Switch 1 |
| #define LSb16avioGbl_HDMIRX_VCLK_CTRL_clkD3Switch 1 |
| #define bavioGbl_HDMIRX_VCLK_CTRL_clkD3Switch 1 |
| #define MSK32avioGbl_HDMIRX_VCLK_CTRL_clkD3Switch 0x00000002 |
| #define BA_avioGbl_HDMIRX_VCLK_CTRL_clkSel 0x046C |
| #define B16avioGbl_HDMIRX_VCLK_CTRL_clkSel 0x046C |
| #define LSb32avioGbl_HDMIRX_VCLK_CTRL_clkSel 2 |
| #define LSb16avioGbl_HDMIRX_VCLK_CTRL_clkSel 2 |
| #define bavioGbl_HDMIRX_VCLK_CTRL_clkSel 3 |
| #define MSK32avioGbl_HDMIRX_VCLK_CTRL_clkSel 0x0000001C |
| #define avioGbl_HDMIRX_VCLK_CTRL_clkSel_d2 0x1 |
| #define avioGbl_HDMIRX_VCLK_CTRL_clkSel_d4 0x2 |
| #define avioGbl_HDMIRX_VCLK_CTRL_clkSel_d6 0x3 |
| #define avioGbl_HDMIRX_VCLK_CTRL_clkSel_d8 0x4 |
| #define avioGbl_HDMIRX_VCLK_CTRL_clkSel_d12 0x5 |
| #define BA_avioGbl_HDMIRX_VCLK_CTRL_clkEn 0x046C |
| #define B16avioGbl_HDMIRX_VCLK_CTRL_clkEn 0x046C |
| #define LSb32avioGbl_HDMIRX_VCLK_CTRL_clkEn 5 |
| #define LSb16avioGbl_HDMIRX_VCLK_CTRL_clkEn 5 |
| #define bavioGbl_HDMIRX_VCLK_CTRL_clkEn 1 |
| #define MSK32avioGbl_HDMIRX_VCLK_CTRL_clkEn 0x00000020 |
| #define RA_avioGbl_SWRST_CTRL 0x0470 |
| #define BA_avioGbl_SWRST_CTRL_audio0SyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_audio0SyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_audio0SyncRstn 0 |
| #define LSb16avioGbl_SWRST_CTRL_audio0SyncRstn 0 |
| #define bavioGbl_SWRST_CTRL_audio0SyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_audio0SyncRstn 0x00000001 |
| #define BA_avioGbl_SWRST_CTRL_audio1SyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_audio1SyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_audio1SyncRstn 1 |
| #define LSb16avioGbl_SWRST_CTRL_audio1SyncRstn 1 |
| #define bavioGbl_SWRST_CTRL_audio1SyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_audio1SyncRstn 0x00000002 |
| #define BA_avioGbl_SWRST_CTRL_audio2SyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_audio2SyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_audio2SyncRstn 2 |
| #define LSb16avioGbl_SWRST_CTRL_audio2SyncRstn 2 |
| #define bavioGbl_SWRST_CTRL_audio2SyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_audio2SyncRstn 0x00000004 |
| #define BA_avioGbl_SWRST_CTRL_audio3SyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_audio3SyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_audio3SyncRstn 3 |
| #define LSb16avioGbl_SWRST_CTRL_audio3SyncRstn 3 |
| #define bavioGbl_SWRST_CTRL_audio3SyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_audio3SyncRstn 0x00000008 |
| #define BA_avioGbl_SWRST_CTRL_audio4SyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_audio4SyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_audio4SyncRstn 4 |
| #define LSb16avioGbl_SWRST_CTRL_audio4SyncRstn 4 |
| #define bavioGbl_SWRST_CTRL_audio4SyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_audio4SyncRstn 0x00000010 |
| #define BA_avioGbl_SWRST_CTRL_audioHdSyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_audioHdSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_audioHdSyncRstn 5 |
| #define LSb16avioGbl_SWRST_CTRL_audioHdSyncRstn 5 |
| #define bavioGbl_SWRST_CTRL_audioHdSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_audioHdSyncRstn 0x00000020 |
| #define BA_avioGbl_SWRST_CTRL_spdifRxSyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_spdifRxSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_spdifRxSyncRstn 6 |
| #define LSb16avioGbl_SWRST_CTRL_spdifRxSyncRstn 6 |
| #define bavioGbl_SWRST_CTRL_spdifRxSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_spdifRxSyncRstn 0x00000040 |
| #define BA_avioGbl_SWRST_CTRL_vppSyncRstn 0x0470 |
| #define B16avioGbl_SWRST_CTRL_vppSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_vppSyncRstn 7 |
| #define LSb16avioGbl_SWRST_CTRL_vppSyncRstn 7 |
| #define bavioGbl_SWRST_CTRL_vppSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_vppSyncRstn 0x00000080 |
| #define BA_avioGbl_SWRST_CTRL_eddcSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_eddcSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_eddcSyncRstn 8 |
| #define LSb16avioGbl_SWRST_CTRL_eddcSyncRstn 8 |
| #define bavioGbl_SWRST_CTRL_eddcSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_eddcSyncRstn 0x00000100 |
| #define BA_avioGbl_SWRST_CTRL_appSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_appSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_appSyncRstn 9 |
| #define LSb16avioGbl_SWRST_CTRL_appSyncRstn 9 |
| #define bavioGbl_SWRST_CTRL_appSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_appSyncRstn 0x00000200 |
| #define BA_avioGbl_SWRST_CTRL_biuSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_biuSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_biuSyncRstn 10 |
| #define LSb16avioGbl_SWRST_CTRL_biuSyncRstn 10 |
| #define bavioGbl_SWRST_CTRL_biuSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_biuSyncRstn 0x00000400 |
| #define BA_avioGbl_SWRST_CTRL_CarDeintSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_CarDeintSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_CarDeintSyncRstn 11 |
| #define LSb16avioGbl_SWRST_CTRL_CarDeintSyncRstn 11 |
| #define bavioGbl_SWRST_CTRL_CarDeintSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_CarDeintSyncRstn 0x00000800 |
| #define BA_avioGbl_SWRST_CTRL_hdmiRxSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_hdmiRxSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_hdmiRxSyncRstn 12 |
| #define LSb16avioGbl_SWRST_CTRL_hdmiRxSyncRstn 12 |
| #define bavioGbl_SWRST_CTRL_hdmiRxSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_hdmiRxSyncRstn 0x00001000 |
| #define BA_avioGbl_SWRST_CTRL_fpllSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_fpllSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_fpllSyncRstn 13 |
| #define LSb16avioGbl_SWRST_CTRL_fpllSyncRstn 13 |
| #define bavioGbl_SWRST_CTRL_fpllSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_fpllSyncRstn 0x00002000 |
| #define BA_avioGbl_SWRST_CTRL_vipPipeSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_vipPipeSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_vipPipeSyncRstn 14 |
| #define LSb16avioGbl_SWRST_CTRL_vipPipeSyncRstn 14 |
| #define bavioGbl_SWRST_CTRL_vipPipeSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_vipPipeSyncRstn 0x00004000 |
| #define BA_avioGbl_SWRST_CTRL_scl1dSbSyncRstn 0x0471 |
| #define B16avioGbl_SWRST_CTRL_scl1dSbSyncRstn 0x0470 |
| #define LSb32avioGbl_SWRST_CTRL_scl1dSbSyncRstn 15 |
| #define LSb16avioGbl_SWRST_CTRL_scl1dSbSyncRstn 15 |
| #define bavioGbl_SWRST_CTRL_scl1dSbSyncRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_scl1dSbSyncRstn 0x00008000 |
| #define BA_avioGbl_SWRST_CTRL_mclkspfClkRstn 0x0472 |
| #define B16avioGbl_SWRST_CTRL_mclkspfClkRstn 0x0472 |
| #define LSb32avioGbl_SWRST_CTRL_mclkspfClkRstn 16 |
| #define LSb16avioGbl_SWRST_CTRL_mclkspfClkRstn 0 |
| #define bavioGbl_SWRST_CTRL_mclkspfClkRstn 1 |
| #define MSK32avioGbl_SWRST_CTRL_mclkspfClkRstn 0x00010000 |
| #define RA_avioGbl_SWPDWN_CTRL 0x0474 |
| #define BA_avioGbl_SWPDWN_CTRL_hdmirx_PDWN 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_hdmirx_PDWN 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_hdmirx_PDWN 0 |
| #define LSb16avioGbl_SWPDWN_CTRL_hdmirx_PDWN 0 |
| #define bavioGbl_SWPDWN_CTRL_hdmirx_PDWN 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_hdmirx_PDWN 0x00000001 |
| #define BA_avioGbl_SWPDWN_CTRL_hdmitx_PDWN 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_hdmitx_PDWN 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_hdmitx_PDWN 1 |
| #define LSb16avioGbl_SWPDWN_CTRL_hdmitx_PDWN 1 |
| #define bavioGbl_SWPDWN_CTRL_hdmitx_PDWN 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_hdmitx_PDWN 0x00000002 |
| #define BA_avioGbl_SWPDWN_CTRL_aio64bDhub_PDWN 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_aio64bDhub_PDWN 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_aio64bDhub_PDWN 2 |
| #define LSb16avioGbl_SWPDWN_CTRL_aio64bDhub_PDWN 2 |
| #define bavioGbl_SWPDWN_CTRL_aio64bDhub_PDWN 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_aio64bDhub_PDWN 0x00000004 |
| #define BA_avioGbl_SWPDWN_CTRL_vpp128bDhub_PDWN 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_vpp128bDhub_PDWN 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_vpp128bDhub_PDWN 3 |
| #define LSb16avioGbl_SWPDWN_CTRL_vpp128bDhub_PDWN 3 |
| #define bavioGbl_SWPDWN_CTRL_vpp128bDhub_PDWN 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_vpp128bDhub_PDWN 0x00000008 |
| #define BA_avioGbl_SWPDWN_CTRL_hdmirx_PDLVMC 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_hdmirx_PDLVMC 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_hdmirx_PDLVMC 4 |
| #define LSb16avioGbl_SWPDWN_CTRL_hdmirx_PDLVMC 4 |
| #define bavioGbl_SWPDWN_CTRL_hdmirx_PDLVMC 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_hdmirx_PDLVMC 0x00000010 |
| #define BA_avioGbl_SWPDWN_CTRL_hdmitx_PDLVMC 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_hdmitx_PDLVMC 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_hdmitx_PDLVMC 5 |
| #define LSb16avioGbl_SWPDWN_CTRL_hdmitx_PDLVMC 5 |
| #define bavioGbl_SWPDWN_CTRL_hdmitx_PDLVMC 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_hdmitx_PDLVMC 0x00000020 |
| #define BA_avioGbl_SWPDWN_CTRL_aio64bDhub_PDLVMC 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_aio64bDhub_PDLVMC 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_aio64bDhub_PDLVMC 6 |
| #define LSb16avioGbl_SWPDWN_CTRL_aio64bDhub_PDLVMC 6 |
| #define bavioGbl_SWPDWN_CTRL_aio64bDhub_PDLVMC 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_aio64bDhub_PDLVMC 0x00000040 |
| #define BA_avioGbl_SWPDWN_CTRL_vpp128bDhub_PDLVMC 0x0474 |
| #define B16avioGbl_SWPDWN_CTRL_vpp128bDhub_PDLVMC 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_vpp128bDhub_PDLVMC 7 |
| #define LSb16avioGbl_SWPDWN_CTRL_vpp128bDhub_PDLVMC 7 |
| #define bavioGbl_SWPDWN_CTRL_vpp128bDhub_PDLVMC 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_vpp128bDhub_PDLVMC 0x00000080 |
| #define BA_avioGbl_SWPDWN_CTRL_hdmirx_PDFVSSM 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_hdmirx_PDFVSSM 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_hdmirx_PDFVSSM 8 |
| #define LSb16avioGbl_SWPDWN_CTRL_hdmirx_PDFVSSM 8 |
| #define bavioGbl_SWPDWN_CTRL_hdmirx_PDFVSSM 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_hdmirx_PDFVSSM 0x00000100 |
| #define BA_avioGbl_SWPDWN_CTRL_hdmitx_PDFVSSM 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_hdmitx_PDFVSSM 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_hdmitx_PDFVSSM 9 |
| #define LSb16avioGbl_SWPDWN_CTRL_hdmitx_PDFVSSM 9 |
| #define bavioGbl_SWPDWN_CTRL_hdmitx_PDFVSSM 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_hdmitx_PDFVSSM 0x00000200 |
| #define BA_avioGbl_SWPDWN_CTRL_aio64bDhub_PDFVSSM 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_aio64bDhub_PDFVSSM 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_aio64bDhub_PDFVSSM 10 |
| #define LSb16avioGbl_SWPDWN_CTRL_aio64bDhub_PDFVSSM 10 |
| #define bavioGbl_SWPDWN_CTRL_aio64bDhub_PDFVSSM 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_aio64bDhub_PDFVSSM 0x00000400 |
| #define BA_avioGbl_SWPDWN_CTRL_vpp128bDhub_PDFVSSM 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_vpp128bDhub_PDFVSSM 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_vpp128bDhub_PDFVSSM 11 |
| #define LSb16avioGbl_SWPDWN_CTRL_vpp128bDhub_PDFVSSM 11 |
| #define bavioGbl_SWPDWN_CTRL_vpp128bDhub_PDFVSSM 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_vpp128bDhub_PDFVSSM 0x00000800 |
| #define BA_avioGbl_SWPDWN_CTRL_axiMeter0_PDWN 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_axiMeter0_PDWN 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_axiMeter0_PDWN 12 |
| #define LSb16avioGbl_SWPDWN_CTRL_axiMeter0_PDWN 12 |
| #define bavioGbl_SWPDWN_CTRL_axiMeter0_PDWN 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_axiMeter0_PDWN 0x00001000 |
| #define BA_avioGbl_SWPDWN_CTRL_axiMeter0_PDLVMC 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_axiMeter0_PDLVMC 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_axiMeter0_PDLVMC 13 |
| #define LSb16avioGbl_SWPDWN_CTRL_axiMeter0_PDLVMC 13 |
| #define bavioGbl_SWPDWN_CTRL_axiMeter0_PDLVMC 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_axiMeter0_PDLVMC 0x00002000 |
| #define BA_avioGbl_SWPDWN_CTRL_axiMeter0_PDFVSSM 0x0475 |
| #define B16avioGbl_SWPDWN_CTRL_axiMeter0_PDFVSSM 0x0474 |
| #define LSb32avioGbl_SWPDWN_CTRL_axiMeter0_PDFVSSM 14 |
| #define LSb16avioGbl_SWPDWN_CTRL_axiMeter0_PDFVSSM 14 |
| #define bavioGbl_SWPDWN_CTRL_axiMeter0_PDFVSSM 1 |
| #define MSK32avioGbl_SWPDWN_CTRL_axiMeter0_PDFVSSM 0x00004000 |
| #define RA_avioGbl_HDMI_CLK_EN 0x0478 |
| #define BA_avioGbl_HDMI_CLK_EN_HdmiTx 0x0478 |
| #define B16avioGbl_HDMI_CLK_EN_HdmiTx 0x0478 |
| #define LSb32avioGbl_HDMI_CLK_EN_HdmiTx 0 |
| #define LSb16avioGbl_HDMI_CLK_EN_HdmiTx 0 |
| #define bavioGbl_HDMI_CLK_EN_HdmiTx 1 |
| #define MSK32avioGbl_HDMI_CLK_EN_HdmiTx 0x00000001 |
| #define BA_avioGbl_HDMI_CLK_EN_EddcMaster 0x0478 |
| #define B16avioGbl_HDMI_CLK_EN_EddcMaster 0x0478 |
| #define LSb32avioGbl_HDMI_CLK_EN_EddcMaster 1 |
| #define LSb16avioGbl_HDMI_CLK_EN_EddcMaster 1 |
| #define bavioGbl_HDMI_CLK_EN_EddcMaster 1 |
| #define MSK32avioGbl_HDMI_CLK_EN_EddcMaster 0x00000002 |
| #define RA_avioGbl_RWTC_31to0 0x047C |
| #define BA_avioGbl_RWTC_31to0_value 0x047C |
| #define B16avioGbl_RWTC_31to0_value 0x047C |
| #define LSb32avioGbl_RWTC_31to0_value 0 |
| #define LSb16avioGbl_RWTC_31to0_value 0 |
| #define bavioGbl_RWTC_31to0_value 32 |
| #define MSK32avioGbl_RWTC_31to0_value 0xFFFFFFFF |
| #define RA_avioGbl_RWTC_57to32 0x0480 |
| #define BA_avioGbl_RWTC_57to32_value 0x0480 |
| #define B16avioGbl_RWTC_57to32_value 0x0480 |
| #define LSb32avioGbl_RWTC_57to32_value 0 |
| #define LSb16avioGbl_RWTC_57to32_value 0 |
| #define bavioGbl_RWTC_57to32_value 26 |
| #define MSK32avioGbl_RWTC_57to32_value 0x03FFFFFF |
| #define RA_avioGbl_VIPPIPECLK_CTRL 0x0484 |
| #define BA_avioGbl_VIPPIPECLK_CTRL_vipClkSel 0x0484 |
| #define B16avioGbl_VIPPIPECLK_CTRL_vipClkSel 0x0484 |
| #define LSb32avioGbl_VIPPIPECLK_CTRL_vipClkSel 0 |
| #define LSb16avioGbl_VIPPIPECLK_CTRL_vipClkSel 0 |
| #define bavioGbl_VIPPIPECLK_CTRL_vipClkSel 1 |
| #define MSK32avioGbl_VIPPIPECLK_CTRL_vipClkSel 0x00000001 |
| #define RA_avioGbl_DHUB64_CTRL 0x0488 |
| #define BA_avioGbl_DHUB64_CTRL_aRCache_aio64bDhub 0x0488 |
| #define B16avioGbl_DHUB64_CTRL_aRCache_aio64bDhub 0x0488 |
| #define LSb32avioGbl_DHUB64_CTRL_aRCache_aio64bDhub 0 |
| #define LSb16avioGbl_DHUB64_CTRL_aRCache_aio64bDhub 0 |
| #define bavioGbl_DHUB64_CTRL_aRCache_aio64bDhub 4 |
| #define MSK32avioGbl_DHUB64_CTRL_aRCache_aio64bDhub 0x0000000F |
| #define BA_avioGbl_DHUB64_CTRL_aWCache_aio64bDhub 0x0488 |
| #define B16avioGbl_DHUB64_CTRL_aWCache_aio64bDhub 0x0488 |
| #define LSb32avioGbl_DHUB64_CTRL_aWCache_aio64bDhub 4 |
| #define LSb16avioGbl_DHUB64_CTRL_aWCache_aio64bDhub 4 |
| #define bavioGbl_DHUB64_CTRL_aWCache_aio64bDhub 3 |
| #define MSK32avioGbl_DHUB64_CTRL_aWCache_aio64bDhub 0x00000070 |
| |
| #define w32avioGbl_HDMIRX_VCLK_CTRL {\ |
| UNSG32 uHDMIRX_VCLK_CTRL_clkSwitch : 1;\ |
| UNSG32 uHDMIRX_VCLK_CTRL_clkD3Switch : 1;\ |
| UNSG32 uHDMIRX_VCLK_CTRL_clkSel : 3;\ |
| UNSG32 uHDMIRX_VCLK_CTRL_clkEn : 1;\ |
| UNSG32 RSVDx46C_b6 : 26;\ |
| } |
| |
| typedef union T32avioGbl_HDMIRX_VCLK_CTRL |
| { UNSG32 u32; |
| struct w32avioGbl_HDMIRX_VCLK_CTRL; |
| } T32avioGbl_HDMIRX_VCLK_CTRL; |
| |
| typedef struct SIE_ADAC_ctrl { |
| /////////////////////////////////////////////////////////// |
| #define GET32ADAC_ctrl_DAC_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32ADAC_ctrl_DAC_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ADAC_ctrl_DAC_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16ADAC_ctrl_DAC_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ADAC_ctrl_MODE_SEL(r32) _BFGET_(r32, 1, 1) |
| #define SET32ADAC_ctrl_MODE_SEL(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16ADAC_ctrl_MODE_SEL(r16) _BFGET_(r16, 1, 1) |
| #define SET16ADAC_ctrl_MODE_SEL(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32ADAC_ctrl_RESET(r32) _BFGET_(r32, 2, 2) |
| #define SET32ADAC_ctrl_RESET(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16ADAC_ctrl_RESET(r16) _BFGET_(r16, 2, 2) |
| #define SET16ADAC_ctrl_RESET(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32ADAC_ctrl_SE_EN(r32) _BFGET_(r32, 3, 3) |
| #define SET32ADAC_ctrl_SE_EN(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16ADAC_ctrl_SE_EN(r16) _BFGET_(r16, 3, 3) |
| #define SET16ADAC_ctrl_SE_EN(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32ADAC_ctrl_CP_EN(r32) _BFGET_(r32, 4, 4) |
| #define SET32ADAC_ctrl_CP_EN(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16ADAC_ctrl_CP_EN(r16) _BFGET_(r16, 4, 4) |
| #define SET16ADAC_ctrl_CP_EN(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32ADAC_ctrl_OSR(r32) _BFGET_(r32, 6, 5) |
| #define SET32ADAC_ctrl_OSR(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16ADAC_ctrl_OSR(r16) _BFGET_(r16, 6, 5) |
| #define SET16ADAC_ctrl_OSR(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32ADAC_ctrl_TEST_SEL(r32) _BFGET_(r32, 9, 7) |
| #define SET32ADAC_ctrl_TEST_SEL(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16ADAC_ctrl_TEST_SEL(r16) _BFGET_(r16, 9, 7) |
| #define SET16ADAC_ctrl_TEST_SEL(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define GET32ADAC_ctrl_TEST_EN(r32) _BFGET_(r32,10,10) |
| #define SET32ADAC_ctrl_TEST_EN(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16ADAC_ctrl_TEST_EN(r16) _BFGET_(r16,10,10) |
| #define SET16ADAC_ctrl_TEST_EN(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32ADAC_ctrl_EN_TEST_ADAC(r32) _BFGET_(r32,11,11) |
| #define SET32ADAC_ctrl_EN_TEST_ADAC(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16ADAC_ctrl_EN_TEST_ADAC(r16) _BFGET_(r16,11,11) |
| #define SET16ADAC_ctrl_EN_TEST_ADAC(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32ADAC_ctrl_CP_FREQ_SEL(r32) _BFGET_(r32,13,12) |
| #define SET32ADAC_ctrl_CP_FREQ_SEL(r32,v) _BFSET_(r32,13,12,v) |
| #define GET16ADAC_ctrl_CP_FREQ_SEL(r16) _BFGET_(r16,13,12) |
| #define SET16ADAC_ctrl_CP_FREQ_SEL(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32ADAC_ctrl_CHOP_FREQ_SEL(r32) _BFGET_(r32,15,14) |
| #define SET32ADAC_ctrl_CHOP_FREQ_SEL(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16ADAC_ctrl_CHOP_FREQ_SEL(r16) _BFGET_(r16,15,14) |
| #define SET16ADAC_ctrl_CHOP_FREQ_SEL(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_DAC_EN : 1; |
| UNSG32 u_MODE_SEL : 1; |
| UNSG32 u_RESET : 1; |
| UNSG32 u_SE_EN : 1; |
| UNSG32 u_CP_EN : 1; |
| UNSG32 u_OSR : 2; |
| UNSG32 u_TEST_SEL : 3; |
| UNSG32 u_TEST_EN : 1; |
| UNSG32 u_EN_TEST_ADAC : 1; |
| UNSG32 u_CP_FREQ_SEL : 2; |
| UNSG32 u_CHOP_FREQ_SEL : 2; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32ADAC_ctrl_DAC_RSVD_IN(r32) _BFGET_(r32,19, 0) |
| #define SET32ADAC_ctrl_DAC_RSVD_IN(r32,v) _BFSET_(r32,19, 0,v) |
| |
| #define GET32ADAC_ctrl_TEST_MODE(r32) _BFGET_(r32,20,20) |
| #define SET32ADAC_ctrl_TEST_MODE(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16ADAC_ctrl_TEST_MODE(r16) _BFGET_(r16, 4, 4) |
| #define SET16ADAC_ctrl_TEST_MODE(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| UNSG32 u_DAC_RSVD_IN : 20; |
| UNSG32 u_TEST_MODE : 1; |
| UNSG32 RSVDx4_b21 : 11; |
| /////////////////////////////////////////////////////////// |
| } SIE_ADAC_ctrl; |
| |
| #endif |
| |
