| /* |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * Register address mapping configure file for rom testing code. |
| */ |
| |
| ////// |
| /// don't edit! auto-generated by docc: avio_memmap.h |
| //////////////////////////////////////////////////////////// |
| #ifndef avio_memmap_h |
| #define avio_memmap_h (){} |
| |
| |
| #include "ctypes.h" |
| |
| #pragma pack(1) |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef _DOCC_H_BITOPS_ |
| #define _DOCC_H_BITOPS_ (){} |
| |
| #define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0) |
| #define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb)) |
| #define _bCLRMASK_(b) (~_bSETMASK_(b)) |
| #define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb)) |
| #define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb))) |
| #define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0) |
| |
| #endif |
| |
| |
| |
| ////// |
| /// |
| /// $INTERFACE AVIO_MEMMAP (4,4) |
| /// # # ---------------------------------------------------------- |
| /// : VPP128B_DHUB_REG_BASE 0x0 |
| /// ### |
| /// * Base address of VPP 128 bit DHUB control Registers |
| /// * 256 KB |
| /// ### |
| /// : VPP128B_DHUB_REG_SIZE 0x40000 |
| /// ### |
| /// * Size of VPP 128bit DHUB Registers memory mapping |
| /// ### |
| /// : VPP128B_DHUB_REG_DEC_BIT 0x12 |
| /// ### |
| /// * 256 KB has a 16 bits offset |
| /// ### |
| /// : AIO64B_DHUB_REG_BASE 0x40000 |
| /// ### |
| /// * Base address of AIO 64bit DHUB control Registers |
| /// * 128 KB |
| /// ### |
| /// : AIO64B_DHUB_REG_SIZE 0x20000 |
| /// ### |
| /// * Size of AIO 64bit DHUB Registers memory mapping |
| /// ### |
| /// : AIO64B_DHUB_REG_DEC_BIT 0x11 |
| /// ### |
| /// * 128 KB has a 17 bits offset |
| /// ### |
| /// : VPP_REG_BASE 0x60000 |
| /// ### |
| /// * Base address of Video Post Process control Registers |
| /// * 128 KB |
| /// ### |
| /// : VPP_REG_SIZE 0x20000 |
| /// ### |
| /// * Size of Video Post Process Registers memory mapping |
| /// ### |
| /// : VPP_REG_DEC_BIT 0x11 |
| /// ### |
| /// * 128 KB has a 16 bits offset |
| /// ### |
| /// : AVIO_RESERVED0_REG_BASE 0x80000 |
| /// ### |
| /// * Base address for AVIO Reserved Registers |
| /// * 128 KB |
| /// ### |
| /// : AVIO_RESERVED0_REG_SIZE 0x20000 |
| /// ### |
| /// * Size of AVIO Reserved Registers |
| /// ### |
| /// : AVIO_RESERVED0_REG_DEC_BIT 0x11 |
| /// ### |
| /// * 128 KB has a 17-bit offset |
| /// ### |
| /// : AVIO_GBL_BASE 0xA0000 |
| /// ### |
| /// * Base address for AVIO Global Registers |
| /// * 64 KB |
| /// ### |
| /// : AVIO_GBL_SIZE 0x10000 |
| /// ### |
| /// * Size of AVIO Global Registers |
| /// ### |
| /// : AVIO_GBL_DEC_BIT 0x10 |
| /// ### |
| /// * 64 KB has a 16-bit offset |
| /// ### |
| /// : AVIO_BCM_REG_BASE 0xB0000 |
| /// ### |
| /// * AVIO BCM Registers |
| /// * 64KB |
| /// ### |
| /// : AVIO_BCM_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of AVIO BCM Registers |
| /// ### |
| /// : AVIO_BCM_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : AVIO_I2S_REG_BASE 0xC0000 |
| /// ### |
| /// * Base address for I2S Registers |
| /// * 64 KB |
| /// ### |
| /// : AVIO_I2S_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of I2S Registers memory mapping |
| /// ### |
| /// : AVIO_I2S_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64 KB has a 16 bits offset |
| /// ### |
| /// : AVIO_HDMITX_REG_BASE 0xD0000 |
| /// ### |
| /// * Base address for HDMI-TX registers |
| /// * 16KB |
| /// ### |
| /// : AVIO_HDMITX_REG_SIZE 0x4000 |
| /// ### |
| /// * Size of HDMI-TX registers |
| /// ### |
| /// : AVIO_HDMITX_REG_DEC_BIT 0xE |
| /// ### |
| /// * 16 KB has a 14 bits offset |
| /// ### |
| /// : AVIO_EDDC_REG_BASE 0xD4000 |
| /// ### |
| /// * Base address of EDDC control Registers |
| /// * 16 KB |
| /// ### |
| /// : AVIO_EDDC_REG_SIZE 0x4000 |
| /// ### |
| /// * Size of EDDC registers |
| /// ### |
| /// : AVIO_EDDC_REG_DEC_BIT 0xE |
| /// ### |
| /// * 16 KB has a 14 bits offset |
| /// ### |
| /// : AVIO_HDMIRXPIPE_REG_BASE 0xD8000 |
| /// ### |
| /// * 32KB space reserved |
| /// * 32KB |
| /// ### |
| /// : AVIO_HDMIRXPIPE_REG_SIZE 0x8000 |
| /// ### |
| /// * Size of reserved1 registers |
| /// ### |
| /// : AVIO_HDMIRXPIPE_REG_DEC_BIT 0xF |
| /// ### |
| /// * 32 KB has a 15 bits offset |
| /// ### |
| /// : AVIO_HDMIRX_REG_BASE 0xE0000 |
| /// ### |
| /// * 32KB space reserved |
| /// * 32KB |
| /// ### |
| /// : AVIO_HDMIRX_REG_SIZE 0x8000 |
| /// ### |
| /// * Size of reserved2 registers |
| /// ### |
| /// : AVIO_HDMIRX_REG_DEC_BIT 0xF |
| /// ### |
| /// * 32 KB has a 15 bits offset |
| /// ### |
| /// : AVIO_RESERVED3_REG_BASE 0xE8000 |
| /// ### |
| /// * 32KB space reserved |
| /// * 32KB |
| /// ### |
| /// : AVIO_RESERVED3_REG_SIZE 0x8000 |
| /// ### |
| /// * Size of reserved3 registers |
| /// ### |
| /// : AVIO_RESERVED3_REG_DEC_BIT 0xF |
| /// ### |
| /// * 32 KB has a 15 bits offset |
| /// ### |
| /// : AVIO_RESERVED4_REG_BASE 0xF0000 |
| /// ### |
| /// * 32KB space reserved |
| /// * 32KB |
| /// ### |
| /// : AVIO_RESERVED4_REG_SIZE 0x8000 |
| /// ### |
| /// * Size of reserved4 registers |
| /// ### |
| /// : AVIO_RESERVED4_REG_DEC_BIT 0xF |
| /// ### |
| /// * 32 KB has a 15 bits offset |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_AVIO_MEMMAP |
| #define h_AVIO_MEMMAP (){} |
| |
| #define AVIO_MEMMAP_VPP128B_DHUB_REG_BASE 0x0 |
| #define AVIO_MEMMAP_VPP128B_DHUB_REG_SIZE 0x40000 |
| #define AVIO_MEMMAP_VPP128B_DHUB_REG_DEC_BIT 0x12 |
| #define AVIO_MEMMAP_AIO64B_DHUB_REG_BASE 0x40000 |
| #define AVIO_MEMMAP_AIO64B_DHUB_REG_SIZE 0x20000 |
| #define AVIO_MEMMAP_AIO64B_DHUB_REG_DEC_BIT 0x11 |
| #define AVIO_MEMMAP_VPP_REG_BASE 0x60000 |
| #define AVIO_MEMMAP_VPP_REG_SIZE 0x20000 |
| #define AVIO_MEMMAP_VPP_REG_DEC_BIT 0x11 |
| #define AVIO_MEMMAP_AVIO_RESERVED0_REG_BASE 0x80000 |
| #define AVIO_MEMMAP_AVIO_RESERVED0_REG_SIZE 0x20000 |
| #define AVIO_MEMMAP_AVIO_RESERVED0_REG_DEC_BIT 0x11 |
| #define AVIO_MEMMAP_AVIO_GBL_BASE 0xA0000 |
| #define AVIO_MEMMAP_AVIO_GBL_SIZE 0x10000 |
| #define AVIO_MEMMAP_AVIO_GBL_DEC_BIT 0x10 |
| #define AVIO_MEMMAP_AVIO_BCM_REG_BASE 0xB0000 |
| #define AVIO_MEMMAP_AVIO_BCM_REG_SIZE 0x10000 |
| #define AVIO_MEMMAP_AVIO_BCM_REG_DEC_BIT 0x10 |
| #define AVIO_MEMMAP_AVIO_I2S_REG_BASE 0xC0000 |
| #define AVIO_MEMMAP_AVIO_I2S_REG_SIZE 0x10000 |
| #define AVIO_MEMMAP_AVIO_I2S_REG_DEC_BIT 0x10 |
| #define AVIO_MEMMAP_AVIO_HDMITX_REG_BASE 0xD0000 |
| #define AVIO_MEMMAP_AVIO_HDMITX_REG_SIZE 0x4000 |
| #define AVIO_MEMMAP_AVIO_HDMITX_REG_DEC_BIT 0xE |
| #define AVIO_MEMMAP_AVIO_EDDC_REG_BASE 0xD4000 |
| #define AVIO_MEMMAP_AVIO_EDDC_REG_SIZE 0x4000 |
| #define AVIO_MEMMAP_AVIO_EDDC_REG_DEC_BIT 0xE |
| #define AVIO_MEMMAP_AVIO_HDMIRXPIPE_REG_BASE 0xD8000 |
| #define AVIO_MEMMAP_AVIO_HDMIRXPIPE_REG_SIZE 0x8000 |
| #define AVIO_MEMMAP_AVIO_HDMIRXPIPE_REG_DEC_BIT 0xF |
| #define AVIO_MEMMAP_AVIO_HDMIRX_REG_BASE 0xE0000 |
| #define AVIO_MEMMAP_AVIO_HDMIRX_REG_SIZE 0x8000 |
| #define AVIO_MEMMAP_AVIO_HDMIRX_REG_DEC_BIT 0xF |
| #define AVIO_MEMMAP_AVIO_RESERVED3_REG_BASE 0xE8000 |
| #define AVIO_MEMMAP_AVIO_RESERVED3_REG_SIZE 0x8000 |
| #define AVIO_MEMMAP_AVIO_RESERVED3_REG_DEC_BIT 0xF |
| #define AVIO_MEMMAP_AVIO_RESERVED4_REG_BASE 0xF0000 |
| #define AVIO_MEMMAP_AVIO_RESERVED4_REG_SIZE 0x8000 |
| #define AVIO_MEMMAP_AVIO_RESERVED4_REG_DEC_BIT 0xF |
| /////////////////////////////////////////////////////////// |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: AVIO_MEMMAP |
| //////////////////////////////////////////////////////////// |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #pragma pack() |
| |
| #endif |
| ////// |
| /// ENDOFFILE: avio_memmap.h |
| //////////////////////////////////////////////////////////// |
| |
