| /* |
| * Copyright (C) 2018 Synaptics Incorporated. All rights reserved. |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND |
| * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, |
| * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY |
| * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE |
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR |
| * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE |
| * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND |
| * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS |
| * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF |
| * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT |
| * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY |
| * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS. |
| */ |
| |
| // |
| // This code initialises the Integrator board (eg REMAP) before calling |
| // TCM Initialization and MMU Initialization if they exist. |
| // this allows scatter loading to relocate code into the TCMs |
| // |
| |
| #ifndef _MMU_64_H_ |
| #define _MMU_64_H_ |
| |
| /* |
| * Basic assumption |
| */ |
| #define ENTRY_SIZE 8 |
| #define PAGE_SIZE 0x1000 |
| |
| #define LEVEL1_BLOCK_SIZE (1 << 30) // 1GB |
| #define LEVEL2_BLOCK_SIZE (1 << 21) // 2MB |
| |
| #define LEVEL1_TABLE_OFFSET 0 |
| #define LEVEL2_TABLE_OFFSET 0x1000 |
| |
| #define VA_BIT_WIDTH (32) // 4GB |
| #define TOTAL_VA_SIZE (1 << VA_BIT_WIDTH) |
| #define MEMORY_ADDR_START (0x00000000) |
| #define MEMORY_ADDR_END (0x40000000) // 1GB |
| #define C_MEMORY_ADDR_START (0x00000000) |
| #define C_MEMORY_ADDR_END (0x18000000) // 384MB |
| #define NC_MEMORY_ADDR_START (0x18000000) |
| #define NC_MEMORY_ADDR_END (0x20000000) // 512MB |
| #define IO_ADDR_START (0xF0000000) |
| #define IO_ADDR_END (0x100000000) // 512MB |
| |
| /* |
| * MAIR flags. |
| */ |
| #define MT_DEVICE_NGNRNE 0 // Device non-Gathering, non-Reordering, No Early write acknowledgement. |
| #define MT_DEVICE_NGNRE 1 // Device non-Gathering, non-Reordering, Early Write Acknowledgement. |
| #define MT_NORMAL_NC 2 // Normal Memory, un-cacheable |
| #define MT_NORMAL_C 3 // Normal Memory, cacheable |
| |
| #define MT_DEVICE_NGNRNE_ATTR 0x00 |
| #define MT_DEVICE_NGNRE_ATTR 0x04 |
| #define MT_NORMAL_NC_ATTR 0x44 |
| #define MT_NORMAL_C_ATTR 0xff |
| |
| #define MAIR_VALUE ((MT_DEVICE_NGNRNE_ATTR << (MT_DEVICE_NGNRNE * 8)) | \ |
| (MT_DEVICE_NGNRE_ATTR << (MT_DEVICE_NGNRE * 8)) | \ |
| (MT_NORMAL_NC_ATTR << (MT_NORMAL_NC * 8)) | \ |
| (MT_NORMAL_C_ATTR << (MT_NORMAL_C * 8))) |
| |
| /* |
| * TCR flags. |
| */ |
| #define VA_BITS (VA_BIT_WIDTH) |
| #define PA_SIZE_4G (0) // 32 bits physical address |
| #define PA_SIZE_64G (1) // 36 bits physical address |
| #define PA_SIZE_1T (2) // 40 bits physical address |
| #define TCR_T0SZ(x) ((64 - (x)) << 0) |
| #define TCR_IRGN_NC (0 << 8) |
| #define TCR_IRGN_WBWA (1 << 8) |
| #define TCR_IRGN_WT (2 << 8) |
| #define TCR_IRGN_WBNWA (3 << 8) |
| #define TCR_IRGN_MASK (3 << 8) |
| #define TCR_ORGN_NC (0 << 10) |
| #define TCR_ORGN_WBWA (1 << 10) |
| #define TCR_ORGN_WT (2 << 10) |
| #define TCR_ORGN_WBNWA (3 << 10) |
| #define TCR_ORGN_MASK (3 << 10) |
| #define TCR_SHARED_NON (0 << 12) |
| #define TCR_SHARED_OUTER (1 << 12) |
| #define TCR_SHARED_INNER (2 << 12) |
| #define TCR_TG0_4K (0 << 14) |
| #define TCR_TG0_64K (1 << 14) |
| #define TCR_TG0_16K (2 << 14) |
| #define TCR_EL2_IPS_BITS(x) ((x) << 16) |
| #define TCR_TBI_IGNORED (1 << 20) |
| |
| /* PTWs cacheable, inner/outer WBWA and non-shareable */ |
| #define TCR_VALUE (TCR_TG0_4K | \ |
| TCR_SHARED_NON | \ |
| TCR_ORGN_WBWA | \ |
| TCR_IRGN_WBWA | \ |
| TCR_T0SZ(VA_BITS) | \ |
| TCR_TBI_IGNORED | \ |
| TCR_EL2_IPS_BITS(PA_SIZE_64G)) |
| |
| /* |
| * SCTLR flags. |
| */ |
| #define SCTLR_M (1 << 0) |
| #define SCTLR_A (1 << 1) |
| #define SCTLR_C (1 << 2) |
| #define SCTLR_I (1 << 12) |
| |
| /* |
| * PAGE description attribute |
| */ |
| #define PDM_NS (0 << 63) |
| #define PDM_AP (0 << 61) // read/write |
| #define PDM_UXN (0 << 60) // unprivilege excutable |
| #define PDM_PXN (0 << 59) // excutable |
| #define PDM_ATTRS (PDM_UXN|PDM_PXN|PDM_AP|PDM_NS|0x3) |
| |
| /* |
| * PAGE attributes |
| */ |
| #define PAGE_UXN (0 << 54) // unprivilege excutable |
| #define PAGE_PXN (0 << 53) // excutable |
| #define PAGE_CONTIGUOUS (1 << 52) // contiguous ttb |
| #define PAGE_AF (1 << 10) |
| #define PAGE_S (3 << 8) // inner shareable |
| #define PAGE_AP (0 << 6) // read/write only for EL1 |
| #define PAGE_NS (0 << 5) |
| #define PAGE_ATTRINX(x) ((x) << 2) |
| #define PAGE_ATTRS(x) (PAGE_UXN|PAGE_PXN|PAGE_CONTIGUOUS|PAGE_AF|PAGE_S|PAGE_AP|PAGE_NS|PAGE_ATTRINX(x)|0x1) |
| |
| #endif //_MMU_64_H_ |