| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2021 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/reset/amlogic,meson-t3-reset.h> |
| #include <dt-bindings/clock/t3-clkc.h> |
| #include <dt-bindings/clock/amlogic,t3-audio-clk.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/gpio/meson-t3-gpio.h> |
| #include <dt-bindings/power/t3-pd.h> |
| #include <dt-bindings/pwm/pwm.h> |
| #include <dt-bindings/pwm/meson.h> |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/input/meson_ir.h> |
| #include <dt-bindings/iio/adc/amlogic-saradc.h> |
| #include "meson-ir-map.dtsi" |
| #include "mesong12a-bifrost.dtsi" |
| / { |
| cpus:cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0:cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| #cooling-cells = <2>; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_DYN_CLK>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_PRE_CLK>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| multi_tables_available; |
| operating-points-v2 = <&cpu_opp_table0>, |
| <&cpu_opp_table1>, |
| <&cpu_opp_table2>, |
| <&cpu_opp_table3>; |
| cpu-supply = <&vddcpu0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <230>; |
| }; |
| |
| CPU1:cpu@1{ |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| #cooling-cells = <2>; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_DYN_CLK>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_PRE_CLK>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| multi_tables_available; |
| operating-points-v2 = <&cpu_opp_table0>, |
| <&cpu_opp_table1>, |
| <&cpu_opp_table2>, |
| <&cpu_opp_table3>; |
| cpu-supply = <&vddcpu0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <230>; |
| }; |
| |
| CPU2:cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| #cooling-cells = <2>; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_DYN_CLK>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_PRE_CLK>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| multi_tables_available; |
| operating-points-v2 = <&cpu_opp_table0>, |
| <&cpu_opp_table1>, |
| <&cpu_opp_table2>, |
| <&cpu_opp_table3>; |
| cpu-supply = <&vddcpu0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <230>; |
| }; |
| |
| CPU3:cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| #cooling-cells = <2>; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_DYN_CLK>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_PRE_CLK>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| multi_tables_available; |
| operating-points-v2 = <&cpu_opp_table0>, |
| <&cpu_opp_table1>, |
| <&cpu_opp_table2>, |
| <&cpu_opp_table3>; |
| cpu-supply = <&vddcpu0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <230>; |
| }; |
| |
| idle-states { |
| entry-method = "arm,psci-0.2"; |
| CPU_SLEEP_0: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0010000>; |
| local-timer-stop; |
| entry-latency-us = <4000>; |
| exit-latency-us = <5000>; |
| min-residency-us = <10000>; |
| }; |
| SYSTEM_SLEEP_0: system-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0000000>; |
| entry-latency-us = <0x3fffffff>; |
| exit-latency-us = <0x40000000>; |
| min-residency-us = <0xffffffff>; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 0xff08>, |
| <GIC_PPI 14 0xff08>, |
| <GIC_PPI 11 0xff08>, |
| <GIC_PPI 10 0xff08>; |
| }; |
| |
| gic: interrupt-controller@fff01000 { |
| compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xfff01000 0 0x1000>, |
| <0x0 0xfff02000 0 0x0100>; |
| interrupts = <GIC_PPI 9 0xf04>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| secmon { |
| compatible = "amlogic,secmon"; |
| memory-region = <&secmon_reserved>; |
| reserve_mem_size = <0x00300000>; |
| in_base_func = <0x82000020>; |
| out_base_func = <0x82000021>; |
| inout_size_func = <0x8200002a>; |
| clear_range = <0x05100000 0x200000>; |
| }; |
| |
| meson_suspend:pm { |
| compatible = "amlogic, pm"; |
| status = "okay"; |
| device_name = "aml_pm"; |
| clr_reboot_mode; /* clr reboot mode in shutdown callback */ |
| reg = <0x0 0xfe010288 0x0 0x4>, /*SYSCTRL_STATUS_REG2*/ |
| <0x0 0xfe0102dc 0x0 0x4>; /*SYSCTRL_STICKY_REG7*/ |
| }; |
| |
| aml_reboot { |
| compatible = "aml, reboot"; |
| status = "okay"; |
| sys_reset = <0x84000009>; |
| sys_poweroff = <0x84000008>; |
| dis_nb_cpus_in_shutdown; |
| }; |
| |
| cma_shrinker: cma_shrinker { |
| compatible = "amlogic, cma-shrinker"; |
| status = "okay"; |
| adj = <0 100 200 250 900 950>; |
| free = <8192 12288 16384 24576 28672 32768>; |
| }; |
| |
| xtal: xtal-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| arm_pmu { |
| compatible = "arm,armv8-pmuv3"; |
| private-interrupts; |
| interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; |
| |
| reg = <0x0 0xff634680 0x0 0x4>; |
| }; |
| |
| ddr_bandwidth { |
| compatible = "amlogic,ddr-bandwidth-t3"; |
| status = "okay"; |
| reg = <0 0xfe036000 0 0x400 |
| 0 0xfe034000 0 0x400 |
| 0 0xfe0a0000 0 0x100>; |
| interrupts = <0 332 IRQ_TYPE_EDGE_RISING |
| 0 336 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "ddr_bandwidth"; |
| }; |
| |
| dmc_monitor { |
| compatible = "amlogic,dmc_monitor-t3"; |
| status = "okay"; |
| reg = <0 0xfe036000 0 0x400 |
| 0 0xfe034000 0 0x400>; |
| reg_base = <0xfe036000>; |
| interrupts = <0 333 IRQ_TYPE_EDGE_RISING |
| 0 337 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pwrdm: power-domains { |
| compatible = "amlogic,t3-power-domain"; |
| #power-domain-cells = <1>; |
| status = "okay"; |
| }; |
| |
| galcore { |
| compatible = "amlogic, galcore"; |
| dev_name = "galcore"; |
| status = "okay"; |
| clocks = <&clkc CLKID_CTS_NNA_AXI_CLK>, |
| <&clkc CLKID_CTS_NNA_CORE_CLK>, |
| <&clkc CLKID_SYS1_PLL>; |
| clock-names = "cts_vipnanoq_axi_clk_composite", |
| "cts_vipnanoq_core_clk_composite", |
| "sys1_pll"; |
| assigned-clocks = <&clkc CLKID_SYS1_PLL>; |
| assigned-clock-rates = <1704000000>; |
| interrupts = <0 59 4>; |
| interrupt-names = "galcore"; |
| power-domains = <&pwrdm PDID_T3_NNA>; |
| reg = <0x0 0xfdb00000 0x0 0x40000 |
| 0x0 0xfe090000 0x0 0x2000 |
| 0x0 0xfe00c0a4 0x0 0x4 |
| 0x0 0xfe00c0a8 0x0 0x4 |
| 0x0 0xfe00c034 0x0 0x4 |
| 0X0 0xfe000220 0X0 0x4>; |
| reg-names = "NN_REG","NN_SRAM","NN_MEM0", |
| "NN_MEM1","NN_RESET","NN_CLK"; |
| nn_power_version = <5>; |
| }; |
| |
| vrtc: rtc@0xfe010288 { |
| compatible = "amlogic,meson-vrtc"; |
| reg = <0x0 0xfe010288 0x0 0x4>; //SYSCTRL_STATUS_REG2 |
| status = "okay"; |
| mboxes = <&mhu_fifo 3>; |
| }; |
| |
| aml_reboot { |
| compatible = "aml, reboot"; |
| sys_reset = <0x84000009>; |
| sys_poweroff = <0x84000008>; |
| dis_nb_cpus_in_shutdown; |
| }; |
| |
| mhu_fifo: mhu@0 { |
| status = "okay"; |
| compatible = "amlogic, meson_mhu_fifo"; |
| reg = <0x0 0xfe006000 0x0 0x1000>, /* mhu wr fifo */ |
| <0x0 0xfe007180 0x0 0x80>, /* mhu set reg */ |
| <0x0 0xfe007200 0x0 0x80>, /* mhu clr reg */ |
| <0x0 0xfe007280 0x0 0x80>, /* mhu sts reg */ |
| <0x0 0xfe007040 0x0 0xc0>; /* mhu irqctrl reg */ |
| interrupts = <0 248 1>; /* irq top */ |
| mbox-irqmax = <64>; |
| mbox-irqctlr = <0>; |
| mbox-nums = <4>; |
| mbox-names = "dsp_dev", |
| "ap_to_dspa", |
| "ao_dev", |
| "ap_to_ao"; |
| mboxes = <&mhu_fifo 0>, |
| <&mhu_fifo 1>, |
| <&mhu_fifo 2>, |
| <&mhu_fifo 3>; |
| mbox-id = <0x0 0x1 0x2 0x3>; |
| mbox-wr-rd = <1>; |
| #mbox-cells = <1>; |
| }; |
| |
| vdac { |
| compatible = "amlogic, vdac-t3"; |
| status = "okay"; |
| }; |
| |
| adc: adc { |
| compatible = "amlogic, adc-t3"; |
| status = "okay"; |
| reg = <0x0 0xfe072000 0x0 0x2000/* afe reg base */ |
| 0x0 0xfe008000 0x0 0x2000/* hiu base */ |
| >; |
| }; |
| |
| jtag { |
| compatible = "amlogic, jtag"; |
| status = "okay"; |
| select = "disable"; /* disable/jtag_a/jtag_b */ |
| pinctrl-names="jtag_a_pins"; |
| pinctrl-0=<&jtag_a_pins>; |
| }; |
| |
| hifi4dsp: hifi4dsp { |
| compatible = "amlogic, hifi4dsp"; |
| memory-region = <&dsp_fw_reserved>; |
| reg = <0 0xfe340018 0 0x114>, /*dspa base address*/ |
| <0 0xfe350018 0 0x114>, /*dspb base address*/ |
| <0 0x0 0 0x0>, /*dspa status counter*/ |
| <0 0x0 0 0x0>, /*dspb status counter*/ |
| <0 0x30000000 0 0x80000>; /*dsp shm region*/ |
| dsp-monitor-period-ms = <1000>; |
| reg-names = "dspa_top_reg", "dspb_top_reg"; |
| clocks = <&clkc CLKID_DSPA>; |
| clock-names = "dspa_clk"; |
| dsp-start-mode = <1>; /*0:scpi start mode,1:smc start mode*/ |
| dsp-cnt = <1>; |
| dspaoffset = <0xa0000>; |
| dspboffset = <0x8a0000>; |
| bootlocation = <1>; /*1: boot from DDR, 2: from sram, 3...*/ |
| boot_sram_addr = <0xfff00000>; |
| boot_sram_size = <0x80000>; |
| //dspsrambase = <0xf7100000>; |
| //dspsramsize = <0x100000>; |
| suspend_resume_support = <1 0>; |
| power-domains = <&pwrdm PDID_T3_DSPA>; |
| power-domain-names = "dspa"; |
| status = "okay"; |
| }; |
| |
| vddcpu0: pwm_b-regulator { |
| compatible = "pwm-regulator"; |
| pwms = <&pwm_ab MESON_PWM_1 1500 0>; |
| regulator-name = "vddcpu0"; |
| regulator-min-microvolt = <689000>; |
| regulator-max-microvolt = <1049000>; |
| regulator-always-on; |
| max-duty-cycle = <1500>; |
| /* Voltage Duty-Cycle */ |
| voltage-table = <1049000 0>, |
| <1039000 3>, |
| <1029000 6>, |
| <1019000 9>, |
| <1009000 12>, |
| <999000 14>, |
| <989000 17>, |
| <979000 20>, |
| <969000 23>, |
| <959000 26>, |
| <949000 29>, |
| <939000 31>, |
| <929000 34>, |
| <919000 37>, |
| <909000 40>, |
| <899000 43>, |
| <889000 45>, |
| <879000 48>, |
| <869000 51>, |
| <859000 54>, |
| <849000 56>, |
| <839000 59>, |
| <829000 62>, |
| <819000 65>, |
| <809000 68>, |
| <799000 70>, |
| <789000 73>, |
| <779000 76>, |
| <769000 79>, |
| <759000 81>, |
| <749000 84>, |
| <739000 87>, |
| <729000 89>, |
| <719000 92>, |
| <709000 95>, |
| <699000 98>, |
| <689000 100>; |
| status = "okay"; |
| }; |
| |
| cpu_opp_table0: cpu_opp_table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp00 { |
| opp-hz = /bits/ 64 <100000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp01 { |
| opp-hz = /bits/ 64 <250000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <667000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <799000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <809000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1404000000>; |
| opp-microvolt = <829000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <849000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <879000>; |
| }; |
| opp09 { |
| opp-hz = /bits/ 64 <1704000000>; |
| opp-microvolt = <909000>; |
| }; |
| opp10 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <969000>; |
| }; |
| opp11 { |
| opp-hz = /bits/ 64 <1920000000>; |
| opp-microvolt = <1009000>; |
| }; |
| }; |
| |
| cpu_opp_table1: cpu_opp_table1 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp00 { |
| opp-hz = /bits/ 64 <100000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp01 { |
| opp-hz = /bits/ 64 <250000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <667000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <799000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <809000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1404000000>; |
| opp-microvolt = <829000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <849000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <879000>; |
| }; |
| opp09 { |
| opp-hz = /bits/ 64 <1704000000>; |
| opp-microvolt = <909000>; |
| }; |
| opp10 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <969000>; |
| }; |
| opp11 { |
| opp-hz = /bits/ 64 <1920000000>; |
| opp-microvolt = <1009000>; |
| }; |
| }; |
| |
| cpu_opp_table2: cpu_opp_table2 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp00 { |
| opp-hz = /bits/ 64 <100000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp01 { |
| opp-hz = /bits/ 64 <250000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <667000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <799000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1404000000>; |
| opp-microvolt = <809000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <809000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <829000>; |
| }; |
| opp09 { |
| opp-hz = /bits/ 64 <1704000000>; |
| opp-microvolt = <859000>; |
| }; |
| opp10 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <909000>; |
| }; |
| opp11 { |
| opp-hz = /bits/ 64 <1920000000>; |
| opp-microvolt = <989000>; |
| }; |
| }; |
| |
| cpu_opp_table3: cpu_opp_table3 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp00 { |
| opp-hz = /bits/ 64 <100000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp01 { |
| opp-hz = /bits/ 64 <250000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <667000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <789000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <799000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1404000000>; |
| opp-microvolt = <799000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <809000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <819000>; |
| }; |
| opp09 { |
| opp-hz = /bits/ 64 <1704000000>; |
| opp-microvolt = <839000>; |
| }; |
| opp10 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <879000>; |
| }; |
| opp11 { |
| opp-hz = /bits/ 64 <1920000000>; |
| opp-microvolt = <929000>; |
| }; |
| }; |
| |
| cpufreq-meson { |
| compatible = "amlogic, cpufreq-meson"; |
| status = "okay"; |
| }; |
| |
| saradc: saradc@fe026000 { |
| compatible = "amlogic,meson-g12a-saradc", |
| "amlogic,meson-saradc"; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| clocks = <&xtal>, |
| <&clkc CLKID_SYS_CLK_SAR_ADC>, |
| <&clkc CLKID_SARADC>, |
| <&clkc CLKID_SARADC_SEL>; |
| clock-names = "clkin", "core", |
| "adc_clk", "adc_sel"; |
| interrupts = <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>; |
| reg = <0x00 0xfe026000 0x00 0x48>; |
| }; |
| |
| dolby_fw: dolby_fw { |
| compatible = "amlogic, dolby_fw"; |
| mem_size = <0x100000>; |
| status = "okay"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| apb4: apb4@fe000000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xfe000000 0x0 0x480000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; |
| |
| reset: reset-controller@2000 { |
| compatible = "amlogic,meson-t7-reset"; |
| reg = <0x0 0x2000 0x0 0x98>; |
| #reset-cells = <1>; |
| }; |
| |
| watchdog@2100 { |
| compatible = "amlogic,meson-sc2-wdt"; |
| status = "okay"; |
| /* 0:userspace, 1:kernel */ |
| amlogic,feed_watchdog_mode = <1>; |
| reg = <0x0 0x2100 0x0 0x10>; |
| clocks = <&xtal>; |
| }; |
| |
| clkc: clock-controller { |
| compatible = "amlogic,t3-clkc"; |
| #clock-cells = <1>; |
| reg = <0x0 0x0 0x0 0x230>, |
| <0x0 0x8000 0x0 0x3e4>, |
| <0x0 0xe140 0x0 0x20>; |
| reg-names = "basic", "pll", |
| "cpu_clk"; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| status = "okay"; |
| }; |
| |
| meson_clk_msr@48000 { |
| compatible = "amlogic,meson-t3-clk-measure"; |
| reg = <0x0 0x48000 0x0 0x1c>; |
| }; |
| |
| uart_B: serial@7a000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x7a000 0x0 0x18>; |
| interrupts = <0 169 1>; |
| status = "disabled"; |
| clocks = <&xtal>; |
| clock-names = "clk_uart"; |
| xtal_tick_en = <2>; |
| fifosize = < 64 >; |
| pinctrl-names = "default"; |
| //pinctrl-0 = <&a_uart_pins1>; |
| }; |
| |
| periphs_pinctrl: pinctrl@4000 { |
| compatible = "amlogic,meson-t3-periphs-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio: bank@4000 { |
| reg = <0x0 0x4000 0x0 0x0054>, |
| <0x0 0x40c0 0x0 0x030c>; |
| reg-names = "mux", "gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&periphs_pinctrl 0 0 136>; |
| }; |
| }; |
| |
| analog_pinctrl: analog-pinctrl@4054 { |
| compatible = "amlogic,meson-t3-analog-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| analog_gpio: analog-bank@4054 { |
| reg = <0x0 0x4054 0x0 0x0008>, |
| <0x0 0x43cc 0x0 0x0008>; |
| reg-names = "mux", "gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&analog_pinctrl 0 0 3>; |
| }; |
| }; |
| |
| gpio_intc: interrupt-controller@4080 { |
| compatible = "amlogic,meson-t3-gpio-intc", |
| "amlogic,meson-gpio-intc"; |
| reg = <0x0 0x4080 0x0 0x20>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| amlogic,channel-interrupts = |
| <10 11 12 13 14 15 16 17 18 19 20 21>; |
| }; |
| |
| spicc0: spi@50000 { |
| compatible = "amlogic,meson-g12-spicc"; |
| reg = <0x0 0x50000 0x0 0x44>; |
| interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_SYS_CLK_SPICC0>, |
| <&clkc CLKID_SPICC0>; |
| clock-names = "core", "async"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&pwrdm PDID_T3_SPICC0>; |
| status = "disabled"; |
| }; |
| |
| spicc1: spi@52000 { |
| compatible = "amlogic,meson-g12-spicc"; |
| reg = <0x0 0x52000 0x0 0x44>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_SYS_CLK_SPICC1>, |
| <&clkc CLKID_SPICC1>; |
| clock-names = "core", "async"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&pwrdm PDID_T3_SPICC1>; |
| status = "disabled"; |
| }; |
| |
| spicc2: spi@54000 { |
| compatible = "amlogic,meson-g12-spicc"; |
| reg = <0x0 0x54000 0x0 0x44>; |
| interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_SYS_CLK_SPICC2>, |
| <&clkc CLKID_SPICC2>; |
| clock-names = "core", "async"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&pwrdm PDID_T3_SPICC2>; |
| status = "disabled"; |
| }; |
| |
| spifc: spi@56000 { |
| compatible = "amlogic,meson-spifc"; |
| status = "disabled"; |
| reg = <0x0 0x56000 0x0 0x80>; |
| clock-names = "default"; |
| clocks = <&clkc CLKID_SYS_CLK_SPIFC>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spifc_all_pins>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| spi-nor@0 { |
| compatible = "jedec,spi-nor"; |
| status = "disabled"; |
| reg = <0>; |
| spi-max-frequency = <16000000>; |
| }; |
| }; |
| |
| pwm_ab: pwm@58000 { |
| compatible = "amlogic,meson-v2-pwm"; |
| reg = <0x0 0x58000 0x0 0x24>; |
| #pwm-cells = <3>; |
| clocks = <&clkc CLKID_PWM_A>, |
| <&clkc CLKID_PWM_B>; |
| clock-names = "clkin0", "clkin1"; |
| status = "okay"; |
| }; |
| |
| pwm_cd: pwm@5a000 { |
| compatible = "amlogic,meson-v2-pwm"; |
| reg = <0x0 0x5a000 0x0 0x24>; |
| #pwm-cells = <3>; |
| clocks = <&clkc CLKID_PWM_C>, |
| <&clkc CLKID_PWM_D>; |
| clock-names = "clkin0", "clkin1"; |
| status = "disabled"; |
| }; |
| |
| pwm_ef: pwm@5c000 { |
| compatible = "amlogic,meson-v2-pwm"; |
| reg = <0x0 0x5c000 0x0 0x24>; |
| #pwm-cells = <3>; |
| clocks = <&clkc CLKID_PWM_E>, |
| <&clkc CLKID_PWM_F>; |
| clock-names = "clkin0", "clkin1"; |
| status = "disabled"; |
| }; |
| |
| pwm_gh: pwm@5e000 { |
| compatible = "amlogic,meson-v2-pwm"; |
| reg = <0x0 0x5e000 0x0 0x24>; |
| #pwm-cells = <3>; |
| clocks = <&clkc CLKID_PWM_G>, |
| <&clkc CLKID_PWM_H>; |
| clock-names = "clkin0", "clkin1"; |
| status = "disabled"; |
| }; |
| |
| pwm_ij: pwm@60000 { |
| compatible = "amlogic,meson-v2-pwm"; |
| reg = <0x0 0x60000 0x0 0x24>; |
| #pwm-cells = <3>; |
| clocks = <&clkc CLKID_PWM_I>, |
| <&clkc CLKID_PWM_J>; |
| clock-names = "clkin0", "clkin1"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@66000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x66000 0x0 0x48>; |
| interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_SYS_CLK_I2C_M_A>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@68000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x68000 0x0 0x48>; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_SYS_CLK_I2C_M_B>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@6a000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x6a000 0x0 0x48>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_SYS_CLK_I2C_M_C>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@6c000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x6c000 0x0 0x48>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_SYS_CLK_I2C_M_D>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@6e000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x6e000 0x0 0x48>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_SYS_CLK_I2C_M_E>; |
| status = "disabled"; |
| }; |
| |
| ir: ir@8000 { |
| compatible = "amlogic, meson-ir"; |
| reg = <0x0 0x84040 0x0 0xA4>, |
| <0x0 0x84000 0x0 0x20>; |
| status = "disabled"; |
| protocol = <REMOTE_TYPE_NEC>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; |
| map = <&custom_maps>; |
| max_frame_time = <200>; |
| }; |
| |
| irblaster: meson-irblaster@fe08410c { |
| compatible = "amlogic, meson_irblaster"; |
| status = "okay"; |
| reg = <0x0 0x8410c 0x0 0x10>; |
| #irblaster-cells = <2>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; |
| //pinctrl-names = "default"; |
| //pinctrl-0 = <&irblaster_pins2>; |
| }; |
| |
| eth_phy: mdio-multiplexer@28000 { |
| compatible = "amlogic,g12a-mdio-mux"; |
| reg = <0x0 0x28000 0x0 0xa4>; |
| |
| clocks = <&clkc CLKID_SYS_CLK_ETHPHY>, |
| <&xtal>, |
| <&clkc CLKID_MPLL_50M>; |
| clock-names = "pclk", "clkin0", "clkin1"; |
| mdio-parent-bus = <&mdio0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enet_type = <5>; |
| tx_amp_src = <0xFE010330>; |
| |
| ext_mdio: mdio@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| int_mdio: mdio@1 { |
| reg = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| internal_ephy: ethernet_phy@8 { |
| compatible = "ethernet-phy-id0180.3301", |
| "ethernet-phy-ieee802.3-c22"; |
| interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <8>; |
| max-speed = <100>; |
| }; |
| }; |
| }; |
| |
| cpu_version { |
| compatible = "amlogic,meson-gx-ao-secure", "syscon"; |
| reg=<0x0 0x10220 0x0 0x140>; |
| }; |
| }; |
| |
| ethmac: ethernet@fdc00000 { |
| compatible = "amlogic,meson-axg-dwmac", |
| "snps,dwmac-3.70a", |
| "snps,dwmac"; |
| reg = <0x0 0xfdc00000 0x0 0x10000>, |
| <0x0 0xfe024000 0x0 0x8>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| power-domains = <&pwrdm PDID_T3_ETH>; |
| clocks = <&clkc CLKID_SYS_CLK_ETH>, |
| <&clkc CLKID_FCLK_DIV2>, |
| <&clkc CLKID_MPLL2>; |
| clock-names = "stmmaceth", "clkin0", "clkin1"; |
| rx-fifo-depth = <4096>; |
| tx-fifo-depth = <2048>; |
| /*1:inphy; 2:exphy;*/ |
| internal_phy = <1>; |
| status = "disabled"; |
| |
| mdio0: mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,dwmac-mdio"; |
| }; |
| }; |
| |
| uart_A: serial@fe078000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0xfe078000 0x0 0x18>; |
| interrupts = <0 168 1>; |
| status = "disabled"; |
| clocks = <&xtal |
| &clkc CLKID_SYS_CLK_UART_A>; |
| clock-names = "clk_uart", |
| "clk_gate"; |
| xtal_tick_en = <2>; |
| fifosize = < 64 >; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&a_uart_pins1>; |
| }; |
| |
| uart_C: serial@fe07c000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0xfe07c000 0x0 0x18>; |
| interrupts = <0 170 1>; |
| status = "disabled"; |
| clocks = <&xtal |
| &clkc CLKID_SYS_CLK_UART_C>; |
| clock-names = "clk_uart", |
| "clk_gate"; |
| xtal_tick_en = <2>; |
| fifosize = < 64 >; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&c_uart_pins1>; |
| }; |
| |
| uart_D: serial@fe07e000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0xfe07e000 0x0 0x18>; |
| interrupts = <0 171 1>; |
| status = "disabled"; |
| clocks = <&xtal |
| &clkc CLKID_SYS_CLK_UART_D>; |
| clock-names = "clk_uart", |
| "clk_gate"; |
| xtal_tick_en = <2>; |
| fifosize = < 64 >; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&d_uart_pins1>; |
| }; |
| |
| sd_emmc_c: mmc@fe08c000 { |
| compatible = "amlogic,meson-axg-mmc"; |
| reg = <0x0 0xfe08c000 0x0 0x800>, |
| <0x0 0xfe000168 0x0 0x4>, |
| <0x0 0xfe004000 0x0 0x4>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_C>, |
| <&clkc CLKID_SD_EMMC_C_CLK_SEL>, |
| <&clkc CLKID_SD_EMMC_C_CLK>, |
| <&xtal>, |
| <&clkc CLKID_GP0_PLL>, |
| <&clkc CLKID_GP0_PLL>; |
| clock-names = "core", "mux0", "mux1", |
| "clkin0", "clkin1", "clkin2"; |
| card_type = <1>; |
| src_clk_rate = <1152000000>; |
| mmc_debug_flag; |
| ignore_desc_busy; |
| tx_delay = <16>; |
| // resets = <&reset RESET_SD_EMMC_C>; |
| }; |
| |
| sd_emmc_b: sd@fe08a000 { |
| compatible = "amlogic,meson-axg-mmc"; |
| reg = <0x0 0xfe08a000 0x0 0x800>, |
| <0x0 0xfe00016c 0x0 0x4>, |
| <0x0 0xfe004008 0x0 0x4>; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_B>, |
| <&clkc CLKID_SD_EMMC_B_CLK_SEL>, |
| <&clkc CLKID_SD_EMMC_B_CLK>, |
| <&xtal>, |
| <&clkc CLKID_GP0_PLL>, |
| <&clkc CLKID_GP0_PLL>; |
| clock-names = "core", "mux0", "mux1", |
| "clkin0", "clkin1","clkin2"; |
| //card_type = <5>; |
| card_type = <3>; |
| cap-sdio-irq; |
| keep-power-in-suspend; |
| src_clk_rate = <1152000000>; |
| use_intf3_tuning; |
| mmc_debug_flag; |
| //resets = <&reset RESET_SD_EMMC_B>; |
| }; |
| |
| // sd_emmc_b: sd@fe08a000 { |
| // compatible = "amlogic,meson-axg-mmc"; |
| // reg = <0x0 0xfe08a000 0x0 0x800>, |
| // <0x0 0xfe00016c 0x0 0x4>, |
| // <0x0 0xfe004008 0x0 0x4>; |
| // interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; |
| // status = "disabled"; |
| // clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_B>, |
| // <&clkc CLKID_SD_EMMC_B_CLK_SEL>, |
| // <&clkc CLKID_SD_EMMC_B_CLK>, |
| // <&xtal>, |
| // <&clkc CLKID_FCLK_DIV2>; |
| // clock-names = "core", "mux0", "mux1", |
| // "clkin0", "clkin1"; |
| // card_type = <5>; |
| // mmc_debug_flag; |
| // //resets = <&reset RESET_SD_EMMC_B>; |
| // }; |
| |
| dummy_codec:dummy{ |
| #sound-dai-cells = <0>; |
| compatible = "amlogic, aml_dummy_codec"; |
| status = "okay"; |
| }; |
| video_composer { |
| compatible = "amlogic, video_composer"; |
| dev_name = "video_composer"; |
| status = "okay"; |
| }; |
| acodec:codec { |
| #sound-dai-cells = <0>; |
| compatible = "amlogic, t3_acodec"; |
| reg = <0x0 0xfe01a000 0x0 0x1c>; |
| tdmout_index = <1>; |
| tdmin_index = <1>; |
| dat0_ch_sel = <1>; |
| reset-names = "acodec"; |
| resets = <&reset RESET_ACODEC>; |
| |
| status = "okay"; |
| }; |
| |
| audio_data: audio_data { |
| compatible = "amlogic, audio_data"; |
| mem_in_base_cmd = <0x82000020>; |
| query_licence_cmd = <0x82000050>; |
| status = "okay"; |
| }; |
| |
| amaudio: amaudio { |
| compatible = "amlogic, amaudio"; |
| reg = <0x0 0xfe440000 0x0 0x10000>; |
| reg-names = "otp_tee_base"; |
| status = "okay"; |
| }; |
| |
| audiobus: audiobus@0xFE330000 { |
| compatible = "amlogic, audio-controller", "simple-bus"; |
| reg = <0x0 0xFE330000 0x0 0x3000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xFE330000 0x0 0x3000>; |
| |
| power-domains = <&pwrdm PDID_T3_AUDIO>; |
| chip_id = <0x38>; |
| status = "okay"; |
| |
| clkaudio: audio_clocks { |
| compatible = "amlogic, t3-audio-clocks"; |
| #clock-cells = <1>; |
| reg = <0x0 0x0 0x0 0xb0>; |
| status = "okay"; |
| }; |
| ddr_manager { |
| compatible = |
| "amlogic, t5-audio-ddr-manager"; |
| interrupts = < |
| GIC_SPI 32 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 33 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 34 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 45 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 36 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 37 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 38 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 46 IRQ_TYPE_EDGE_RISING |
| >; |
| interrupt-names = |
| "toddr_a", "toddr_b", "toddr_c", |
| "toddr_d", |
| "frddr_a", "frddr_b", "frddr_c", |
| "frddr_d"; |
| status = "okay"; |
| }; |
| |
| pinctrl_audio: pinctrl { |
| compatible = "amlogic, audio-pinctrl"; |
| status = "okay"; |
| }; |
| };/* end of audiobus*/ |
| |
| vpu: vpu { |
| compatible = "amlogic, vpu-t3"; |
| status = "okay"; |
| reg = <0x0 0xfe000000 0x0 0x100 /* clk */ |
| 0x0 0xfe00c000 0x0 0x70 /* pwrctrl */ |
| 0x0 0xff000000 0x0 0xa000>; /* vcbus */ |
| clocks = <&clkc CLKID_VAPB>, |
| <&clkc CLKID_VPU_0>, |
| <&clkc CLKID_VPU_1>, |
| <&clkc CLKID_VPU>; |
| clock-names = "vapb_clk", |
| "vpu_clk0", |
| "vpu_clk1", |
| "vpu_clk"; |
| clk_level = <7>; |
| /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ |
| /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ |
| }; |
| |
| /*if you want to use vdin just modify status to "ok"*/ |
| vdin0: vdin0 {/*common define*/ |
| compatible = "amlogic, vdin-t3"; |
| dev_name = "vdin0"; |
| /*status = "disabled";*/ |
| /*memory-region = <&vdin0_cma_reserved>;*/ |
| reserve-iomap = "true"; |
| flag_cma = <0x101>;/*1:share with codec_mm;2:cma alone*/ |
| /*MByte, if 10bit disable: 64M(YUV422), |
| *if 10bit enable: 64*1.5 = 96M(YUV422) |
| *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M |
| *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M |
| *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M |
| *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M |
| * onebuffer: |
| * worst case:(4096*2160*3 + 2M(afbce issue)) = 27.5M |
| * dw:960x540x3 = 1.5M |
| * total size:(27.5+1.5)x buffernumber |
| */ |
| /*cma_size = <174>;*/ |
| /*frame_buff_num = <6>;*/ |
| interrupts = <0 210 1 /* vdin0 vsync */ |
| /*0 214 1*/ /* vdin1 write down*/ |
| /*0 206 1*/ /* vpu crash */ |
| /*0 213 1*/>; /* vdin0 write down*/ |
| interrupt-names = "vsync_int" |
| /*"mif2_meta_wr_done_int"*/ |
| /*"vpu_crash_int",*/ |
| /*"write_done_int"*/; |
| rdma-irq = <2>; |
| clocks = <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_VDIN_MEAS>; |
| clock-names = "fclk_div5", "cts_vdin_meas_clk"; |
| vdin_id = <0>; |
| /*vdin write mem color depth support: |
| * bit0:support 8bit |
| * bit1:support 9bit |
| * bit2:support 10bit |
| * bit3:support 12bit |
| * bit4:support yuv422 10bit full pack mode (from txl new add) |
| * bit5:force yuv422 to yuv444 malloc (for vdin0 debug) |
| * bit8:use 8bit at 4k_50/60hz_10bit |
| * bit9:use 10bit at 4k_50/60hz_10bit |
| * bit10: support 10bit when double write |
| */ |
| tv_bit_mode = <0x235>; |
| /* afbce_bit_mode: (amlogic frame buff compression encoder) |
| * bit0 -- enable afbce |
| * bit1 -- enable afbce compression-lossy |
| * bit4 -- afbce for 4k |
| * bit5 -- afbce for 1080p |
| * bit6 -- afbce for 720p |
| * bit7 -- afbce for smaller resolution |
| */ |
| afbce_bit_mode = <0x11>; |
| /* urgent_en; */ |
| double_write_en; |
| v4l_support_en; |
| }; |
| |
| vdin1: vdin1 {/*common define*/ |
| compatible = "amlogic, vdin-t3"; |
| dev_name = "vdin1"; |
| /*status = "disabled";*/ |
| reserve-iomap = "true"; |
| /*memory-region = <&vdin1_cma_reserved>;*/ |
| flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ |
| interrupts = <0 212 1>; |
| interrupt-names = "vsync_int"/*, "vpu_crash_int",*/ |
| /*"write_done_int"*/; |
| rdma-irq = <4>; |
| /*clocks = <&clock CLK_FPLL_DIV5>, |
| * <&clock CLK_VDIN_MEAS_CLK>; |
| *clock-names = "fclk_div5", "cts_vdin_meas_clk"; |
| */ |
| vdin_id = <1>; |
| tv_bit_mode = <0x15>; |
| }; |
| |
| amvdec_656in { |
| /*bt656 gpio conflict with i2c0*/ |
| compatible = "amlogic, bt656in-t3"; |
| dev_name = "amvdec_656in"; |
| status = "okay"; |
| reg = <0x0 0xfe0ba000 0x0 0x7c>; |
| clocks = <&clkc CLKID_BT656_CLK>, |
| <&clkc CLKID_SYS_CLK_BT656_PCLK>; |
| clock-names = "cts_bt656_clk1", |
| "clk_gate_bt656_pclk1"; |
| /* bt656in1, bt656in2 */ |
| bt656in1 { |
| bt656_id = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| /* eARC */ |
| audio_earc: bus@fe333000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xfe333000 0x0 0x1000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xfe333000 0x0 0x1000>; |
| |
| earc: earc@0 { |
| compatible = "amlogic, t3-snd-earc"; |
| #sound-dai-cells = <0>; |
| |
| status = "disabled"; |
| |
| reg = <0x0 0x0 0x0 0x400>, |
| <0x0 0x400 0x0 0x200>, |
| <0x0 0x600 0x0 0x200>; |
| reg-names = "tx_cmdc", |
| "tx_dmac", |
| "tx_top"; |
| |
| clocks = < &clkaudio CLKID_EARCTX_CMDC |
| &clkaudio CLKID_EARCTX_DMAC |
| &clkc CLKID_FCLK_DIV4 |
| &clkc CLKID_MPLL2 |
| >; |
| clock-names = |
| "tx_cmdc", |
| "tx_dmac", |
| "tx_cmdc_srcpll", |
| "tx_dmac_srcpll"; |
| |
| interrupts = < |
| GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names ="earc_tx"; |
| }; |
| }; |
| |
| /* Sound iomap */ |
| aml_snd_iomap { |
| compatible = "amlogic, snd-iomap"; |
| status = "okay"; |
| #address-cells=<2>; |
| #size-cells=<2>; |
| ranges; |
| pdm_bus { |
| reg = <0x0 0xFE331000 0x0 0x400>; |
| }; |
| audiobus_base { |
| reg = <0x0 0xFE330000 0x0 0x1000>; |
| }; |
| audiolocker_base { |
| reg = <0x0 0xFE331400 0x0 0x400>; |
| }; |
| eqdrc_base { |
| reg = <0x0 0xFE332000 0x0 0x1000>; |
| }; |
| vad_base { |
| reg = <0x0 0xFE331800 0x0 0x400>; |
| }; |
| resampleA_base { |
| reg = <0x0 0xFE331c00 0x0 0x104>; |
| }; |
| resampleB_base { |
| reg = <0x0 0xFE334000 0x0 0x104>; |
| }; |
| }; |
| |
| //hdmirx arc |
| hdmirx_arc { |
| compatible = "amlogic, hdmirx-arc-iomap"; |
| reg = <0x0 0xfe39c000 0x0 0x10c>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| reg-names = "hdmirx-arc"; |
| }; |
| |
| aml_bt: aml_bt { |
| compatible = "amlogic, aml-bt"; |
| status = "disabled"; |
| }; |
| |
| aml_wifi: aml_wifi { |
| compatible = "amlogic, aml-wifi"; |
| status = "disabled"; |
| irq_trigger_type = "GPIO_IRQ_LOW"; |
| //dhd_static_buf; |
| pwm_config = <&wifi_pwm_conf>; |
| }; |
| |
| wifi_pwm_conf:wifi_pwm_conf{ |
| pwm_channel1_conf { |
| pwms = <&pwm_ef 0 30550 0>; |
| duty-cycle = <15270>; |
| times = <8>; |
| }; |
| pwm_channel2_conf { |
| pwms = <&pwm_ef 2 30500 0>; |
| duty-cycle = <15250>; |
| times = <12>; |
| }; |
| }; |
| }; |
| |
| aocec: aocec { |
| compatible = "amlogic, aocec-t3"; |
| dev_name = "aocec"; |
| status = "okay"; |
| vendor_name = "Amlogic"; /* Max Chars: 8 */ |
| /* Refer to the following URL at: |
| * http://standards.ieee.org/develop/regauth/oui/oui.txt |
| */ |
| vendor_id = <0x000000>; |
| product_desc = "T3"; /* Max Chars: 16 */ |
| cec_osd_string = "AML_TV"; /* Max Chars: 14 */ |
| cec_version = <5>;/*5:1.4;6:2.0*/ |
| port_num = <3>; |
| output = <0>; |
| cec_sel = <1>;/*1:use one ip, 2:use 2 ip*/ |
| ee_cec; /*use cec a or b*/ |
| arc_port_mask = <0x2>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>;/*0:snps*/ |
| interrupt-names = "hdmi_aocecb"; |
| pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; |
| pinctrl-0=<&cec_b>; |
| pinctrl-1=<&cec_b>; |
| pinctrl-2=<&cec_b>; |
| clocks = <&clkc CLKID_CECB_32K_CLKOUT>; |
| clock-names = "cecb_clk"; |
| reg = <0x0 0xfe044000 0x0 0x2000 |
| 0x0 0xfe010000 0x0 0x2000 |
| 0x0 0xfe000000 0x0 0x2000>; |
| reg-names = "ao","periphs","clock"/*ao_exit sys_ctrl clk_ctrl*/; |
| }; |
| |
| aml_dma { |
| compatible = "amlogic,aml_txlx_dma"; |
| reg = <0x0 0xfe440400 0x0 0x48>; |
| interrupts = <0 24 1>; |
| |
| aml_aes { |
| compatible = "amlogic,aes_g12a_dma"; |
| dev_name = "aml_aes_dma"; |
| status = "okay"; |
| iv_swap = /bits/ 8 <0x0>; |
| }; |
| |
| aml_sha { |
| compatible = "amlogic,sha_dma"; |
| dev_name = "aml_sha_dma"; |
| status = "okay"; |
| }; |
| |
| aml_tdes { |
| compatible = "amlogic,tdes_dma"; |
| dev_name = "aml_tdes_dma"; |
| status = "okay"; |
| }; |
| |
| }; |
| |
| rng { |
| compatible = "amlogic,meson-rng"; |
| status = "okay"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| reg = <0x0 0xfe440788 0x0 0x0c>; |
| quality = /bits/ 16 <1000>; |
| version = <2>; |
| }; |
| |
| vclk_serve: vclk_serve { |
| compatible = "amlogic, vclk_serve"; |
| status = "okay"; |
| reg = <0x0 0xfe008000 0x0 0x400 /* ana reg */ |
| 0x0 0xfe000000 0x0 0x4a0>; /* clk reg */ |
| }; |
| |
| vout_mux: vout_mux { |
| compatible = "amlogic, vout_mux-t3"; |
| status = "okay"; |
| }; |
| |
| vout: vout { |
| compatible = "amlogic, vout"; |
| status = "okay"; |
| }; |
| |
| vout2: vout2 { |
| compatible = "amlogic, vout2"; |
| status = "okay"; |
| }; |
| |
| dummy_venc: dummy_venc { |
| compatible = "amlogic, dummy_venc_t3"; |
| status = "okay"; |
| }; |
| |
| vrr0: vrr0 { |
| compatible = "amlogic, vrr-t3"; |
| status = "okay"; |
| index = <0>; |
| line_delay = <150>; |
| }; |
| |
| canvas: canvas { |
| compatible = "amlogic, meson, canvas"; |
| status = "okay"; |
| reg = <0x0 0xfe036048 0x0 0x2000>; |
| }; |
| |
| meson_uvm { |
| compatible = "amlogic, meson_uvm"; |
| status = "okay"; |
| }; |
| |
| meson_videotunnel{ |
| compatible = "amlogic, meson_videotunnel"; |
| status = "okay"; |
| }; |
| |
| rdma { |
| compatible = "amlogic, meson-t3, rdma"; |
| status = "okay"; |
| interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "rdma"; |
| /* after sc2 */ |
| reset-names = "rdma"; |
| resets = <&reset RESET_RDMA>; |
| rdma_table_page_count = <16>; |
| }; |
| |
| codec_io: codec_io { |
| compatible = "amlogic, meson-t3, codec-io"; |
| status = "okay"; |
| #address-cells=<2>; |
| #size-cells=<2>; |
| ranges; |
| reg = <0x0 0xfe002000 0x0 0x2000>, |
| <0x0 0xfe320000 0x0 0x10000>, |
| <0x0 0x0 0x0 0x0>, |
| <0x0 0x0 0x0 0x00>, |
| <0x0 0xff000000 0x0 0x40000>, |
| <0x0 0xfe036000 0x0 0x2000>, |
| <0x0 0x0 0x0 0x0>, |
| <0x0 0xfe0a8000 0x0 0x2000>; |
| reg-names = "cbus", |
| "dosbus", |
| "hiubus", |
| "aobus", |
| "vcbus", |
| "dmcbus", |
| "efusebus", |
| "nocbus"; |
| }; |
| amvenc_avc{ |
| compatible = "amlogic, amvenc_avc"; |
| dev_name = "amvenc_avc"; |
| status = "okay"; |
| clocks = <&clkc CLKID_HCODEC>; |
| clock-names = "cts_hcodec_aclk"; |
| interrupts = <0 93 1>; |
| interrupt-names = "mailbox_2"; |
| reset-names = "hcodec_rst"; |
| //resets = <&reset RESET_BRG_HCODEC_PIPL0>; |
| }; |
| jpegenc{ |
| compatible = "amlogic, jpegenc"; |
| dev_name = "jpegenc"; |
| status = "okay"; |
| clocks = <&clkc CLKID_HCODEC>; |
| clock-names = "clk_jpeg_enc"; |
| interrupts = <0 93 1>; |
| interrupt-names = "mailbox_2"; |
| reset-names = "jpegenc_rst"; |
| //resets = <&reset RESET_BRG_HCODEC_PIPL0>; |
| }; |
| |
| ion_dev { |
| compatible = "amlogic, ion_dev"; |
| memory-region = <&ion_cma_reserved |
| &ion_fb_reserved |
| &ion_secure_reserved>; |
| }; |
| |
| fb: fb { |
| compatible = "amlogic, fb-t3"; |
| memory-region = <&logo_reserved>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 194 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; |
| /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ |
| display_mode_default = "1080p60hz"; |
| scale_mode = <1>; |
| /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ |
| display_size_default = <1920 1080 1920 2160 32>; |
| /*1920*1080*4*3 = 0x17BB000*/ |
| }; |
| |
| dmx_aucpu: aucpu { |
| compatible = "amlogic, aucpu"; |
| dev_name = "aml_aucpu"; |
| status = "okay"; |
| interrupts = <0 77 1>; |
| interrupt-names = "aucpu_irq"; |
| #address-cells=<2>; |
| #size-cells=<2>; |
| ranges; |
| io_reg_base{ |
| reg = <0x0 0xfe09e080 0x0 0x100>; |
| }; |
| }; |
| |
| ge2d { |
| compatible = "amlogic, ge2d-t3"; |
| status = "okay"; |
| interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "ge2d"; |
| clocks = <&clkc CLKID_VAPB>, |
| <&clkc CLKID_SYS_CLK_G2D>, |
| <&clkc CLKID_GE2D_GATE>; |
| clock-names = "clk_vapb_0", |
| "clk_ge2d", |
| "clk_ge2d_gate"; |
| reg = <0x0 0xff040000 0x0 0x100>; |
| power-domains = <&pwrdm PDID_T3_GE2D>; |
| }; |
| |
| amlvecm: amlvecm { |
| compatible = "amlogic, vecm-t3"; |
| dev_name = "aml_vecm"; |
| clocks = <&clkc CLKID_VID_LOCK>; |
| clock-names = "cts_vid_lock_clk"; |
| }; |
| |
| amdolby_vision { |
| compatible = "amlogic, dolby_vision_t3"; |
| dev_name = "aml_amdolby_vision_driver"; |
| status = "okay"; |
| tv_mode = <1>;/*1:enabel ;0:disable*/ |
| }; |
| |
| mesonstream { |
| compatible = "amlogic, codec, streambuf"; |
| dev_name = "mesonstream"; |
| status = "okay"; |
| clocks = <&clkc CLKID_SYS_CLK_DOS |
| &clkc CLKID_VDEC |
| &clkc CLKID_HCODEC |
| &clkc CLKID_HEVCF |
| &clkc CLKID_HEVCB>; |
| clock-names = "vdec", |
| "clk_vdec_mux", |
| "clk_hcodec_mux", |
| "clk_hevcf_mux", |
| "clk_hevcb_mux"; |
| assigned-clock-parents = <&clkc CLKID_VDEC_0>, |
| <&clkc CLKID_HEVCF_0>, |
| <&clkc CLKID_HEVCB_0>; |
| assigned-clocks = <&clkc CLKID_VDEC>, |
| <&clkc CLKID_HEVCF>, |
| <&clkc CLKID_HEVCB>; |
| }; |
| |
| vdec { |
| compatible = "amlogic, vdec-pm-pd"; |
| dev_name = "vdec.0"; |
| status = "okay"; |
| interrupts = <0 3 1 |
| 0 23 1 |
| 0 32 1 |
| 0 91 1 |
| 0 92 1 |
| 0 93 1 |
| 0 72 1>; |
| interrupt-names = "vsync", |
| "demux", |
| "parser", |
| "mailbox_0", |
| "mailbox_1", |
| "mailbox_2", |
| "parser_b"; |
| power-domains = <&pwrdm PDID_T3_DOS_VDEC>, |
| <&pwrdm PDID_T3_DOS_HEVC>, |
| <&pwrdm PDID_T3_DOS_HCODEC>; |
| power-domain-names = "pwrc-vdec", |
| "pwrc-hevc", "pwrc-hcodec"; |
| }; |
| vdec_cpu_ver: cpu_ver_name { |
| compatible = "amlogic, cpu-major-id-t3"; |
| }; |
| vcodec_dec { |
| compatible = "amlogic, vcodec-dec"; |
| dev_name = "aml-vcodec-dec"; |
| status = "okay"; |
| }; |
| |
| meson-amvideom { |
| compatible = "amlogic, amvideom-t3"; |
| dev_name = "amvideom"; |
| status = "okay"; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 194 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "vsync", "vsync_viu2", "pre_vsync"; |
| }; |
| |
| vpu_security { |
| compatible = "amlogic, meson-t3, vpu_security"; |
| status = "okay"; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "vpu_security"; |
| }; |
| |
| di_local { |
| compatible = "amlogic, di-local"; |
| status = "okay"; |
| }; |
| |
| multi-di { |
| compatible = "amlogic, dim-t3"; |
| status = "okay"; |
| /* 0:use reserved; 1:use cma; 2:use cma as reserved */ |
| flag_cma = <4>; //<1>; |
| //memory-region = <&di_reserved>; |
| memory-region = <&di_cma_reserved>; |
| interrupts = <0 203 1 |
| 0 202 1 |
| 0 81 1 |
| 0 285 1>; |
| interrupt-names = "pre_irq", "post_irq", "aisr_irq", "dct_irq"; |
| clocks = <&clkc CLKID_VPU_CLKB>, |
| <&clkc CLKID_VPU>; |
| clock-names = "vpu_clkb", |
| "vpu_mux"; |
| clock-range = <334 667>; |
| /* buffer-size = <3621952>;(yuv422 8bit) */ |
| buffer-size = <4074560>;/*yuv422 fullpack*/ |
| /* reserve-iomap = "true"; */ |
| /* if enable nr10bit, set nr10bit-support to 1 */ |
| post-wr-support = <1>; |
| nr10bit-support = <1>; |
| nrds-enable = <1>; |
| pps-enable = <1>; |
| dct = <2>;//decontour enable |
| hf = <2>; //enable aisr |
| /*************************************************** |
| * t3 support 4k ,same with t7 ,no canvas, |
| * post_nub---default is 11 |
| * (T7/T3/SC2/S4 new path)post 11*5222400 = 56M,local 7*4075520 = 28m |
| * flag_cma---0: use reserved; 1:use cma; 2:use cma as reserved 4:use codec mem |
| * en_4k :en_4k---0: not support 4K; 1: enable 4K |
| * 2: dynamic: vdin: 4k enable, other source 4k disable |
| * 8: when 4k,output with a resolution is below 1080p |
| * keep_dec_vf---0:not keep; 1: keep dec vf for p; |
| * 2: dynamic keep dec vf for p,other is disable |
| * po_fmt---1: NV21/8; 2: nv12/8; 3: AFBC 422/10BIT; |
| * 4: dynamic(4K AFBC,10/422); |
| * 6: dynamic(from decoder 4K source,out is AFBC,10/420),other is 422/10BIT |
| * bypass_mem---0:nr not bypass; 1: nr bypass; 2: when 4k input ,nr is bypass; |
| * 3: bypass nr for 4k,but not from vdin; |
| * alloc_sct---0:not support; bit 0: for 4k; bit 1: for 1080p |
| * hf---0:not enable; 1: enable |
| ***************************************************/ |
| }; |
| |
| cpu_tsensor: cpu_tsensor@fe022000 { |
| compatible = "amlogic, r1p1-tsensor"; |
| status = "okay"; |
| reg = <0x0 0xfe022000 0x0 0x50>; |
| tsensor_id = <1>; |
| cal_type = <0x11>; |
| cal_coeff = <324 424 3159 9411>; |
| rtemp = <115000>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_TS_CLK>; |
| clock-names = "ts_comp"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| nna_tsensor: a53_tsensor@fe020000 { |
| compatible = "amlogic, r1p1-tsensor"; |
| status = "okay"; |
| reg = <0x0 0xfe020000 0x0 0x50>; |
| tsensor_id = <2>; |
| cal_type = <0x11>; |
| cal_coeff = <324 424 3159 9411>; |
| rtemp = <115000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_TS_CLK>; |
| clock-names = "ts_comp"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| vpu_tsensor: gpu_tsensor@fe01c000 { |
| compatible = "amlogic, r1p1-tsensor"; |
| status = "okay"; |
| reg = <0x0 0xfe01c000 0x0 0x50>; |
| tsensor_id = <3>; |
| cal_type = <0x11>; |
| cal_coeff = <324 424 3159 9411>; |
| rtemp = <115000>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_TS_CLK>; |
| clock-names = "ts_comp"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| meson_cooldev: meson-cooldev@0 { |
| status = "okay"; |
| compatible = "amlogic, meson-cooldev"; |
| cooling_devices { |
| cpucore_cool_cluster0 { |
| cluster_id = <0>; |
| node_name = "cpucore_cool0"; |
| device_type = "cpucore"; |
| }; |
| gpufreq_cool { |
| dyn_coeff = <358>; |
| node_name = "bifrost"; |
| device_type = "gpufreq"; |
| }; |
| }; |
| cpucore_cool0:cpucore_cool0 { |
| #cooling-cells = <2>; |
| }; |
| };/*meson cooling devices end*/ |
| |
| thermal-zones { |
| soc_thermal: soc_thermal { |
| polling-delay = <1000>; |
| polling-delay-passive = <100>; |
| sustainable-power = <5160>; |
| thermal-sensors = <&cpu_tsensor 0>; |
| trips { |
| cpuswitch_on: trip-point@0 { |
| temperature = <80000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| cpucontrol: trip-point@1 { |
| temperature = <90000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| cpucritical: trip-point@2 { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| cooling-maps { |
| cpufreq_cooling_map { |
| trip = <&cpucontrol>; |
| cooling-device = <&CPU0 0 8>; |
| contribution = <1024>; |
| }; |
| gpufreq_cooling_map { |
| trip = <&cpucontrol>; |
| cooling-device = <&gpu 0 3>; |
| contribution = <1024>; |
| }; |
| }; |
| }; |
| nna_thermal: nna_thermal { |
| polling-delay = <2000>; |
| polling-delay-passive = <1000>; |
| sustainable-power = <960>; |
| thermal-sensors = <&nna_tsensor 1>; |
| trips { |
| nnaswitch_on: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| nnacontrol: trip-point@1 { |
| temperature = <100000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| nnacritical: trip-point@2 { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| vpu_thermal: vpu_thermal { |
| polling-delay = <2000>; |
| polling-delay-passive = <1000>; |
| sustainable-power = <400>; |
| thermal-sensors = <&vpu_tsensor 2>; |
| trips { |
| vpuswitch_on: trip-point@0 { |
| temperature = <85000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| vpucontrol: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| vpucritical: trip-point@2 { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| };/*thermal zone end*/ |
| |
| crg20: crg@fdd00000 { |
| compatible = "amlogic, crg"; |
| status = "disabled"; |
| reg = <0x0 0xfdd00000 0x0 0x100000>; |
| interrupts = <0 131 4>; |
| usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>; |
| cpu-type = "gxl"; |
| clock-src = "usb3.0"; |
| clocks = <&clkc CLKID_SYS_CLK_USB>; |
| clock-names = "crg_general"; |
| }; |
| |
| crg30: crg@fde00000 { |
| compatible = "amlogic, crg"; |
| status = "disabled"; |
| reg = <0x0 0xfde00000 0x0 0x100000>; |
| interrupts = <0 130 4>; |
| usb-phy = <&usb2_m31_phy>, <&usb3_m31_phy>; |
| cpu-type = "gxl"; |
| clock-src = "usb3.0"; |
| clocks = <&clkc CLKID_SYS_CLK_USB>; |
| clock-names = "crg_general"; |
| }; |
| |
| usb2_phy_v2: usb2phy@fe03a000 { |
| compatible = "amlogic, amlogic-new-usb2-v2"; |
| status = "disable"; |
| #phy-cells = <0>; |
| reg = <0x0 0xfe03a020 0x0 0x60 |
| 0x0 0xFE002000 0x0 0x100 |
| 0x0 0xfe03e000 0x0 0x2000 |
| 0x0 0xfe032000 0x0 0x2000 |
| 0x0 0xfe030000 0x0 0x2000>; |
| pll-setting-1 = <0x09400414>; |
| pll-setting-2 = <0x927E0000>; |
| pll-setting-3 = <0xac5f69e5>; |
| pll-setting-4 = <0xbe18>; |
| pll-setting-5 = <0x7>; |
| pll-setting-6 = <0x78000>; |
| pll-setting-7 = <0xe0004>; |
| pll-setting-8 = <0xe000c>; |
| dis-thred-enhance = <0x2>;/**t3-0x38:bit[27-28]**/ |
| version = <3>; |
| //power-domains = <&pwrdm PDID_SC2_USB_COMB>; |
| phy20-reset-level-bit = <9>; |
| phy21-reset-level-bit = <3>; |
| phy22-reset-level-bit = <2>; |
| usb-reset-bit = <4>; |
| reset-level = <0x40>; |
| otg-phy-index = <0>; |
| usb-phy-trim-reg = <0xfe010330>; |
| }; |
| |
| usb3_phy_v2: usb3phy@fe03a080 { |
| compatible = "amlogic, amlogic-new-usb3-v2"; |
| status = "disable"; |
| #phy-cells = <0>; |
| reg = <0x0 0xfe03a080 0x0 0x20 |
| 0x0 0xfe002000 0x0 0x100>; |
| phy-reg = <0xfe02a000>; |
| phy-reg-size = <0x2000>; |
| usb2-phy-reg = <0xfe03a000>; |
| usb2-phy-reg-size = <0x80>; |
| xhci-port-a-reg = <0xfdd00420>; |
| clocks = <&clkc CLKID_PCIE_PLL>; |
| clock-names = "pcie_refpll"; |
| interrupts = <0 281 4>; |
| version = <1>; |
| }; |
| |
| usb2_m31_phy: usb2m31phy { |
| compatible = "amlogic, amlogic-usb2-m31-phy"; |
| status = "disable"; |
| #phy-cells = <0>; |
| }; |
| |
| usb3_m31_phy: usb3m31phy { |
| compatible = "amlogic, amlogic-usb3-m31-phy"; |
| status = "disable"; |
| #phy-cells = <0>; |
| reg = <0x0 0xfe002000 0x0 0x100>; |
| clocks = <&clkc CLKID_PCIE_PLL>; |
| clock-names = "pcie_refpll"; |
| reset-level = <0x40>; |
| phy-reg = <0xfe02a000>; |
| phy-reg-size = <0x2000>; |
| m31phy-reset-level-bit = <45>; |
| m31ctl-reset-level-bit = <6>; |
| }; |
| |
| dwc2_a: dwc2_a@fdf00000 { |
| compatible = "amlogic,dwc2"; |
| status = "disable"; |
| device_name = "dwc2_a"; |
| reg = <0x0 0xfdf00000 0x0 0x100000>; |
| interrupts = <0 129 4>; |
| pl-periph-id = <0>; /** lm name */ |
| clock-src = "usb0"; /** clock src */ |
| port-id = <0>; /** ref to mach/usb.h */ |
| port-type = <2>; /** 0: otg, 1: host, 2: slave */ |
| port-speed = <0>; /** 0: default, high, 1: full */ |
| port-config = <0>; /** 0: default */ |
| /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ |
| port-dma = <0>; |
| port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ |
| usb-fifo = <728>; |
| cpu-type = "v2"; |
| phy-reg = <0xfe03a000>; |
| phy-reg-size = <0xa0>; |
| /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/ |
| phy-interface = <0x2>; |
| clocks = <&clkc CLKID_SYS_CLK_USB |
| &clkc CLKID_SYS_CLK_USB>; |
| clock-names = "usb_general", |
| "usb1"; |
| }; |
| |
| pcie: pcie@f8000000 { |
| compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie"; |
| reg = <0x0 0xf8000000 0x0 0x400000 |
| 0x0 0xfe02c000 0x0 0x2000 |
| 0x0 0xf8400000 0x0 0x200000 |
| 0x0 0xfe02a000 0x0 0x2000 |
| 0x0 0xfe002044 0x0 0x10>; |
| reg-names = "elbi", "cfg", "config", "phy", "reset"; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; |
| #interrupt-cells = <1>; |
| bus-range = <0x0 0xff>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0 0xf8600000 0x0 0x100000 |
| /* downstream I/O */ |
| 0x82000000 0 0xf8700000 0x0 0xf8700000 0 0x1900000>; |
| /* non-prefetchable memory */ |
| num-lanes = <1>; |
| pcie-num = <1>; |
| |
| clocks = <&clkc CLKID_PCIE_PLL |
| &clkc CLKID_SYS_CLK_PCIE |
| &clkc CLKID_SYS_CLK_PCIE_PHY |
| &clkc CLKID_PCIE_HCSL>; |
| clock-names = "pcie_refpll", |
| "pcie", |
| "pcie_phy", |
| "pcie_hcsl"; |
| /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ |
| gpio-type = <2>; |
| pcie-apb-rst-bit = <14>; |
| pcie-phy-rst-bit = <13>; |
| pcie-ctrl-a-rst-bit = <12>; |
| pwr-ctl = <0>; |
| phy-type = <1>; |
| power-domains = <&pwrdm PDID_T3_PCIE>; |
| pcie-ctrl-sleep-shift = <15>; |
| pcie-hhi-mem-pd-shift = <26>; |
| pcie-hhi-mem-pd-mask = <0xf>; |
| pcie-ctrl-iso-shift = <15>; |
| status = "disabled"; |
| }; |
| |
| cpu_info { |
| compatible = "amlogic, cpuinfo"; |
| status = "okay"; |
| cpuinfo_cmd = <0x82000044>; |
| }; |
| |
| lut_dma:lut_dma { |
| compatible = "amlogic, meson-t7, lut_dma"; |
| status = "okay"; |
| }; |
| |
| efuse: efuse{ |
| compatible = "amlogic, efuse"; |
| read_cmd = <0x82000030>; |
| write_cmd = <0x82000031>; |
| get_max_cmd = <0x82000033>; |
| mem_in_base_cmd = <0x82000020>; |
| mem_out_base_cmd = <0x82000021>; |
| efuse_pattern_size = <0x600>; |
| key = <&efusekey>; |
| clock-names = "efuse_clk"; |
| status = "okay"; |
| }; |
| |
| efusekey:efusekey{ |
| keynum = <4>; |
| key0 = <&key_0>; |
| key1 = <&key_1>; |
| key2 = <&key_2>; |
| key3 = <&key_3>; |
| key_0:key_0{ |
| keyname = "mac"; |
| offset = <0>; |
| size = <6>; |
| }; |
| key_1:key_1{ |
| keyname = "mac_bt"; |
| offset = <6>; |
| size = <6>; |
| }; |
| key_2:key_2{ |
| keyname = "mac_wifi"; |
| offset = <12>; |
| size = <6>; |
| }; |
| key_3:key_3{ |
| keyname = "usid"; |
| offset = <18>; |
| size = <16>; |
| }; |
| }; |
| |
| state_led: state_led { |
| compatible = "amlogic,state-led-aocpu"; |
| status = "disabled"; |
| }; |
| }; |
| |
| &periphs_pinctrl { |
| emmc_pins: emmc { |
| mux-0 { |
| groups = "emmc_nand_d0", |
| "emmc_nand_d1", |
| "emmc_nand_d2", |
| "emmc_nand_d3", |
| "emmc_nand_d4", |
| "emmc_nand_d5", |
| "emmc_nand_d6", |
| "emmc_nand_d7", |
| "emmc_cmd"; |
| function = "emmc"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| |
| mux-1 { |
| groups = "emmc_clk"; |
| function = "emmc"; |
| bias-disable; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| emmc_ds_pins: emmc-ds { |
| mux { |
| groups = "emmc_nand_ds"; |
| function = "emmc"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| emmc_clk_gate_pins: emmc_clk_gate { |
| mux { |
| groups = "GPIOB_8"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| /* sdemmc portB */ |
| sd_clk_cmd_pins:sd_clk_cmd_pins { |
| mux { |
| groups = "sdcard_cmd"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| mux1 { |
| groups = "sdcard_clk"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sd_all_pins:sd_all_pins { |
| mux { |
| groups = "sdcard_d0", |
| "sdcard_d1", |
| "sdcard_d2", |
| "sdcard_d3", |
| "sdcard_cmd"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| mux1 { |
| groups = "sdcard_clk"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sd_clk_gate_pins: sd_clk_gate { |
| mux { |
| groups = "GPIOC_4"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sd_all_pd_pins:sd_all_pd_pins { |
| mux { |
| groups = "GPIOC_0", |
| "GPIOC_1", |
| "GPIOC_2", |
| "GPIOC_3", |
| "GPIOC_4", |
| "GPIOC_5"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| output-low; |
| }; |
| }; |
| |
| sd_1bit_pins:sd_1bit_pins { |
| mux { |
| groups = "sdcard_d0", |
| "sdcard_cmd"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| mux1 { |
| groups = "sdcard_clk"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| pwm_a_pins1: pwm_a_pins1 { |
| mux { |
| groups = "pwm_a_e"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| hdmirx_a_mux:hdmirx_a_mux { |
| mux { |
| groups = "hdmirx_hpd_a", |
| "hdmirx_5vdet_a", |
| "hdmirx_sda_a", |
| "hdmirx_scl_a"; |
| function = "hdmirx"; |
| }; |
| }; |
| |
| hdmirx_b_mux:hdmirx_b_mux { |
| mux { |
| groups = "hdmirx_hpd_b", |
| "hdmirx_5vdet_b", |
| "hdmirx_sda_b", |
| "hdmirx_scl_b"; |
| function = "hdmirx"; |
| }; |
| }; |
| |
| hdmirx_c_mux:hdmirx_c_mux { |
| mux { |
| groups = "hdmirx_hpd_c", |
| "hdmirx_5vdet_c", |
| "hdmirx_sda_c", |
| "hdmirx_scl_c"; |
| function = "hdmirx"; |
| }; |
| }; |
| |
| cec_b: cec_b { |
| mux { |
| groups = "cec"; |
| function = "cec"; |
| }; |
| }; |
| |
| irblaster_pins1:irblaster_pin1 { |
| mux { |
| groups = "remote_out_d1"; |
| function = "remote_out"; |
| }; |
| }; |
| |
| irblaster_pins2:irblaster_pin2 { |
| mux { |
| groups = "remote_out_d9"; |
| function = "remote_out"; |
| }; |
| }; |
| |
| irblaster_pins3:irblaster_pin3 { |
| mux { |
| groups = "remote_out_b"; |
| function = "remote_out"; |
| }; |
| }; |
| |
| pwm_a_pins2: pwm_a_pins2 { |
| mux { |
| groups = "pwm_a_c"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_b_pins1: pwm_b_pins1 { |
| mux { |
| groups = "pwm_b_e"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins2: pwm_b_pins2 { |
| mux { |
| groups = "pwm_b_c"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins3: pwm_b_pins3 { |
| mux { |
| groups = "pwm_b_z"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins4: pwm_b_pins4 { |
| mux { |
| groups = "pwm_b_h14"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_c_pins1: pwm_c_pins1 { |
| mux { |
| groups = "pwm_c_d5"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins2: pwm_c_pins2 { |
| mux { |
| groups = "pwm_c_d7"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_d_pins1: pwm_d_pins1 { |
| mux { |
| groups = "pwm_d_d6"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins2: pwm_d_pins2 { |
| mux { |
| groups = "pwm_d_d9"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins3: pwm_d_pins3 { |
| mux { |
| groups = "pwm_d_c"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins4: pwm_d_pins4 { |
| mux { |
| groups = "pwm_d_z"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins5: pwm_d_pins5 { |
| mux { |
| groups = "pwm_d_h5"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins6: pwm_d_pins6 { |
| mux { |
| groups = "pwm_d_h12"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins7: pwm_d_pins7 { |
| mux { |
| groups = "pwm_d_m1"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins8: pwm_d_pins8 { |
| mux { |
| groups = "pwm_d_m24"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_e_pins1: pwm_e_pins1 { |
| mux { |
| groups = "pwm_e_d"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins2: pwm_e_pins2 { |
| mux { |
| groups = "pwm_e_z"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_f_pins1: pwm_f_pins1 { |
| mux { |
| groups = "pwm_f_c"; |
| function = "pwm_f"; |
| drive-strength-microamp = <500>; |
| }; |
| }; |
| |
| pwm_f_pins2: pwm_f_pins2 { |
| mux { |
| groups = "pwm_f_h13"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins3: pwm_f_pins3 { |
| mux { |
| groups = "pwm_f_m23"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins4: pwm_f_pins4 { |
| mux { |
| groups = "pwm_f_m26"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_g_pins1: pwm_g_pins1 { |
| mux { |
| groups = "pwm_g_m8"; |
| function = "pwm_g"; |
| }; |
| }; |
| |
| pwm_g_pins2: pwm_g_pins2 { |
| mux { |
| groups = "pwm_g_z"; |
| function = "pwm_g"; |
| }; |
| }; |
| |
| pwm_h_pins1: pwm_h_pins1 { |
| mux { |
| groups = "pwm_h_z"; |
| function = "pwm_h"; |
| }; |
| }; |
| |
| pwm_h_pins2: pwm_h_pins2 { |
| mux { |
| groups = "pwm_h_m9"; |
| function = "pwm_h"; |
| }; |
| }; |
| |
| pwm_i_pins1: pwm_i_pins1 { |
| mux { |
| groups = "pwm_i_z"; |
| function = "pwm_i"; |
| }; |
| }; |
| |
| pwm_i_pins2: pwm_i_pins2 { |
| mux { |
| groups = "pwm_i_m10"; |
| function = "pwm_i"; |
| }; |
| }; |
| |
| pwm_j_pins1: pwm_j_pins1 { |
| mux { |
| groups = "pwm_j_z"; |
| function = "pwm_j"; |
| }; |
| }; |
| |
| pwm_j_pins2: pwm_j_pins2 { |
| mux { |
| groups = "pwm_j_m11"; |
| function = "pwm_j"; |
| }; |
| }; |
| |
| pwm_c_hiz_pins: pwm_c_hiz_pins { |
| mux { |
| groups = "pwm_c_hiz_d"; |
| function = "pwm_c_hiz"; |
| }; |
| }; |
| |
| pwm_d_hiz_pins: pwm_d_hiz_pins { |
| mux { |
| groups = "pwm_d_hiz_d"; |
| function = "pwm_d_hiz"; |
| }; |
| }; |
| |
| lcd_vbyone_a_pins: lcd_vbyone_a_pin { |
| mux { |
| groups = "vx1_a_lockn","vx1_a_htpdn"; |
| function = "vx1_a"; |
| }; |
| }; |
| |
| lcd_vbyone_a_off_pins: lcd_vbyone_a_off_pin { |
| mux { |
| groups = "GPIOH_0","GPIOH_8"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| lcd_vbyone_b_pins: lcd_vbyone_b_pin { |
| mux { |
| groups = "vx1_b_lockn","vx1_b_htpdn"; |
| function = "vx1_b"; |
| }; |
| }; |
| |
| lcd_vbyone_b_off_pins: lcd_vbyone_b_off_pin { |
| mux { |
| groups = "GPIOH_9","GPIOH_10"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| lcd_tcon_p2p_pins: lcd_tcon_p2p_pin { |
| mux { |
| groups = "tcon_1","tcon_2","tcon_3", |
| "tcon_4","tcon_5","tcon_6", |
| "tcon_lock"; |
| function = "tcon"; |
| }; |
| }; |
| |
| lcd_tcon_p2p_usit_pins: lcd_tcon_p2p_usit_pin { |
| mux { |
| groups = "tcon_1","tcon_2","tcon_3", |
| "tcon_4","tcon_5","tcon_6", |
| "tcon_sfc_h0"; |
| function = "tcon"; |
| }; |
| }; |
| |
| lcd_tcon_p2p_off_pins: lcd_tcon_p2p_off_pin { |
| mux { |
| groups = "GPIOH_1","GPIOH_2","GPIOH_3", |
| "GPIOH_4","GPIOH_5","GPIOH_6", |
| "GPIOH_0"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| lcd_tcon_mlvds_pins: lcd_tcon_mlvds_pin { |
| mux { |
| groups = "tcon_0","tcon_1","tcon_2","tcon_3", |
| "tcon_4","tcon_5","tcon_6"; |
| function = "tcon"; |
| }; |
| }; |
| |
| lcd_tcon_mlvds_off_pins: lcd_tcon_mlvds_off_pin { |
| mux { |
| groups = "GPIOH_0","GPIOH_1","GPIOH_2","GPIOH_3", |
| "GPIOH_4","GPIOH_5","GPIOH_6"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| remote_pins: remote_pin { |
| mux { |
| groups = "remote_input"; |
| function = "remote_input"; |
| bias-disable; |
| }; |
| }; |
| |
| spdifout_z: spdifout_z { |
| mux { /* GPIOZ_19 */ |
| groups = "spdif_out_z19"; |
| function = "spdif_out"; |
| }; |
| }; |
| |
| spdifout_z_mute: spdifout_z_mute { |
| mux { /* GPIOZ_19 */ |
| groups = "GPIOZ_19"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| mclk_1_pins: mclk_1_pin { |
| mux { /* GPIOH_14 */ |
| groups = "mclk_1_h"; |
| function = "mclk"; |
| }; |
| }; |
| |
| i2c0_pins1:i2c0_pins1 { |
| mux { |
| groups = "i2c0_sda_z", |
| "i2c0_sck_z"; |
| function = "i2c0"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_pins1:i2c1_pins1 { |
| mux { |
| groups = "i2c1_sda_d", |
| "i2c1_sck_d"; |
| function = "i2c1"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_pins2:i2c1_pins2 { |
| mux { |
| groups = "i2c1_sda_c", |
| "i2c1_sck_c"; |
| function = "i2c1"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins1:i2c2_pins1 { |
| mux { |
| groups = "i2c2_sda_e", |
| "i2c2_sck_e"; |
| function = "i2c2"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins2:i2c2_pins2 { |
| mux { |
| groups = "i2c2_sda_h21", |
| "i2c2_sck_h20"; |
| function = "i2c2"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins3:i2c2_pins3 { |
| mux { |
| groups = "i2c2_sda_h11", |
| "i2c2_sck_h10"; |
| function = "i2c2"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins4:i2c2_pins4 { |
| mux { |
| groups = "i2c2_sda_h25", |
| "i2c2_sck_h24"; |
| function = "i2c2"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins5:i2c2_pins5 { |
| mux { |
| groups = "i2c2_sda_m", |
| "i2c2_sck_m"; |
| function = "i2c2"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c3_pins1:i2c3_pins1 { |
| mux { |
| groups = "i2c3_sda_h23", |
| "i2c3_sck_h22"; |
| function = "i2c3"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c3_pins2:i2c3_pins2 { |
| mux { |
| groups = "i2c3_sda_m", |
| "i2c3_sck_m"; |
| function = "i2c3"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c4_pins1:i2c4_pins1 { |
| mux { |
| groups = "i2c4_sda_h27", |
| "i2c4_sck_h26"; |
| function = "i2c4"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c4_pins2:i2c4_pins2 { |
| mux { |
| groups = "i2c4_sda_m", |
| "i2c4_sck_m"; |
| function = "i2c4"; |
| drive-strength-microamp = <3000>; |
| bias-disable; |
| }; |
| }; |
| |
| a_uart_pins1:a_uart1 { |
| mux { |
| groups = "uart_a_tx_c", |
| "uart_a_rx_c", |
| "uart_a_cts_c", |
| "uart_a_rts_c"; |
| function = "uart_a"; |
| }; |
| }; |
| |
| a_uart_pins2:a_uart2 { |
| mux { |
| groups = "uart_a_tx_z", |
| "uart_a_rx_z", |
| "uart_a_cts_z", |
| "uart_a_rts_z"; |
| function = "uart_a"; |
| }; |
| }; |
| |
| c_uart_pins1:c_uart1 { |
| mux { |
| groups = "uart_c_tx_d", |
| "uart_c_rx_d"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| c_uart_pins2:c_uart2 { |
| mux { |
| groups = "uart_c_tx_h1", |
| "uart_c_rx_h2"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| c_uart_pins3:c_uart3 { |
| mux { |
| groups = "uart_c_tx_h22", |
| "uart_c_rx_h23"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| c_uart_pins4:c_uart4 { |
| mux { |
| groups = "uart_c_tx_h18", |
| "uart_c_rx_h19"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| jtag_a_pins: jtag_a_pin { |
| mux { |
| groups = "jtag_a_tdi", |
| "jtag_a_tdo", |
| "jtag_a_clk", |
| "jtag_a_tms"; |
| function = "jtag_a"; |
| }; |
| }; |
| |
| c_uart_pins5:c_uart5 { |
| mux { |
| groups = "uart_c_tx_m", |
| "uart_c_rx_m"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| d_uart_pins1:d_uart1 { |
| mux { |
| groups = "uart_d_tx_z", |
| "uart_d_rx_z"; |
| function = "uart_d"; |
| }; |
| }; |
| |
| d_uart_pins2:d_uart2 { |
| mux { |
| groups = "uart_d_tx_m", |
| "uart_d_rx_m"; |
| function = "uart_d"; |
| }; |
| }; |
| |
| atvdemod_agc_pins: atvdemod_agc_pins { |
| mux { |
| groups = "atv_if_agc_z6"; |
| function = "atv_if_agc"; |
| }; |
| }; |
| |
| dtvdemod_if_agc_pins: dtvdemod_if_agc_pins { |
| mux { |
| groups = "dtv_if_agc_z6"; |
| function = "dtv_if_agc"; |
| }; |
| }; |
| |
| dtvdemod_rf_agc_pins: dtvdemod_rf_agc_pins { |
| mux { |
| groups = "dtv_rf_agc_z6"; |
| function = "dtv_rf_agc"; |
| }; |
| }; |
| |
| dvb_p_ts2_pins: dvb_p_ts2_pins { |
| mux { |
| groups = "tsin_b_din0", |
| "tsin_b_din1", |
| "tsin_b_din2", |
| "tsin_b_din3", |
| "tsin_b_din4", |
| "tsin_b_din5", |
| "tsin_b_din6", |
| "tsin_b_din7", |
| "tsin_b_clk", |
| "tsin_b_sop", |
| "tsin_b_valid"; |
| function = "tsin_b"; |
| }; |
| }; |
| dvb_ci_bus_pins: dvb_ci_bus_pins { |
| mux { |
| groups = "cicam_a0", "cicam_a1", |
| "cicam_data0", "cicam_data1", |
| "cicam_data2", "cicam_data3", |
| "cicam_data4", "cicam_data5", |
| "cicam_data6", "cicam_data7", |
| "cicam_cen", "cicam_oen", |
| "cicam_wen", "cicam_iordn", |
| "cicam_iowrn", |
| "cicam_reset", "cicam_waitn"; |
| function = "cicam"; |
| }; |
| }; |
| ci_ts_pins: ci_ts_pins { |
| mux { |
| groups = "tsout_sop_z", |
| "tsout_valid_z", |
| "tsout_d0_z", |
| "tsout_d1_z", |
| "tsout_d2_z", |
| "tsout_d3_z", |
| "tsout_d4_z", |
| "tsout_d5_z", |
| "tsout_d6_z", |
| "tsout_d7_z"; |
| function = "tsout"; |
| }; |
| }; |
| ci_addr_pins: ci_addr_pins { |
| mux { |
| groups = "cicam_a2", |
| "cicam_a3", "cicam_a4", |
| "cicam_a5", "cicam_a6", |
| "cicam_a7", "cicam_a8", |
| "cicam_a9", |
| "cicam_a10", "cicam_a11"; |
| function = "cicam"; |
| }; |
| }; |
| |
| ci_ts_clk_pins: ci_ts_clk_pins { |
| mux { |
| groups = "tsout_clk_z"; |
| function = "tsout"; |
| }; |
| }; |
| ci_gpio_pins: ci_gpio_pins { |
| mux { |
| groups = "GPIOZ_7"; |
| function = "gpio_periphs"; |
| }; |
| }; |
| diseqc_out: diseqc_out { |
| mux {/*only use out, don't support */ |
| groups = "diseqc_out_z0"; |
| function = "diseqc_out"; |
| bias-pull-down; |
| }; |
| }; |
| |
| spicc0_pins_h: spicc0_pins_h { |
| mux { |
| groups = "spi_a_mosi_h10", |
| "spi_a_miso_h9", |
| //"spi_a_ss0_h8",used as GPIOH_8 |
| "spi_a_clk_h11"; |
| function = "spi_a"; |
| drive-strength-microamp = <2000>; |
| }; |
| }; |
| |
| spicc0_pins_m: spicc0_pins_m { |
| mux { |
| groups = "spi_a_mosi_m", |
| "spi_a_miso_m", |
| //"spi_a_ss0_m",used as GPIOM_22 |
| "spi_a_clk_m"; |
| function = "spi_a"; |
| drive-strength-microamp = <2000>; |
| }; |
| }; |
| |
| spicc0_pins_z: spicc0_pins_z { |
| mux { |
| groups = "spi_a_mosi_z1", |
| "spi_a_miso_z0", |
| //"spi_a_ss0_z3",used as GPIOZ_3 |
| "spi_a_clk_z2"; |
| function = "spi_a"; |
| drive-strength-microamp = <2000>; |
| }; |
| }; |
| |
| spicc1_pins: spicc1_pins { |
| mux { |
| groups = "spi_b_mosi_h", |
| "spi_b_miso_h", |
| //"spi_b_ss0_h",used as GPIOH_24 |
| "spi_b_clk_h"; |
| function = "spi_b"; |
| drive-strength-microamp = <2000>; |
| }; |
| }; |
| |
| spicc2_pins: spicc2_pins { |
| mux { |
| groups = "spi_c_mosi", |
| "spi_c_miso", |
| //"spi_c_ss0",used as GPIOC_3 |
| "spi_c_clk"; |
| function = "spi_c"; |
| drive-strength-microamp = <2000>; |
| }; |
| }; |
| |
| spifc_all_pins: spifc_all_pins { |
| mux { |
| groups = "spif_hold", |
| "spif_mo", |
| "spif_mi", |
| "spif_clk", |
| "spif_wp", |
| "spif_cs"; |
| function = "spif"; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| }; |
| |
| &gpu{ |
| reg = <0 0xFE400000 0 0x04000>, /*mali APB bus base address*/ |
| <0 0xFE002000 0 0x01000>, /*reset register*/ |
| <0 0xFF800000 0 0x01000>, /*aobus TODO update*/ |
| <0 0xFE000000 0 0x01000>, /*hiubus for clk cntl*/ |
| <0 0xFE002000 0 0x01000>; /*reset register*/ |
| |
| interrupts = <0 144 4>, <0 145 4>, <0 146 4>; |
| interrupt-names = "GPU", "MMU", "JOB"; |
| num_of_pp = <2>; |
| system-coherency = <31>; |
| clocks = <&clkc CLKID_MALI>; |
| clock-names = "gpu_mux"; |
| |
| /* |
| * Mali clocking is provided by two identical clock paths |
| * MALI_0 and MALI_1 muxed to a single clock by a glitch |
| * free mux to safely change frequency while running. |
| */ |
| assigned-clocks = <&clkc CLKID_MALI_0_SEL>, |
| <&clkc CLKID_MALI_0>, |
| <&clkc CLKID_MALI>; /* Glitch free mux */ |
| assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, |
| <0>, /* Do Nothing */ |
| <&clkc CLKID_MALI_0>; |
| assigned-clock-rates = <0>, /* Do Nothing */ |
| <800000000>, |
| <0>; /* Do Nothing */ |
| |
| tbl = <&dvfs250_cfg |
| &dvfs400_cfg |
| &dvfs500_cfg |
| &dvfs666_cfg |
| &dvfs800_cfg |
| &dvfs800_cfg>; |
| |
| reset_cfg:reset_cfg { |
| reg_level = <0x11>; |
| reg_mask = <0x21>; |
| reg_bit = <2>; |
| }; |
| |
| capb_reset:capb_reset { |
| reg_level = <0x11>; |
| reg_mask = <0x21>; |
| reg_bit = <1>; |
| }; |
| }; |
