| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2021 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __DT_BINDINGS_T5W_AOCLKC_H |
| #define __DT_BINDINGS_T5W_AOCLKC_H |
| |
| #define CLKID_AO_CLK81 0 |
| #define CLKID_SARADC_MUX 1 |
| #define CLKID_SARADC_DIV 2 |
| #define CLKID_SARADC_GATE 3 |
| #define CLKID_AO_AHB_BUS 4 |
| #define CLKID_AO_IR 5 |
| #define CLKID_AO_I2C_MASTER 6 |
| #define CLKID_AO_I2C_SLAVE 7 |
| #define CLKID_AO_UART1 8 |
| #define CLKID_AO_PROD_I2C 9 |
| #define CLKID_AO_UART2 10 |
| #define CLKID_AO_IR_BLASTER 11 |
| #define CLKID_AO_SAR_ADC 12 |
| #define CLKID_CECB_32K_CLKIN 13 |
| #define CLKID_CECB_32K_DIV 14 |
| #define CLKID_CECB_32K_MUX_PRE 15 |
| #define CLKID_CECB_32K_CLKOUT 16 |
| |
| #define NR_AOCLKS 17 |
| |
| #endif /* __DT_BINDINGS_T5W_AOCLKC_H */ |
