| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef _DT_BINDINGS_AMLOGIC_MESON_T3_RESET_H |
| #define _DT_BINDINGS_AMLOGIC_MESON_T3_RESET_H |
| |
| /* RESET0 */ |
| /* 0-1 */ |
| #define RESET_U2PHY23 2 |
| #define RESET_U2PHY22 3 |
| #define RESET_USB 4 |
| #define RESET_U2DRD 5 |
| #define RESET_U3DRD 6 |
| #define RESET_U3DRD_PIPE0 7 |
| /* 8 */ |
| #define RESET_U2PHY21 9 |
| /* 10 */ |
| #define RESET_HDMI20_AES 11 |
| #define RESET_HDMIRX 12 |
| #define RESET_HDMIRX_APB 13 |
| /* 14 */ |
| #define RESET_VPU_HDMI_AXI 15 |
| /* 16 */ |
| #define RESET_BRG_VCBUS_DEC 17 |
| #define RESET_VCBUS 18 |
| #define RESET_VID_PLL_DIV 19 |
| #define RESET_VDI6_RST_N 20 |
| #define RESET_GE2D 21 |
| /* 22 */ |
| #define RESET_VID_LOCK 23 |
| #define RESET_VENC0 24 |
| #define RESET_VDAC 25 |
| #define RESET_VENC2 26 |
| #define RESET_VENC1 27 |
| #define RESET_RDMA 28 |
| /* 29 */ |
| #define RESET_VIU 30 |
| #define RESET_VENC 31 |
| |
| /* RESET1 */ |
| #define RESET_AUDIOG 32 |
| #define RESET_MALI_CAPB3G 33 |
| #define RESET_MALIG 34 |
| #define RESET_DDRPLLG 35 |
| #define RESET_DMCG 36 |
| #define RESET_DOS_CAPB3G 37 |
| #define RESET_DOSG 38 |
| /* 39-40 */ |
| #define RESET_I_DEBUGA 41 |
| #define RESET_M31_UTMIG 42 |
| #define RESET_I_DSPA 43 |
| #define RESET_PCIE_AG 44 |
| #define RESET_PCIE_PHYG 45 |
| #define RESET_PCIE_APBG 46 |
| #define RESET_PCIEPHY_PIPEG 47 |
| #define RESET_ETHG 48 |
| /* 49-50 */ |
| #define RESET_COMBO_DPHY_CHAN0 51 |
| #define RESET_COMBO_DPHY_CHAN1 52 |
| /* 53-55 */ |
| #define RESET_DMC1G 56 |
| #define RESET_DEMODG 57 |
| /* 58-61 */ |
| #define RESET_DDR1PLLG 62 |
| /* 63 */ |
| |
| /* RESET2 */ |
| /* 64 */ |
| #define RESET_RESET_N_IR_CTRL 65 |
| /* 66-67 */ |
| #define RESET_RESET_N_SPICC_2 68 |
| #define RESET_TCON 69 |
| /* 70-71 */ |
| #define RESET_SMART_CARD 72 |
| #define RESET_SPICC_0 73 |
| #define RESET_SPICC_1 74 |
| #define RESET_RSA 75 |
| /* 76 */ |
| #define RESET_FRC_APB 77 |
| #define RESET_FRC_RDMA 78 |
| #define RESET_FRC 79 |
| #define RESET_MSR_CLK 80 |
| #define RESET_SPIFC 81 |
| #define RESET_SAR_ADC 82 |
| #define RESET_BT 83 |
| /* 84-87 */ |
| #define RESET_ACODEC 88 |
| #define RESET_CEC 89 |
| #define RESET_AFIFO 90 |
| #define RESET_WATCHDOG 91 |
| /* 92 */ |
| #define RESET_TVFE 93 |
| #define RESET_ATV_DMD 94 |
| #define RESET_ADEC 95 |
| |
| /* RESET3 */ |
| #define RESET_BRG_RSA_AP_PIPEL 96 |
| #define RESET_BRG_PCIETONOCDEV_PIPEL 97 |
| #define RESET_BRG_AMPIPE_NANA_RESETN 98 |
| #define RESET_BRG_CPUTONOCSYS_PIPEL 99 |
| /* 100-126*/ |
| #define RESET_A55_ACE 127 |
| |
| /* RESET4 */ |
| /* 128-131 */ |
| #define RESET_PWM_AB 132 |
| #define RESET_PWM_CD 133 |
| #define RESET_PWM_EF 134 |
| #define RESET_PWM_GH 135 |
| #define RESET_PWM_IJ 136 |
| /* 137 */ |
| #define RESET_UART_A 138 |
| #define RESET_UART_B 139 |
| #define RESET_UART_C 140 |
| #define RESET_UART_D 141 |
| #define RESET_NNA 142 |
| #define RESET_CIPLUS 143 |
| #define RESET_I2C_S_A 144 |
| #define RESET_I2C_M_A 145 |
| #define RESET_I2C_M_B 146 |
| #define RESET_I2C_M_C 147 |
| #define RESET_I2C_M_D 148 |
| #define RESET_I2C_M_E 149 |
| /* 150-152 */ |
| #define RESET_SD_EMMC_B 153 |
| #define RESET_SD_EMMC_C 154 |
| /* 155 */ |
| #define RESET_TS_CPU 156 |
| #define RESET_TS_NNA 157 |
| #define RESET_TS_VPU 158 |
| /* 159 */ |
| |
| /* RESET5 */ |
| #define RESET_BRG_NOCDDR_DDR1 160 |
| #define RESET_BRG_NOCDDR_DDR0 161 |
| #define RESET_BRG_NOCDDR_MAIN 162 |
| #define RESET_BRG_NOCDDR_ALL 163 |
| #define RESET_BRG_NOCDDR_GPU 164 |
| #define RESET_BRG_NOCDDR_CPU 165 |
| #define RESET_BRG_NOCDDR_NNA 166 |
| /* 167 */ |
| #define RESET_BRG_NOCDEV_SYS 168 |
| #define RESET_BRG_NOCDEV_MAIN 169 |
| #define RESET_BRG_NOCDEV_HDMI 170 |
| #define RESET_BRG_NOCDEV_ALL 171 |
| /* 172 */ |
| #define RESET_BRG_NOCDOS_VDEC 173 |
| #define RESET_BRG_NOCDOS_HECVF 174 |
| #define RESET_BRG_NOCDOS_HEVCB 175 |
| #define RESET_BRG_NOCDOS_HCODEC 176 |
| #define RESET_BRG_NOCDOS_GE2D 177 |
| /* 178 */ |
| #define RESET_BRG_NOCDOS_SYS 179 |
| #define RESET_BRG_NOCDOS_MAIN 180 |
| #define RESET_BRG_NOCDOS_ALL 181 |
| #define RESET_BRG_NOCVPU_MAIN 182 |
| #define RESET_BRG_NOCVPU_ALL 183 |
| #define RESET_BRG_NOCVPU_SYS 184 |
| #define RESET_BRG_NOCSYS_CPU 185 |
| /* 186 */ |
| #define RESET_BRG_NOCSYS_DSPA 187 |
| #define RESET_BRG_NOCSYS_VAPB 188 |
| #define RESET_BRG_NOCSYS_SYS 189 |
| #define RESET_BRG_NOCSYS_MAIN 190 |
| #define RESET_BRG_NOCSYS_ALL 191 |
| |
| /* RESET6 */ |
| #define RESET_BRG_VDEC_PIPEL 192 |
| #define RESET_BRG_HEVCF_DMC_PIPEL 193 |
| #define RESET_BRG_VPU_TOP_APB_PIPEL 194 |
| #define RESET_BRG_HDMIRXTONOCDEV_PIPEL 195 |
| #define RESET_BRG_MALITONOCDDR_PIPEL 196 |
| #define RESET_BRG_NOCVPUTONOCDDR_PIPEL 197 |
| #define RESET_BRG_NOCSYSTONOCDDR_PIPEL 198 |
| #define RESET_BRG_NOCDOSTONOCDDR_PIPEL 199 |
| #define RESET_BRG_NOCDEVTONOCDDR_PIPEL 200 |
| #define RESET_BRG_CPUTONOCDDR_PIPEL 201 |
| /* 202 */ |
| #define RESET_BRG_NOCDOS_APB_PIPEL 203 |
| /* 204 */ |
| #define RESET_BRG_DSPTONOCSYS_PIPEL 205 |
| #define RESET_BRG_USB3TONOCDEV_PIPEL 206 |
| #define RESET_BRG_USB2TONOCDEV_PIPEL 207 |
| #define RESET_BRG_ETH_HDMIRX_APB_PIPEL 208 |
| #define RESET_BRG_DOS_APB_PIPEL 209 |
| #define RESET_BRG_GE2D_APB_PIPEL 210 |
| #define RESET_BRG_ACODEC_APB_PIPEL 211 |
| #define RESET_BRG_USB_PCIE_CTRL_APB_PIPEL 212 |
| #define RESET_BRG_USB_PCIE_PHY_APB_PIPEL 213 |
| #define RESET_BRG_ETH_AHB_PIPEL 214 |
| #define RESET_BRG_USB0_AHB_PIPEL 215 |
| #define RESET_BRG_USB1_AHB_PIPEL 216 |
| #define RESET_BRG_USB2_AHB_PIPEL 217 |
| #define RESET_BRG_USB2DEVTONOCDEV_AHB_PIPEL 218 |
| #define RESET_BRG_AMPIPE_ETH_RESETN 219 |
| #define RESET_BRG_FRC_TOP_APB_PIPEL 220 |
| #define RESET_BRG_AM2AXI0_RESETN 221 |
| #define RESET_BRG_AM2AXI1_RESETN 222 |
| #define RESET_BRG_AM2AXI2_RESETN 223 |
| |
| #endif |
