| /* |
| * Copyright (c) 2017, 2020-2021, The Linux Foundation. All rights reserved. |
| * |
| * Permission to use, copy, modify, and/or distribute this software for any |
| * purpose with or without fee is hereby granted, provided that the above |
| * copyright notice and this permission notice appear in all copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| */ |
| |
| &soc { |
| tmc_etr: tmc@6048000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb961>; |
| |
| reg = <0x6048000 0x1000>, |
| <0x6064000 0x15000>; |
| reg-names = "tmc-base", "bam-base"; |
| memory-region = <&q6_etr_region>; |
| |
| interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "byte-cntr-irq"; |
| |
| arm,buffer-size = <0x100000>; |
| arm,sg-enable; |
| |
| coresight-ctis = <&cti0 &cti8>; |
| coresight-name = "coresight-tmc-etr"; |
| |
| funnel-address = <0x6041000 0x1000>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port{ |
| tmc_etr_in_replicator: endpoint { |
| slave-mode; |
| remote-endpoint = <&replicator_out_tmc_etr>; |
| }; |
| }; |
| }; |
| |
| replicator: replicator@6046000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb909>; |
| |
| reg = <0x6046000 0x1000>; |
| reg-names = "replicator-base"; |
| |
| coresight-name = "coresight-replicator"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports{ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| replicator_out_tmc_etr:endpoint { |
| remote-endpoint = |
| <&tmc_etr_in_replicator>; |
| }; |
| }; |
| port@1 { |
| reg = <0>; |
| replicator_in_tmc_etf:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&tmc_etf_out_replicator>; |
| }; |
| }; |
| }; |
| }; |
| |
| tmc_etf: tmc@6047000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb961>; |
| |
| reg = <0x6047000 0x1000>; |
| reg-names = "tmc-base"; |
| |
| coresight-ctis = <&cti0 &cti8>; |
| coresight-name = "coresight-tmc-etf"; |
| arm,default-sink; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports{ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| tmc_etf_out_replicator:endpoint { |
| remote-endpoint = |
| <&replicator_in_tmc_etf>; |
| }; |
| }; |
| port@1 { |
| reg = <0>; |
| tmc_etf_in_funnel_in0:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_in0_out_tmc_etf>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_in0: funnel@6041000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0x6041000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-in0"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_in0_out_tmc_etf:endpoint { |
| remote-endpoint = |
| <&tmc_etf_in_funnel_in0>; |
| }; |
| }; |
| port@1 { |
| reg = <3>; |
| funnel_in0_in_funnel_center:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_center_out_funnel_in0>; |
| }; |
| }; |
| port@2 { |
| reg = <4>; |
| funnel_in0_in_funnel_right:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_right_out_funnel_in0>; |
| }; |
| }; |
| port@3 { |
| reg = <5>; |
| funnel_in0_in_funnel_mm:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_mm_out_funnel_in0>; |
| }; |
| }; |
| port@4 { |
| reg = <6>; |
| funnel_in0_in_tpda:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&tpda_out_funnel_in0>; |
| }; |
| }; |
| port@5 { |
| reg = <7>; |
| funnel_in0_in_stm:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&stm_out_funnel_in0>; |
| }; |
| }; |
| port@6 { |
| reg = <0>; |
| funnel_in0_in_rpm_etm0:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&rpm_etm0_out_funnel_in0>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_center: funnel@6100000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0x6100000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-center"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_center_out_funnel_in0:endpoint { |
| remote-endpoint = |
| <&funnel_in0_in_funnel_center>; |
| }; |
| }; |
| port@1 { |
| reg = <2>; |
| funnel_center_in_dbgui:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&dbgui_out_funnel_center>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_right: funnel@6120000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0x6120000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-right"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_right_out_funnel_in0:endpoint { |
| remote-endpoint = |
| <&funnel_in0_in_funnel_right>; |
| }; |
| }; |
| port@1 { |
| reg = <3>; |
| funnel_right_in_funnel_apss0:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_apss0_out_funnel_right>; |
| }; |
| }; |
| }; |
| |
| }; |
| |
| funnel_mm: funnel@6130000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0x6130000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-mm"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_mm_out_funnel_in0:endpoint { |
| remote-endpoint = |
| <&funnel_in0_in_funnel_mm>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <6>; |
| funnel_mm_in_atb:endpoint { |
| slave-mode; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_apss0: funnel@61a1000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0x61a1000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-apss0"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_apss0_out_funnel_right:endpoint { |
| remote-endpoint = |
| <&funnel_right_in_funnel_apss0>; |
| }; |
| }; |
| port@1 { |
| reg = <0>; |
| funnel_apss0_in_etm0:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&etm0_out_funnel_apss0>; |
| }; |
| }; |
| port@2 { |
| reg = <1>; |
| funnel_apss0_in_etm1:endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&etm1_out_funnel_apss0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm0: etm@619c000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0x619c000 0x1000>; |
| |
| coresight-name = "coresight-etm0"; |
| cpu = <&CPU0>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port{ |
| etm0_out_funnel_apss0:endpoint { |
| remote-endpoint = <&funnel_apss0_in_etm0>; |
| }; |
| }; |
| }; |
| |
| etm1: etm@619d000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0x619d000 0x1000>; |
| |
| coresight-name = "coresight-etm1"; |
| cpu = <&CPU1>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port{ |
| etm1_out_funnel_apss0:endpoint { |
| remote-endpoint = <&funnel_apss0_in_etm1>; |
| }; |
| }; |
| }; |
| |
| rpm_etm0 { |
| compatible = "qcom,coresight-remote-etm"; |
| |
| coresight-name = "coresight-rpm-etm0"; |
| qcom,inst-id = <4>; |
| |
| port{ |
| rpm_etm0_out_funnel_in0: endpoint { |
| remote-endpoint = <&funnel_in0_in_rpm_etm0>; |
| }; |
| }; |
| }; |
| |
| stm: stm@6002000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb962>; |
| |
| reg = <0x6002000 0x1000>, |
| <0x9280000 0x180000>; |
| reg-names = "stm-base", "stm-stimulus-base"; |
| |
| coresight-name = "coresight-stm"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port{ |
| stm_out_funnel_in0:endpoint { |
| remote-endpoint = <&funnel_in0_in_stm>; |
| }; |
| }; |
| }; |
| |
| cti0: cti@6010000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6010000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti0"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti1: cti@6011000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6011000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti1"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti2: cti@6012000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6012000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti2"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti3: cti@6013000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6013000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti3"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti4: cti@6014000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6014000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti4"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti5: cti@6015000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6015000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti5"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti6: cti@6016000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6016000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti6"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti7: cti@6017000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6017000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti7"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti8: cti@6018000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6018000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti8"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti9: cti@6019000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6019000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti9"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti10: cti@601a000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x601a000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti10"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti11: cti@601b000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x601b000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti11"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti12: cti@601c000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x601c000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti12"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti13: cti@601d000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x601d000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti13"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti14: cti@601e000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x601e000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti14"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti15: cti@601f000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x601f000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti15"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti_cpu0: cti@6198000{ |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6198000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu0"; |
| cpu = <&CPU0>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti_cpu1: cti@6199000{ |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x6199000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu1"; |
| cpu = <&CPU1>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| cti_rpm_cpu0: cti@610c000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| reg = <0x610c000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-rpm-cpu0"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| csr: csr@6001000 { |
| compatible = "qcom,coresight-csr"; |
| reg = <0x6001000 0x1000>; |
| reg-names = "csr-base"; |
| |
| coresight-name = "coresight-csr"; |
| qcom,blk-size = <1>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| |
| dbgui: dbgui@6108000 { |
| compatible = "qcom,coresight-dbgui"; |
| reg = <0x6108000 0x1000>; |
| reg-names = "dbgui-base"; |
| |
| coresight-name = "coresight-dbgui"; |
| |
| qcom,dbgui-addr-offset = <0x30>; |
| qcom,dbgui-data-offset = <0x130>; |
| qcom,dbgui-size = <64>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port{ |
| dbgui_out_funnel_center:endpoint { |
| remote-endpoint = <&funnel_center_in_dbgui>; |
| }; |
| }; |
| }; |
| |
| tpda: tpda@6004000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b969>; |
| reg = <0x6004000 0x1000>; |
| reg-names = "tpda-base"; |
| |
| coresight-name = "coresight-tpda"; |
| |
| qcom,tpda-atid = <64>; |
| qcom,cmb-elem-size = <0 32>; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| port@0 { |
| reg=<0>; |
| tpda_out_funnel_in0:endpoint { |
| remote-endpoint = <&funnel_in0_in_tpda>; |
| }; |
| }; |
| port@1 { |
| reg=<0>; |
| tpda_in_tpdm_dcc: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&tpdm_dcc_out_tpda>; |
| }; |
| }; |
| }; |
| }; |
| |
| tpdm_dcc: tpdm@6110000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b968>; |
| reg = <0x6110000 0x1000>; |
| reg-names = "tpdm-base"; |
| |
| coresight-name = "coresight-tpdm-dcc"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port{ |
| tpdm_dcc_out_tpda:endpoint { |
| remote-endpoint = <&tpda_in_tpdm_dcc>; |
| }; |
| }; |
| }; |
| |
| hwevent: hwevent@6101000 { |
| compatible = "qcom,coresight-hwevent"; |
| reg = <0x6101000 0x148>, |
| <0x6101fb0 0x4>, |
| <0x6121000 0x148>, |
| <0x6121fb0 0x4>, |
| <0x6131000 0x148>, |
| <0x6131fb0 0x4>, |
| <0x6130fb0 0x4>, |
| <0x6130000 0x148>, |
| <0x6041fb0 0x4>, |
| <0x6041000 0x148>; |
| reg-names = "center-wrapper-mux", "center-wrapper-lockaccess", |
| "right-wrapper-mux", "right-wrapper-lockaccess", |
| "mm-wrapper-mux", "mm-wrapper-lockaccess", |
| "mm-fun-lockaccess", "mm-fun", "in-fun-lockaccess", |
| "in-fun"; |
| |
| coresight-name = "coresight-hwevent"; |
| |
| clocks = <&gcc GCC_QDSS_DAP_CLK>, |
| <&gcc GCC_QDSS_AT_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| no-ports; |
| }; |
| }; |