| /dts-v1/; |
| /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
| * |
| * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. |
| * |
| * Permission to use, copy, modify, and/or distribute this software for any |
| * purpose with or without fee is hereby granted, provided that the above |
| * copyright notice and this permission notice appear in all copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| */ |
| |
| #include "ipq5018-mp03.1.dts" |
| |
| / { |
| model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2"; |
| compatible = "qcom,ipq5018-ap-mp03.1-c2", "qcom,ipq5018-mp03.1", "qcom,ipq5018"; |
| |
| aliases { |
| serial0 = &blsp1_uart1; |
| ethernet0 = "/soc/dp1"; |
| ethernet1 = "/soc/dp2"; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| bootargs-append = " swiotlb=1 clk_ignore_unused"; |
| }; |
| soc { |
| qpic_bam: dma@7984000{ |
| status = "disabled"; |
| }; |
| |
| nand: qpic-nand@79b0000 { |
| status = "disabled"; |
| }; |
| |
| wifi0: wifi@c000000 { |
| status = "ok"; |
| }; |
| |
| mdio0: mdio@88000 { |
| status = "ok"; |
| |
| ethernet-phy@0 { |
| reg = <7>; |
| }; |
| }; |
| |
| mdio1: mdio@90000 { |
| status = "ok"; |
| pinctrl-0 = <&mdio1_pins>; |
| pinctrl-names = "default"; |
| phy-reset-gpio = <&tlmm 39 0>; |
| ethernet-phy@0 { |
| reg = <0>; |
| }; |
| |
| ethernet-phy@1 { |
| reg = <1>; |
| }; |
| |
| ethernet-phy@2 { |
| reg = <2>; |
| }; |
| |
| ethernet-phy@3 { |
| reg = <3>; |
| }; |
| }; |
| |
| ess-instance { |
| num_devices = <0x2>; |
| ess-switch@0x39c00000 { |
| compatible = "qcom,ess-switch-ipq50xx"; |
| device_id = <0>; |
| switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/ |
| cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/ |
| qcom,port_phyinfo { |
| port@0 { |
| port_id = <1>; |
| phy_address = <7>; |
| }; |
| port@1 { |
| port_id = <2>; |
| forced-speed = <1000>; |
| forced-duplex = <1>; |
| }; |
| }; |
| led_source@0 { |
| source = <0>; |
| mode = "normal"; |
| speed = "all"; |
| blink_en = "enable"; |
| active = "high"; |
| }; |
| }; |
| ess-switch1@1 { |
| compatible = "qcom,ess-switch-qca83xx"; |
| device_id = <1>; |
| switch_access_mode = "mdio"; |
| mdio-bus = <&mdio1>; |
| reset_gpio = <&tlmm 0x27 0>; |
| switch_cpu_bmp = <0x40>; /* cpu port bitmap */ |
| switch_lan_bmp = <0x1e>; /* lan port bitmap */ |
| switch_wan_bmp = <0x0>; /* wan port bitmap */ |
| qca,ar8327-initvals = < |
| 0x00004 0x7600000 /* PAD0_MODE */ |
| 0x00008 0x1000000 /* PAD5_MODE */ |
| 0x0000c 0x80 /* PAD6_MODE */ |
| 0x00010 0x2613a0 /* PORT6 FORCE MODE*/ |
| 0x000e4 0xaa545 /* MAC_POWER_SEL */ |
| 0x000e0 0xc74164de /* SGMII_CTRL */ |
| 0x0007c 0x4e /* PORT0_STATUS */ |
| 0x00094 0x4e /* PORT6_STATUS */ |
| >; |
| qcom,port_phyinfo { |
| port@0 { |
| port_id = <1>; |
| phy_address = <0>; |
| }; |
| port@1 { |
| port_id = <2>; |
| phy_address = <1>; |
| }; |
| port@2 { |
| port_id = <3>; |
| phy_address = <2>; |
| }; |
| port@3 { |
| port_id = <4>; |
| phy_address = <3>; |
| }; |
| }; |
| }; |
| }; |
| |
| dp1 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>; |
| clock-names = "nss-snoc-gmac-axi-clk"; |
| qcom,id = <1>; |
| reg = <0x39C00000 0x10000>; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,mactype = <2>; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <7>; |
| mdio-bus = <&mdio0>; |
| local-mac-address = [000000000000]; |
| phy-mode = "sgmii"; |
| qcom,rx-page-mode = <0>; |
| }; |
| |
| dp2 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>; |
| clock-names = "nss-snoc-gmac-axi-clk"; |
| qcom,id = <2>; |
| reg = <0x39D00000 0x10000>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,mactype = <2>; |
| local-mac-address = [000000000000]; |
| phy-mode = "sgmii"; |
| qcom,rx-page-mode = <0>; |
| }; |
| }; |
| }; |
| &tlmm { |
| pinctrl-0 = <&serial_1_pins &phy_led_pins>; |
| pinctrl-names = "default"; |
| |
| serial_1_pins: serial1-pinmux { |
| pins = "gpio31", "gpio32", "gpio33", "gpio34"; |
| function = "blsp1_uart1"; |
| drive-strength = <8>; |
| bias-pull-down; |
| }; |
| |
| mdio1_pins: mdio_pinmux { |
| mux_0 { |
| pins = "gpio36"; |
| function = "mdc"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| mux_1 { |
| pins = "gpio37"; |
| function = "mdio"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| }; |
| |
| phy_led_pins: phy_led_pins { |
| gephy_led_pin { |
| pins = "gpio46"; |
| function = "led0"; |
| drive-strength = <8>; |
| bias-pull-down; |
| }; |
| }; |
| emmc_pins: emmc_pins { |
| emmc_clk { |
| pins = "gpio9"; |
| function = "sdc1_clk"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| emmc_cmd { |
| pins = "gpio8"; |
| function = "sdc1_cmd"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| emmc_data_0 { |
| pins = "gpio7"; |
| function = "sdc10"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| emmc_data_1 { |
| pins = "gpio6"; |
| function = "sdc11"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| emmc_data_2 { |
| pins = "gpio5"; |
| function = "sdc12"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| emmc_data_3 { |
| pins = "gpio4"; |
| function = "sdc13"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| &sdhc_1 { |
| pinctrl-0 = <&emmc_pins>; |
| pinctrl-names = "default"; |
| qcom,clk-rates = <400000 25000000 50000000 100000000 \ |
| 192000000 384000000>; |
| qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; |
| qcom,nonremovable; |
| status = "ok"; |
| }; |
| |
| |
| |
| &blsp1_uart1 { |
| status = "ok"; |
| }; |
| |
| &pcie_x2 { |
| status = "ok"; |
| perst-gpio = <&tlmm 15 1>; |
| }; |
| |
| &pcie_x2phy { |
| status = "ok"; |
| }; |
| |
| &pcie_x2_rp { |
| status = "ok"; |
| mhi_1: qcom,mhi@1 { |
| reg = <0 0 0 0 0 >; |
| qrtr_instance_id = <0x20>; |
| #address-cells = <0x2>; |
| #size-cells = <0x2>; |
| memory-region = <&mhi_region1>; |
| #if !defined(__CNSS2__) |
| qrtr_node_id = <0x20>; |
| base-addr = <0x4CC00000>; |
| m3-dump-addr = <0x4E000000>; |
| etr-addr = <0x4E100000>; |
| qcom,caldb-addr = <0x4E200000>; |
| qcom,tgt-mem-mode = <0x1>; |
| mhi,max-channels = <30>; |
| mhi,timeout = <10000>; |
| #endif |
| }; |
| }; |
