| // SPDX-License-Identifier: GPL-2.0-only |
| /dts-v1/; |
| /* Copyright (c) 2020 The Linux Foundation. All rights reserved. |
| */ |
| #include "ipq8074-hk01.dtsi" |
| #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> |
| |
| / { |
| model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK01-C5"; |
| compatible = "qcom,ipq8074-ap-hk01-c5", "qcom,ipq8074-ap-hk01", "qcom,ipq8074"; |
| |
| soc { |
| |
| pinctrl@1000000 { |
| mdio_pins: mdio_pinmux { |
| mux_0 { |
| pins = "gpio68"; |
| function = "mdc"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| mux_1 { |
| pins = "gpio69"; |
| function = "mdio"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| }; |
| |
| pcie_sdx_pins: pcie_sdx_pinmux { |
| ap2mdm_err_ftl { |
| pins = "gpio27"; |
| function = "gpio"; |
| drive-strength = <8>; |
| bias-pull-down; |
| }; |
| |
| sdx_pon_gpio { |
| pins = "gpio30"; |
| function = "gpio"; |
| drive-strength = <8>; |
| bias-pull-up; |
| output-high; |
| }; |
| |
| ap2mdm_status { |
| pins = "gpio26"; |
| function = "gpio"; |
| drive-strength = <8>; |
| bias-pull-up; |
| output-high; |
| }; |
| |
| mdm2ap_e911_status { |
| pins = "gpio33"; |
| drive-strength = <8>; |
| bias-pull-down; |
| }; |
| }; |
| |
| pcie_wake_pins: pcie0_wake_gpio { |
| pins = "gpio59"; |
| function = "pcie0_wake"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| }; |
| |
| gpio_keys { |
| status = "disabled"; |
| }; |
| |
| i2c@78b6000 { |
| status = "disabled"; |
| }; |
| |
| mdio@90000 { |
| pinctrl-0 = <&mdio_pins>; |
| pinctrl-names = "default"; |
| phy-reset-gpio = <&tlmm 37 0>; |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| phy1: ethernet-phy@1 { |
| reg = <1>; |
| }; |
| phy2: ethernet-phy@2 { |
| reg = <2>; |
| }; |
| phy3: ethernet-phy@3 { |
| reg = <3>; |
| }; |
| phy4: ethernet-phy@4 { |
| reg = <4>; |
| }; |
| phy5: ethernet-phy@5 { |
| compatible ="ethernet-phy-ieee802.3-c45"; |
| reg = <7>; |
| }; |
| }; |
| |
| dp1 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| qcom,id = <1>; |
| reg = <0x3a001000 0x200>; |
| qcom,mactype = <0>; |
| local-mac-address = [000000000000]; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <0>; |
| phy-mode = "sgmii"; |
| }; |
| |
| dp2 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| qcom,id = <2>; |
| reg = <0x3a001200 0x200>; |
| qcom,mactype = <0>; |
| local-mac-address = [000000000000]; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <1>; |
| phy-mode = "sgmii"; |
| }; |
| |
| dp3 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| qcom,id = <3>; |
| reg = <0x3a001400 0x200>; |
| qcom,mactype = <0>; |
| local-mac-address = [000000000000]; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <2>; |
| phy-mode = "sgmii"; |
| }; |
| |
| dp4 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| qcom,id = <4>; |
| reg = <0x3a001600 0x200>; |
| qcom,mactype = <0>; |
| local-mac-address = [000000000000]; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <3>; |
| phy-mode = "sgmii"; |
| }; |
| |
| dp5 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| qcom,id = <5>; |
| reg = <0x3a001800 0x200>; |
| qcom,mactype = <0>; |
| local-mac-address = [000000000000]; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <4>; |
| phy-mode = "sgmii"; |
| }; |
| |
| dp6 { |
| device_type = "network"; |
| compatible = "qcom,nss-dp"; |
| qcom,id = <6>; |
| reg = <0x3a007000 0x3fff>; |
| qcom,mactype = <1>; |
| local-mac-address = [000000000000]; |
| qcom,link-poll = <1>; |
| qcom,phy-mdio-addr = <7>; |
| phy-mode = "sgmii"; |
| }; |
| |
| ess-switch@3a000000 { |
| switch_cpu_bmp = <0x1>; /* cpu port bitmap */ |
| switch_lan_bmp = <0x3e>; /* lan port bitmap */ |
| switch_wan_bmp = <0x40>; /* wan port bitmap */ |
| switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ |
| switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/ |
| switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/ |
| bm_tick_mode = <0>; /* bm tick mode */ |
| tm_tick_mode = <0>; /* tm tick mode */ |
| port_scheduler_resource { |
| port@0 { |
| port_id = <0>; |
| ucast_queue = <0 143>; |
| mcast_queue = <256 271>; |
| l0sp = <0 35>; |
| l0cdrr = <0 47>; |
| l0edrr = <0 47>; |
| l1cdrr = <0 7>; |
| l1edrr = <0 7>; |
| }; |
| port@1 { |
| port_id = <1>; |
| ucast_queue = <144 159>; |
| mcast_queue = <272 275>; |
| l0sp = <36 39>; |
| l0cdrr = <48 63>; |
| l0edrr = <48 63>; |
| l1cdrr = <8 11>; |
| l1edrr = <8 11>; |
| }; |
| port@2 { |
| port_id = <2>; |
| ucast_queue = <160 175>; |
| mcast_queue = <276 279>; |
| l0sp = <40 43>; |
| l0cdrr = <64 79>; |
| l0edrr = <64 79>; |
| l1cdrr = <12 15>; |
| l1edrr = <12 15>; |
| }; |
| port@3 { |
| port_id = <3>; |
| ucast_queue = <176 191>; |
| mcast_queue = <280 283>; |
| l0sp = <44 47>; |
| l0cdrr = <80 95>; |
| l0edrr = <80 95>; |
| l1cdrr = <16 19>; |
| l1edrr = <16 19>; |
| }; |
| port@4 { |
| port_id = <4>; |
| ucast_queue = <192 207>; |
| mcast_queue = <284 287>; |
| l0sp = <48 51>; |
| l0cdrr = <96 111>; |
| l0edrr = <96 111>; |
| l1cdrr = <20 23>; |
| l1edrr = <20 23>; |
| }; |
| port@5 { |
| port_id = <5>; |
| ucast_queue = <208 223>; |
| mcast_queue = <288 291>; |
| l0sp = <52 55>; |
| l0cdrr = <112 127>; |
| l0edrr = <112 127>; |
| l1cdrr = <24 27>; |
| l1edrr = <24 27>; |
| }; |
| port@6 { |
| port_id = <6>; |
| ucast_queue = <224 239>; |
| mcast_queue = <292 295>; |
| l0sp = <56 59>; |
| l0cdrr = <128 143>; |
| l0edrr = <128 143>; |
| l1cdrr = <28 31>; |
| l1edrr = <28 31>; |
| }; |
| port@7 { |
| port_id = <7>; |
| ucast_queue = <240 255>; |
| mcast_queue = <296 299>; |
| l0sp = <60 63>; |
| l0cdrr = <144 159>; |
| l0edrr = <144 159>; |
| l1cdrr = <32 35>; |
| l1edrr = <32 35>; |
| }; |
| }; |
| port_scheduler_config { |
| port@0 { |
| port_id = <0>; |
| l1scheduler { |
| group@0 { |
| sp = <0 1>; /*L0 SPs*/ |
| /*cpri cdrr epri edrr*/ |
| cfg = <0 0 0 0>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| /*unicast queues*/ |
| ucast_queue = <0 4 8>; |
| /*multicast queues*/ |
| mcast_queue = <256 260>; |
| /*sp cpri cdrr epri edrr*/ |
| cfg = <0 0 0 0 0>; |
| }; |
| group@1 { |
| ucast_queue = <1 5 9>; |
| mcast_queue = <257 261>; |
| cfg = <0 1 1 1 1>; |
| }; |
| group@2 { |
| ucast_queue = <2 6 10>; |
| mcast_queue = <258 262>; |
| cfg = <0 2 2 2 2>; |
| }; |
| group@3 { |
| ucast_queue = <3 7 11>; |
| mcast_queue = <259 263>; |
| cfg = <0 3 3 3 3>; |
| }; |
| }; |
| }; |
| port@1 { |
| port_id = <1>; |
| l1scheduler { |
| group@0 { |
| sp = <36>; |
| cfg = <0 8 0 8>; |
| }; |
| group@1 { |
| sp = <37>; |
| cfg = <1 9 1 9>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <144>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <272>; |
| mcast_loop_pri = <4>; |
| cfg = <36 0 48 0 48>; |
| }; |
| }; |
| }; |
| port@2 { |
| port_id = <2>; |
| l1scheduler { |
| group@0 { |
| sp = <40>; |
| cfg = <0 12 0 12>; |
| }; |
| group@1 { |
| sp = <41>; |
| cfg = <1 13 1 13>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <160>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <276>; |
| mcast_loop_pri = <4>; |
| cfg = <40 0 64 0 64>; |
| }; |
| }; |
| }; |
| port@3 { |
| port_id = <3>; |
| l1scheduler { |
| group@0 { |
| sp = <44>; |
| cfg = <0 16 0 16>; |
| }; |
| group@1 { |
| sp = <45>; |
| cfg = <1 17 1 17>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <176>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <280>; |
| mcast_loop_pri = <4>; |
| cfg = <44 0 80 0 80>; |
| }; |
| }; |
| }; |
| port@4 { |
| port_id = <4>; |
| l1scheduler { |
| group@0 { |
| sp = <48>; |
| cfg = <0 20 0 20>; |
| }; |
| group@1 { |
| sp = <49>; |
| cfg = <1 21 1 21>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <192>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <284>; |
| mcast_loop_pri = <4>; |
| cfg = <48 0 96 0 96>; |
| }; |
| }; |
| }; |
| port@5 { |
| port_id = <5>; |
| l1scheduler { |
| group@0 { |
| sp = <52>; |
| cfg = <0 24 0 24>; |
| }; |
| group@1 { |
| sp = <53>; |
| cfg = <1 25 1 25>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <208>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <288>; |
| mcast_loop_pri = <4>; |
| cfg = <52 0 112 0 112>; |
| }; |
| }; |
| }; |
| port@6 { |
| port_id = <6>; |
| l1scheduler { |
| group@0 { |
| sp = <56>; |
| cfg = <0 28 0 28>; |
| }; |
| group@1 { |
| sp = <57>; |
| cfg = <1 29 1 29>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <224>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <292>; |
| mcast_loop_pri = <4>; |
| cfg = <56 0 128 0 128>; |
| }; |
| }; |
| }; |
| port@7 { |
| port_id = <7>; |
| l1scheduler { |
| group@0 { |
| sp = <60>; |
| cfg = <0 32 0 32>; |
| }; |
| group@1 { |
| sp = <61>; |
| cfg = <1 33 1 33>; |
| }; |
| }; |
| l0scheduler { |
| group@0 { |
| ucast_queue = <240>; |
| ucast_loop_pri = <16>; |
| mcast_queue = <296>; |
| cfg = <60 0 144 0 144>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| }; |
| |
| &spmi_bus { |
| pmic@0 { |
| compatible ="qcom,spmi-pmic"; |
| reg = <0x0 SPMI_USID>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pm8074_gpios: gpios@c000 { |
| compatible = "qcom,pm8074-gpio"; |
| reg = <0xc000>; |
| gpio-controller; |
| gpio-ranges = <&pm8074_gpios 0 0 12>; |
| #gpio-cells = <2>; |
| interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, |
| <0 0xc1 0 IRQ_TYPE_NONE>, |
| <0 0xc2 0 IRQ_TYPE_NONE>, |
| <0 0xc3 0 IRQ_TYPE_NONE>, |
| <0 0xc4 0 IRQ_TYPE_NONE>, |
| <0 0xc5 0 IRQ_TYPE_NONE>, |
| <0 0xc6 0 IRQ_TYPE_NONE>, |
| <0 0xc7 0 IRQ_TYPE_NONE>, |
| <0 0xc8 0 IRQ_TYPE_NONE>, |
| <0 0xc9 0 IRQ_TYPE_NONE>, |
| <0 0xca 0 IRQ_TYPE_NONE>, |
| <0 0xcb 0 IRQ_TYPE_NONE>; |
| pinctrl-0 = <&pm8074_gpio>; |
| pinctrl-names = "default"; |
| |
| pm8074_gpio: pmm8074_gpio { |
| pinconf { |
| pins = "gpio6"; |
| function = PMIC_GPIO_FUNC_NORMAL; |
| bias-pull-up; |
| output-high; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| &pcie0 { |
| pinctrl-0 = <&pcie_sdx_pins>, <&pcie_wake_pins>; |
| pinctrl-names = "default"; |
| e911-gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>; |
| |
| interrupts-extended = <&tlmm 59 IRQ_TYPE_LEVEL_HIGH>, |
| <&tlmm 33 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "wake_gpio", "mdm2ap_e911"; |
| |
| link_retries_count = <100>; |
| |
| status = "ok"; |
| |
| pcie0_rp: pcie0_rp { |
| reg = <0 0 0 0 0>; |
| }; |
| }; |
| |
| &pcie0_rp { |
| #address-cells = <5>; |
| #size-cells = <0>; |
| |
| status = "ok"; |
| aliases { |
| mhi_netdev2 = &mhi_netdev_2; |
| }; |
| mhi_0: qcom,mhi@0 { |
| reg = <0 0 0 0 0 >; |
| |
| ap2mdm-gpio = <&tlmm 26 0>; |
| mdm2ap-gpio = <&tlmm 25 0>; |
| |
| // controller specific configuration |
| qcom,iommu-dma = "disabled"; |
| |
| // mhi bus specific settings |
| mhi,ssr-negotiate; |
| |
| mhi_devices: mhi_devices { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mhi_netdev_0: mhi_rmnet@0 { |
| reg = <0x0>; |
| mhi,chan = "IP_HW0"; |
| mhi,interface-name = "rmnet_mhi"; |
| mhi,mru = <0x4000>; |
| mhi,chain-skb; |
| }; |
| |
| mhi_rmnet@1 { |
| reg = <0x1>; |
| mhi,chan = "IP_HW0_RSC"; |
| mhi,mru = <0x8000>; |
| mhi,rsc-parent = <&mhi_netdev_0>; |
| }; |
| |
| mhi_netdev_2: mhi_rmnet@2 { |
| reg = <0x2>; |
| mhi,chan = "IP_SW0"; |
| mhi,interface-name = "rmnet_mhi_sw"; |
| mhi,mru = <0x4000>; |
| mhi,disable-chain-skb; |
| }; |
| |
| mhi_qrtr { |
| mhi,chan = "IPCR"; |
| qom,net-id = <3>; |
| }; |
| }; |
| |
| }; |
| }; |
