drivers/net/wireless/ath/ath11k/pci.h

/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
 */
#ifndef _ATH11K_PCI_H
#define _ATH11K_PCI_H

#include <linux/mhi.h>
#include <linux/msi.h>

#include "core.h"

#define PCIE_SOC_GLOBAL_RESET			0x3008
#define PCIE_SOC_GLOBAL_RESET_V			1

#define WLAON_WARM_SW_ENTRY			0x1f80504
#define WLAON_SOC_RESET_CAUSE_REG		0x01f8060c

#define PCIE_Q6_COOKIE_ADDR			0x01f80500
#define PCIE_Q6_COOKIE_DATA			0xc0000000

/* register to wake the UMAC from power collapse */
#define PCIE_SCRATCH_0_SOC_PCIE_REG		0x4040

/* register used for handshake mechanism to validate UMAC is awake */
#define PCIE_SOC_WAKE_PCIE_LOCAL_REG		0x3004
#define ATH11K_MAX_PCI_DOMAINS 2

#define PCIE_PCIE_PARF_LTSSM			0x1e081b0
#define PARM_LTSSM_VALUE			0x111

#define GCC_GCC_PCIE_HOT_RST			0x1e402bc
#define GCC_GCC_PCIE_HOT_RST_VAL		0x10

#define PCIE_PCIE_INT_ALL_CLEAR			0x1e08228
#define PCIE_SMLH_REQ_RST_LINK_DOWN		0x2
#define PCIE_INT_CLEAR_ALL			0xffffffff

#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \
		(ab->hw_params.regs->pcie_qserdes_sysclk_en_sel)
#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL	0x10
#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK	0xffffffff
#define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \
		(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base)
#define PCIE_PCS_OSC_DTCT_CONFIG1_VAL		0x02
#define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \
		(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)
#define PCIE_PCS_OSC_DTCT_CONFIG2_VAL		0x52
#define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \
		(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)
#define PCIE_PCS_OSC_DTCT_CONFIG4_VAL		0xff
#define PCIE_PCS_OSC_DTCT_CONFIG_MSK		0x000000ff

#define WLAON_QFPROM_PWR_CTRL_REG		0x01f8031c
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK		0x4

#define STR_CONV(str) #str

#define ATH11K_PCI_DP_IRQS_NAME(x) \
	STR_CONV(pci##x##_wbm2host_tx_completions_ring1),\
	STR_CONV(pci##x##_wbm2host_tx_completions_ring2),\
	STR_CONV(pci##x##_wbm2host_tx_completions_ring3),\
	STR_CONV(pci##x##_lmac_reo_misc_irq),\
	STR_CONV(pci##x##_reo2host_destination_ring1),\
	STR_CONV(pci##x##_reo2host_destination_ring2),\
	STR_CONV(pci##x##_reo2host_destination_ring3),\
	STR_CONV(pci##x##_reo2host_destination_ring4),\
	/* Currently only 8 msi are registered */ \
	STR_CONV(pci##x##_dp_res1),\
	STR_CONV(pci##x##_dp_res2),\
	STR_CONV(pci##x##_dp_res3),\

#define ATH11K_PCI_CE_IRQS_NAME(x) \
	STR_CONV(pci##x##_ce0),\
	STR_CONV(pci##x##_ce1),\
	STR_CONV(pci##x##_ce2),\
	STR_CONV(pci##x##_ce3),\
	STR_CONV(pci##x##_ce4),\
	STR_CONV(pci##x##_ce5),\
	STR_CONV(pci##x##_ce6),\
	STR_CONV(pci##x##_ce7),\
	STR_CONV(pci##x##_ce8),\
	STR_CONV(pci##x##_ce9),\
	STR_CONV(pci##x##_ce10),\
	STR_CONV(pci##x##_ce11),\

struct ath11k_msi_user {
	char *name;
	int num_vectors;
	u32 base_vector;
};

struct ath11k_msi_config {
	int total_vectors;
	int total_users;
	struct ath11k_msi_user *users;
};

enum ath11k_pci_flags {
	ATH11K_PCI_FLAG_INIT_DONE,
	ATH11K_PCI_FLAG_IS_MSI_64,
	ATH11K_PCI_ASPM_RESTORE,
};

enum ath11k_msi_supported_hw {
	ATH11K_MSI_CONFIG_QCA6390,
	ATH11K_MSI_CONFIG_QCN9074,
	ATH11K_MSI_CONFIG_QCN6122,
};

static const struct ath11k_msi_config ath11k_msi_config[] = {
	{
		.total_vectors = 32,
		.total_users = 4,
		.users = (struct ath11k_msi_user[]) {
			{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
			{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
			{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
			{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
		},
	},
	{
		.total_vectors = 16,
		.total_users = 3,
		.users = (struct ath11k_msi_user[]) {
			{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
			{ .name = "CE", .num_vectors = 5, .base_vector = 3 },
			{ .name = "DP", .num_vectors = 8, .base_vector = 8 },
		},
	},
	{
		.total_vectors = 13,
		.total_users = 2,
		.users = (struct ath11k_msi_user[]) {
			{ .name = "CE", .num_vectors = 5, .base_vector = 0 },
			{ .name = "DP", .num_vectors = 8, .base_vector = 5 },
		},
	},
};

struct ath11k_pci {
	struct pci_dev *pdev;
	struct ath11k_base *ab;
	u16 dev_id;
	char amss_path[100];
	u32 msi_ep_base_data;
	struct mhi_controller *mhi_ctrl;
	const struct ath11k_msi_config *msi_config;
	unsigned long mhi_state;
	u32 register_window;

	/* protects register_window above */
	spinlock_t window_lock;

	/* enum ath11k_pci_flags */
	unsigned long flags;
	u16 link_ctl;
};

static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
{
	return (struct ath11k_pci *)ab->drv_priv;
}

int ath11k_pci_get_user_msi_assignment(struct ath11k_base *ab,
				       const struct ath11k_msi_config *msi_config,
				       u32 msi_ep_base_data, char *user_name,
				       int *num_vectors, u32 *user_base_data,
				       u32 *base_vector);
int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector);
void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
int ath11k_pci_start(struct ath11k_base *ab);
void ath11k_pci_stop(struct ath11k_base *ab);
void ath11k_pci_ext_irq_enable(struct ath11k_base *ab);
void ath11k_pci_ext_irq_disable(struct ath11k_base *ab);
void ath11k_pci_get_qgic_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
				     u32 *msi_addr_hi);
int ath11k_get_user_qgic_msi_assignment(struct ath11k_base *ab, char *user_name,
					int *num_vectors, u32 *user_base_data,
					u32 *base_vector);
int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
				   u8 *ul_pipe, u8 *dl_pipe);
u32 ath11k_pci_get_window_offset(struct ath11k_base *ab,
				 u32 offset);
void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id,
			       u32 *msi_idx);
void ath11k_pci_config_static_window(struct ath11k_base *ab);
void ath11k_pci_free_irq(struct ath11k_base *ab);
int ath11k_ipci_start(struct ath11k_base *ab);
void ath11k_ipci_write32(struct ath11k_base *ab, u32 offset, u32 value);
u32 ath11k_ipci_read32(struct ath11k_base *ab, u32 offset);
int ath11k_pci_config_gic_msi_irq(struct ath11k_base *ab, struct platform_device *pdev,
		struct msi_desc *msi_desc, int i);
int ath11k_pci_ext_config_gic_msi_irq(struct ath11k_base *ab, struct platform_device *pdev,
		struct msi_desc *msi_desc, int i);
#endif