| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2021 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/gpio/meson-t5w-gpio.h> |
| #include <dt-bindings/input/meson_rc.h> |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/pwm/pwm.h> |
| #include <dt-bindings/pwm/meson.h> |
| #include <dt-bindings/reset/amlogic,meson-t5w-reset.h> |
| #include <dt-bindings/clock/t5w-clkc.h> |
| #include <dt-bindings/clock/t5w-aoclkc.h> |
| #include <dt-bindings/power/t5-pd.h> |
| #include <dt-bindings/mailbox/amlogic,mbox.h> |
| #include <dt-bindings/clock/amlogic,t3-audio-clk.h> |
| #include "mesong12a-bifrost.dtsi" |
| #include "meson-ir-map.dtsi" |
| #include <dt-bindings/thermal/thermal.h> |
| #include <dt-bindings/iio/adc/amlogic-saradc.h> |
| |
| / { |
| compatible = "amlogic"; |
| |
| cpus:cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| #cooling-cells = <2>;/* min followed by max */ |
| CPU0:cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x0>; |
| //timer=<&timer_a>; |
| enable-method = "psci"; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_CLK_DYN>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_CLK_FINAL>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| operating-points-v2 = <&cpu_opp_table0>; |
| cpu-supply = <&vddcpu0>; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <80>; |
| #cooling-cells = <2>; |
| }; |
| |
| CPU1:cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x1>; |
| // //timer=<&timer_b>; |
| enable-method = "psci"; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_CLK_DYN>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_CLK_FINAL>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| operating-points-v2 = <&cpu_opp_table0>; |
| cpu-supply = <&vddcpu0>; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <80>; |
| #cooling-cells = <2>; |
| }; |
| |
| CPU2:cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x2>; |
| // //timer=<&timer_c>; |
| enable-method = "psci"; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_CLK_DYN>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_CLK_FINAL>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| operating-points-v2 = <&cpu_opp_table0>; |
| cpu-supply = <&vddcpu0>; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <80>; |
| #cooling-cells = <2>; |
| }; |
| |
| CPU3:cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55","arm,armv8"; |
| reg = <0x0 0x3>; |
| // //timer=<&timer_d>; |
| enable-method = "psci"; |
| clocks = <&clkc CLKID_CPU_CLK>, |
| <&clkc CLKID_CPU_CLK_DYN>, |
| <&clkc CLKID_SYS_PLL>, |
| <&clkc CLKID_DSU_CLK>, |
| <&clkc CLKID_DSU_CLK_FINAL>; |
| clock-names = "core_clk", |
| "low_freq_clk_parent", |
| "high_freq_clk_parent", |
| "dsu_clk", |
| "dsu_pre_parent"; |
| operating-points-v2 = <&cpu_opp_table0>; |
| cpu-supply = <&vddcpu0>; |
| cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>; |
| voltage-tolerance = <0>; |
| clock-latency = <50000>; |
| dynamic-power-coefficient = <80>; |
| #cooling-cells = <2>; |
| }; |
| |
| idle-states { |
| entry-method = "arm,psci"; |
| CPU_SLEEP_0: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0010000>; |
| local-timer-stop; |
| entry-latency-us = <5000>; |
| exit-latency-us = <5000>; |
| min-residency-us = <20000>; |
| }; |
| SYSTEM_SLEEP_0: system-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0000000>; |
| entry-latency-us = <0x3fffffff>; |
| exit-latency-us = <0x40000000>; |
| min-residency-us = <0xffffffff>; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 0xff01>, |
| <GIC_PPI 14 0xff01>, |
| <GIC_PPI 11 0xff01>, |
| <GIC_PPI 10 0xff01>; |
| }; |
| |
| timer_bc { |
| //compatible = "arm,bc-timer"; |
| status = "disabled"; |
| reg = <0x0 0xffd0f190 0x0 0x4 0x0 0xffd0f194 0x0 0x4>; |
| timer_name = "Meson TimerF"; |
| clockevent-rating =<300>; |
| clockevent-shift =<20>; |
| clockevent-features =<0x23>; |
| interrupts = <0 60 1>; |
| bit_enable =<16>; |
| bit_mode =<12>; |
| bit_resolution =<0>; |
| }; |
| |
| vrtc: rtc@ff8000a8 { |
| compatible = "amlogic,meson-vrtc"; |
| reg = <0x0 0xff8000a8 0x0 0x4>; |
| status = "okay"; |
| mboxes = <&mbox_pl 1>; |
| }; |
| |
| reboot { |
| compatible = "aml, reboot"; |
| sys_reset = <0x84000009>; |
| sys_poweroff = <0x84000008>; |
| reg = <0x0 0xff80023c 0x0 0x4>; /* AO_SEC_SD_CFG15 */ |
| status = "okay"; |
| }; |
| |
| arm_pmu { |
| compatible = "arm,armv8-pmuv3"; |
| private-interrupts; |
| /* clusterb-enabled; */ |
| interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
| |
| reg = <0x0 0xff634680 0x0 0x4>; |
| cpumasks = <0xf>; |
| /* default 10ms */ |
| relax-timer-ns = <10000000>; |
| /* default 10000us */ |
| max-wait-cnt = <10000>; |
| }; |
| |
| vbat: fixedregulator0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vbat"; |
| regulator-min-microvolt = <12000000>; |
| regulator-max-microvolt = <12000000>; |
| regulator-always-on; |
| }; |
| |
| vcc5v_reg: fixedregulator@1{ |
| vin-supply = <&vbat>; |
| compatible = "regulator-fixed"; |
| regulator-name = "VCC_5V"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vddq_reg: fixedregulator@2 { |
| compatible = "regulator-fixed"; |
| vin-supply = <&vbat>; |
| regulator-name = "VDDQ"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vddao3v3_reg: fixedregulator@3{ |
| vin-supply = <&vbat>; |
| compatible = "regulator-fixed"; |
| regulator-name = "VDDAO_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vddao1v8_reg: fixedregulator@4{ |
| vin-supply = <&vddao3v3_reg>; |
| compatible = "regulator-fixed"; |
| regulator-name = "VDDAO_1V8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| gic: interrupt-controller@2c001000 { |
| compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <2>; |
| interrupt-controller; |
| reg = <0x0 0xffc01000 0x0 0x1000>, |
| <0x0 0xffc02000 0x0 0x0100>; |
| interrupts = <GIC_PPI 9 0xf04>; |
| }; |
| |
| secmon { |
| compatible = "amlogic, secmon"; |
| memory-region = <&secmon_reserved>; |
| in_base_func = <0x82000020>; |
| out_base_func = <0x82000021>; |
| inout_size_func = <0x8200002a>; |
| reserve_mem_size = <0x00300000>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| xtal: xtal-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| aml_pm { |
| compatible = "amlogic, pm"; |
| status = "okay"; |
| device_name = "aml_pm"; |
| reg = <0x0 0xff8000a8 0x0 0x4>, /*SYSCTRL_STATUS_REG2*/ |
| <0x0 0xff6345cc 0x0 0x4>; /*PREG_STICKY_REG3*/ |
| }; |
| |
| cpuinfo { |
| compatible = "amlogic, cpuinfo"; |
| status = "okay"; |
| cpuinfo_cmd = <0x82000044>; |
| }; |
| |
| vddcpu0: pwmb-regulator { |
| compatible = "pwm-regulator"; |
| pwms = <&pwm_ab MESON_PWM_1 1500 0>; |
| regulator-name = "vddcpu0"; |
| regulator-min-microvolt = <690000>; |
| regulator-max-microvolt = <1050000>; |
| regulator-always-on; |
| max-duty-cycle = <1500>; |
| /* Voltage Duty-Cycle */ |
| voltage-table = <1050000 0>, |
| <1040000 3>, |
| <1030000 6>, |
| <1020000 9>, |
| <1010000 12>, |
| <1000000 14>, |
| <990000 17>, |
| <980000 20>, |
| <970000 23>, |
| <960000 26>, |
| <950000 29>, |
| <940000 31>, |
| <930000 34>, |
| <920000 37>, |
| <910000 40>, |
| <900000 43>, |
| <890000 45>, |
| <880000 48>, |
| <870000 51>, |
| <860000 54>, |
| <850000 56>, |
| <840000 59>, |
| <830000 62>, |
| <820000 65>, |
| <810000 68>, |
| <800000 70>, |
| <790000 73>, |
| <780000 76>, |
| <770000 79>, |
| <760000 81>, |
| <750000 84>, |
| <740000 87>, |
| <730000 89>, |
| <720000 92>, |
| <710000 95>, |
| <700000 98>, |
| <690000 100>; |
| status = "okay"; |
| }; |
| |
| cpu_opp_table0: cpu_opp_table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp00 { |
| opp-hz = /bits/ 64 <100000000>; |
| opp-microvolt = <790000>; |
| }; |
| opp01 { |
| opp-hz = /bits/ 64 <250000000>; |
| opp-microvolt = <790000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <790000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <667000000>; |
| opp-microvolt = <790000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <800000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <810000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1392000000>; |
| opp-microvolt = <830000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1512000000>; |
| opp-microvolt = <850000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <880000>; |
| }; |
| opp09 { |
| opp-hz = /bits/ 64 <1704000000>; |
| opp-microvolt = <910000>; |
| }; |
| opp10 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <970000>; |
| }; |
| opp11 { |
| opp-hz = /bits/ 64 <1920000000>; |
| opp-microvolt = <1010000>; |
| }; |
| }; |
| |
| cpufreq-meson { |
| compatible = "amlogic, cpufreq-meson"; |
| status = "okay"; |
| }; |
| |
| efuse: efuse { |
| compatible = "amlogic, efuse"; |
| read_cmd = <0x82000030>; |
| write_cmd = <0x82000031>; |
| get_max_cmd = <0x82000033>; |
| mem_in_base_cmd = <0x82000020>; |
| mem_out_base_cmd = <0x82000021>; |
| key = <&efusekey>; |
| clocks = <&clkc CLKID_CLK81_EFUSE>; |
| clock-names = "efuse_clk"; |
| status = "okay"; |
| }; |
| |
| efusekey: efusekey { |
| keynum = <4>; |
| key0 = <&key_0>; |
| key1 = <&key_1>; |
| key2 = <&key_2>; |
| key3 = <&key_3>; |
| key_0:key_0 { |
| keyname = "mac"; |
| offset = <0>; |
| size = <6>; |
| }; |
| key_1:key_1 { |
| keyname = "mac_bt"; |
| offset = <6>; |
| size = <6>; |
| }; |
| key_2:key_2 { |
| keyname = "mac_wifi"; |
| offset = <12>; |
| size = <6>; |
| }; |
| key_3:key_3 { |
| keyname = "usid"; |
| offset = <18>; |
| size = <16>; |
| }; |
| }; |
| |
| defendkey: defendkey { |
| compatible = "amlogic, defendkey"; |
| reg=<0x0 0xff800228 0x0 0x4>; |
| mem_size = <0x100000>; |
| status = "okay"; |
| }; |
| |
| provisionkey { |
| compatible = "amlogic, provisionkey"; |
| status = "okay"; |
| key-permit-default = "write"; |
| //new key not need add dts if started with KEY_PROVISION_ |
| KEY_PROVISION_XXX { }; |
| //test_my_added_keyname { }; |
| };//End provisionkey |
| |
| fb: fb { |
| compatible = "amlogic, fb-t5w"; |
| memory-region = <&logo_reserved>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 56 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; |
| /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ |
| display_mode_default = "1080p60hz"; |
| scale_mode = <1>; |
| /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ |
| display_size_default = <1920 1080 1920 2160 32>; |
| /*1920*1080*4*3 = 0x17BB000*/ |
| display_device_cnt = <2>; |
| /* for fixed path: OSD3->VPP1 */ |
| }; |
| |
| vpu: vpu { |
| compatible = "amlogic, vpu-t5w"; |
| status = "okay"; |
| clocks = <&clkc CLKID_VAPB>, |
| <&clkc CLKID_VPU_0>, |
| <&clkc CLKID_VPU_1>, |
| <&clkc CLKID_VPU>, |
| <&clkc CLKID_CLK81_VPU_INTR>; |
| clock-names = "vapb_clk", |
| "vpu_clk0", |
| "vpu_clk1", |
| "vpu_clk", |
| "vpu_intr_gate"; |
| reg = <0x0 0xff646000 0x0 0x200 /* clk */ |
| 0x0 0xff644000 0x0 0x100 /* pwrctrl */ |
| 0x0 0xff900000 0x0 0xa000>; /* vcbus */ |
| clk_level = <7>; |
| /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ |
| /* 4: 333.3M 5: 400.0M */ |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| aobus: aobus@ff800000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xff800000 0x0 0xb000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff800000 0x0 0xb000>; |
| |
| cpu_version { |
| reg = <0x0 0x220 0x0 0x4>; |
| }; |
| |
| rti: sys-ctrl@0 { |
| compatible = "amlogic,meson-gx-ao-sysctrl", |
| "simple-mfd", "syscon"; |
| reg = <0x0 0x0 0x0 0x300>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0x0 0x0 0x300>; |
| |
| sec_AO: ao-secure@140 { |
| compatible = "amlogic,meson-gx-ao-secure", |
| "syscon"; |
| reg = <0x0 0x140 0x0 0x140>; |
| amlogic,has-chip-id; |
| }; |
| |
| clkc_AO: clock-controller@2 { |
| compatible = "amlogic,t5w-aoclkc"; |
| #clock-cells = <1>; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| }; |
| }; |
| |
| remote: rc@8040 { |
| compatible = "amlogic, meson-ir"; |
| reg = <0x0 0x8040 0x0 0xA4>, |
| <0x0 0x8000 0x0 0x20>; |
| status = "okay"; |
| protocol = <REMOTE_TYPE_NEC>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&remote_pins>; |
| map = <&custom_maps>; |
| max_frame_time = <200>; |
| }; |
| |
| irblaster: meson-irblaster@14c { |
| compatible = "amlogic, meson_irblaster"; |
| reg = <0x0 0x14c 0x0 0x10>, |
| <0x0 0x40 0x0 0x4>; |
| #irblaster-cells = <2>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| pinctrl_aobus: pinctrl@14 { |
| compatible = "amlogic,meson-t5w-aobus-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio_ao: ao-bank@14 { |
| reg = <0x0 0x14 0x0 0x8>, |
| <0x0 0x24 0x0 0x14>, |
| <0x0 0x1c 0x0 0x8>; |
| reg-names = "mux", "gpio", "ds"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_aobus 0 0 13>; |
| }; |
| }; |
| |
| }; |
| |
| pinctrl_periphs: pinctrl@ff6346c0 { |
| compatible = "amlogic,meson-t5w-periphs-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio: banks@ff6346c0 { |
| reg = <0x0 0xff6346c0 0x0 0xb0>, |
| <0x0 0xff6344e8 0x0 0x18>, |
| <0x0 0xff634520 0x0 0x18>, |
| <0x0 0xff634440 0x0 0x4c>; |
| reg-names = "mux", |
| "pull", |
| "pull-enable", |
| "gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_periphs 0 0 118>; |
| }; |
| }; |
| |
| crg: crg@ff500000 { |
| compatible = "amlogic, crg"; |
| status = "disabled"; |
| reg = <0x0 0xff500000 0x0 0x100000>; |
| interrupts = <0 30 4>; |
| usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>; |
| cpu-type = "gxl"; |
| clock-src = "usb3.0"; |
| clocks = <&clkc CLKID_CLK81_USB_GENERAL>; |
| clock-names = "crg_general"; |
| }; |
| |
| usb2_phy_v2: usb2phy@ffe09000 { |
| compatible = "amlogic, amlogic-new-usb2-v2"; |
| status = "disabled"; |
| reg = <0x0 0xffe09000 0x0 0x80 |
| 0x0 0xffd01008 0x0 0x100 |
| 0x0 0xff636000 0x0 0x2000 |
| 0x0 0xff63a000 0x0 0x2000 |
| 0x0 0xff658000 0x0 0x2000>; |
| pll-setting-1 = <0x09400414>; |
| pll-setting-2 = <0x927E0000>; |
| pll-setting-3 = <0xac5f69e5>; |
| pll-setting-4 = <0xbe18>; |
| pll-setting-5 = <0x7>; |
| pll-setting-6 = <0x78000>; |
| pll-setting-7 = <0xe0004>; |
| pll-setting-8 = <0xe000c>; |
| version = <3>; |
| pwr-ctl = <0>; |
| usb-phy-trim-reg = <0xff800270>; |
| }; |
| |
| usb3_phy_v2: usb3phy@ffe09080 { |
| compatible = "amlogic, amlogic-new-usb3-v2"; |
| status = "disable"; |
| reg = <0x0 0xffe09080 0x0 0x20 |
| 0x0 0xffd01008 0x0 0x100>; |
| phy-reg = <0xff646000>; |
| phy-reg-size = <0x2000>; |
| usb2-phy-reg = <0xffe09000>; |
| usb2-phy-reg-size = <0x80>; |
| interrupts = <0 16 4>; |
| pwr-ctl = <0>; |
| }; |
| |
| dwc2_a: dwc2_a@ff400000 { |
| compatible = "amlogic, dwc2"; |
| status = "disabled"; |
| device_name = "dwc2_a"; |
| reg = <0x0 0xff400000 0x0 0x40000>; |
| interrupts = <0 31 4>; |
| pl-periph-id = <0>; /** lm name */ |
| clock-src = "usb0"; /** clock src */ |
| port-id = <0>; /** ref to mach/usb.h */ |
| port-type = <2>; /** 0: otg, 1: host, 2: slave */ |
| port-speed = <0>; /** 0: default, high, 1: full */ |
| port-config = <0>; /** 0: default */ |
| /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ |
| port-dma = <0>; |
| port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ |
| usb-fifo = <728>; |
| cpu-type = "v2"; |
| phy-reg = <0xffe09000>; |
| phy-reg-size = <0xa0>; |
| /** phy-interface: 0x0: amlogic-v1 phy, 0x1: synopsys phy **/ |
| /** 0x2: amlogic-v2 phy **/ |
| phy-interface = <0x2>; |
| clocks = <&clkc CLKID_CLK81_USB_GENERAL |
| &clkc CLKID_CLK81_USB1_TO_DDR>; |
| clock-names = "usb_general", |
| "usb1"; |
| }; |
| |
| dolby_fw: dolby_fw { |
| compatible = "amlogic, dolby_fw"; |
| mem_size = <0x100000>; |
| status = "okay"; |
| }; |
| |
| aml_dma { |
| compatible = "amlogic,aml_txlx_dma"; |
| reg = <0x0 0xff63e000 0x0 0x48>; |
| interrupts = <0 180 1>; |
| |
| aml_aes { |
| compatible = "amlogic,aes_g12a_dma"; |
| dev_name = "aml_aes_dma"; |
| status = "okay"; |
| }; |
| |
| aml_sha { |
| compatible = "amlogic,sha_dma"; |
| dev_name = "aml_sha_dma"; |
| status = "okay"; |
| }; |
| |
| aml_tdes { |
| compatible = "amlogic,tdes_dma"; |
| dev_name = "aml_tdes_dma"; |
| status = "okay"; |
| }; |
| }; |
| |
| cbus: cbus@ffd00000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xffd00000 0x0 0x27000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x27000>; |
| |
| gpio_intc: interrupt-controller@f080 { |
| compatible = "amlogic,meson-gpio-intc", |
| "amlogic,meson-t5w-gpio-intc"; |
| reg = <0x0 0xf080 0x0 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| amlogic,channel-interrupts = |
| <64 65 66 67 68 69 70 71>; |
| }; |
| |
| wdt: watchdog@0f0d0 { |
| compatible = "amlogic,meson-gxbb-wdt"; |
| status = "okay"; |
| /* 0:userspace, 1:kernel */ |
| amlogic,feed_watchdog_mode = <1>; |
| reg = <0x0 0xf0d0 0x0 0x10>; |
| clocks = <&xtal>; |
| }; |
| |
| clk-measure@18000 { |
| compatible = "amlogic,meson-t5w-clk-measure"; |
| reg = <0x0 0x18000 0x0 0x10>; |
| }; |
| |
| i2c0: i2c@1f000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x1f000 0x0 0x20>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_CLK81_I2C>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@1e000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x1e000 0x0 0x20>; |
| interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_CLK81_I2C>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@1d000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x1d000 0x0 0x20>; |
| interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_CLK81_I2C>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@1c000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0x1c000 0x0 0x20>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_CLK81_I2C>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| pwm_ab: pwm@1b000 { |
| compatible = "amlogic,meson-t5d-ee-pwm"; |
| reg = <0x0 0x1b000 0x0 0x20>; |
| #pwm-cells = <3>; |
| clocks = <&xtal>, |
| <&xtal>, |
| <&xtal>, |
| <&xtal>; |
| clock-names = "clkin0", |
| "clkin1", |
| "clkin2", |
| "clkin3"; |
| /* default xtal 24m clkin0-clkin2 and |
| * clkin1-clkin3 should be set the same |
| */ |
| status = "okay"; |
| }; |
| |
| pwm_cd: pwm@1a000 { |
| compatible = "amlogic,meson-t5d-ee-pwm"; |
| reg = <0x0 0x1a000 0x0 0x20>; |
| #pwm-cells = <3>; |
| clocks = <&xtal>, |
| <&xtal>, |
| <&xtal>, |
| <&xtal>; |
| clock-names = "clkin0", |
| "clkin1", |
| "clkin2", |
| "clkin3"; |
| status = "disabled"; |
| }; |
| |
| pwm_ef: pwm@19000 { |
| compatible = "amlogic,meson-t5d-ee-pwm"; |
| reg = <0x0 0x19000 0x0 0x20>; |
| #pwm-cells = <3>; |
| clocks = <&xtal>, |
| <&xtal>, |
| <&xtal>, |
| <&xtal>; |
| clock-names = "clkin0", |
| "clkin1", |
| "clkin2", |
| "clkin3"; |
| status = "disabled"; |
| }; |
| |
| uart_A: serial@24000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x24000 0x0 0x18>; |
| interrupts = <0 26 1>; |
| status = "disabled"; |
| clocks = <&xtal |
| &clkc CLKID_CLK81_UART0>; |
| clock-names = "clk_uart", |
| "clk_gate"; |
| fifosize = < 128 >; |
| #pinctrl-names = "default"; |
| #pinctrl-0 = <&a_uart_pins0>; |
| }; |
| |
| uart_B: serial@23000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x23000 0x0 0x18>; |
| interrupts = <0 75 1>; |
| status = "okay"; |
| clocks = <&xtal>; |
| clock-names = "clk_uart"; |
| xtal_tick_en = <2>; |
| fifosize = < 64 >; |
| /* 0 not support; 1 support */ |
| support-sysrq = <0>; |
| }; |
| |
| uart_C: serial@22000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x22000 0x0 0x18>; |
| interrupts = <0 93 1>; |
| status = "disabled"; |
| clocks = <&xtal |
| &clkc CLKID_CLK81_UART2>; |
| clock-names = "clk_uart", |
| "clk_gate"; |
| fifosize = < 64 >; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&c_uart_pins>; |
| }; |
| |
| reset: reset-controller@1004 { |
| compatible = "amlogic,meson-t5d-reset"; |
| reg = <0x0 0x1004 0x0 0x9C>; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| sd_emmc_c: mmc@ffe07000 { |
| compatible = "amlogic,meson-axg-mmc"; |
| reg = <0x0 0xffe07000 0x0 0x800>, |
| <0x0 0xff64625c 0x0 0x4>, |
| <0x0 0xff6346c0 0x0 0x4>; |
| interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&clkc CLKID_SD_EMMC_C>, |
| <&clkc CLKID_SD_EMMC_C_SEL>, |
| <&clkc CLKID_SD_EMMC_C>, |
| // <&clkc CLKID_SD_EMMC_C_MUX>, |
| // <&clkc CLKID_SD_EMMC_C_GATE>, |
| <&xtal>, |
| <&clkc CLKID_GP0_PLL>, |
| <&clkc CLKID_GP0_PLL>; |
| |
| clock-names = "core", "mux0", "mux1", |
| "clkin0", "clkin1", "clkin2"; |
| card_type = <1>; |
| tx_delay = <20>; |
| save_para = <0>; |
| src_clk_rate = <1152000000>; |
| compute_cmd_delay = <0>; |
| compute_coef = <0>; |
| mmc_debug_flag; |
| /* 1:mmc card(include eMMC), |
| * 2:sd card(include tSD) |
| */ |
| }; |
| |
| sd_emmc_b: sd@ffe05000 { |
| compatible = "amlogic,meson-axg-mmc"; |
| reg = <0x0 0xffe05000 0x0 0x800>, |
| <0x0 0xff646264 0x0 0x4>, |
| <0x0 0xff6346fc 0x0 0x4>; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clocks = <&clkc CLKID_SD_EMMC_B>, |
| <&clkc CLKID_SD_EMMC_B_SEL>, |
| <&clkc CLKID_SD_EMMC_B>, |
| <&xtal>, |
| <&clkc CLKID_FCLK_DIV2>; |
| clock-names = "core", "mux0", "mux1", |
| "clkin0", "clkin1"; |
| card_type = <3>; |
| mmc_debug_flag; |
| //resets = <&reset RESET_SD_EMMC_B>; |
| }; |
| |
| mtd_nand: nfc@0xFFE07800 { |
| compatible = "amlogic,meson-nfc-single-ecc"; |
| status = "disabled"; |
| reg = <0x0 0xFFE07800 0x0 0x200>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; |
| |
| pinctrl-names = "nand_norb_mod", "nand_cs_only"; |
| pinctrl-0 = <&all_nand_pins>; |
| pinctrl-1 = <&nand_cs_pins>; |
| clocks = <&clkc CLKID_SD_EMMC_C>, |
| <&clkc CLKID_FCLK_DIV2>; |
| clock-names = "gate", "fdiv2pll"; |
| |
| nand_clk_ctrl = <0xFFE07000>; |
| /*partitions defined in dts*/ |
| }; |
| |
| saradc:saradc { |
| compatible = "amlogic,meson-g12a-saradc"; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| clocks = <&xtal>, |
| <&clkc_AO CLKID_AO_SAR_ADC>, |
| <&clkc_AO CLKID_SARADC_GATE>, |
| <&clkc_AO CLKID_SARADC_MUX>; |
| clock-names = "clkin", "core", |
| "adc_clk", "adc_sel"; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; |
| reg = <0x0 0xff809000 0x0 0x48>; |
| }; |
| |
| clkc: clock-controller@0 { |
| compatible = "amlogic,t5w-clkc"; |
| reg = <0 0xff646000 0 0x400>, |
| <0 0xff63c000 0 0x400>; |
| reg-names = "basic", "cpu"; |
| #clock-cells = <1>; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| status = "okay"; |
| }; |
| |
| pwrdm: power-domains { |
| compatible = "amlogic,t5w-power-domain"; |
| #power-domain-cells = <1>; |
| status = "okay"; |
| }; |
| |
| mbox_pl: mhu@ff63c420 { |
| status = "okay"; |
| compatible = "amlogic, meson_mhu_pl"; |
| reg = <0x0 0xff63c420 0x0 0x4>, /*from ao sts registers */ |
| <0x0 0xff63c428 0x0 0x4>, /*to ao set registers */ |
| <0x0 0xff63c430 0x0 0x4>, /*to ao clr registers */ |
| <0x0 0xfffc7400 0x0 0x400>; /*to ao payload */ |
| interrupts = <0 210 1>, /* ap Rev se*/ |
| <0 136 1>; /* ap Send se*/ |
| mbox-names = "ao_dev", |
| "ap_to_ao"; |
| #mbox-cells = <1>; |
| mboxes = <&mbox_pl 0>, |
| <&mbox_pl 1>; |
| mbox-nums = <2>; |
| mbox-mb = <1>; |
| }; |
| |
| mbox_user: mbox-user@0 { |
| status = "okay"; |
| compatible = "amlogic, meson-mbox-user"; |
| mbox-nums = <1>; |
| mbox-names = "ree2aocpu"; |
| mboxes = <&mbox_pl 1>; |
| mbox-dests = <MAILBOX_AOCPU>; |
| }; |
| |
| jtag { |
| compatible = "amlogic, jtag"; |
| status = "okay"; |
| select = "disable"; /* disable/apao */ |
| interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; |
| pinctrl-names="jtag_a_pins"; |
| pinctrl-0=<&jtag_apao_pins>; |
| }; |
| |
| vclk_serve: vclk_serve { |
| compatible = "amlogic, vclk_serve"; |
| status = "okay"; |
| reg = <0x0 0xff63c000 0x0 0x400 /* ana reg */ |
| 0x0 0xff646000 0x0 0x4a0>; /* clk reg */ |
| }; |
| |
| vout_mux: vout_mux { |
| compatible = "amlogic, vout_mux"; |
| status = "okay"; |
| }; |
| |
| vout: vout { |
| compatible = "amlogic, vout"; |
| status = "okay"; |
| |
| /* fr_policy: |
| * 0: disable |
| * 1: nearby (only for 60->59.94 and 30->29.97) |
| * 2: force (60/50/30/24/59.94/23.97) |
| */ |
| fr_policy = <0>; |
| }; |
| |
| vdac { |
| compatible = "amlogic, vdac-t5w"; |
| status = "okay"; |
| }; |
| |
| adc: adc { |
| compatible = "amlogic, adc-t5w"; |
| status = "okay"; |
| reg = <0x0 0xff654000 0x0 0x2000/* afe reg base */ |
| 0x0 0xff63c000 0x0 0x2000/* hiu base */ |
| >; |
| }; |
| |
| rdma { |
| compatible = "amlogic, meson-t3, rdma"; |
| status = "okay"; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "rdma"; |
| /* after sc2 */ |
| reset-names = "rdma"; |
| resets = <&reset RESET_RDMA>; |
| rdma_table_page_count = <16>; |
| }; |
| |
| audiobus: audiobus@0xff600000 { |
| compatible = "amlogic, audio-controller", "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| reg = <0x0 0xff600000 0x0 0x3000>; |
| ranges = <0x0 0x0 0x0 0xff600000 0x0 0x3000>; |
| chip_id = <0x3b>; |
| clkaudio:audio_clocks { |
| compatible = "amlogic, t3-audio-clocks"; |
| #clock-cells = <1>; |
| reg = <0x0 0x0 0x0 0xb0>; |
| }; |
| ddr_manager { |
| compatible = |
| "amlogic, t5-audio-ddr-manager"; |
| interrupts = < |
| GIC_SPI 148 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 149 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 150 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 48 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 152 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 153 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 154 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 49 IRQ_TYPE_EDGE_RISING |
| >; |
| interrupt-names = |
| "toddr_a", "toddr_b", "toddr_c", |
| "toddr_d", |
| "frddr_a", "frddr_b", "frddr_c", |
| "frddr_d"; |
| }; |
| |
| pinctrl_audio: pinctrl { |
| compatible = "amlogic, audio-pinctrl"; |
| }; |
| };/* end of audiobus*/ |
| |
| /* Sound iomap */ |
| aml_snd_iomap { |
| compatible = "amlogic, snd-iomap"; |
| status = "okay"; |
| #address-cells=<2>; |
| #size-cells=<2>; |
| ranges; |
| pdm_bus { |
| reg = <0x0 0xFF601000 0x0 0x400>; |
| }; |
| audiobus_base { |
| reg = <0x0 0xFF600000 0x0 0x1000>; |
| }; |
| audiolocker_base { |
| reg = <0x0 0xFF601400 0x0 0x400>; |
| }; |
| eqdrc_base { |
| reg = <0x0 0xFF602000 0x0 0x1000>; |
| }; |
| vad_base { |
| reg = <0x0 0xFF601800 0x0 0x400>; |
| }; |
| resampleA_base { |
| reg = <0x0 0xFF601C00 0x0 0x104>; |
| }; |
| resampleB_base { |
| reg = <0x0 0xFF604000 0x0 0x104>; |
| }; |
| }; |
| |
| /* eARC */ |
| audio_earc: bus@ff603000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xff603000 0x0 0x1000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff603000 0x0 0x1000>; |
| earc: earc@0 { |
| compatible = "amlogic, t7-snd-earc"; |
| #sound-dai-cells = <0>; |
| |
| status = "disabled"; |
| |
| reg =<0x0 0x0 0x0 0x400>, |
| <0x0 0x400 0x0 0x200>, |
| <0x0 0x600 0x0 0x200>; |
| reg-names = "tx_cmdc", |
| "tx_dmac", |
| "tx_top"; |
| clocks = < &clkaudio CLKID_EARCTX_CMDC |
| &clkaudio CLKID_EARCTX_DMAC |
| &clkc CLKID_FCLK_DIV4 |
| &clkc CLKID_MPLL2 |
| >; |
| clock-names = |
| "tx_cmdc", |
| "tx_dmac", |
| "tx_cmdc_srcpll", |
| "tx_dmac_srcpll"; |
| |
| interrupts = < |
| GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names ="earc_tx"; |
| }; |
| }; |
| |
| //hdmirx arc |
| hdmirx_arc { |
| compatible = "amlogic, hdmirx-arc-iomap"; |
| reg = <0x0 0xff68c000 0x0 0x3>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff68c000 0x0 0x3>; |
| reg-names = "hdmirx-arc"; |
| }; |
| |
| dummy_codec:dummy { |
| #sound-dai-cells = <0>; |
| compatible = "amlogic, aml_dummy_codec"; |
| status = "okay"; |
| }; |
| |
| acodec:codec { |
| #sound-dai-cells = <0>; |
| compatible = "amlogic, t5w_acodec"; |
| status = "okay"; |
| reg = <0x0 0xff632000 0x0 0x1c>; |
| tdmout_index = <1>; |
| tdmin_index = <1>; |
| dat0_ch_sel = <1>; |
| reset-names = "acodec"; |
| resets = <&reset RESET_AUDIO_CODEC>; |
| }; |
| |
| audio_data: audio_data { |
| compatible = "amlogic, audio_data"; |
| mem_in_base_cmd = <0x82000020>; |
| query_licence_cmd = <0x82000050>; |
| status = "okay"; |
| }; /* Audio Related end */ |
| |
| amaudio: amaudio { |
| compatible = "amlogic, amaudio"; |
| reg = <0x0 0xff610000 0x0 0x10000>; |
| reg-names = "otp_tee_base"; |
| status = "okay"; |
| }; |
| codec_io: codec_io { |
| compatible = "amlogic, meson-t5w, codec-io"; |
| status = "okay"; |
| #address-cells=<2>; |
| #size-cells=<2>; |
| ranges; |
| reg = <0x0 0xffd00000 0x0 0x2000>, |
| <0x0 0xff620000 0x0 0x10000>, |
| <0x0 0xff63c000 0x0 0x2000>, |
| <0x0 0xff800000 0x0 0x10000>, |
| <0x0 0xff900000 0x0 0x40000>, |
| <0x0 0xff638000 0x0 0x2000>, |
| <0x0 0xff630000 0x0 0x2000>; |
| reg-names = "cbus", |
| "dosbus", |
| "hiubus", |
| "aobus", |
| "vcbus", |
| "dmcbus", |
| "efusebus"; |
| }; |
| |
| mesonstream { |
| compatible = "amlogic, codec, streambuf"; |
| dev_name = "mesonstream"; |
| status = "okay"; |
| clocks = <&clkc CLKID_CLK81_DOS |
| &clkc CLKID_VDEC |
| &clkc CLKID_HEVCF>; |
| clock-names = "vdec", |
| "clk_vdec_mux", |
| "clk_hevcf_mux"; |
| assigned-clock-parents = <&clkc CLKID_VDEC_0>, |
| <&clkc CLKID_HEVCF_0>; |
| assigned-clocks = <&clkc CLKID_VDEC>, |
| <&clkc CLKID_HEVCF>; |
| }; |
| |
| vdec { |
| compatible = "amlogic, vdec-pm-pd"; |
| dev_name = "vdec.0"; |
| status = "okay"; |
| interrupts = <0 3 1 |
| 0 23 1 |
| 0 32 1 |
| 0 43 1 |
| 0 44 1 |
| 0 45 1 |
| 0 74 1>; |
| interrupt-names = "vsync", |
| "demux", |
| "parser", |
| "mailbox_0", |
| "mailbox_1", |
| "mailbox_2", |
| "parser_b"; |
| power-domains = <&pwrdm PDID_T5_DOS_VDEC>, |
| <&pwrdm PDID_T5_DOS_HEVC>; |
| power-domain-names = "pwrc-vdec", |
| "pwrc-hevc"; |
| }; |
| |
| vdec_cpu_ver: cpu_ver_name { |
| compatible = "amlogic, cpu-major-id-t5w"; |
| }; |
| |
| vcodec_dec { |
| compatible = "amlogic, vcodec-dec"; |
| dev_name = "aml-vcodec-dec"; |
| status = "okay"; |
| }; |
| |
| canvas: canvas { |
| compatible = "amlogic, meson, canvas"; |
| status = "okay"; |
| reg = <0x0 0xfe036048 0x0 0x2000>; |
| }; |
| |
| ion_dev { |
| compatible = "amlogic, ion_dev"; |
| memory-region = <&ion_cma_reserved |
| &ion_fb_reserved>; |
| }; |
| |
| amlvecm: amlvecm { |
| compatible = "amlogic, vecm-t5w"; |
| dev_name = "aml_vecm"; |
| clocks = <&clkc CLKID_VID_LOCK>; |
| clock-names = "cts_vid_lock_clk"; |
| }; |
| amdolby_vision { |
| compatible = "amlogic, dolby_vision_t5w"; |
| dev_name = "aml_amdolby_vision_driver"; |
| status = "okay"; |
| tv_mode = <1>;/*1:enabel ;0:disable*/ |
| }; |
| |
| meson-amvideom { |
| compatible = "amlogic, amvideom-t5w"; |
| dev_name = "amvideom"; |
| status = "okay"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "vsync", "vsync_viu2"; |
| }; |
| |
| meson_videotunnel{ |
| compatible = "amlogic, meson_videotunnel"; |
| status = "okay"; |
| }; |
| |
| lut_dma { |
| compatible = "amlogic, meson-t7, lut_dma"; |
| status = "okay"; |
| }; |
| |
| ge2d { |
| compatible = "amlogic, ge2d-t5w"; |
| status = "okay"; |
| interrupts = <0 146 1>; |
| interrupt-names = "ge2d"; |
| clocks = <&clkc CLKID_GE2D>; |
| clock-names = "clk_ge2d_gate"; |
| reg = <0x0 0xff940000 0x0 0x10000>; |
| }; |
| |
| /*if you want to use vdin just modify status to "ok"*/ |
| vdin0: vdin0 {/*common define*/ |
| compatible = "amlogic, vdin-t5w"; |
| dev_name = "vdin0"; |
| /*status = "disabled";*/ |
| /*memory-region = <&vdin0_cma_reserved>;*/ |
| reserve-iomap = "true"; |
| flag_cma = <0x101>;/*1:share with codec_mm;2:cma alone*/ |
| /*MByte, if 10bit disable: 64M(YUV422), |
| *if 10bit enable: 64*1.5 = 96M(YUV422) |
| *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M |
| *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M |
| *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M |
| *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M |
| * onebuffer: |
| * worst case:(4096*2160*3 + 2M(afbce issue)) = 27.5M |
| * dw:960x540x3 = 1.5M |
| * total size:(27.5+1.5)x buffernumber |
| */ |
| /*cma_size = <174>;*/ |
| /*frame_buff_num = <6>;*/ |
| interrupts = <0 83 1 /* vdin0 vsync */ |
| /*0 214 1*/ /* vdin1 write down*/ |
| /*0 206 1*/ /* vpu crash */ |
| /*0 213 1*/>; /* vdin0 write down*/ |
| interrupt-names = "vsync_int" |
| /*"mif2_meta_wr_done_int"*/ |
| /*"vpu_crash_int",*/ |
| /*"write_done_int"*/; |
| rdma-irq = <2>; |
| clocks = <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_VDIN_MEAS>; |
| clock-names = "fclk_div5", "cts_vdin_meas_clk"; |
| vdin_id = <0>; |
| /*vdin write mem color depth support: |
| * bit0:support 8bit |
| * bit1:support 9bit |
| * bit2:support 10bit |
| * bit3:support 12bit |
| * bit4:support yuv422 10bit full pack mode (from txl new add) |
| * bit5:force yuv422 to yuv444 malloc (for vdin0 debug) |
| * bit8:use 8bit at 4k_50/60hz_10bit |
| * bit9:use 10bit at 4k_50/60hz_10bit |
| * bit10: support 10bit when double write |
| */ |
| tv_bit_mode = <0x235>; |
| /* afbce_bit_mode: (amlogic frame buff compression encoder) |
| * bit0 -- enable afbce |
| * bit1 -- enable afbce compression-lossy |
| * bit4 -- afbce for 4k |
| * bit5 -- afbce for 1080p |
| * bit6 -- afbce for 720p |
| * bit7 -- afbce for smaller resolution |
| */ |
| afbce_bit_mode = <0x11>; |
| /* urgent_en; */ |
| double_write_en; |
| v4l_support_en; |
| }; |
| |
| vdin1: vdin1 {/*common define*/ |
| compatible = "amlogic, vdin-t5w"; |
| dev_name = "vdin1"; |
| /*status = "disabled";*/ |
| reserve-iomap = "true"; |
| /*memory-region = <&vdin1_cma_reserved>;*/ |
| flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ |
| interrupts = <0 85 1>; |
| interrupt-names = "vsync_int"/*, "vpu_crash_int",*/ |
| /*"write_done_int"*/; |
| rdma-irq = <4>; |
| /*clocks = <&clock CLK_FPLL_DIV5>, |
| * <&clock CLK_VDIN_MEAS_CLK>; |
| *clock-names = "fclk_div5", "cts_vdin_meas_clk"; |
| */ |
| vdin_id = <1>; |
| tv_bit_mode = <0x15>; |
| }; |
| |
| di_local { |
| compatible = "amlogic, di-local"; |
| status = "okay"; |
| }; |
| |
| multi-di { |
| compatible = "amlogic, dim-t3"; |
| status = "okay"; |
| /* 0:use reserved; 1:use cma; 2:use cma as reserved */ |
| flag_cma = <4>; //<1>; |
| //memory-region = <&di_reserved>; |
| memory-region = <&di_cma_reserved>; |
| interrupts = <0 46 1 |
| 0 40 1 |
| 0 39 1>; |
| interrupt-names = "pre_irq", "post_irq","dct_irq"; |
| clocks = <&clkc CLKID_VPU_CLKB>, |
| <&clkc CLKID_VPU>; |
| clock-names = "vpu_clkb", |
| "vpu_mux"; |
| clock-range = <334 667>; |
| /* buffer-size = <3621952>;(yuv422 8bit) */ |
| buffer-size = <4074560>;/*yuv422 fullpack*/ |
| /* reserve-iomap = "true"; */ |
| /* if enable nr10bit, set nr10bit-support to 1 */ |
| post-wr-support = <1>; |
| nr10bit-support = <1>; |
| nrds-enable = <1>; |
| pps-enable = <1>; |
| en_4k = <1>; |
| keep_dec_vf = <2>; |
| po_fmt = <6>; |
| post_nub = <11>; |
| alloc_sct = <1>; |
| hf = <0>; |
| dct = <2>; |
| sub_v = <1>;//sub version for t5w |
| /*************************************************** |
| * t5w t3 support 4k ,same with t7 ,no canvas, |
| * post_nub---default is 11 |
| * (T7/T3/SC2/S4 new path) |
| * post 11*5222400 = 56M,local 7*4075520 = 28m |
| * flag_cma---0: use reserved; 1:use cma; |
| * 2:use cma as reserved 4:use codec mem |
| * en_4k :en_4k---0: not support 4K; 1: enable 4K |
| * 2: dynamic: vdin: 4k enable, |
| * other source 4k disable |
| * 8: when 4k, |
| * output with a resolution is below 1080p |
| * keep_dec_vf---0:not keep; 1: keep dec vf for p; |
| * 2: dynamic keep dec vf for p,other is disable |
| * po_fmt---1: NV21/8; 2: nv12/8; 3: AFBC 422/10BIT; |
| * 4: dynamic(4K AFBC,10/422); |
| * 6: dynamic(from decoder 4K source, |
| * out is AFBC,10/420), |
| * other is 422/10BIT |
| * bypass_mem---0:nr not bypass; 1: nr bypass; |
| * 2: when 4k input ,nr is bypass; |
| * 3: bypass nr for 4k,but not from vdin; |
| * alloc_sct---0:not support; bit 0: for 4k; bit 1: for 1080p |
| * hf---0:not enable; 1: enable |
| * dct---0:not enable; 1: enable 1 ch; 2: enable 2 ch |
| * sub_v---0:major; 1: sub |
| ***************************************************/ |
| }; |
| |
| eth_phy: mdio-multiplexer@ff64c000 { |
| compatible = "amlogic,g12a-mdio-mux"; |
| reg = <0x0 0xff64c000 0x0 0xa4>; |
| clocks = <&clkc CLKID_CLK81_ETH_PHY>, |
| <&xtal>, |
| <&clkc CLKID_MPLL_50M>; |
| clock-names = "pclk", "clkin0", "clkin1"; |
| mdio-parent-bus = <&mdio0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enet_type = <4>; |
| tx_amp_src = <0xFF800270>; |
| |
| ext_mdio: mdio@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| int_mdio: mdio@1 { |
| reg = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| internal_ephy: ethernet_phy@8 { |
| compatible = "ethernet-phy-id0180.3301", |
| "ethernet-phy-ieee802.3-c22"; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <8>; |
| max-speed = <100>; |
| }; |
| }; |
| }; |
| |
| ethmac: ethernet@ff3f0000 { |
| compatible = "amlogic,meson-axg-dwmac", |
| "snps,dwmac-3.70a", |
| "snps,dwmac"; |
| reg = <0x0 0xff3f0000 0x0 0x10000>, |
| <0x0 0xff634400 0x0 0x8>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| clocks = <&clkc CLKID_CLK81_ETH_CORE>, |
| <&clkc CLKID_FCLK_DIV2>, |
| <&clkc CLKID_MPLL2>; |
| clock-names = "stmmaceth", "clkin0", "clkin1"; |
| rx-fifo-depth = <4096>; |
| tx-fifo-depth = <2048>; |
| status = "disabled"; |
| |
| mdio0: mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,dwmac-mdio"; |
| }; |
| }; |
| |
| aocec: aocec { |
| compatible = "amlogic, aocec-t5w"; |
| device_name = "aocec"; |
| status = "okay"; |
| vendor_name = "Amlogic"; /* Max Chars: 8 */ |
| /* Refer to the following URL at: |
| * http://standards.ieee.org/develop/regauth/oui/oui.txt |
| */ |
| vendor_id = <0xffffff>; |
| product_desc = "t5w"; /* Max Chars: 16 */ |
| cec_osd_string = "AML_TV"; /* Max Chars: 14 */ |
| cec_version = <5>; /*5:1.4;6:2.0*/ |
| port_num = <3>; |
| ee_cec; |
| cec_sel = <1>; |
| output = <0>; /*output port number*/ |
| arc_port_mask = <0x2>; |
| interrupts = <0 203 1>; |
| interrupt-names = "hdmi_aocecb"; |
| pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; |
| pinctrl-0=<&aocecb_mux>; |
| pinctrl-1=<&aocecb_mux>; |
| pinctrl-2=<&aocecb_mux>; |
| reg = <0x0 0xFF800000 0x0 0x400>; |
| reg-names = "ao"; |
| }; |
| |
| ionvideo { |
| compatible = "amlogic, ionvideo"; |
| status = "okay"; |
| }; |
| |
| amlvideo { |
| compatible = "amlogic, amlvideo"; |
| status = "okay"; |
| }; |
| |
| meson_uvm { |
| compatible = "amlogic, meson_uvm"; |
| status = "okay"; |
| }; |
| |
| video_composer { |
| compatible = "amlogic, video_composer"; |
| dev_name = "video_composer"; |
| status = "okay"; |
| }; |
| |
| /* POST PROCESS MANAGER */ |
| ppmgr_reserved:linux,ppmgr { |
| compatible = "amlogic, ppmgr_memory"; |
| size = <0x0 0x0>; |
| }; |
| |
| ppmgr { |
| compatible = "amlogic, ppmgr"; |
| memory-region = <&ppmgr_reserved>; |
| status = "okay"; |
| }; |
| |
| amlvideo2_0 { |
| compatible = "amlogic, amlvideo2"; |
| dev_name = "amlvideo2"; |
| status = "okay"; |
| amlvideo2_id = <0>; |
| cma_mode = <1>; |
| }; |
| |
| amlvideo2_1 { |
| compatible = "amlogic, amlvideo2"; |
| dev_name = "amlvideo2"; |
| status = "okay"; |
| amlvideo2_id = <1>; |
| cma_mode = <1>; |
| }; |
| |
| video_queue { |
| compatible = "amlogic, video_queue"; |
| dev_name = "videoqueue"; |
| status = "okay"; |
| }; |
| |
| p_tsensor: p_tsensor@ff634800 { |
| compatible = "amlogic, r1p1-tsensor"; |
| status = "okay"; |
| reg = <0x0 0xff634800 0x0 0x50>, |
| <0x0 0xff800268 0x0 0x4>; |
| tsensor_id = <0>; |
| cal_type = <0x1>; |
| cal_coeff = <324 424 3159 9411>; |
| rtemp = <115000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_TS_CLK>; // CLKID_TS_COMP>; |
| clock-names = "ts_comp"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| meson_cooldev: meson-cooldev@0 { |
| status = "okay"; |
| compatible = "amlogic, meson-cooldev"; |
| cooling_devices { |
| ddr_cool { |
| ddr_reg = <0xff6384b4>; |
| ddr_status = <3>; |
| ddr_bits = <8 15>; |
| ddr_data = <0x4c 0x26 0x13>; |
| node_name = "ddr_cool0"; |
| device_type = "ddr"; |
| }; |
| cpucore_cool_cluster0 { |
| cluster_id = <0>; |
| node_name = "cpucore0"; |
| device_type = "cpucore"; |
| }; |
| gpufreq_cool { |
| dyn_coeff = <245>; |
| node_name = "bifrost"; |
| device_type = "gpufreq"; |
| }; |
| }; |
| ddr_cool0:ddr_cool0 { |
| #cooling-cells = <2>; /* min followed by max */ |
| }; |
| cpucore0:cpucore0 { |
| #cooling-cells = <2>; /* min followed by max */ |
| }; |
| };/*meson cooling devices end*/ |
| |
| thermal-zones { |
| soc_thermal: soc_thermal { |
| polling-delay = <1000>; |
| polling-delay-passive = <100>; |
| sustainable-power = <1100>; |
| thermal-sensors = <&p_tsensor 0>; |
| trips { |
| pswitch_on: trip-point@0 { |
| temperature = <85000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| pcontrol: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <5000>; |
| type = "passive"; |
| }; |
| pcritical: trip-point@2 { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| cooling-maps { |
| cpufreq_cooling_map { |
| trip = <&pcontrol>; |
| cooling-device = <&CPU0 0 8>; |
| contribution = <1024>; |
| }; |
| }; |
| }; |
| }; /*thermal zone end*/ |
| |
| ddr_bandwidth { |
| compatible = "amlogic,ddr-bandwidth-t5w"; |
| status = "okay"; |
| reg = <0x0 0xff638000 0x0 0x400 |
| 0x0 0xff638c00 0x0 0x100>; |
| interrupts = <0 53 1>; |
| interrupt-names = "ddr_bandwidth"; |
| }; |
| |
| dmc_monitor { |
| compatible = "amlogic,dmc_monitor-t5w"; |
| status = "okay"; |
| reg = <0x0 0xff638000 0x0 0x400>; |
| reg_base = <0xff639000>; |
| interrupts = <0 52 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| aml_bt: aml_bt { |
| compatible = "amlogic, aml-bt"; |
| status = "disabled"; |
| }; |
| |
| aml_wifi: aml_wifi { |
| compatible = "amlogic, aml-wifi"; |
| status = "disabled"; |
| irq_trigger_type = "GPIO_IRQ_LOW"; |
| /* dhd_static_buf; */ /*use bcm wifi*/ |
| //pinctrl-0 = <&pwm_e_pins>; |
| //pinctrl-names = "default"; |
| pwm_config = <&wifi_pwm_conf>; |
| }; |
| |
| wifi_pwm_conf:wifi_pwm_conf{ |
| pwm_channel1_conf { |
| pwms = <&pwm_ef 1 30550 0>; |
| duty-cycle = <15270>; |
| times = <8>; |
| }; |
| pwm_channel2_conf { |
| pwms = <&pwm_ef 3 30500 0>; |
| duty-cycle = <15250>; |
| times = <12>; |
| }; |
| }; |
| |
| vpu_security { |
| compatible = "amlogic, meson-t3, vpu_security"; |
| status = "okay"; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "vpu_security"; |
| }; |
| }; |
| }; /* end of / */ |
| |
| &pinctrl_periphs { |
| i2c0_z_pins:i2c0_z { |
| mux { |
| groups = "i2c0_sck_z", |
| "i2c0_sda_z"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c0_z_pins_slp_input:i2c0_z_slp_input { |
| mux { |
| groups = "GPIOZ_4", "GPIOZ_5"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c0_z_pins_slp_low:i2c0_z_slp_low { |
| mux { |
| groups = "GPIOZ_4", "GPIOZ_5"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| i2c1_c_pins:i2c1_c { |
| mux { |
| groups = "i2c1_sck_c", |
| "i2c1_sda_c"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strengtc-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_c_pins_slp_input:i2c1_c_slp_input { |
| mux { |
| groups = "GPIOC_13", "GPIOC_14"; |
| function = "gpio_peripcs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_c_pins_slp_low:i2c1_c_slp_low { |
| mux { |
| groups = "GPIOC_13", "GPIOC_14"; |
| function = "gpio_peripcs"; |
| output-low; |
| }; |
| }; |
| |
| i2c2_h_pins1:i2c2_h { |
| mux { |
| groups = "i2c2_sck_h20", |
| "i2c2_sda_h21"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c2_h_pins1_slp_input:i2c2_h_slp_input { |
| mux { |
| groups = "GPIOH_20", "GPIOH_21"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_h_pins1_slp_low:i2c2_h_slp_low { |
| mux { |
| groups = "GPIOH_20", "GPIOH_21"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| i2c2_h_pins2:i2c2_h { |
| mux { |
| groups = "i2c2_sck_h10", |
| "i2c2_sda_h11"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c2_h_pins2_slp_input:i2c2_h_slp_input { |
| mux { |
| groups = "GPIOH_10", "GPIOH_11"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_h_pins2_slp_low:i2c2_h_slp_low { |
| mux { |
| groups = "GPIOH_10", "GPIOH_11"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| i2c2_h_pins3:i2c2_h { |
| mux { |
| groups = "i2c2_sck_h24", |
| "i2c2_sda_h25"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c2_h_pins3_slp_input:i2c2_h_slp_input { |
| mux { |
| groups = "GPIOH_24", "GPIOH_25"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_h_pins3_slp_low:i2c2_h_slp_low { |
| mux { |
| groups = "GPIOH_24", "GPIOH_25"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| i2c2_m_pins4:i2c2_m { |
| mux { |
| groups = "i2c2_sck_m", |
| "i2c2_sda_m"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c2_m_pins4_slp_input:i2c2_m_slp_input { |
| mux { |
| groups = "GPIOM_25", "GPIOH_26"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_m_pins4_slp_low:i2c2_m_slp_low { |
| mux { |
| groups = "GPIOM_25", "GPIOH_26"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| i2c3_h_pins1:i2c3_h { |
| mux { |
| groups = "i2c3_sck_h24", |
| "i2c3_sda_h25"; |
| function = "i2c3"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c3_h_pins1_slp_input:i2c3_h_slp_input { |
| mux { |
| groups = "GPIOH_24", "GPIOH_25"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c3_h_pins1_slp_low:i2c3_h_slp_low { |
| mux { |
| groups = "GPIOH_24", "GPIOH_25"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| i2c3_h_pins2:i2c3_h { |
| mux { |
| groups = "i2c3_sck_h22", |
| "i2c3_sda_h23"; |
| function = "i2c3"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c3_h_pins2_slp_input:i2c3_h_slp_input { |
| mux { |
| groups = "GPIOH_22", "GPIOH_23"; |
| function = "gpio_periphs"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c3_h_pins2_slp_low:i2c3_h_slp_low { |
| mux { |
| groups = "GPIOH_22", "GPIOH_23"; |
| function = "gpio_periphs"; |
| output-low; |
| }; |
| }; |
| |
| sd_iso7816_pins:sd_iso7816_pins { |
| mux { |
| groups = "iso7816_clk_z", |
| "iso7816_data_z"; |
| function = "iso7816"; |
| input-enable; |
| bias-pull-down; |
| }; |
| }; |
| |
| hdmirx_a_mux:hdmirx_a_mux { |
| mux { |
| groups = "hdmirx_a_hpd", |
| "hdmirx_a_det", |
| "hdmirx_a_sda", |
| "hdmirx_a_sck"; |
| function = "hdmirx_a"; |
| }; |
| }; |
| |
| hdmirx_b_mux:hdmirx_b_mux { |
| mux { |
| groups = "hdmirx_b_hpd", |
| "hdmirx_b_det", |
| "hdmirx_b_sda", |
| "hdmirx_b_sck"; |
| function = "hdmirx_b"; |
| }; |
| }; |
| |
| hdmirx_c_mux:hdmirx_c_mux { |
| mux { |
| groups = "hdmirx_c_hpd", |
| "hdmirx_c_det", |
| "hdmirx_c_sda", |
| "hdmirx_c_sck"; |
| function = "hdmirx_c"; |
| }; |
| }; |
| |
| pwm_a_pins: pwm_a_pins { |
| mux { |
| groups = "pwm_a"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_b_pins1: pwm_b_pins1 { |
| mux { |
| groups = "pwm_b_z"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins2: pwm_b_pins2 { |
| mux { |
| groups = "pwm_b_h"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_c_pins: pwm_c_pins { |
| mux { |
| groups = "pwm_c"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_d_pins1: pwm_d_pins1 { |
| mux { |
| groups = "pwm_d_z"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins2: pwm_d_pins2 { |
| mux { |
| groups = "pwm_d_h5"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins3: pwm_d_pins3 { |
| mux { |
| groups = "pwm_d_h12"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins4: pwm_d_pins4 { |
| mux { |
| groups = "pwm_d_m1"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins5: pwm_d_pins5 { |
| mux { |
| groups = "pwm_d_m23"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_e_pins1: pwm_e_pins1 { |
| mux { |
| groups = "pwm_e_z"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins2: pwm_e_pins2 { |
| mux { |
| groups = "pwm_e_h"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins3: pwm_e_pins3 { |
| mux { |
| groups = "pwm_e_m"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_f_pins1: pwm_f_pins1 { |
| mux { |
| groups = "pwm_f_z"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins2: pwm_f_pins2 { |
| mux { |
| groups = "pwm_f_c"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins3: pwm_f_pins3 { |
| mux { |
| groups = "pwm_f_m"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| irblaster_pins: irblaster_pins { |
| mux { |
| groups = "remote_out"; |
| function = "remote_out"; |
| }; |
| }; |
| |
| /* sdemmc portC */ |
| emmc_clk_cmd_pins: emmc_clk_cmd_pins { |
| mux { |
| groups = "emmc_clk", |
| "emmc_cmd"; |
| function = "emmc"; |
| input-enable; |
| bias-pull-up; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| emmc_conf_pull_up: emmc_conf_pull_up { |
| mux { |
| groups = "emmc_nand_d7", |
| "emmc_nand_d6", |
| "emmc_nand_d5", |
| "emmc_nand_d4", |
| "emmc_nand_d3", |
| "emmc_nand_d2", |
| "emmc_nand_d1", |
| "emmc_nand_d0", |
| "emmc_clk", |
| "emmc_cmd"; |
| function = "emmc"; |
| input-enable; |
| bias-pull-up; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| emmc_conf_pull_done: emmc_conf_pull_done { |
| mux { |
| groups = "emmc_nand_ds"; |
| function = "emmc"; |
| input-enable; |
| bias-pull-down; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| ao_to_sd_uart_pins: ao_to_sd_uart_pins { |
| mux { |
| groups ="uart_ao_a_rx_w3", |
| "uart_ao_a_tx_w2", |
| "uart_ao_a_rx_w7", |
| "uart_ao_a_tx_w6", |
| "uart_ao_a_rx_w11", |
| "uart_ao_a_tx_w10"; |
| function = "uart_ao_a_ee"; |
| bias-pull-up; |
| input-enable; |
| }; |
| }; |
| |
| emmc_pins_sleep:emmc_all_pins_sleep { |
| mux { |
| groups = "GPIOB_0", |
| "GPIOB_1", |
| "GPIOB_2", |
| "GPIOB_3", |
| "GPIOB_4", |
| "GPIOB_5", |
| "GPIOB_6", |
| "GPIOB_7"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| mux1 { |
| groups = "GPIOB_8", |
| "GPIOB_9", |
| "GPIOB_10", |
| "GPIOB_11"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| /* sdemmc portB */ |
| sd_clk_cmd_pins:sd_clk_cmd_pins { |
| mux { |
| groups = "sdcard_cmd"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| mux1 { |
| groups = "sdcard_clk"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sd_all_pins:sd_all_pins { |
| mux { |
| groups = "sdcard_d0", |
| "sdcard_d1", |
| "sdcard_d2", |
| "sdcard_d3", |
| "sdcard_cmd"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| mux1 { |
| groups = "sdcard_clk"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sd_clk_gate_pins: sd_clk_gate { |
| mux { |
| groups = "GPIOC_4"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sd_all_pd_pins:sd_all_pd_pins { |
| mux { |
| groups = "GPIOC_0", |
| "GPIOC_1", |
| "GPIOC_2", |
| "GPIOC_3", |
| "GPIOC_4", |
| "GPIOC_5"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| output-low; |
| }; |
| }; |
| |
| sd_1bit_pins:sd_1bit_pins { |
| mux { |
| groups = "sdcard_d0", |
| "sdcard_cmd"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| mux1 { |
| groups = "sdcard_clk"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| all_nand_pins: all_nand_pins { |
| mux { |
| groups = "emmc_nand_d0", |
| "emmc_nand_d1", |
| "emmc_nand_d2", |
| "emmc_nand_d3", |
| "emmc_nand_d4", |
| "emmc_nand_d5", |
| "emmc_nand_d6", |
| "emmc_nand_d7", |
| "nand_ce0", |
| "nand_ale", |
| "nand_cle", |
| "nand_wen_clk", |
| "nand_ren_wr"; |
| function = "nand"; |
| input-enable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| nand_cs_pins:nand_cs { |
| mux { |
| groups = "nand_ce0"; |
| function = "nand"; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| a_uart_pins0:a_uart { |
| mux { |
| groups = "uart_a_tx_c", |
| "uart_a_rx_c", |
| "uart_a_cts_c", |
| "uart_a_rts_c"; |
| function = "uart_a"; |
| }; |
| }; |
| |
| a_uart_pins1:a_uart1 { |
| mux { |
| groups = "uart_a_tx_z", |
| "uart_a_rx_z", |
| "uart_a_cts_z", |
| "uart_a_rts_z"; |
| function = "uart_a"; |
| }; |
| }; |
| |
| b_uart_pins0:b_uart { |
| mux { |
| groups = "uart_b_tx_w2", |
| "uart_b_rx_w3"; |
| function = "uart_b"; |
| }; |
| }; |
| |
| b_uart_pins1:b_uart1 { |
| mux { |
| groups = "uart_b_tx_w6", |
| "uart_b_tx_w7"; |
| function = "uart_b"; |
| }; |
| }; |
| |
| b_uart_pins2:b_uart2 { |
| mux { |
| groups = "uart_b_tx_w10", |
| "uart_b_tx_w11"; |
| function = "uart_b"; |
| }; |
| }; |
| |
| c_uart_pins:c_uart { |
| mux { |
| groups = "uart_c_tx_h1", |
| "uart_c_rx_h2"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| spdifin_z19_pins: spdifin { |
| mux { /* GPIOZ_19 */ |
| groups = "spdif_in_z"; |
| function = "spdif_in"; |
| }; |
| }; |
| |
| atvdemod_agc_pins: atvdemod_agc_pins { |
| mux { |
| groups = "atv_if_agc_z6"; |
| function = "atv"; |
| }; |
| }; |
| |
| dtvdemod_if_agc_pins: dtvdemod_if_agc_pins { |
| mux { |
| groups = "dtv_if_agc_z6"; |
| function = "dtv"; |
| }; |
| }; |
| |
| dtvdemod_rf_agc_pins: dtvdemod_rf_agc_pins { |
| mux { |
| groups = "dtv_rf_agc_z6"; |
| function = "dtv"; |
| }; |
| }; |
| |
| diseqc_out: diseqc_out { |
| mux { |
| groups = "diseqc_out_z0"; |
| function = "diseqc_out"; |
| bias-pull-down; |
| }; |
| }; |
| |
| lcd_vbyone_a_pins: lcd_vbyone_a_pin { |
| mux { |
| groups = "vx1_a_lockn","vx1_a_htpdn"; |
| function = "vx1"; |
| }; |
| }; |
| |
| lcd_vbyone_a_off_pins: lcd_vbyone_a_off_pin { |
| mux { |
| groups = "GPIOH_0","GPIOH_8"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| lcd_vbyone_b_pins: lcd_vbyone_b_pin { |
| mux { |
| groups = "vx1_b_lockn","vx1_b_htpdn"; |
| function = "vx1"; |
| }; |
| }; |
| |
| lcd_vbyone_b_off_pins: lcd_vbyone_b_off_pin { |
| mux { |
| groups = "GPIOH_9","GPIOH_10"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| lcd_tcon_p2p_pins: lcd_tcon_p2p_pin { |
| mux { |
| groups = "tcon_1","tcon_2","tcon_3", |
| "tcon_4","tcon_5","tcon_6", |
| "tcon_lock"; |
| function = "tcon"; |
| }; |
| }; |
| |
| lcd_tcon_p2p_usit_pins: lcd_tcon_p2p_usit_pin { |
| mux { |
| groups = "tcon_1","tcon_2","tcon_3", |
| "tcon_4","tcon_5","tcon_6", |
| "tcon_sfc_h0"; |
| function = "tcon"; |
| }; |
| }; |
| |
| lcd_tcon_p2p_off_pins: lcd_tcon_p2p_off_pin { |
| mux { |
| groups = "GPIOH_1","GPIOH_2","GPIOH_3", |
| "GPIOH_4","GPIOH_5","GPIOH_6", |
| "GPIOH_0"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| lcd_tcon_mlvds_pins: lcd_tcon_mlvds_pin { |
| mux { |
| groups = "tcon_0","tcon_1","tcon_2","tcon_3", |
| "tcon_4","tcon_5","tcon_6"; |
| function = "tcon"; |
| }; |
| }; |
| |
| lcd_tcon_mlvds_off_pins: lcd_tcon_mlvds_off_pin { |
| mux { |
| groups = "GPIOH_0","GPIOH_1","GPIOH_2","GPIOH_3", |
| "GPIOH_4","GPIOH_5","GPIOH_6"; |
| function = "gpio_periphs"; |
| input-enable; |
| }; |
| }; |
| |
| aocecb_mux:aocecb_mux { |
| mux { |
| groups = "cec"; |
| function = "cec"; |
| }; |
| }; |
| |
| mclk_1_pins: mclk_1_pin { |
| mux { /* GPIOH_14 */ |
| groups = "mclk_1_h"; |
| function = "mclk"; |
| }; |
| }; |
| dvb_p_ts1_pins: dvb_p_ts1_pins { |
| mux { |
| groups = "tsin_b_d0", |
| "tsin_b_d1", |
| "tsin_b_d2", |
| "tsin_b_d3", |
| "tsin_b_d4", |
| "tsin_b_d5", |
| "tsin_b_d6", |
| "tsin_b_d7", |
| "tsin_b_clk", |
| "tsin_b_sop", |
| "tsin_b_valid"; |
| function = "tsin_b"; |
| }; |
| }; |
| dvb_ci_bus_pins_all: dvb_ci_bus_pins_all { |
| mux { |
| groups = "cicam_a0", "cicam_a1", "cicam_a2_c", "cicam_a3_c", "cicam_a4_c", |
| "cicam_a5_c", "cicam_a6_c", "cicam_a7_c", "cicam_a8_c", "cicam_a9_c", |
| "cicam_a10_c", "cicam_a11_c", |
| "cicam_data0", "cicam_data1", "cicam_data2", "cicam_data3", |
| "cicam_data4", "cicam_data5", "cicam_data6", "cicam_data7", |
| "cicam_cen", "cicam_oen", "cicam_wen", "cicam_iordn", "cicam_iowrn", |
| "cicam_reset"; |
| function = "cicam"; |
| }; |
| }; |
| dvb_ci_bus_pins: dvb_ci_bus_pins { |
| mux { |
| groups = "cicam_a0", "cicam_a1", |
| "cicam_data0", "cicam_data1", "cicam_data2", "cicam_data3", |
| "cicam_data4", "cicam_data5", "cicam_data6", "cicam_data7", |
| "cicam_cen", "cicam_oen", "cicam_wen", "cicam_iordn", "cicam_iowrn", |
| "cicam_reset"; |
| function = "cicam"; |
| }; |
| }; |
| ci_ts_pins: ci_ts_pins { |
| mux { |
| groups = "tsout_sop", |
| "tsout_valid", |
| "tsout_d0", |
| "tsout_d1", |
| "tsout_d2", |
| "tsout_d3", |
| "tsout_d4", |
| "tsout_d5", |
| "tsout_d6", |
| "tsout_d7"; |
| function = "tsout"; |
| }; |
| }; |
| ci_addr_pins: ci_addr_pins { |
| mux { |
| groups = "cicam_a2", "cicam_a3", "cicam_a4", |
| "cicam_a5", "cicam_a6", "cicam_a7", "cicam_a8", "cicam_a9", |
| "cicam_a10", "cicam_a11"; |
| function = "cicam"; |
| }; |
| }; |
| ci_ts_clk_pins: ci_ts_clk_pins { |
| mux { |
| groups = "tsout_clk"; |
| function = "tsout"; |
| }; |
| }; |
| ci_gpio_pins: ci_gpio_pins { |
| mux { |
| groups = "GPIOZ_7"; |
| function = "gpio_periphs"; |
| }; |
| }; |
| }; |
| |
| &pinctrl_aobus { |
| i2c1_ao_pins1:i2c1_ao { |
| mux { |
| groups = "i2c1_ao_sck", |
| "i2c1_ao_sda"; |
| function = "i2c1_ao"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c1_ao_pins1_slp_input:i2c1_ao_slp_input { |
| mux { |
| groups = "GPIOD_2", "GPIOD_3"; |
| function = "gpio_aobus"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_ao_pins1_slp_low:i2c1_ao_slp_low { |
| mux { |
| groups = "GPIOD_2", "GPIOD_3"; |
| function = "gpio_aobus"; |
| output-low; |
| }; |
| }; |
| |
| i2c2_ao_pins2:i2c2_ao { |
| mux { |
| groups = "i2c2_ao_sck", |
| "i2c2_ao_sda"; |
| function = "i2c2_ao"; |
| bias-disable; |
| drive-strength-mihroamp = <3000>; |
| }; |
| }; |
| |
| i2c2_ao_pins2_slp_input:i2c2_ao_slp_input { |
| mux { |
| groups = "GPIOE_0", "GPIOE_1"; |
| function = "gpio_aobus"; |
| input-enable; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_ao_pins2_slp_low:i2c2_ao_slp_low { |
| mux { |
| groups = "GPIOE_0", "GPIOE_1"; |
| function = "gpio_aobus"; |
| output-low; |
| }; |
| }; |
| |
| remote_pins:remote_pin { |
| mux { |
| groups = "remote_input_ao"; |
| function = "remote_input_ao"; |
| }; |
| }; |
| spdifout_d8_pins: spdifout_a { |
| mux { /* GPIOD_8 */ |
| groups = "spdif_out_a_ao"; |
| function = "spdif_out_a_ao"; |
| }; |
| }; |
| |
| spdifout_d8_mute: spdifout_a_mute { |
| mux { /* GPIOD_8 */ |
| groups = "GPIOD_8"; |
| function = "gpio_aobus"; |
| }; |
| }; |
| |
| irblaster_ao_pins1:irblaster_ao_pins1 { |
| mux { |
| groups = "remote_out_ao1"; |
| function = "remote_out_ao"; |
| }; |
| }; |
| |
| irblaster_ao_pins2:irblaster_ao_pins2 { |
| mux { |
| groups = "remote_out_ao9"; |
| function = "remote_out_ao"; |
| }; |
| }; |
| |
| jtag_apao_pins:jtag_apao_pin { |
| mux { |
| groups = "jtag_a_tdi", |
| "jtag_a_tdo", |
| "jtag_a_clk", |
| "jtag_a_tms"; |
| function = "jtag_a"; |
| }; |
| }; |
| |
| }; |
| |
| &gpu{ |
| reg = <0 0xFFE40000 0 0x40000>, /*mali APB bus base address*/ |
| <0 0xFFD01000 0 0x01000>, /*reset register*/ |
| <0 0xFF800000 0 0x01000>, /*aobus for gpu pmu domain*/ |
| <0 0xFF646000 0 0x01000>, /*gpu clk cntl*/ |
| <0 0xFFD01000 0 0x01000>; /*reset register*/ |
| clocks = <&clkc CLKID_MALI>; |
| clock-names = "gpu_mux"; |
| |
| /* |
| * Mali clocking is provided by two identical clock paths |
| * MALI_0 and MALI_1 muxed to a single clock by a glitch |
| * free mux to safely change frequency while running. |
| */ |
| assigned-clocks = <&clkc CLKID_MALI_0_SEL>, |
| <&clkc CLKID_MALI_0>, |
| <&clkc CLKID_MALI>; /* Glitch free mux */ |
| assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, |
| <0>, /* Do Nothing */ |
| <&clkc CLKID_MALI_0>; |
| assigned-clock-rates = <0>, /* Do Nothing */ |
| <800000000>, |
| <0>; /* Do Nothing */ |
| |
| tbl = <&dvfs285_cfg |
| &dvfs400_cfg |
| &dvfs500_cfg |
| &dvfs666_cfg |
| &dvfs800_cfg |
| &dvfs800_cfg>; /* the last one of table is for preheat */ |
| }; |
