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nest-open-source / manifest_repos / kernel / 9398cc34ac0688d293c2dff535a4025e4140b0b1 / . / arch / arm64 / boot / dts / amlogic / mesont7.dtsi
blob: 6f5953bcdd33ed192f2d0792df329a8f95c8e942 [file] [log] [blame]
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/clock/amlogic,t7-clkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/t7-pd.h>
#include <dt-bindings/clock/amlogic,t7-audio-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/meson-t7-gpio.h>
#include <dt-bindings/reset/amlogic,meson-t7-reset.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/meson_ir.h>
#include "meson-ir-map.dtsi"
#include "mesong12a-bifrost.dtsi"
/ {
cpus:cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0:cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1:cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_A73_CLK>,
<&clkc CLKID_A73_DYN_CLK>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <550>;
#cooling-cells = <2>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_A73_CLK>,
<&clkc CLKID_A73_DYN_CLK>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <550>;
#cooling-cells = <2>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_A73_CLK>,
<&clkc CLKID_A73_DYN_CLK>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <550>;
#cooling-cells = <2>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_A73_CLK>,
<&clkc CLKID_A73_DYN_CLK>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <550>;
#cooling-cells = <2>;
};
CPU4:cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <632>;
dynamic-power-coefficient = <110>;
#cooling-cells = <2>;
};
CPU5:cpu@101{
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <632>;
dynamic-power-coefficient = <110>;
#cooling-cells = <2>;
};
CPU6:cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <632>;
dynamic-power-coefficient = <110>;
#cooling-cells = <2>;
};
CPU7:cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <632>;
dynamic-power-coefficient = <110>;
#cooling-cells = <2>;
};
idle-states {
entry-method = "arm,psci-0.2";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <4000>;
exit-latency-us = <5000>;
min-residency-us = <10000>;
};
SYSTEM_SLEEP_0: system-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0000000>;
entry-latency-us = <0x3fffffff>;
exit-latency-us = <0x40000000>;
min-residency-us = <0xffffffff>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 0xff08>,
<GIC_PPI 14 0xff08>,
<GIC_PPI 11 0xff08>,
<GIC_PPI 10 0xff08>;
};
timer_bc {
/*compatible = "amlogic,bc-timer";*/
reg= <0x0 0xfe0100D8 0x0 0x4 0x0 0xfe0100DC 0x0 0x4>;
timer_name = "Meson TimerD";
clockevent-rating=<300>;
clockevent-shift=<20>;
clockevent-features=<0x23>;
interrupts = <0 3 1>;
bit_enable=<7>;
bit_mode=<6>;
bit_resolution=<0>;
resolution_1us=<1>;
min_delta_ns=<10>;
};
arm_pmu {
compatible = "arm,armv8-pmuv3";
/* private-interrupts; */
clusterb-enabled;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xfe00e340 0x0 0x4>,
<0x0 0xfe00e280 0x0 0x04>;
cpumasks = <0x0f 0xf0>;
/* default 10ms */
relax-timer-ns = <10000000>;
/* default 10000us */
max-wait-cnt = <10000>;
};
gic: interrupt-controller@fff01000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfff01000 0 0x1000>,
<0x0 0xfff02000 0 0x0100>;
interrupts = <GIC_PPI 9 0xf04>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
meson_suspend:pm {
compatible = "amlogic, pm";
status = "okay";
device_name = "aml_pm";
reg = <0x0 0xfe010288 0x0 0x4>, /*SYSCTRL_STATUS_REG2*/
<0x0 0xfe0102dc 0x0 0x4>; /*SYSCTRL_STICKY_REG7*/
};
aml_reboot {
compatible = "aml, reboot";
sys_reset = <0x84000009>;
sys_poweroff = <0x84000008>;
dis_nb_cpus_in_shutdown;
};
secmon {
compatible = "amlogic, secmon";
memory-region = <&secmon_reserved>;
in_base_func = <0x82000020>;
out_base_func = <0x82000021>;
inout_size_func = <0x8200002a>;
reserve_mem_size = <0x03300000>;
clear_range = <0x05100000 0x200000>;
};
cma_shrinker: cma_shrinker {
compatible = "amlogic, cma-shrinker";
status = "okay";
adj = <0 100 200 250 900 950>;
free = <8192 12288 16384 24576 28672 32768>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
cpu_info {
compatible = "amlogic, cpuinfo";
status = "okay";
cpuinfo_cmd = <0x82000044>;
};
vrtc: rtc@0xfe010288 {
compatible = "amlogic,meson-vrtc";
reg = <0x0 0xfe010288 0x0 0x4>;
status = "okay";
mboxes = <&mhu_fifo 5>;
};
pwrdm: power-domains {
compatible = "amlogic,t7-power-domain";
#power-domain-cells = <1>;
status = "okay";
};
nna_top_ports_wrapper_0: nna_top_ports_wrapper@fe372000 {
compatible = "amazon,nna-1.0";
device-name = "acenna0";
status = "okay";
clocks = <&clkc CLKID_ANAKIN_CLK>;
clock-names = "nna_clk_gate";
assigned-clocks =<&clkc CLKID_ANAKIN_0_MUX>,
<&clkc CLKID_ANAKIN>,
<&clkc CLKID_ANAKIN_CLK>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_ANAKIN_0>,
<0>;
assigned-clock-rates = <0>,
<0>,
<800000000>;
interrupt-names = "nna_interrupt";
interrupts = <0 187 1>;
minor-number = <0>;
power-domains = <&pwrdm PDID_T7_NNA_CORE0>,
<&pwrdm PDID_T7_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe372000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_1: nna_top_ports_wrapper@fe373000 {
compatible = "amazon,nna-1.1";
device-name = "acenna1";
status = "okay";
clocks = <&clkc CLKID_ANAKIN_CLK>;
clock-names = "nna_clk_gate";
assigned-clocks =<&clkc CLKID_ANAKIN_0_MUX>,
<&clkc CLKID_ANAKIN>,
<&clkc CLKID_ANAKIN_CLK>;
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_ANAKIN_0>,
<0>;
assigned-clock-rates = <0>,
<0>,
<800000000>;
interrupt-names = "nna_interrupt";
interrupts = <0 188 1>;
minor-number = <1>;
power-domains = <&pwrdm PDID_T7_NNA_CORE1>,
<&pwrdm PDID_T7_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe373000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_2: nna_top_ports_wrapper@fe370000 {
compatible = "amazon,nna-1.2";
device-name = "acenna2";
status = "okay";
clocks = <&clkc CLKID_ANAKIN_CLK>;
clock-names = "nna_clk_gate";
assigned-clocks =<&clkc CLKID_ANAKIN_0_MUX>,
<&clkc CLKID_ANAKIN>,
<&clkc CLKID_ANAKIN_CLK>;
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_ANAKIN_0>,
<0>;
assigned-clock-rates = <0>,
<0>,
<800000000>;
interrupt-names = "nna_interrupt";
interrupts = <0 185 1>;
minor-number = <2>;
power-domains = <&pwrdm PDID_T7_NNA_CORE2>,
<&pwrdm PDID_T7_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe370000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_3: nna_top_ports_wrapper@fe371000 {
compatible = "amazon,nna-1.3";
device-name = "acenna3";
status = "okay";
clocks = <&clkc CLKID_ANAKIN_CLK>;
clock-names = "nna_clk_gate";
assigned-clocks =<&clkc CLKID_ANAKIN_0_MUX>,
<&clkc CLKID_ANAKIN>,
<&clkc CLKID_ANAKIN_CLK>;
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_ANAKIN_0>,
<0>;
assigned-clock-rates = <0>,
<0>,
<800000000>;
interrupt-names = "nna_interrupt";
interrupts = <0 186 1>;
minor-number = <3>;
power-domains = <&pwrdm PDID_T7_NNA_CORE3>,
<&pwrdm PDID_T7_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe371000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
dolby_fw: dolby_fw {
compatible = "amlogic, dolby_fw";
mem_size = <0x100000>;
status = "okay";
};
jtag {
compatible = "amlogic, jtag";
status = "okay";
select = "disable"; /* disable/jtag_a/jtag_b */
pinctrl-names="jtag_a_pins", "jtag_b_pins";
pinctrl-0=<&jtag_a_pins>;
pinctrl-1=<&jtag_b_pins>;
};
hifi4dsp: hifi4dsp {
compatible = "amlogic, hifi4dsp";
memory-region = <&dsp_fw_reserved>;
reg = <0 0xfe340018 0 0x114>, /*dspa base address*/
<0 0xfe350018 0 0x114>, /*dspb base address*/
<0 0xfe010258 0 0x4>, /*dspa status counter*/
<0 0xfe01025c 0 0x4>, /*dspb status counter*/
<0 0x40820000 0 0x80000>; /*dsp shm region*/
dsp-monitor-period-ms = <1000>;
reg-names = "dspa_top_reg", "dspb_top_reg";
clocks = <&clkc CLKID_DSPA_CLK>, <&clkc CLKID_DSPB_CLK>;
clock-names = "dspa_clk", "dspb_clk";
dsp-start-mode = <1>; /*0:scpi start mode,1:smc start mode*/
dsp-cnt = <2>;
dspaoffset = <0xa0000>;
dspboffset = <0x8a0000>;
bootlocation = <1>; /*1: boot from DDR, 2: from sram, 3...*/
/*remember:set dspaoffset to 0x0 when use sram longcall remap*/
optimize_longcall = <1 1>;
sram_remap_addr = <0x40700000 0xf7000000 0x40700000 0xf7000000>;
boot_sram_addr = <0xf7000000>;
boot_sram_size = <0x100000>;
//dspsrambase = <0xf7100000>;
//dspsramsize = <0x100000>;
power-domains = <&pwrdm PDID_T7_DSPA>,
<&pwrdm PDID_T7_DSPB>;
power-domain-names = "dspa", "dspb";
//dsp_logbuff = <0x40000000 0x1000 0x40002000 0x1000>;
logbuff-polling-period-ms = <50>;
status = "okay";
};
vddcpua: pwmao_d-regulator {
compatible = "pwm-regulator";
pwms = <&pwmao_cd MESON_PWM_1 1500 0>;
regulator-name = "vddcpua";
regulator-min-microvolt = <689000>;
regulator-max-microvolt = <1049000>;
regulator-always-on;
max-duty-cycle = <1500>;
/* Voltage Duty-Cycle */
voltage-table = <1049000 0>,
<1039000 3>,
<1029000 6>,
<1019000 9>,
<1009000 12>,
<999000 14>,
<989000 17>,
<979000 20>,
<969000 23>,
<959000 26>,
<949000 29>,
<939000 31>,
<929000 34>,
<919000 37>,
<909000 40>,
<899000 43>,
<889000 45>,
<879000 48>,
<869000 51>,
<859000 54>,
<849000 56>,
<839000 59>,
<829000 62>,
<819000 65>,
<809000 68>,
<799000 70>,
<789000 73>,
<779000 76>,
<769000 79>,
<759000 81>,
<749000 84>,
<739000 87>,
<729000 89>,
<719000 92>,
<709000 95>,
<699000 98>,
<689000 100>;
status = "disabled";
};
vddcpub: pwmao_b-regulator {
compatible = "pwm-regulator";
pwms = <&pwmao_ab MESON_PWM_1 1500 0>;
regulator-name = "vddcpub";
regulator-min-microvolt = <689000>;
regulator-max-microvolt = <1049000>;
regulator-always-on;
max-duty-cycle = <1500>;
/* Voltage Duty-Cycle */
voltage-table = <1049000 0>,
<1039000 3>,
<1029000 6>,
<1019000 9>,
<1009000 12>,
<999000 14>,
<989000 17>,
<979000 20>,
<969000 23>,
<959000 26>,
<949000 29>,
<939000 31>,
<929000 34>,
<919000 37>,
<909000 40>,
<899000 43>,
<889000 45>,
<879000 48>,
<869000 51>,
<859000 54>,
<849000 56>,
<839000 59>,
<829000 62>,
<819000 65>,
<809000 68>,
<799000 70>,
<789000 73>,
<779000 76>,
<769000 79>,
<759000 81>,
<749000 84>,
<739000 87>,
<729000 89>,
<719000 92>,
<709000 95>,
<699000 98>,
<689000 100>;
status = "disabled";
};
a73pwm_opp_table0: a73pwm_opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <819000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <819000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <819000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <819000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <819000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <829000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <849000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <869000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <909000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <939000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <1009000>;
};
};
a73pwm_opp_table1: a73pwm_opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <819000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <819000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <819000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <819000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <819000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <829000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <849000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <869000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <909000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <939000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <1009000>;
};
};
a73pwm_opp_table2: a73pwm_opp_table2 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <799000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <799000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <799000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <799000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <809000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <829000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <849000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <859000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <889000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <919000>;
};
opp11 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <969000>;
};
};
a73pwm_opp_table3: a73pwm_opp_table3 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <789000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <789000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <789000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <789000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <809000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <819000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <829000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <849000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <859000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <879000>;
};
opp11 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <919000>;
};
};
a53pwm_opp_table0: a53pwm_opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <769000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <769000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <769000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <769000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <769000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <839000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <869000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <909000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <949000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1009000>;
};
};
a53pwm_opp_table1: a53pwm_opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <769000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <769000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <769000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <769000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <769000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <839000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <869000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <909000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <949000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1009000>;
};
};
a53pwm_opp_table2: a53pwm_opp_table2 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <759000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <759000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <759000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <759000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <769000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <789000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <799000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <829000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <859000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <899000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <949000>;
};
};
a53pwm_opp_table3: a53pwm_opp_table3 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <749000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <749000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <749000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <749000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <769000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <779000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <789000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <809000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <829000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <859000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <919000>;
};
};
a53buck_opp_table0: a53buck_opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <770000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <770000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <770000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <770000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <770000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <810000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <840000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <870000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <910000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <950000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1010000>;
};
};
a53buck_opp_table1: a53buck_opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <770000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <770000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <770000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <770000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <770000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <810000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <840000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <870000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <910000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <950000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1010000>;
};
};
a53buck_opp_table2: a53buck_opp_table2 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <760000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <760000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <760000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <760000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <770000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <790000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <800000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <830000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <860000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <900000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <950000>;
};
};
a53buck_opp_table3: a53buck_opp_table3 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <750000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <750000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <750000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <750000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <770000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <780000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <790000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <810000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <830000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <860000>;
};
opp10 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <920000>;
};
};
cpufreq-meson {
compatible = "amlogic, cpufreq-meson";
status = "okay";
};
saradc: saradc@fe026000 {
compatible = "amlogic,meson-g12a-saradc",
"amlogic,meson-saradc";
status = "disabled";
#io-channel-cells = <1>;
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SARADC_GATE>,
<&clkc CLKID_SARADC_MUX>;
clock-names = "clkin", "core",
"adc_clk", "adc_sel";
interrupts = <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>;
reg = <0x00 0xfe026000 0x00 0x48>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apb4: apb4@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
clkc: clock-controller {
compatible = "amlogic,t7-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x49c>,
<0x0 0x8000 0x0 0x320>,
<0x0 0xe040 0x0 0xbc>;
reg-names = "basic", "pll",
"cpu_clk";
clocks = <&xtal>;
clock-names = "xtal";
status = "okay";
};
meson_clk_msr@48000 {
compatible = "amlogic,meson-t7-clk-measure";
reg = <0x0 0x48000 0x0 0x1c>;
};
watchdog@2100 {
compatible = "amlogic,meson-sc2-wdt";
status = "okay";
/* 0:userspace, 1:kernel */
amlogic,feed_watchdog_mode = <1>;
reg = <0x0 0x2100 0x0 0x10>;
clocks = <&xtal>;
};
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,meson-t7-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4000 {
reg = <0x0 0x4000 0x0 0x0064>,
<0x0 0x40c0 0x0 0x0220>;
reg-names = "mux", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 157>;
};
};
gpio_intc: interrupt-controller@4080 {
compatible = "amlogic,meson-t7-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x4080 0x0 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts =
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
spicc0: spi@50000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x50000 0x0 0x44>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>,
<&clkc CLKID_SPICC0_GATE>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pwrdm PDID_T7_SPICC0>;
status = "disabled";
};
spicc1: spi@52000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x52000 0x0 0x44>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>,
<&clkc CLKID_SPICC1_GATE>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pwrdm PDID_T7_SPICC1>;
status = "disabled";
};
spicc2: spi@54000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x54000 0x0 0x44>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC2>,
<&clkc CLKID_SPICC2_GATE>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pwrdm PDID_T7_SPICC2>;
status = "disabled";
};
spicc3: spi@4a000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x4a000 0x0 0x44>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC3>,
<&clkc CLKID_SPICC3_GATE>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pwrdm PDID_T7_SPICC3>;
status = "disabled";
};
spicc4: spi@4c000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x4c000 0x0 0x44>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC4>,
<&clkc CLKID_SPICC4_GATE>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pwrdm PDID_T7_SPICC4>;
status = "disabled";
};
spicc5: spi@4e000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x4e000 0x0 0x44>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC5>,
<&clkc CLKID_SPICC5_GATE>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pwrdm PDID_T7_SPICC5>;
status = "disabled";
};
spifc: spi@56000 {
compatible = "amlogic,meson-spifc";
status = "disabled";
reg = <0x0 0x56000 0x0 0x80>;
clock-names = "default";
clocks = <&clkc CLKID_SPIFC>;
pinctrl-names = "default";
pinctrl-0 = <&spifc_all_pins>;
#address-cells = <1>;
#size-cells = <0>;
spi-nor@0 {
compatible = "jedec,spi-nor";
status = "disabled";
reg = <0>;
spi-max-frequency = <16000000>;
};
};
pwm_ab: pwm@58000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x58000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_A_GATE>,
<&clkc CLKID_PWM_B_GATE>;
clock-names = "clkin0", "clkin1";
status = "okay";
};
pwm_cd: pwm@5a000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x5a000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_C_GATE>,
<&clkc CLKID_PWM_D_GATE>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwm_ef: pwm@5c000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x5c000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_E_GATE>,
<&clkc CLKID_PWM_F_GATE>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwmao_ab: pwm@5e000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x5e000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_AO_A_GATE>,
<&clkc CLKID_PWM_AO_B_GATE>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwmao_cd: pwm@60000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x60000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_AO_C_GATE>,
<&clkc CLKID_PWM_AO_D_GATE>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwmao_ef: pwm@30000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x30000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_AO_E_GATE>,
<&clkc CLKID_PWM_AO_F_GATE>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwmao_gh: pwm@32000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x32000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_AO_G_GATE>,
<&clkc CLKID_PWM_AO_H_GATE>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
i2c0: i2c@66000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x66000 0x0 0x48>;
interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_M_A>;
status = "disabled";
};
i2c1: i2c@68000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x68000 0x0 0x48>;
interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_M_B>;
status = "disabled";
};
i2c2: i2c@6a000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x6a000 0x0 0x48>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_M_C>;
status = "disabled";
};
i2c3: i2c@6c000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x6c000 0x0 0x48>;
interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_M_D>;
status = "disabled";
};
i2c4: i2c@6e000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x6e000 0x0 0x48>;
interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_M_E>;
status = "disabled";
};
i2c5: i2c@70000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x070000 0x0 0x48>;
interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_M_F>;
status = "disabled";
};
i2c_AO_A: i2c@76000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x076000 0x0 0x48>;
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_AO_A>;
status = "disabled";
};
i2c_AO_B: i2c@86000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x086000 0x0 0x48>;
interrupts = <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C_AO_B>;
status = "disabled";
};
uart_B: serial@7a000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <0 169 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART_B>;
clock-names = "clk_uart",
"clk_gate";
xtal_tick_en = <2>;
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&b_uart_pins>;
support-sysrq = <1>; /* 0 not support*/
};
eth_phy: mdio-multiplexer@28000 {
compatible = "amlogic,g12a-mdio-mux";
reg = <0x0 0x28000 0x0 0xa4>;
clocks = <&clkc CLKID_ETHPHY>,
<&xtal>,
<&clkc CLKID_MPLL_50M>;
clock-names = "pclk", "clkin0", "clkin1";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
enet_type = <5>;
tx_amp_src = <0xFE010330>;
ext_mdio: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
int_mdio: mdio@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
internal_ephy: ethernet_phy@8 {
compatible = "ethernet-phy-id0180.3301",
"ethernet-phy-ieee802.3-c22";
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
reg = <8>;
max-speed = <100>;
};
};
};
reset: reset-controller@2000 {
compatible = "amlogic,meson-t7-reset";
reg = <0x0 0x2000 0x0 0x98>;
#reset-cells = <1>;
};
cpu_version {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg=<0x0 0x10220 0x0 0x140>;
amlogic,has-chip-id;
};
};
crg_phy_20: crgphy20@fe03c000 {
compatible = "amlogic, amlogic-crg-drd-usb2";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe03a000 0x0 0x80
0x0 0xFE002000 0x0 0x100
0x0 0xfe03c000 0x0 0x2000>;
pll-setting-1 = <0x09400414>;
pll-setting-2 = <0x927E0000>;
pll-setting-3 = <0xac5f69e5>;
pll-setting-4 = <0xbe18>;
pll-setting-5 = <0x8000fff>;
pll-setting-6 = <0x78000>;
pll-setting-7 = <0xe0004>;
pll-setting-8 = <0xe000c>;
dis-thred-enhance = <0x2>;/**t7-0x38:bit[26-27]**/
version = <2>;
//power-domains = <&pwrdm PDID_SC2_USB_COMB>;
phy0-reset-level-bit = <8>;
usb-reset-bit = <4>;
reset-level = <0x40>;
pwr-ctl = <0>;
clocks = <&clkc CLKID_USB>;
clock-names = "crg_general";
phy-id = <0>;
};
crg_phy_21: crgphy21@fe03e000 {
compatible = "amlogic, amlogic-crg-drd-usb2";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe03a020 0x0 0x60
0x0 0xFE002000 0x0 0x100
0x0 0xfe03e000 0x0 0x2000>;
pll-setting-1 = <0x09400414>;
pll-setting-2 = <0x927E0000>;
pll-setting-3 = <0xac5f69e5>;
pll-setting-4 = <0xbe18>;
pll-setting-5 = <0x8000fff>;
pll-setting-6 = <0x78000>;
pll-setting-7 = <0xe0004>;
pll-setting-8 = <0xe000c>;
dis-thred-enhance = <0x2>;/**t7-0x38:bit[26-27]**/
version = <2>;
//power-domains = <&pwrdm PDID_SC2_USB_COMB>;
phy0-reset-level-bit = <9>;
usb-reset-bit = <4>;
reset-level = <0x40>;
pwr-ctl = <0>;
clocks = <&clkc CLKID_USB>;
clock-names = "crg_general";
phy-id = <1>;
};
crg3_phy_21: crg3phy21@fe03a080 {
compatible = "amlogic, amlogic-crg-drd-usb3";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe03a080 0x0 0x20>;
phy1-reg = <0xfe062000>;
phy1-reg-size = <0x2000>;
phy-pcie-reg = <0xfe02a000>;
phy-pcie-reg-size = <0x2000>;
reset-reg = <0xFE002000>;
reset-reg-size = <0x100>;
reset-level = <0x40>;
usb3-apb-reset-bit = <23>;
usb3-phy-reset-bit = <22>;
usb3-reset-shit = <0x4>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie_hcsl";
phy-id = <1>;
};
crg3_phy_20: crg3phy20@fe03a080 {
compatible = "amlogic, amlogic-crg-drd-usb3";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe03a080 0x0 0x20>;
phy1-reg = <0xfe062000>;
phy1-reg-size = <0x2000>;
phy-pcie-reg = <0xfe02a000>;
phy-pcie-reg-size = <0x2000>;
reset-reg = <0xFE002000>;
reset-reg-size = <0x100>;
reset-level = <0x40>;
usb3-apb-reset-bit = <23>;
usb3-phy-reset-bit = <22>;
usb3-reset-shit = <0x4>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie_hcsl";
phy-id = <0>;
};
crg20_otg: crg20otg@fe03a000 {
compatible = "amlogic, amlogic-crg-otg";
status = "disabled";
usb2-phy-reg = <0xfe03a000>;
usb2-phy-reg-size = <0x80>;
usb3-phy-reg = <0xfe03a080>;
usb3-phy-reg-size = <0x20>;
interrupts = <0 129 IRQ_TYPE_EDGE_RISING>;
};
crg21_otg: crg21otg@fe03a020 {
compatible = "amlogic, amlogic-crg-otg";
status = "disabled";
usb2-phy-reg = <0xfe03a020>;
usb2-phy-reg-size = <0x60>;
usb3-phy-reg = <0xfe03a080>;
usb3-phy-reg-size = <0x20>;
interrupts = <0 281 IRQ_TYPE_EDGE_RISING>;
};
crg2_drd: crg2drd@fdd00000 {
status = "disabled";
reg = <0x0 0xfdd00000 0x0 0x100000>;
interrupts = <0 131 IRQ_TYPE_EDGE_RISING>;
usb-phy = <&crg_phy_21>, <&crg3_phy_21>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_USB>;
clock-names = "crg_general";
};
crg3_drd: crg3drd@fde00000 {
status = "disabled";
reg = <0x0 0xfde00000 0x0 0x100000>;
interrupts = <0 130 IRQ_TYPE_EDGE_RISING>;
usb-phy = <&crg_phy_20>, <&crg3_phy_20>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_USB>;
clock-names = "crg_general";
};
crg_udc_3: crgudc3@0xfde00000 {
compatible = "amlogic, crg_udc";
status = "disable";
device_name = "crg_udc_3";
reg = <0x0 0xfde00000 0x0 0x100000>;
interrupts = <0 130 IRQ_TYPE_EDGE_RISING>;
clock-src = "usb0"; /** clock src */
port-speed = <5>; /** 0: default, high, 1: full */
phy-reg = <0xfe03a000>;
phy-reg-size = <0xa0>;
clocks = <&clkc CLKID_USB>;
clock-names = "usb_general";
phy-id = <0>;
};
crg_udc_2: crgudc2@0xfdd00000 {
compatible = "amlogic, crg_udc";
status = "disable";
device_name = "crg_udc_2";
reg = <0x0 0xfdd00000 0x0 0x100000>;
interrupts = <0 131 IRQ_TYPE_EDGE_RISING>;
clock-src = "usb0"; /** clock src */
port-speed = <3>; /** 0: default, high, 1: full */
phy-reg = <0xfe03a020>;
phy-reg-size = <0xa0>;
clocks = <&clkc CLKID_USB>;
clock-names = "usb_general";
phy-id = <1>;
};
dummy_codec:dummy{
#sound-dai-cells = <0>;
compatible = "amlogic, aml_dummy_codec";
status = "okay";
};
acodec:codec {
#sound-dai-cells = <0>;
compatible = "amlogic, tm2_revb_acodec";
reg = <0x0 0xfe01a000 0x0 0x1c>;
tdmout_index = <0>;
tdmin_index = <0>;
dat0_ch_sel = <1>;
reset-names = "acodec";
resets = <&reset RESET_ACODEC>;
status = "okay";
};
audio_data: audio_data {
compatible = "amlogic, audio_data";
mem_in_base_cmd = <0x82000020>;
query_licence_cmd = <0x82000050>;
status = "okay";
};
amaudio: amaudio {
compatible = "amlogic, amaudio";
reg = <0x0 0xfe440000 0x0 0x10000>;
reg-names = "otp_tee_base";
status = "okay";
};
audiobus: audiobus@0xFE330000 {
compatible = "amlogic, audio-controller", "simple-bus";
reg = <0x0 0xFE330000 0x0 0x3000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xFE330000 0x0 0x3000>;
power-domains = <&pwrdm PDID_T7_AUDIO>;
chip_id = <0x36>;
status = "okay";
clkaudio: audio_clocks {
compatible = "amlogic, t7-audio-clocks";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0xb0>;
status = "okay";
};
ddr_manager {
compatible =
"amlogic, t5-audio-ddr-manager";
interrupts = <
GIC_SPI 32 IRQ_TYPE_EDGE_RISING
GIC_SPI 33 IRQ_TYPE_EDGE_RISING
GIC_SPI 34 IRQ_TYPE_EDGE_RISING
GIC_SPI 45 IRQ_TYPE_EDGE_RISING
GIC_SPI 36 IRQ_TYPE_EDGE_RISING
GIC_SPI 37 IRQ_TYPE_EDGE_RISING
GIC_SPI 38 IRQ_TYPE_EDGE_RISING
GIC_SPI 46 IRQ_TYPE_EDGE_RISING
>;
interrupt-names =
"toddr_a", "toddr_b", "toddr_c",
"toddr_d",
"frddr_a", "frddr_b", "frddr_c",
"frddr_d";
status = "okay";
};
pinctrl_audio: pinctrl {
compatible = "amlogic, audio-pinctrl";
status = "okay";
};
};/* end of audiobus*/
/* eARC */
audio_earc: bus@fe333000 {
compatible = "simple-bus";
reg = <0x0 0xfe333000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe333000 0x0 0x1000>;
earc: earc@0 {
compatible = "amlogic, t7-snd-earc";
#sound-dai-cells = <0>;
status = "disabled";
reg = <0x0 0x0 0x0 0x400>,
<0x0 0x400 0x0 0x200>,
<0x0 0x600 0x0 0x200>,
<0x0 0x800 0x0 0x400>,
<0x0 0xc00 0x0 0x200>,
<0x0 0xe00 0x0 0x200>;
reg-names = "tx_cmdc",
"tx_dmac",
"tx_top",
"rx_cmdc",
"rx_dmac",
"rx_top";
clocks = < &clkaudio CLKID_EARCRX_CMDC
&clkaudio CLKID_EARCRX_DMAC
&clkc CLKID_FCLK_DIV4
&clkc CLKID_FCLK_DIV4
&clkaudio CLKID_EARCTX_CMDC
&clkaudio CLKID_EARCTX_DMAC
&clkc CLKID_FCLK_DIV4
&clkc CLKID_MPLL1
>;
clock-names =
"rx_cmdc",
"rx_dmac",
"rx_cmdc_srcpll",
"rx_dmac_srcpll",
"tx_cmdc",
"tx_dmac",
"tx_cmdc_srcpll",
"tx_dmac_srcpll";
interrupts = <
GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "earc_rx", "earc_tx";
};
};
/* Sound iomap */
aml_snd_iomap {
compatible = "amlogic, snd-iomap";
status = "okay";
#address-cells=<2>;
#size-cells=<2>;
ranges;
pdm_bus {
reg = <0x0 0xFE331000 0x0 0x400>;
};
audiobus_base {
reg = <0x0 0xFE330000 0x0 0x1000>;
};
audiolocker_base {
reg = <0x0 0xFE331400 0x0 0x400>;
};
eqdrc_base {
reg = <0x0 0xFE332000 0x0 0x1000>;
};
vad_base {
reg = <0x0 0xFE331800 0x0 0x400>;
};
resampleA_base {
reg = <0x0 0xFE331c00 0x0 0x104>;
};
resampleB_base {
reg = <0x0 0xFE334000 0x0 0x104>;
};
};
//hdmirx arc
hdmirx_arc {
compatible = "amlogic, hdmirx-arc-iomap";
reg = <0x0 0xfe39c000 0x0 0x10c>;
#address-cells = <2>;
#size-cells = <2>;
reg-names = "hdmirx-arc";
};
pcie: pcie@f5000000 {
compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie";
reg = <0x0 0xf5000000 0x0 0x400000
0x0 0xfe02c000 0x0 0x2000
0x0 0xf5400000 0x0 0x200000
0x0 0xfe02a000 0x0 0x2000
0x0 0xfe002044 0x0 0x10>;
reg-names = "elbi", "cfg", "config", "phy", "reset";
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ranges = <0x81000000 0 0 0 0xf5600000 0x0 0x100000
/* downstream I/O */
0x82000000 0 0xf5700000 0x0 0xf5700000 0 0x1900000>;
/* non-prefetchable memory */
num-lanes = <1>;
pcie-num = <1>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE
&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
"pcie_phy",
"pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <14>;
pcie-phy-rst-bit = <13>;
pcie-ctrl-a-rst-bit = <12>;
pwr-ctl = <0>;
power-domains = <&pwrdm PDID_T7_PCIE>;
pcie-ctrl-sleep-shift = <15>;
pcie-hhi-mem-pd-shift = <26>;
pcie-hhi-mem-pd-mask = <0xf>;
pcie-ctrl-iso-shift = <15>;
status = "disabled";
};
sd_emmc_c: mmc@fe08c000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xfe08c000 0x0 0x800>,
<0x0 0xfe000168 0x0 0x4>,
<0x0 0xfe004000 0x0 0x4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK_MUX>,
<&clkc CLKID_SD_EMMC_C_CLK>,
<&xtal>,
<&clkc CLKID_GP0_PLL>,
<&clkc CLKID_GP0_PLL>;
clock-names = "core", "mux0", "mux1",
"clkin0", "clkin1", "clkin2";
card_type = <1>;
src_clk_rate = <1152000000>;
mmc_debug_flag;
ignore_desc_busy;
tx_delay = <16>;
nwr_cnt = <12>;
// resets = <&reset RESET_SD_EMMC_C>;
};
sd_emmc_b: sd@fe08a000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xfe08a000 0x0 0x800>,
<0x0 0xfe00016c 0x0 0x4>,
<0x0 0xfe00401c 0x0 0x4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK_MUX>,
<&clkc CLKID_SD_EMMC_B_CLK>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "mux0", "mux1",
"clkin0", "clkin1";
card_type = <5>;
mmc_debug_flag;
//resets = <&reset RESET_SD_EMMC_B>;
};
sd_emmc_a: sdio@fe088000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xfe088000 0x0 0x800>,
<0x0 0xfe00016c 0x0 0x4>,
<0x0 0xfe004008 0x0 0x4>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_CLK_MUX>,
<&clkc CLKID_SD_EMMC_A_CLK>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "mux0", "mux1",
"clkin0", "clkin1";
card_type = <3>;
cap-sdio-irq;
keep-power-in-suspend;
use_intf3_tuning;
mmc_debug_flag;
//resets = <&reset RESET_SD_EMMC_A>;
};
ethmac: ethernet@fdc00000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-4.00";
reg = <0x0 0xfdc00000 0x0 0x10000>,
<0x0 0xfe024000 0x0 0x8>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
power-domains = <&pwrdm PDID_T7_ETH>;
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
/*1:inphy; 2:exphy;*/
internal_phy = <2>;
cali_val = <0x80000>;
status = "disabled";
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
uart_A: serial@fe078000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0xfe078000 0x0 0x18>;
interrupts = <0 168 1>;
status = "disabled";
clocks = <&xtal>;
clock-names = "clk_uart";
xtal_tick_en = <2>;
fifosize = < 64 >;
pinctrl-names = "default";
//pinctrl-0 = <&a_uart_pins1>;
};
// uart_A: serial@fe078000 {
// compatible = "amlogic, meson-uart";
// reg = <0x0 0xfe078000 0x0 0x18>;
// interrupts = <0 168 1>;
// status = "disabled";
// clocks = <&xtal
// &clkc CLKID_UART_A>;
// clock-names = "clk_uart",
// "clk_gate";
// xtal_tick_en = <3>;
// fifosize = < 128 >;
// pinctrl-names = "default";
// pinctrl-0 = <&a_uart_pins1>;
// };
//
uart_C: serial@fe07c000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0xfe07c000 0x0 0x18>;
interrupts = <0 170 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART_C>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&c_uart_pins>;
};
uart_D: serial@fe07e000 {
compatible = "amlogic,meson-uart";
status = "disabled";
reg = <0x0 0xfe07e000 0x0 0x18>;
interrupts = <0 171 1>;
clocks = <&xtal
&clkc CLKID_UART_D>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&d_uart_pins1>;
};
uart_E: serial@fe080000 {
compatible = "amlogic,meson-uart";
status = "disabled";
reg = <0x0 0xfe080000 0x0 0x18>;
interrupts = <0 172 1>;
clocks = <&xtal
&clkc CLKID_UART_E>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&e_uart_pins>;
};
uart_F: serial@fe082000 {
compatible = "amlogic,meson-uart";
status = "disabled";
reg = <0x0 0xfe082000 0x0 0x18>;
interrupts = <0 173 1>;
clocks = <&xtal
&clkc CLKID_UART_F>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&f_uart_pins>;
};
};
mesonstream {
compatible = "amlogic, codec, streambuf";
dev_name = "mesonstream";
status = "okay";
clocks = <&clkc CLKID_DOS
&clkc CLKID_VDEC_MUX
&clkc CLKID_HCODEC_MUX
&clkc CLKID_HEVCF_MUX
&clkc CLKID_HEVCB_MUX>;
clock-names = "vdec",
"clk_vdec_mux",
"clk_hcodec_mux",
"clk_hevcf_mux",
"clk_hevcb_mux";
assigned-clock-parents = <&clkc CLKID_VDEC_P0>,
<&clkc CLKID_HEVCF_P0>,
<&clkc CLKID_HEVCB_P0>;
assigned-clocks = <&clkc CLKID_VDEC_MUX>,
<&clkc CLKID_HEVCF_MUX>,
<&clkc CLKID_HEVCB_MUX>;
};
isp_sc: isp-sc@fe3b1400 {
compatible = "amlogic, isp-sc";
reg = <0x0 0xfe3b1400 0x0 0x00000400>,
<0x0 0xfe3b1800 0x0 0x00000400>,
<0x0 0xfe3b1c00 0x0 0x00000400>,
<0x0 0xfe3b2000 0x0 0x00000400>;
reg-names = "isp_sc0", "isp_sc1", "isp_sc2", "isp_crop";
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 308 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "isp_sc0", "isp_sc1", "isp_sc2", "isp_crop";
};
isp_md: isp-md@fe3b2800 {
compatible = "amlogic, isp-md";
reg = <0x0 0xfe3b2800 0x0 0x00000400>;
reg-names = "isp_md";
interrupts = <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "isp_md";
};
isp_flicker: isp-flicker@fe3b2c00 {
compatible = "amlogic, isp-flicker";
reg = <0x0 0xfe3b2c00 0x0 0x00000400>;
reg-names = "isp_flicker";
interrupts = <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "isp_flicker";
};
isp_cmpr: isp-cmpr@fe3b4000 {
compatible = "amlogic, isp-cmpr";
reg = <0x0 0xfe3b4000 0x0 0x00001800>,
<0x0 0xfe3b3000 0x0 0x0001000>;
reg-names = "isp_cmpr","isp_top";
interrupts = <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 316 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tnr_cmpr","adapt_cmpr";
};
isp: isp@fa000000 {
compatible = "arm, isp";
reg = <0x0 0xfa000000 0x0 0x00040000>;
reg-names = "ISP";
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ISP";
clk-level = <0>;
clocks = <&clkc CLKID_MIPI_ISP>,
<&clkc CLKID_MIPI_CSI_PHY0>;
clock-names = "cts_mipi_isp_clk",
"cts_mipi_csi_phy_clk0";
assigned-clock-parents = <&clkc CLKID_MIPI_CSI_PHY0>;
assigned-clocks = <&clkc CLKID_MIPI_CSI_PHY_CLK>;
power-domains = <&pwrdm PDID_T7_ISP>;
link-device = <&isp_sc>;
att-device = <&isp_flicker>;
cmpr-device = <&isp_cmpr>;
md-device = <&isp_md>;
};
adapter: isp-adapter@fe3b0000 {
compatible = "amlogic, isp-adapter";
reg = <0x0 0xfe3b0000 0x0 0x00005800>,
<0x0 0xfe3b0800 0x0 0x00000400>;
reg-names = "adapter","adapter2";
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "adapter-irq";
};
phycsi: phy-csi@fe3be000 {
compatible = "amlogic, phy-csi";
reg = <0x0 0xfe3bfc00 0x0 0x00000400>,
<0x0 0xfe3bf800 0x0 0x00000400>,
<0x0 0xfe3bf400 0x0 0x00000400>,
<0x0 0xfe3bf000 0x0 0x00000400>,
<0x0 0xfe3bdc00 0x0 0x00000100>,
<0x0 0xfe3bec00 0x0 0x00000400>,
<0x0 0xfe3be800 0x0 0x00000400>,
<0x0 0xfe3be400 0x0 0x00000400>,
<0x0 0xfe3be000 0x0 0x00000400>;
reg-names = "csi2_phy0", "csi2_phy1", "csi2_phy2", "csi2_phy3", "aphy_reg",
"csi0_host", "csi1_host", "csi2_host", "csi3_host";
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "phy0-irq",
"phy1-irq",
"phy2-irq",
"phy3-irq",
"csi-host0-intr1",
"csi-host0-intr2",
"csi-host1-intr1",
"csi-host1-intr2",
"csi-host2-intr1",
"csi-host2-intr2",
"csi-host3-intr1",
"csi-host3-intr2";
link-device = <&adapter>;
};
vdec {
compatible = "amlogic, vdec-pm-pd";
dev_name = "vdec.0";
status = "okay";
interrupts = <0 3 1
0 23 1
0 32 1
0 91 1
0 92 1
0 93 1
0 72 1>;
interrupt-names = "vsync",
"demux",
"parser",
"mailbox_0",
"mailbox_1",
"mailbox_2",
"parser_b";
power-domains = <&pwrdm PDID_T7_DOS_VDEC>,
<&pwrdm PDID_T7_DOS_HCODEC>,
<&pwrdm PDID_T7_DOS_HEVC>,
<&pwrdm PDID_T7_DOS_WAVE>;
power-domain-names = "pwrc-vdec",
"pwrc-hcodec",
"pwrc-hevc",
"pwrc-wave";
};
cpu_ver_name {
compatible = "amlogic, cpu-major-id-t7";
};
vcodec_dec {
compatible = "amlogic, vcodec-dec";
dev_name = "aml-vcodec-dec";
status = "okay";
};
multi-di {
compatible = "amlogic, dim-t7";
status = "okay";
/* 0:use reserved; 1:use cma; 2:use cma as reserved */
flag_cma = <4>; //<1>;
//memory-region = <&di_reserved>;
//memory-region = <&di_cma_reserved>;
interrupts = <0 203 1
0 202 1>;
interrupt-names = "pre_irq", "post_irq";
clocks = <&clkc CLKID_VPU_CLKB>,
<&clkc CLKID_VPU>;
clock-names = "vpu_clkb",
"vpu_mux";
clock-range = <334 667>;
/* buffer-size = <3621952>;(yuv422 8bit) */
buffer-size = <4074560>;/*yuv422 fullpack*/
/* reserve-iomap = "true"; */
/* if enable nr10bit, set nr10bit-support to 1 */
post-wr-support = <1>;
nr10bit-support = <1>;
nrds-enable = <1>;
pps-enable = <1>;
en_4k = <1>;
keep_dec_vf = <2>;
po_fmt = <6>;
post_nub = <11>;
alloc_sct = <1>;
hf = <0>;
/***************************************************
* t3 support 4k ,same with t7 ,no canvas,
* post_nub---default is 11
* (T7/T3/SC2/S4 new path)
* post 11*5222400 = 56M,local 7*4075520 = 28m
* flag_cma---0: use reserved; 1:use cma;
* 2:use cma as reserved 4:use codec mem
* en_4k :en_4k---0: not support 4K; 1: enable 4K
* 2: dynamic: vdin: 4k enable,
* other source 4k disable
* 8: when 4k,
* output with a resolution is below 1080p
* keep_dec_vf---0:not keep; 1: keep dec vf for p;
* 2: dynamic keep dec vf for p,other is disable
* po_fmt---1: NV21/8; 2: nv12/8; 3: AFBC 422/10BIT;
* 4: dynamic(4K AFBC,10/422);
* 6: dynamic(from decoder 4K source,
* out is AFBC,10/420),
* other is 422/10BIT
* bypass_mem---0:nr not bypass; 1: nr bypass;
* 2: when 4k input ,nr is bypass;
* 3: bypass nr for 4k,but not from vdin;
* alloc_sct---0:not support; bit 0: for 4k; bit 1: for 1080p
* hf---0:not enable; 1: enable
***************************************************/
};
ddr_bandwidth {
compatible = "amlogic,ddr-bandwidth-t7";
status = "okay";
reg = <0 0xfe036000 0 0x400
0 0xfe034000 0 0x400
0 0xfe0a0000 0 0x100>;
interrupts = <0 332 IRQ_TYPE_EDGE_RISING
0 336 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ddr_bandwidth";
};
dmc_monitor {
compatible = "amlogic,dmc_monitor-t7";
status = "okay";
reg = <0 0xfe036000 0 0x400
0 0xfe034000 0 0x400>;
reg_base = <0xfe036000>;
interrupts = <0 333 IRQ_TYPE_EDGE_RISING
0 337 IRQ_TYPE_EDGE_RISING>;
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx-t7";
dev_name = "amhdmitx";
status = "disabled";
power-domains = <&pwrdm PDID_T7_VI_CLK2>;
vend-data = <&vend_data>;
pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
pinctrl-0=<&hdmitx_hpd>;
pinctrl-1=<&hdmitx_ddc>;
interrupts = <0 204 1>;
interrupt-names = "hdmitx_hpd";
enc_idx = <0>;
reg = <0x0 0xff000000 0x0 0x40000>,
<0x0 0xfe380000 0x0 0x10000>,
<0x0 0xfe300000 0x0 0x10000>,
<0x0 0xfe010000 0x0 0x2000>,
<0x0 0xfe00c000 0x0 0x2000>,
<0x0 0xfe008000 0x0 0x2000>,
<0x0 0xfe002000 0x0 0x2000>,
<0x0 0xfe000000 0x0 0x2000>,
<0x0 0xfe004000 0x0 0x200>;
reg-names = "vpu",
"hdmitxcor",
"hdmitxtop",
"sysctrl",
"pwrctrl",
"anactrl",
"resetctrl",
"clkctrl",
"padctrl";
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
};
};
aocec: aocec {
compatible = "amlogic, aocec-t7";
dev_name = "aocec";
status = "okay";
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* Refer to the following URL at:
* http://standards.ieee.org/develop/regauth/oui/oui.txt
*/
vendor_id = <0x000000>;
product_desc = "T7"; /* Max Chars: 16 */
cec_osd_string = "AML_TV"; /* Max Chars: 14 */
cec_version = <5>;/*5:1.4;6:2.0*/
port_num = <4>;
output = <1>;
cec_sel = <1>;/*1:use one ip, 2:use 2 ip*/
/*ee_cec;*/ /*use cec a or b*/
arc_port_mask = <0x2>;
interrupts = <GIC_SPI 180 IRQ_TYPE_EDGE_RISING/*0:snps*/
GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;/*1:ts*/
interrupt-names = "hdmi_aocecb","hdmi_aocec";
pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep";
pinctrl-0=<&cec_a>;
pinctrl-1=<&cec_b>;
pinctrl-2=<&cec_b>;
clocks = <&clkc CLKID_CECA_32K_CLKOUT>,
<&clkc CLKID_CECB_32K_CLKOUT>;
clock-names = "ceca_clk","cecb_clk";
reg = <0x0 0xfe044000 0x0 0x2ff
0x0 0xfe004000 0x0 0x2000
0x0 0xfe000000 0x0 0xfff>;
reg-names = "ao","periphs","clock"/*ao_exit hdmirx hhi*/;
};
aml_dma {
compatible = "amlogic,aml_txlx_dma";
reg = <0x0 0xfe440400 0x0 0x48>;
interrupts = <0 24 1>;
aml_aes {
compatible = "amlogic,aes_g12a_dma";
dev_name = "aml_aes_dma";
status = "okay";
iv_swap = /bits/ 8 <0x0>;
};
aml_sha {
compatible = "amlogic,sha_dma";
dev_name = "aml_sha_dma";
status = "okay";
};
aml_tdes {
compatible = "amlogic,tdes_dma";
dev_name = "aml_tdes_dma";
status = "okay";
};
};
rng {
compatible = "amlogic,meson-rng";
status = "okay";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xfe440788 0x0 0x0c>;
quality = /bits/ 16 <1000>;
version = <2>;
};
canvas: canvas{
compatible = "amlogic, meson, canvas";
dev_name = "amlogic-canvas";
status = "okay";
reg = <0x0 0xfe036048 0x0 0x2000>;
};
codec_io: codec_io {
compatible = "amlogic, meson-t7, codec-io";
status = "okay";
#address-cells=<2>;
#size-cells=<2>;
ranges;
/* use cbus space for reset_ctrl*/
reg = <0x0 0xfe002000 0x0 0x2000>,
<0x0 0xfe320000 0x0 0x10000>,
<0x0 0x0 0x0 0x0>,
<0x0 0x0 0x0 0x00>,
<0x0 0xff000000 0x0 0x40000>,
<0x0 0xfe036000 0x0 0x2000>,
<0x0 0x0 0x0 0x0>;
reg-names = "cbus",
"dosbus",
"hiubus",
"aobus",
"vcbus",
"dmcbus",
"efusebus";
};
jpegenc{
compatible = "amlogic, jpegenc";
dev_name = "jpegenc";
status = "okay";
clocks = <&clkc CLKID_DOS
&clkc CLKID_VAPB
&clkc CLKID_HCODEC_MUX>;
clock-names =
"clk_dos",
"clk_apb_dos",
"clk_jpeg_enc";
/*
clocks = <&clkc CLKID_HCODEC_P0>;
clock-names = "hcodec_p0";
*/
power-domains = <&pwrdm PDID_T7_DOS_HCODEC>;
interrupts = <0 91 1 0 92 1 0 93 1>;
interrupt-names = "dos_mbox_slow_irq0", "dos_mbox_slow_irq1", "dos_mbox_slow_irq2";
//reset-names = "jpegenc_rst";
//resets = <&reset RESET_BRG_HCODEC_PIPL0>;
};
aml_enc {
compatible = "cnm, MultiEnc";
dev_name = "amvenc_multi";
status = "okay";
config_mm_sz_mb = <200>;
clocks = <&clkc CLKID_DOS
&clkc CLKID_VAPB
&clkc CLKID_WAVE_A_GATE
&clkc CLKID_WAVE_B_GATE
&clkc CLKID_WAVE_C_GATE>;
clock-names =
"clk_dos",
"clk_apb_dos",
"clk_MultiEnc_A",
"clk_MultiEnc_B",
"clk_MultiEnc_C";
interrupts = <0 94 1 0 95 1>;
interrupt-names = "multienc_irq", "multienc_idle_irq";
#address-cells=<2>;
#size-cells=<2>;
pwr-ctl = <0>;
power-domains = <&pwrdm PDID_T7_DOS_WAVE>;
ranges;
io_reg_base {
reg = <0x0 0xfe310000 0x0 0x10000>;
};
};
vpu: vpu {
compatible = "amlogic, vpu-t7";
status = "okay";
reg = <0x0 0xfe000000 0x0 0x100 /* clk */
0x0 0xfe00c000 0x0 0x70 /* pwrctrl */
0x0 0xff000000 0x0 0xa000>; /* vcbus */
clocks = <&clkc CLKID_VAPB>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU_1>,
<&clkc CLKID_VPU>;
clock-names = "vapb_clk",
"vpu_intr_gate",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
};
meson_uvm{
compatible = "amlogic, meson_uvm";
status = "okay";
};
meson_videotunnel{
compatible = "amlogic, meson_videotunnel";
status = "okay";
};
video_composer {
compatible = "amlogic, video_composer";
dev_name = "video_composer";
status = "okay";
};
rdma{
compatible = "amlogic, meson-t7, rdma";
status = "okay";
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "rdma";
/* after sc2 */
reset-names = "rdma";
resets = <&reset RESET_RDMA>;
rdma_table_page_count = <16>;
};
vclk_serve: vclk_serve {
compatible = "amlogic, vclk_serve";
status = "okay";
reg = <0x0 0xfe008000 0x0 0x400 /* ana reg */
0x0 0xfe000000 0x0 0x4a0>; /* clk reg */
};
dummy_venc: dummy_venc {
compatible = "amlogic, dummy_venc_t7";
status = "okay";
};
vout_mux: vout_mux {
compatible = "amlogic, vout_mux-t7";
status = "okay";
};
vout: vout {
compatible = "amlogic, vout";
status = "okay";
};
vout2: vout2 {
compatible = "amlogic, vout2";
status = "okay";
};
vout3: vout3 {
compatible = "amlogic, vout3";
status = "okay";
};
vrr0: vrr0 {
compatible = "amlogic, vrr-t3";
status = "okay";
index = <0>;
};
vrr1: vrr1 {
compatible = "amlogic, vrr-t3";
status = "okay";
index = <1>;
};
vrr2: vrr2 {
compatible = "amlogic, vrr-t3";
status = "okay";
index = <2>;
};
ir: ir@8000 {
compatible = "amlogic, meson-ir";
reg = <0x0 0xfe084040 0x0 0xA4>,
<0x0 0xfe084000 0x0 0x20>;
status = "disable";
protocol = <REMOTE_TYPE_NEC>;
interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
map = <&custom_maps>;
max_frame_time = <200>;
};
a73_tsensor: a73_tsensor@fe020000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe020000 0x0 0x50>;
tsensor_id = <1>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK_GATE>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
a53_tsensor: a53_tsensor@fe022000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe022000 0x0 0x50>;
tsensor_id = <2>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK_GATE>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
gpu_tsensor: gpu_tsensor@fe094000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe094000 0x0 0x50>;
tsensor_id = <3>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK_GATE>;
clock-names = "ts_comp";
power-domains = <&pwrdm PDID_T7_MALI_TOP>;
#thermal-sensor-cells = <1>;
};
nna_tsensor: nna_tsensor@fe096000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe096000 0x0 0x50>;
tsensor_id = <4>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK_GATE>;
clock-names = "ts_comp";
power-domains = <&pwrdm PDID_T7_NNA_TOP>;
#thermal-sensor-cells = <1>;
};
hevc_tsensor: hevc_tsensor@fe09a000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe09a000 0x0 0x50>;
tsensor_id = <5>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK_GATE>;
clock-names = "ts_comp";
power-domains = <&pwrdm PDID_T7_DOS_HEVC>;
#thermal-sensor-cells = <1>;
};
vpu_tsensor: vpu_tsensor@fe098000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe098000 0x0 0x50>;
tsensor_id = <6>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK_GATE>;
clock-names = "ts_comp";
power-domains = <&pwrdm PDID_T7_VPU_HDMI>;
#thermal-sensor-cells = <1>;
};
meson_cooldev: meson-cooldev@0 {
status = "okay";
compatible = "amlogic, meson-cooldev";
cooling_devices {
cpucore_cool_cluster0 {
cluster_id = <0>;
node_name = "cpucore_cool0";
device_type = "cpucore";
};
cpucore_cool_cluster1 {
cluster_id = <1>;
node_name = "cpucore_cool1";
device_type = "cpucore";
};
gpufreq_cool {
dyn_coeff = <358>;
node_name = "bifrost";
device_type = "gpufreq";
};
};
cpucore_cool0:cpucore_cool0 {
#cooling-cells = <2>;
};
cpucore_cool1:cpucore_cool1 {
#cooling-cells = <2>;
};
};/*meson cooling devices end*/
thermal-zones {
soc_thermal: soc_thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
sustainable-power = <5160>;
thermal-sensors = <&a73_tsensor 0>;
trips {
a73switch_on: trip-point@0 {
temperature = <80000>;
hysteresis = <5000>;
type = "passive";
};
a73control: trip-point@1 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
a73critical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
cpufreq_cooling_map0 {
trip = <&a73control>;
cooling-device = <&CPU0 0 6>;
contribution = <1024>;
};
};
};
a53_thermal: a53_thermal {
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <960>;
thermal-sensors = <&a53_tsensor 1>;
trips {
a53switch_on: trip-point@0 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
a53control: trip-point@1 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
a53critical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
cpufreq_cooling_map1 {
trip = <&a53control>;
cooling-device = <&CPU4 0 5>;
contribution = <1024>;
};
};
};
gpu_thermal: gpu_thermal {
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <400>;
thermal-sensors = <&gpu_tsensor 2>;
trips {
gpuswitch_on: trip-point@0 {
temperature = <85000>;
hysteresis = <5000>;
type = "passive";
};
gpucontrol: trip-point@1 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
gpucritical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nna_thermal: nna_thermal {
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <3550>;
thermal-sensors = <&nna_tsensor 3>;
trips {
nnaswitch_on: trip-point@0 {
temperature = <85000>;
hysteresis = <5000>;
type = "passive";
};
nnacontrol: trip-point@1 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
nnacritical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
hevc_thermal: hevc_thermal {
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <3550>;
thermal-sensors = <&hevc_tsensor 4>;
trips {
hevcswitch_on: trip-point@0 {
temperature = <85000>;
hysteresis = <5000>;
type = "passive";
};
hevccontrol: trip-point@1 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
hevccritical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
vpu_thermal: vpu_thermal {
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <3550>;
thermal-sensors = <&vpu_tsensor 5>;
trips {
vpuswitch_on: trip-point@0 {
temperature = <85000>;
hysteresis = <5000>;
type = "passive";
};
vpucontrol: trip-point@1 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
vpucritical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};/*thermal zone end*/
ion_dev {
compatible = "amlogic, ion_dev";
memory-region = <&ion_cma_reserved
&ion_secure_reserved
&ion_fb_reserved>;
};
fb: fb {
compatible = "amlogic, fb-t7";
memory-region = <&logo_reserved>;
status = "disabled";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING
GIC_SPI 194 IRQ_TYPE_EDGE_RISING
GIC_SPI 82 IRQ_TYPE_EDGE_RISING
GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "viu-vsync", "viu2-vsync", "viu3-vsync", "rdma";
/* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/
display_mode_default = "1080p60hz";
scale_mode = <1>;
/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
display_size_default = <1920 1080 1920 2160 32>;
};
irblaster: meson-irblaster@fe08410c {
compatible = "amlogic, meson_irblaster";
status = "disabled";
reg = <0x0 0xfe08410c 0x0 0x10>;
#irblaster-cells = <2>;
interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
};
/*if you want to use vdin just modify status to "ok"*/
vdin0: vdin0 {/*common define*/
compatible = "amlogic, vdin-t7";
dev_name = "vdin0";
/*status = "disabled";*/
/*memory-region = <&vdin0_cma_reserved>;*/
reserve-iomap = "true";
flag_cma = <0x101>;/*1:share with codec_mm;2:cma alone*/
/*MByte, if 10bit disable: 64M(YUV422),
*if 10bit enable: 64*1.5 = 96M(YUV422)
*if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M
*if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M
*if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
*if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
* onebuffer:
* worst case:(4096*2160*3 + 2M(afbce issue)) = 27.5M
* dw:960x540x3 = 1.5M
* total size:(27.5+1.5)x buffernumber
*/
/*cma_size = <174>;*/
/*frame_buff_num = <6>;*/
interrupts = <0 210 1 /* vdin0 vsync */
0 214 1 /* vdin1 write down*/
/*0 206 1*/ /* vpu crash */
/*0 213 1*/>; /* vdin0 write down*/
interrupt-names = "vsync_int",
"mif2_meta_wr_done_int"
/*"vpu_crash_int",*/
/*"write_done_int"*/;
rdma-irq = <2>;
clocks = <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_VDIN_MEAS_GATE>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <0>;
/*vdin write mem color depth support:
* bit0:support 8bit
* bit1:support 9bit
* bit2:support 10bit
* bit3:support 12bit
* bit4:support yuv422 10bit full pack mode (from txl new add)
* bit5:force yuv422 to yuv444 malloc (for vdin0 debug)
* bit8:use 8bit at 4k_50/60hz_10bit
* bit9:use 10bit at 4k_50/60hz_10bit
* bit10: support 10bit when double write
*/
tv_bit_mode = <0x235>;
/* afbce_bit_mode: (amlogic frame buff compression encoder)
* bit0 -- enable afbce
* bit1 -- enable afbce compression-lossy
* bit4 -- afbce for 4k
* bit5 -- afbce for 1080p
* bit6 -- afbce for 720p
* bit7 -- afbce for smaller resolution
*/
afbce_bit_mode = <0x11>;
/* urgent_en; */
double_write_en;
};
vdin1: vdin1 {/*common define*/
compatible = "amlogic, vdin-t7";
dev_name = "vdin1";
/*status = "disabled";*/
reserve-iomap = "true";
/*memory-region = <&vdin1_cma_reserved>;*/
flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
interrupts = <0 212 1>;
interrupt-names = "vsync_int"/*, "vpu_crash_int",*/
/*"write_done_int"*/;
rdma-irq = <4>;
/*clocks = <&clock CLK_FPLL_DIV5>,
* <&clock CLK_VDIN_MEAS_CLK>;
*clock-names = "fclk_div5", "cts_vdin_meas_clk";
*/
vdin_id = <1>;
tv_bit_mode = <0x15>;
};
amlvecm: amlvecm {
compatible = "amlogic, vecm-t7";
dev_name = "aml_vecm";
/*status = "okay";*/
/*gamma_en = <1>;*/ /*1:enabel ;0:disable*/
/*wb_en = <1>;*/ /*1:enabel ;0:disable*/
/*cm_en = <1>;*/ /*1:enabel ;0:disable*/
/*wb_sel = <0>;*/ /*1:mtx ;0:gainoff*/
/*vlock_en = <1>;*/ /*1:enable;0:disable*/
/*vlock_mode = <0x8>;*/
/* vlock work mode:
*bit0:auto ENC
*bit1:auto PLL
*bit2:manual PLL
*bit3:manual ENC
*bit4:manual soft ENC
*bit5:manual MIX PLL ENC
*/
/* vlock_pll_m_limit = <1>;*/
/* vlock_line_limit = <2>;*/
clocks = <&clkc CLKID_VID_LOCK>;
clock-names = "cts_vid_lock_clk";
};
amvideom: meson-amvideom {
compatible = "amlogic, amvideom-t7";
dev_name = "amvideom";
status = "okay";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING
GIC_SPI 194 IRQ_TYPE_EDGE_RISING
GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "vsync", "vsync_viu2", "vsync_viu3";
};
vpu_security {
compatible = "amlogic, meson-t7, vpu_security";
dev_name = "amlogic-vpu-security";
status = "okay";
interrupts = <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "vpu_security";
};
dmx_aucpu: aucpu {
compatible = "amlogic, aucpu";
dev_name = "aml_aucpu";
status = "okay";
interrupts = <0 77 1>;
interrupt-names = "aucpu_irq";
#address-cells=<2>;
#size-cells=<2>;
ranges;
io_reg_base{
reg = <0x0 0xfe09e080 0x0 0x100>;
};
};
ge2d {
compatible = "amlogic, ge2d-t7";
status = "okay";
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ge2d";
clocks = <&clkc CLKID_VAPB>,
<&clkc CLKID_G2D>,
<&clkc CLKID_GE2D>;
clock-names = "clk_vapb_0",
"clk_ge2d",
"clk_ge2d_gate";
reg = <0x0 0xff040000 0x0 0x100>;
power-domains = <&pwrdm PDID_T7_GE2D>;
};
aml_bt: aml_bt {
compatible = "amlogic, aml-bt";
status = "disabled";
};
aml_wifi: aml_wifi {
compatible = "amlogic, aml-wifi";
status = "disabled";
irq_trigger_type = "GPIO_IRQ_LOW";
dhd_static_buf;
//pinctrl-0 = <&pwm_e_pins>;
//pinctrl-names = "default";
pwm_config = <&wifi_pwm_conf>;
};
wifi_pwm_conf:wifi_pwm_conf{
pwm_channel1_conf {
pwms = <&pwm_ab 0 30550 0>;
duty-cycle = <15270>;
times = <8>;
};
pwm_channel2_conf {
pwms = <&pwm_ab 2 30500 0>;
duty-cycle = <15250>;
times = <12>;
};
};
gdc {
#address-cells=<2>;
#size-cells=<2>;
status = "okay";
compatible = "amlogic, arm-gdc";
reg = <0 0xfe08e000 0 0x0000100
0 0xfe0104c4 0 0x4>;
interrupts = <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "gdc";
clocks = <&clkc CLKID_GDCCLK_0>,
<&clkc CLKID_GDCCLK>,
<&clkc CLKID_GDC_CLK>;
clock-names = "mux_gate", "mux_sel", "clk_gate";
clk-rate = <800000000>;
power-domains = <&pwrdm PDID_T7_GDC>;
};
amlgdc {
#address-cells=<2>;
#size-cells=<2>;
status = "okay";
compatible = "amlogic, aml-gdc";
reg = <0 0xfe040000 0 0x000015c>;
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "amlgdc";
clocks = <&clkc CLKID_DEWARPCLK_0>,
<&clkc CLKID_DEWARPCLK>,
<&clkc CLKID_DEWARP_CLK>;
clock-names = "mux_gate", "mux_sel", "clk_gate";
clk-rate = <800000000>;
power-domains = <&pwrdm PDID_T7_DEWARP>;
};
mhu_fifo: mhu@0 {
status = "okay";
compatible = "amlogic, meson_mhu_fifo";
reg = <0x0 0xfe006000 0x0 0x1000>, /* mhu wr fifo */
<0x0 0xfe007180 0x0 0x80>, /* mhu set reg */
<0x0 0xfe007200 0x0 0x80>, /* mhu clr reg */
<0x0 0xfe007280 0x0 0x80>, /* mhu sts reg */
<0x0 0xfe007040 0x0 0xc0>; /* mhu irqctrl reg */
interrupts = <0 248 1>; /* irq top */
mbox-irqmax = <64>;
mbox-irqctlr = <0>;
mbox-nums = <6>;
mbox-names = "dsp_dev",
"ap_to_dspa",
"dspb_dev",
"ap_to_dspb",
"ao_dev",
"ap_to_ao";
mboxes = <&mhu_fifo 0>,
<&mhu_fifo 1>,
<&mhu_fifo 2>,
<&mhu_fifo 3>,
<&mhu_fifo 4>,
<&mhu_fifo 5>;
mbox-id = <0x0 0x1 0x6 0x7 0x2 0x3>;
mbox-wr-rd = <1>;
#mbox-cells = <1>;
};
lut_dma:lut_dma {
compatible = "amlogic, meson-t7, lut_dma";
status = "okay";
};
state_led:state_led {
compatible = "amlogic,state-led-aocpu";
status = "disabled";
};
efuse: efuse{
compatible = "amlogic, efuse";
read_cmd = <0x82000030>;
write_cmd = <0x82000031>;
get_max_cmd = <0x82000033>;
mem_in_base_cmd = <0x82000020>;
mem_out_base_cmd = <0x82000021>;
efuse_pattern_size = <0x600>;
key = <&efusekey>;
clock-names = "efuse_clk";
status = "okay";
};
efusekey:efusekey{
keynum = <4>;
key0 = <&key_0>;
key1 = <&key_1>;
key2 = <&key_2>;
key3 = <&key_3>;
key_0:key_0{
keyname = "mac";
offset = <0>;
size = <6>;
};
key_1:key_1{
keyname = "mac_bt";
offset = <6>;
size = <6>;
};
key_2:key_2{
keyname = "mac_wifi";
offset = <12>;
size = <6>;
};
key_3:key_3{
keyname = "usid";
offset = <18>;
size = <16>;
};
};
gpu_opp_table: gpu_opp_table {
compatible = "operating-points-v2";
opp-285 {
opp-hz = /bits/ 64 <285714281>;
opp-microvolt = <1150>;
};
opp-400 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150>;
};
opp-500 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1150>;
};
opp-666 {
opp-hz = /bits/ 64 <666666666>;
opp-microvolt = <1150>;
};
opp-800 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1150>;
};
};
};
&periphs_pinctrl {
i2c0_pins1:i2c0_pins1 {
mux {
groups = "i2c0_sda_t",
"i2c0_sck_t";
function = "i2c0";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c0_pins2:i2c0_pins2 {
mux {
groups = "i2c0_sda_h",
"i2c0_sck_h";
function = "i2c0";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c1_pins1:i2c1_pins1 {
mux {
groups = "i2c1_sda",
"i2c1_sck";
function = "i2c1";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c2_pins1:i2c2_pins1 {
mux {
groups = "i2c2_sda_x",
"i2c2_sck_x";
function = "i2c2";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c2_pins2:i2c2_pins2 {
mux {
groups = "i2c2_sda_t",
"i2c2_sck_t";
function = "i2c2";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c2_pins3:i2c2_pins3 {
mux {
groups = "i2c2_sda_m",
"i2c2_sck_m";
function = "i2c2";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c3_pins1:i2c3_pins1 {
mux {
groups = "i2c3_sda_m",
"i2c3_sck_m";
function = "i2c3";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c3_pins2:i2c3_pins2 {
mux {
groups = "i2c3_sda_h",
"i2c3_sck_h";
function = "i2c3";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c4_pins1:i2c4_pins1 {
mux {
groups = "i2c4_sda_y",
"i2c4_sck_y";
function = "i2c4";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c4_pins2:i2c4_pins2 {
mux {
groups = "i2c4_sda_h",
"i2c4_sck_h";
function = "i2c4";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c5_pins1:i2c5_pins1 {
mux {
groups = "i2c5_sda",
"i2c5_sck";
function = "i2c5";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c0_ao_pins1:i2c0_ao_pins1 {
mux {
groups = "i2c0_ao_sda_d",
"i2c0_ao_sck_d";
function = "i2c0_ao";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c0_ao_pins2:i2c0_ao_pins2 {
mux {
groups = "i2c0_ao_sda_e",
"i2c0_ao_sck_e";
function = "i2c0_ao";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c1_ao_pins1:i2c1_ao_pins1 {
mux {
groups = "i2c1_ao_sda",
"i2c1_ao_sck";
function = "i2c1_ao";
drive-strength-microamp = <3000>;
bias-disable;
};
};
a_uart_pins1:a_uart1 {
mux {
groups = "uart_a_tx_d2",
"uart_a_rx_d3";
function = "uart_a";
};
};
a_uart_pins2:a_uart2 {
mux {
groups = "uart_a_tx_d8",
"uart_a_rx_d9";
function = "uart_a";
};
};
b_uart_pins:b_uart {
mux {
groups = "uart_ao_b_tx",
"uart_ao_b_rx";
function = "uart_ao_b";
};
};
c_uart_pins:c_uart {
mux {
groups = "uart_c_tx",
"uart_c_rx",
"uart_c_cts",
"uart_c_rts";
bias-pull-up;
output-high;
function = "uart_c";
};
};
d_uart_pins1:d_uart1 {
mux {
groups = "uart_d_tx_m",
"uart_d_rx_m";
function = "uart_d";
};
};
d_uart_pins2:d_uart2 {
mux {
groups = "uart_d_tx_y",
"uart_d_rx_y";
function = "uart_d";
};
};
e_uart_pins:e_uart {
mux {
groups = "uart_e_tx",
"uart_e_rx",
"uart_e_cts",
"uart_e_rts";
bias-pull-up;
output-high;
function = "uart_e";
};
};
f_uart_pins:f_uart {
mux {
groups = "uart_f_tx",
"uart_f_rx";
function = "uart_f";
};
};
emmc_pins: emmc {
mux-0 {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_cmd";
function = "emmc";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux-1 {
groups = "emmc_clk";
function = "emmc";
bias-disable;
drive-strength-microamp = <4000>;
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_nand_ds";
function = "emmc";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "GPIOB_8";
function = "gpio_periphs";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
/* sdemmc portB */
sd_clk_cmd_pins:sd_clk_cmd_pins {
mux {
groups = "sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux1 {
groups = "sdcard_clk";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sd_all_pins:sd_all_pins {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux1 {
groups = "sdcard_clk";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sd_clk_gate_pins: sd_clk_gate {
mux {
groups = "GPIOC_4";
function = "gpio_periphs";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
sd_all_pd_pins:sd_all_pd_pins {
mux {
groups = "GPIOC_0",
"GPIOC_1",
"GPIOC_2",
"GPIOC_3",
"GPIOC_4",
"GPIOC_5";
function = "gpio_periphs";
bias-pull-down;
output-low;
};
};
sd_1bit_pins:sd_1bit_pins {
mux {
groups = "sdcard_d0",
"sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux1 {
groups = "sdcard_clk";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sd_clr_all_pins:sd_clr_all_pins {
mux {
groups = "GPIOC_0",
"GPIOC_1",
"GPIOC_2",
"GPIOC_3",
"GPIOC_5";
function = "gpio_periphs";
output-high;
};
mux1 {
groups = "GPIOC_4";
function = "gpio_periphs";
output-low;
};
};
sd_clr_noall_pins:sd_clr_noall_pins {
mux {
groups = "GPIOC_0",
"GPIOC_1",
"GPIOC_4",
"GPIOC_5";
function = "gpio_periphs";
output-high;
};
};
ao_to_sd_uart_pins:ao_to_sd_uart_pins {
mux {
groups = "uart_ao_tx_a_c3",
"uart_ao_rx_a_c2";
function = "uart_ao_a_ee";
bias-pull-up;
input-enable;
};
};
sd_iso7816_pins:sd_iso7816_pins {
mux {
groups = "iso7816_clk_z",
"iso7816_data_z";
function = "iso7816";
input-enable;
bias-pull-down;
};
};
/* sdio port A */
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_clk",
"sdio_cmd";
function = "sdio";
//bias-disable;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sdio_clk_gate_pins: sdio_clk_gate {
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
hdmitx_hpd: hdmitx_hpd {
mux {
groups = "hdmitx_hpd_in";
function = "hdmitx";
bias-disable;
};
};
hdmitx_hpd_gpio: hdmitx_hpd_gpio {
mux {
groups = "GPIOW_15";
function = "gpio_periphs";
bias-disable;
};
};
hdmitx_ddc: hdmitx_ddc {
mux {
groups = "hdmitx_sda_w13",
"hdmitx_sck_w14";
function = "hdmitx";
bias-disable;
drive-strength-microamp = <3000>;
};
};
hdmirx_a_mux:hdmirx_a_mux {
mux {
groups = "hdmirx_a_hpd",
"hdmirx_a_det",
"hdmirx_a_sda",
"hdmirx_a_sck";
function = "hdmirx_a";
};
};
hdmirx_b_mux:hdmirx_b_mux {
mux {
groups = "hdmirx_b_hpd",
"hdmirx_b_det",
"hdmirx_b_sda",
"hdmirx_b_sck";
function = "hdmirx_b";
};
};
hdmirx_c_mux:hdmirx_c_mux {
mux {
groups = "hdmirx_c_hpd",
"hdmirx_c_det",
"hdmirx_c_sda",
"hdmirx_c_sck";
function = "hdmirx_c";
};
};
cec_a: cec_a {
mux {
groups = "cec_a";
function = "cec_a";
};
};
cec_b: cec_b {
mux {
groups = "cec_b";
function = "cec_b";
};
};
jtag_a_pins: jtag_a_pin {
mux {
groups = "jtag_a_tdi",
"jtag_a_tdo",
"jtag_a_clk",
"jtag_a_tms";
function = "jtag_a";
};
};
jtag_b_pins: jtag_b_pin {
mux {
groups = "jtag_b_tdi",
"jtag_b_tdo",
"jtag_b_clk",
"jtag_b_tms";
function = "jtag_b";
};
};
pwm_a_pins: pwm_a_pins {
mux {
groups = "pwm_a";
function = "pwm_a";
drive-strength-microamp = <500>;
};
};
pwm_b_pins: pwm_b_pins {
mux {
groups = "pwm_b";
function = "pwm_b";
};
};
pwm_c_pins: pwm_c_pins {
mux {
groups = "pwm_c";
function = "pwm_c";
};
};
pwm_d_pins: pwm_d_pins {
mux {
groups = "pwm_d";
function = "pwm_d";
};
};
pwm_e_pins: pwm_e_pins {
mux {
groups = "pwm_e";
function = "pwm_e";
};
};
pwm_f_pins: pwm_f_pins {
mux {
groups = "pwm_f";
function = "pwm_f";
};
};
pwm_ao_a_pins: pwm_ao_a_pins {
mux {
groups = "pwm_ao_a";
function = "pwm_ao_a";
};
};
pwm_ao_b_pins: pwm_ao_b_pins {
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
};
};
pwm_ao_c_pins1: pwm_ao_c_pins1 {
mux {
groups = "pwm_ao_c_d";
function = "pwm_ao_c";
};
};
pwm_ao_c_pins2: pwm_ao_c_pins2 {
mux {
groups = "pwm_ao_c_e";
function = "pwm_ao_c";
};
};
pwm_ao_c_hiz_pins: pwm_ao_c_hiz_pins {
mux {
groups = "pwm_ao_c_hiz";
function = "pwm_ao_c";
};
};
pwm_ao_d_pins: pwm_ao_d_pins {
mux {
groups = "pwm_ao_d";
function = "pwm_ao_d";
};
};
pwm_ao_e_pins: pwm_ao_e_pins {
mux {
groups = "pwm_ao_e";
function = "pwm_ao_e";
};
};
pwm_ao_f_pins: pwm_ao_f_pins {
mux {
groups = "pwm_ao_f";
function = "pwm_ao_f";
};
};
pwm_ao_g_pins1: pwm_ao_g_pins1 {
mux {
groups = "pwm_ao_g_d11";
function = "pwm_ao_g";
};
};
pwm_ao_g_pins2: pwm_ao_g_pins2 {
mux {
groups = "pwm_ao_g_d7";
function = "pwm_ao_g";
};
};
pwm_ao_g_pins3: pwm_ao_g_pins3 {
mux {
groups = "pwm_ao_g_e";
function = "pwm_ao_g";
};
};
pwm_ao_g_hiz_pins: pwm_ao_g_hiz_pins {
mux {
groups = "pwm_ao_g_hiz";
function = "pwm_ao_g";
};
};
pwm_ao_h_pins1: pwm_ao_h_pins1 {
mux {
groups = "pwm_ao_h_d5";
function = "pwm_ao_h";
};
};
pwm_ao_h_pins2: pwm_ao_d_pins2 {
mux {
groups = "pwm_ao_h_d10";
function = "pwm_ao_h";
};
};
remote_pins: remote_pin {
mux {
groups = "remote_in";
function = "remote_in";
bias-disable;
};
};
spifc_all_pins: spifc_all_pins {
mux {
groups = "nor_hold",
"nor_d",
"nor_q",
"nor_c",
"nor_wp",
"nor_cs";
function = "nor";
drive-strength-microamp = <3000>;
};
};
spicc0_pins: spicc0_pins {
mux {
groups = "spi0_mosi",
"spi0_miso",
//"spi0_ss0",
"spi0_sclk";
function = "spi0";
drive-strength-microamp = <2000>;
};
};
spicc1_pins_1: spicc1_pins_1 {
mux {
groups = "spi1_mosi_c",
"spi1_miso_c",
//"spi1_ss0_c",
"spi1_sclk_c";
function = "spi1";
drive-strength-microamp = <2000>;
};
};
spicc1_pins_2: spicc1_pins_2 {
mux {
groups = "spi1_mosi_m",
"spi1_miso_m",
//"spi1_ss0_m",
"spi1_sclk_m";
function = "spi1";
drive-strength-microamp = <2000>;
};
};
spicc2_pins: spicc2_pins {
mux {
groups = "spi2_mosi",
"spi2_miso",
//"spi2_ss0",
"spi2_sclk";
function = "spi2";
drive-strength-microamp = <2000>;
};
};
spicc3_pins: spicc3_pins {
mux {
groups = "spi3_mosi",
"spi3_miso",
//"spi3_ss0",
"spi3_sclk";
function = "spi3";
drive-strength-microamp = <2000>;
};
};
spicc4_pins: spicc4_pins {
mux {
groups = "spi4_mosi",
"spi4_miso",
//"spi4_ss0",
"spi4_sclk";
function = "spi4";
drive-strength-microamp = <2000>;
};
};
spicc5_pins: spicc5_pins {
mux {
groups = "spi5_mosi",
"spi5_miso",
//"spi5_ss0",
"spi5_sclk";
function = "spi5";
drive-strength-microamp = <2000>;
};
};
irblaster_pins1:irblaster_pin1 {
mux {
groups = "remote_out_d4";
function = "remote_out";
};
};
irblaster_pins2:irblaster_pin2 {
mux {
groups = "remote_out_d6";
function = "remote_out";
};
};
spdifout_d: spdifout_d {
mux { /* GPIOD_8 */
groups = "spdif_out_d";
function = "spdif_out";
};
};
spdifout_d_mute: spdifout_d_mute {
mux { /* GPIOD_8 */
groups = "GPIOD_8";
function = "gpio_periphs";
output-low;
};
};
spdifout_t: spdifout_t {
mux { /* GPIOT_3 */
groups = "spdif_out_t";
function = "spdif_out";
};
};
spdifout_t_mute: spdifout_t_mute {
mux { /* GPIOT_3 */
groups = "GPIOT_3";
function = "gpio_periphs";
output-low;
};
};
spdifin_d: spdifin_d {
mux {/* GPIOD_9 */
groups = "spdif_in_d";
function = "spdif_in";
};
};
spdifin_t: spdifin_t {
mux {/* GPIOT_4 */
groups = "spdif_in_t";
function = "spdif_in";
};
};
mclk_1_pins: mclk_1_pin {
mux { /* GPIOT_0 */
groups = "mclk1";
function = "mclk";
};
};
mclk_2_pins: mclk_2_pin {
mux { /* GPIOT_13 */
groups = "mclk2";
function = "mclk";
};
};
lcd_vbyone_a_pins: lcd_vbyone_a_pin {
mux {
groups = "vx1_a_htpdn","vx1_a_lockn";
function = "vx1_a";
};
};
lcd_vbyone_b_pins: lcd_vbyone_b_pin {
mux {
groups = "vx1_b_htpdn","vx1_b_lockn";
function = "vx1_b";
};
};
lcd_edp_a_pins: lcd_edp_a_pin {
mux {
groups = "edp_a_hpd";
function = "edp_a";
};
};
lcd_edp_b_pins: lcd_edp_b_pin {
mux {
groups = "edp_b_hpd";
function = "edp_b";
};
};
eth_pins: eth {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_rgmii_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_txen",
"eth_txd0",
"eth_txd1";
function = "eth";
drive-strength-microamp = <4000>;
bias-disable;
};
};
eth_rgmii_pins: eth-rgmii {
mux {
groups = "eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
drive-strength-microamp = <4000>;
bias-disable;
};
};
};
&gpu{
operating-points-v2 = <&gpu_opp_table>;
reg = <0 0xFE400000 0 0x04000>, /*mali APB bus base address*/
<0 0xFE002000 0 0x01000>, /*reset register*/
<0 0xFF800000 0 0x01000>, /*aobus TODO update*/
<0 0xFE000000 0 0x01000>, /*hiubus for clk cntl*/
<0 0xFE002000 0 0x01000>; /*reset register*/
interrupts = <0 144 4>, <0 145 4>, <0 146 4>;
interrupt-names = "GPU", "MMU", "JOB";
power-domains = <&pwrdm PDID_T7_MALI_TOP>;
num_of_pp = <4>;
system-coherency = <0>;
clocks = <&clkc CLKID_MALI_MUX>;
clock-names = "gpu_mux";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI_MUX>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<800000000>,
<0>; /* Do Nothing */
tbl = <&dvfs250_cfg
&dvfs400_cfg
&dvfs500_cfg
&dvfs666_cfg
&dvfs800_cfg
&dvfs800_cfg>;
reset_cfg:reset_cfg {
reg_level = <0x11>;
reg_mask = <0x21>;
reg_bit = <2>;
};
capb_reset:capb_reset {
reg_level = <0x11>;
reg_mask = <0x21>;
reg_bit = <1>;
};
};