Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt

Amlogic Meson AXG DWC PCIE SoC controller

Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.

Additional properties are described here:

Required properties:
- compatible:
	should contain "amlogic,axg-pcie" to identify the core.
- reg:
	Should contain the configuration address space.
- reg-names: Must be
	- "elbi"        External local bus interface registers
	- "cfg"         Meson specific registers
	- "config"      PCIe configuration space
	- "phy"		Meson PCIe phy registers
	- "reset"	Meson PCIe reset registers
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must include the following entries:
	- "pcie_refpll"	PCIe GEN 100M PLL clock
	- "pcie"	PCIe RC clock gate
	- "pcie_phy"	PCIe Phy clock

Example configuration:

	pcie: pcie@f9800000 {
		compatible = "amlogic,amlogic-pcie-v2", "snps,dw-pcie";
		reg = <0x0 0xfc000000 0x0 0x400000
			0x0 0xff648000 0x0 0x2000
			0x0 0xfc400000 0x0 0x200000
			0x0 0xff646000 0x0 0x2000
			0x0 0xffd01080 0x0 0x10>;
		reg-names = "elbi", "cfg", "config", "phy", "reset";
		reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
		interrupts = <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
		bus-range = <0x0 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x81000000 0 0 0 0xfc600000 0x0 0x100000
			0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
		num-lanes = <1>;
		clocks = <&clkc CLKID_PCIE_PLL
			&clkc CLKID_PCIE_COMB
			&clkc CLKID_PCIE_PHY>;
		clock-names = "pcie_refpll",
			"pcie",
			"pcie_phy";
	};