| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __SM1_H |
| #define __SM1_H |
| #include "g12a.h" |
| /* |
| * Clock controller register offsets |
| * |
| * Register offsets from the data sheet are listed in comment blocks below. |
| * Those offsets must be multiplied by 4 before adding them to the base address |
| * to get the right value |
| */ |
| |
| #define HHI_GP1_PLL_CNTL0 0x60 /* 0x18 offset in data sheet */ |
| #define HHI_GP1_PLL_CNTL1 0x64 /* 0x19 offset in data sheet */ |
| #define HHI_GP1_PLL_CNTL2 0x68 /* 0x1a offset in data sheet */ |
| #define HHI_GP1_PLL_CNTL3 0x6C /* 0x1b offset in data sheet */ |
| #define HHI_GP1_PLL_CNTL4 0x70 /* 0x1c offset in data sheet */ |
| #define HHI_GP1_PLL_CNTL5 0x74 /* 0x1d offset in data sheet */ |
| #define HHI_GP1_PLL_CNTL6 0x78 /* 0x1e offset in data sheet */ |
| #define HHI_VIPNANOQ_CLK_CNTL 0x1C8 /* 0x72 offset in data sheet */ |
| #define HHI_SYS_CPU_CLK_CNTL5 0x21C /* 0x87 offset in data sheet */ |
| #define HHI_SYS_CPU_CLK_CNTL6 0x220 /* 0x88 offset in data sheet */ |
| #define HHI_MIPI_CSI_PHY_CLK_CNTL 0x340 /* 0xd0 offset in data sheet */ |
| #define HHI_CSI2_ADAPT_CLK_CNTL 0x3c0 /* 0xf0 offset in data sheet */ |
| |
| #endif /* __SM1_H */ |
