| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __SM1_CLKC_H |
| #define __SM1_CLKC_H |
| |
| #define CLKID_SM1_EE_CLK 0 |
| #define CLKID_GP1_PLL_DCO 1 |
| #define CLKID_GP1_PLL 2 |
| #define CLKID_DSU_PRE_SRC0 3 |
| #define CLKID_DSU_PRE_SRC1 4 |
| #define CLKID_DSU_CLK_DIV0 5 |
| #define CLKID_DSU_CLK_DIV1 6 |
| #define CLKID_DSU_PRE_MUX0 7 |
| #define CLKID_DSU_PRE_MUX1 8 |
| #define CLKID_DSU_PRE_POST_MUX 9 |
| #define CLKID_DSU_PRE_CLK 10 |
| #define CLKID_DSU_CLK 11 |
| #define CLKID_CSI_DIG_CLK 12 |
| #define CLKID_NNA_CLK 13 |
| #define CLKID_PARSER1_CLK 14 |
| #define CLKID_CSI_HOST_CLK 15 |
| #define CLKID_CSI_ADPAT_CLK 16 |
| #define CLKID_TEMP_SENSOR_CLK 17 |
| #define CLKID_CSI_PHY_CLK 18 |
| #define CLKID_VNANOQ_CORE_MUX_CLK 19 |
| #define CLKID_VNANOQ_CORE_DIV_CLK 20 |
| #define CLKID_VNANOQ_CORE_CLK_COMP 21 |
| #define CLKID_VNANOQ_AXI_MUX_CLK 22 |
| #define CLKID_VNANOQ_AXI_DIV_CLK 23 |
| #define CLKID_VNANOQ_AXI_CLK_COMP 24 |
| #define CLKID_MIPI_CSI_PHY_MUX_CLK 25 |
| #define CLKID_MIPI_CSI_PHY_DIV_CLK 26 |
| #define CLKID_MIPI_CSI_PHY_CLK_COMP 27 |
| #define CLKID_CSI_ADAPT_MUX_CLK 28 |
| #define CLKID_CSI_ADAPT_DIV_CLK 29 |
| #define CLKID_CSI_ADAPT_CLK_COMP 30 |
| |
| #define SM1_NR_CLKS 30 |
| #endif /* __G12A_CLKC_H */ |
