| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef _MESON_PMIC6_H |
| #define _MESON_PMIC6_H |
| |
| #include <linux/interrupt.h> |
| |
| /*OTP Registers |
| * range : 0x00 - 0x7f. |
| * 0x00 : reserved. |
| * 0x01 - 0x1f : reserved for internal logic control |
| * 0x20 - 0x7f : reserved for direction connection to the analog blocks |
| */ |
| |
| /*Power Up Slot Register*/ |
| #define PMIC6_POWER_UP_SEL0 0x01 |
| #define PMIC6_POWER_UP_SEL1 0x02 |
| #define PMIC6_POWER_UP_SEL2 0x03 |
| #define PMIC6_POWER_UP_SEL3 0x04 |
| |
| /*Power Down Slot Register*/ |
| #define PMIC6_POWER_DOWN_SEL0 0x05 |
| #define PMIC6_POWER_DOWN_SEL1 0x06 |
| #define PMIC6_POWER_DOWN_SEL2 0x07 |
| #define PMIC6_POWER_DOWN_SEL3 0x08 |
| |
| /*State Control (OTP_STATE_CONTROL)*/ |
| #define PMIC6_STATE_CONTROL0 0x09 |
| #define PMIC6_STATE_CONTROL1 0x0A |
| #define PMIC6_STATE_CONTROL2 0x0B |
| #define PMIC6_STATE_CONTROL3 0x0C |
| #define PMIC6_STATE_CONTROL4 0x0D |
| #define PMIC6_STATE_CONTROL5 0x0E |
| |
| /*General Control0 (OTP_GEN_CONTROL)*/ |
| #define PMIC6_GEN_CONTROL0 0x0F |
| |
| /*Supply Protection Register(OTP_SP_REG_0)*/ |
| #define PMIC6_SP_REG0 0x10 |
| #define PMIC6_SP_REG1 0x11 |
| #define PMIC6_SP_REG2 0x12 |
| #define PMIC6_SP_REG3 0x13 |
| |
| #define PMIC6_OTP_REG_0x20 0x20 |
| #define PMIC6_OTP_REG_0x21 0x21 |
| #define PMIC6_OTP_REG_0x22 0x22 |
| #define PMIC6_OTP_REG_0x23 0x23 |
| #define PMIC6_OTP_REG_0x24 0x24 |
| #define PMIC6_OTP_REG_0x25 0x25 |
| #define PMIC6_OTP_REG_0x26 0x26 |
| #define PMIC6_OTP_REG_0x27 0x27 |
| #define PMIC6_OTP_REG_0x28 0x28 |
| #define PMIC6_OTP_REG_0x29 0x29 |
| #define PMIC6_OTP_REG_0x2a 0x2A |
| #define PMIC6_OTP_REG_0x2b 0x2B |
| #define PMIC6_OTP_REG_0x2c 0x2C |
| #define PMIC6_OTP_REG_0x2d 0x2D |
| #define PMIC6_OTP_REG_0x2e 0x2E |
| #define PMIC6_OTP_REG_0x2f 0x2F |
| |
| #define PMIC6_OTP_REG_0x30 0x30 |
| #define PMIC6_OTP_REG_0x31 0x31 |
| #define PMIC6_OTP_REG_0x32 0x32 |
| #define PMIC6_OTP_REG_0x33 0x33 |
| #define PMIC6_OTP_REG_0x34 0x34 |
| #define PMIC6_OTP_REG_0x35 0x35 |
| #define PMIC6_OTP_REG_0x36 0x36 |
| #define PMIC6_OTP_REG_0x37 0x37 |
| #define PMIC6_OTP_REG_0x38 0x38 |
| #define PMIC6_OTP_REG_0x39 0x39 |
| #define PMIC6_OTP_REG_0x3a 0x3A |
| #define PMIC6_OTP_REG_0x3b 0x3B |
| #define PMIC6_OTP_REG_0x3c 0x3C |
| #define PMIC6_OTP_REG_0x3d 0x3D |
| #define PMIC6_OTP_REG_0x3e 0x3E |
| #define PMIC6_OTP_REG_0x3f 0x3F |
| |
| #define PMIC6_OTP_REG_0x40 0x40 |
| #define PMIC6_OTP_REG_0x41 0x41 |
| #define PMIC6_OTP_REG_0x42 0x42 |
| #define PMIC6_OTP_REG_0x43 0x43 |
| #define PMIC6_OTP_REG_0x44 0x44 |
| #define PMIC6_OTP_REG_0x45 0x45 |
| #define PMIC6_OTP_REG_0x46 0x46 |
| #define PMIC6_OTP_REG_0x47 0x47 |
| #define PMIC6_OTP_REG_0x48 0x48 |
| #define PMIC6_OTP_REG_0x49 0x49 |
| #define PMIC6_OTP_REG_0x4a 0x4A |
| #define PMIC6_OTP_REG_0x4b 0x4B |
| #define PMIC6_OTP_REG_0x4c 0x4C |
| #define PMIC6_OTP_REG_0x4d 0x4D |
| #define PMIC6_OTP_REG_0x4e 0x4E |
| #define PMIC6_OTP_REG_0x4f 0x4F |
| |
| #define PMIC6_OTP_REG_0x50 0x50 |
| #define PMIC6_OTP_REG_0x51 0x51 |
| #define PMIC6_OTP_REG_0x52 0x52 |
| #define PMIC6_OTP_REG_0x53 0x53 |
| #define PMIC6_OTP_REG_0x54 0x54 |
| #define PMIC6_OTP_REG_0x55 0x55 |
| #define PMIC6_OTP_REG_0x56 0x56 |
| #define PMIC6_OTP_REG_0x57 0x57 |
| #define PMIC6_OTP_REG_0x58 0x58 |
| #define PMIC6_OTP_REG_0x59 0x59 |
| #define PMIC6_OTP_REG_0x5a 0x5A |
| #define PMIC6_OTP_REG_0x5b 0x5B |
| #define PMIC6_OTP_REG_0x5c 0x5C |
| #define PMIC6_OTP_REG_0x5d 0x5D |
| #define PMIC6_OTP_REG_0x5e 0x5E |
| #define PMIC6_OTP_REG_0x5f 0x5F |
| |
| #define PMIC6_OTP_REG_0x60 0x60 |
| #define PMIC6_OTP_REG_0x61 0x61 |
| #define PMIC6_OTP_REG_0x62 0x62 |
| #define PMIC6_OTP_REG_0x63 0x63 |
| #define PMIC6_OTP_REG_0x64 0x64 |
| #define PMIC6_OTP_REG_0x65 0x65 |
| #define PMIC6_OTP_REG_0x66 0x66 |
| #define PMIC6_OTP_REG_0x67 0x67 |
| #define PMIC6_OTP_REG_0x68 0x68 |
| #define PMIC6_OTP_REG_0x69 0x69 |
| #define PMIC6_OTP_REG_0x6a 0x6A |
| #define PMIC6_OTP_REG_0x6b 0x6B |
| #define PMIC6_OTP_REG_0x6c 0x6C |
| #define PMIC6_OTP_REG_0x6d 0x6D |
| #define PMIC6_OTP_REG_0x6e 0x6E |
| #define PMIC6_OTP_REG_0x6f 0x6F |
| |
| #define PMIC6_OTP_REG_0x70 0x70 |
| #define PMIC6_OTP_REG_0x71 0x71 |
| #define PMIC6_OTP_REG_0x72 0x72 |
| #define PMIC6_OTP_REG_0x73 0x73 |
| #define PMIC6_OTP_REG_0x74 0x74 |
| #define PMIC6_OTP_REG_0x75 0x75 |
| #define PMIC6_OTP_REG_0x76 0x76 |
| #define PMIC6_OTP_REG_0x77 0x77 |
| #define PMIC6_OTP_REG_0x78 0x78 |
| #define PMIC6_OTP_REG_0x79 0x79 |
| #define PMIC6_OTP_REG_0x7a 0x7A |
| #define PMIC6_OTP_REG_0x7b 0x7B |
| #define PMIC6_OTP_REG_0x7c 0x7C |
| #define PMIC6_OTP_REG_0x7d 0x7D |
| #define PMIC6_OTP_REG_0x7e 0x7E |
| #define PMIC6_OTP_REG_0x7f 0x7F |
| |
| /*NON-OTP Registers*/ |
| #define PMIC6_GEN_CNTL0 0x80 |
| #define PMIC6_GEN_CNTL1 0x81 |
| #define PMIC6_SW_POWER_UP 0x82 |
| #define PMIC6_SW_POWER_DOWN 0x83 |
| #define PMIC6_GEN_STATUS0 0x84 |
| #define PMIC6_GEN_STATUS1 0x85 |
| #define PMIC6_GEN_STATUS2 0x86 |
| #define PMIC6_GEN_STATUS3 0x87 |
| #define PMIC6_OTP_CNTL 0x88 |
| #define PMIC6_WATCHDOG 0x89 |
| #define PMIC6_WATCHDOG_CNT 0x8A |
| #define PMIC6_PWR_KEY 0x8B |
| |
| #define PMIC6_LOW_TIMEBASE 0x8D |
| |
| #define PMIC6_HIGH_TIMEBASE 0x8F |
| |
| #define PMIC6_SYS_CLK_CNTL 0x91 |
| #define PMIC6_SAR_SW_EN_FIELD 0x92 |
| #define PMIC6_SAR_CNTL_REG0 0x93 |
| #define PMIC6_SAR_CNTL_REG1 0x94 |
| #define PMIC6_SAR_CNTL_REG2 0x95 |
| #define PMIC6_SAR_CNTL_REG3 0x96 |
| #define PMIC6_SAR_CNTL_REG4 0x97 |
| #define PMIC6_SAR_CNTL_REG5 0x98 |
| #define PMIC6_SAR_CNTL_REG6 0x99 |
| #define PMIC6_SAR_CNTL_REG7 0x9A |
| #define PMIC6_SAR_CNTL_REG8 0x9B |
| #define PMIC6_SAR_CNTL_REG9 0x9C |
| #define PMIC6_SAR_CNTL_REG10 0x9D |
| #define PMIC6_SAR_CNTL_REG11 0x9E |
| #define PMIC6_SAR_CNTL_REG12 0x9F |
| |
| #define PMIC6_SAR_CNTL_REG13 0xA0 |
| #define PMIC6_SAR_CNTL_REG14 0xA1 |
| #define PMIC6_SAR_CNTL_REG15 0xA2 |
| #define PMIC6_SAR_RD_IBAT_LAST 0xA3 |
| |
| #define PMIC6_SAR_RD_VBAT_OFF 0xA5 |
| |
| #define PMIC6_SAR_RD_VBAT_ACTIVE 0xA7 |
| |
| #define PMIC6_SAR_RD_MANUAL 0xA9 |
| |
| #define PMIC6_SAR_RD_RAW 0xAB |
| |
| #define PMIC6_SAR_CNTL_REG16 0xAD |
| #define PMIC6_SAR_CNTL_REG17 0xAE |
| #define PMIC6_SAR_CNTL_REG18 0xAF |
| #define PMIC6_SAR_CNTL_REG19 0xB0 |
| |
| #define PMIC6_SP_SOFT_RESET0 0xB1 |
| #define PMIC6_SP_SOFT_RESET1 0xB2 |
| |
| #define PMIC6_GPIO_OUT_LEVEL 0xB3 |
| #define PMIC6_GPIO_IN_LEVEL 0xB4 |
| |
| #define PMIC6_IRQ_MASK0 0xB5 |
| #define PMIC6_IRQ_MASK1 0xB6 |
| #define PMIC6_IRQ_MASK2 0xB7 |
| #define PMIC6_IRQ_MASK3 0xB8 |
| #define PMIC6_IRQ_STATUS_CLR0 0xB9 |
| #define PMIC6_IRQ_STATUS_CLR1 0xBA |
| #define PMIC6_IRQ_STATUS_CLR2 0xBB |
| #define PMIC6_IRQ_STATUS_CLR3 0xBC |
| |
| #define PMIC6_SP_DCDC1_2_STATUS 0xBD |
| #define PMIC6_SP_DCDC3_4_STATUS 0xBE |
| |
| #define PMIC6_SP_CHARGER_STATUS0 0xBF |
| #define PMIC6_SP_CHARGER_STATUS1 0xC0 |
| #define PMIC6_SP_CHARGER_STATUS2 0xC1 |
| #define PMIC6_SP_CHARGER_STATUS3 0xC2 |
| #define PMIC6_SP_CHARGER_STATUS4 0xC3 |
| |
| #define PMIC6_SP_LDO1_STATUS 0xC4 |
| #define PMIC6_SP_LDO2_3_STATUS 0xC5 |
| #define PMIC6_SP_LDO4_STATUS 0xC6 |
| |
| #define PMIC6_PIN_MUX_REG0 0xC7 |
| #define PMIC6_PIN_MUX_REG1 0xC8 |
| #define PMIC6_PIN_MUX_REG2 0xC9 |
| #define PMIC6_PIN_MUX_REG3 0xCA |
| #define PMIC6_PIN_MUX_REG4 0xCB |
| #define PMIC6_PIN_MUX_REG5 0xCC |
| #define PMIC6_PIN_MUX_REG6 0xCD |
| #define PMIC6_PIN_MUX_REG7 0xCE |
| #define PMIC6_PIN_MUX_REG8 0xCF |
| #define PMIC6_PIN_MUX_REG9 0xD0 |
| #define PMIC6_PIN_MUX_REG10 0xD1 |
| |
| #define PMIC6_I2C_OTP_ADDR 0xD2 |
| #define PMIC6_I2C_OTP_WDATA 0xD3 |
| |
| #define PMIC6_I2C_OTP_RDATA_BYTE0 0xD4 |
| |
| #define PMIC6_ANALOG_REG0 0xD8 |
| #define PMIC6_ANALOG_REG1 0xD9 |
| #define PMIC6_ANALOG_REG2 0xDA |
| #define PMIC6_ANALOG_REG3 0xDB |
| #define PMIC6_ANALOG_REG4 0xDC |
| #define PMIC6_ANALOG_REG5 0xDD |
| #define PMIC6_ANALOG_REG6 0xDE |
| #define PMIC6_ANALOG_REG7 0xDF |
| #define PMIC6_ANALOG_REG8 0xE0 |
| #define PMIC6_ANALOG_REG9 0xE1 |
| |
| #define PMIC6_CNTL_ADJUST_DC1 0xE2 |
| #define PMIC6_CNTL_ADJUST_DC2 0xE3 |
| #define PMIC6_CNTL_ADJUST_DC3 0xE4 |
| #define PMIC6_CNTL_ADJUST_DC4 0xE5 |
| |
| #define PMIC6_SAR_RD_IBAT_CHG0 0xE6 |
| #define PMIC6_SAR_RD_IBAT_CHG1 0xE7 |
| #define PMIC6_SAR_RD_IBAT_CHG2 0xE8 |
| |
| #define PMIC6_SAR_RD_IBAT_DISCHG0 0xEC |
| #define PMIC6_SAR_RD_IBAT_DISCHG1 0xED |
| #define PMIC6_SAR_RD_IBAT_DISCHG2 0xEE |
| |
| #define PMIC6_SAR_RD_IBAT_CNT_CHG0 0xF2 |
| |
| #define PMIC6_SAR_RD_IBAT_CNT_DISCHG0 0xF6 |
| |
| #define PMIC6_SAR_RD_IBAT_LAST_RAW0 0xFA |
| |
| /*raw result means the result always updated immediately after measurement*/ |
| #define PMIC6_SAR_RD_IBAT_RAW_CHG0 0xFC |
| #define PMIC6_SAR_RD_IBAT_RAW_CHG1 0xFD |
| #define PMIC6_SAR_RD_IBAT_RAW_CHG2 0xFE |
| |
| #define PMIC6_SAR_RD_IBAT_RAW_DISCHG0 0x102 |
| #define PMIC6_SAR_RD_IBAT_RAW_DISCHG1 0x103 |
| #define PMIC6_SAR_RD_IBAT_RAW_DISCHG2 0x104 |
| |
| #define PMIC6_PWM1_TH_REG 0x108 |
| |
| #define PMIC6_PWM1_TL_REG 0x10B |
| |
| #define PMIC6_PWM2_TH_REG 0x10E |
| |
| #define PMIC6_PWM2_TL_REG 0x111 |
| |
| #define PMIC6_PWM_CLK_TCNT_REG 0x114 |
| |
| #define PMIC6_REG_MAX 0x115 |
| |
| /* |
| * PMIC registers bits |
| */ |
| |
| /* PMIC6_IRQ_MASK0 (addr=0xB5) */ |
| |
| /* PMIC6 modules */ |
| #define PMIC6_DRVNAME_REGULATORS "pmic6-regulators" |
| #define PMIC6_DRVNAME_LEDS "pmic6-leds" |
| #define PMIC6_DRVNAME_WATCHDOG "pmic6-watchdog" |
| #define PMIC6_DRVNAME_ONKEY "pmic6-pwrkey" |
| #define PMIC6_DRVNAME_BATTERY "pmic6-battery" |
| #define PMIC6_DRVNAME_GPIO "pmic6-gpio" |
| |
| /*regulator ID*/ |
| enum { |
| PMIC6_DCDC1, |
| PMIC6_DCDC2, |
| PMIC6_DCDC3, |
| PMIC6_LDO1, |
| PMIC6_LDO2, |
| PMIC6_LDO3, |
| PMIC6_REGU_MAX, |
| |
| }; |
| |
| /* Interrupts */ |
| enum pmic6_irqs { |
| PMIC6_IRQ_NTC_UNT = 0, |
| PMIC6_IRQ_NTC_OVT, |
| PMIC6_IRQ_CHG_DCIN_UV_LV, |
| PMIC6_IRQ_CHG_DCIN_OV_LV, |
| PMIC6_IRQ_CHG_OTP, |
| PMIC6_IRQ_CHG_OCP, |
| PMIC6_IRQ_CHG_OVP, |
| PMIC6_IRQ_CHG_DCIN_OK, |
| PMIC6_IRQ_CHG_TIMEOUT, |
| PMIC6_IRQ_CHG_CHGEND, |
| PMIC6_IRQ_DC1_UV, |
| PMIC6_IRQ_DC1_OC, |
| PMIC6_IRQ_DC2_UV, |
| PMIC6_IRQ_DC2_OC, |
| PMIC6_IRQ_DC3_UV, |
| PMIC6_IRQ_DC3_OC, |
| |
| PMIC6_IRQ_VSYS_UVLO = 17, |
| PMIC6_IRQ_LDO1_OV, |
| PMIC6_IRQ_LDO1_UV, |
| PMIC6_IRQ_LDO1_OC, |
| PMIC6_IRQ_LDO2_OV, |
| PMIC6_IRQ_LDO2_UV, |
| PMIC6_IRQ_LDO2_OC, |
| PMIC6_IRQ_LDO3_OV, |
| PMIC6_IRQ_LDO3_UV, |
| PMIC6_IRQ_LDO3_OC, |
| |
| PMIC6_IRQ_PWR_KEY = 30, |
| PMIC6_IRQ_SAR, |
| }; |
| |
| struct meson_pmic { |
| /* Device */ |
| struct device *dev; |
| unsigned int flags; |
| |
| /* Control interface */ |
| struct regmap *regmap; |
| |
| /* Interrupts */ |
| int chip_irq; |
| unsigned int irq_base; |
| struct regmap_irq_chip_data *regmap_irq; |
| }; |
| |
| /* Regulators platform data */ |
| struct pmic6_regulator_data { |
| int id; |
| struct regulator_init_data *initdata; |
| }; |
| |
| struct pmic6_regulators_pdata { |
| unsigned int n_regulators; |
| struct pmic6_regulator_data *regulator_data; |
| }; |
| |
| /* PMIC6 platform data */ |
| struct pmic6_pdata { |
| int (*init)(struct meson_pmic *pmic6); |
| int irq_base; |
| int key_power; |
| unsigned int flags; |
| struct pmic6_regulators_pdata *regulators_pdata; |
| struct led_platform_data *leds_pdata; |
| }; |
| |
| #endif /* _MESON_PMIC6_H */ |
