| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| * Copyright 2017-2018 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx6ul.dtsi" |
| |
| / { |
| model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; |
| compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; |
| |
| aliases { |
| spi5 = &soft_spi; |
| }; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| memory { |
| reg = <0x80000000 0x20000000>; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_sd1_vmmc: regulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| off-on-delay = <20000>; |
| enable-active-high; |
| }; |
| |
| reg_can_3v3: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "can-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_gpio_dvfs: regulator-gpio { |
| compatible = "regulator-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dvfs>; |
| regulator-min-microvolt = <1300000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-name = "gpio_dvfs"; |
| regulator-type = "voltage"; |
| gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; |
| states = <1300000 0x1 1400000 0x0>; |
| }; |
| }; |
| |
| soft_spi: soft-spi { |
| compatible = "spi-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi4>; |
| pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| gpio-sck = <&gpio5 11 0>; |
| gpio-mosi = <&gpio5 10 0>; |
| cs-gpios = <&gpio5 7 0>; |
| num-chipselects = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| gpio_spi: gpio_spi@0 { |
| compatible = "fairchild,74hc595"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0>; |
| registers-number = <1>; |
| registers-default = /bits/ 8 <0x57>; |
| spi-max-frequency = <100000>; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy0>; |
| status = "okay"; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy1>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@2 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <2>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| mag3110@0e { |
| compatible = "fsl,mag3110"; |
| reg = <0x0e>; |
| position = <2>; |
| }; |
| |
| fxls8471@1e { |
| compatible = "fsl,fxls8471"; |
| reg = <0x1e>; |
| position = <0>; |
| interrupt-parent = <&gpio5>; |
| interrupts = <0 8>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock_frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_1>; |
| imx6ul-evk { |
| pinctrl_hog_1: hoggrp-1 { |
| fsl,pins = < |
| MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ |
| MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ |
| MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ |
| MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 |
| >; |
| }; |
| |
| pinctrl_dvfs: dvfsgrp { |
| fsl,pins = < |
| MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 |
| >; |
| }; |
| |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 |
| >; |
| }; |
| |
| pinctrl_enet2: enet2grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 |
| MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 |
| MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1grp_gpio { |
| fsl,pins = < |
| MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 |
| MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 |
| MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2grp_gpio { |
| fsl,pins = < |
| MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 |
| MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 |
| MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 |
| MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 |
| MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 |
| MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 |
| MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 |
| >; |
| }; |
| |
| pinctrl_spi4: spi4grp { |
| fsl,pins = < |
| MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 |
| MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 |
| MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 |
| MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
| MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usb_otg1_id: usbotg1idgrp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2_8bit: usdhc2grp_8bit { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 |
| >; |
| }; |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 |
| >; |
| }; |
| }; |
| }; |
| |
| &qspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi>; |
| status = "okay"; |
| ddrsmp=<0>; |
| |
| flash0: n25q256a@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "micron,n25q256a"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| reg = <0>; |
| }; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb_otg1_id>; |
| dr_mode = "otg"; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| dr_mode = "host"; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usbphy1 { |
| tx-d-cal = <0x5>; |
| }; |
| |
| &usbphy2 { |
| tx-d-cal = <0x5>; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; |
| keep-power-in-suspend; |
| wakeup-source; |
| vmmc-supply = <®_sd1_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| }; |
