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/*
* Copyright (c) 2016 Andreas Färber
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/clock/sc2-clkc.h>
#include <dt-bindings/input/meson_rc.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 16 MiB reserved for Hardware ROM Firmware */
hwrom_reserved: hwrom@0 {
reg = <0x0 0x0 0x0 0x1000000>;
no-map;
};
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@10000000 {
reg = <0x0 0x10000000 0x0 0x200000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xbc00000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
firmware {
sm: secure-monitor {
compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
};
};
efuse: efuse {
compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse";
#address-cells = <1>;
#size-cells = <1>;
};
scpi {
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
clock-output-names = "vcpu";
};
};
scpi_sensors: sensors {
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@2c001000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
sram: sram@f7000000 {
compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram";
reg = <0x0 0xf7000000 0x0 0x48000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xf7000000 0x48000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x47000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x47400 0x400>;
};
};
cbus: cbus@fe070000 {
compatible = "simple-bus";
reg = <0x0 0xfe070000 0x0 0xF000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>;
uart_a: serial@8000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x8000 0x0 0x18>;
clocks = <&xtal>;
status = "disabled";
};
uart_b: serial@a000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0xa000 0x0 0x18>;
clocks = <&xtal>;
status = "disabled";
};
reset: reset-controller@1000 {
compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
reg = <0x0 0x01000 0x0 0x1000>;
#reset-cells = <1>;
};
uart_c: serial@22000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x22000 0x0 0x18>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
jtag {
compatible = "amlogic, jtag";
status = "okay";
select = "disable"; /* disable/jtag-a/jtag-b */
pinctrl-names="jtag_a_pins", "jtag_b_pins";
pinctrl-0=<&jtag_a_pins>;
pinctrl-1=<&jtag_b_pins>;
};
};
periphs: periphs@ff634000 {
compatible = "simple-bus";
reg = <0x0 0xff634000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
};
hiubus: hiubus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
mailbox: mailbox@404 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;
interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
<0 209 IRQ_TYPE_EDGE_RISING>,
<0 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
};
clkc: clock-controller@0 {
compatible = "amlogic,sc2-clkc";
#clock-cells = <1>;
reg = <0x0 0xfe000000 0x0 0x82e8>;
clocks = <&xtal>;
clock-names = "xtal";
};
i2c0: i2c@fe001400 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xfe066000 0x0 0x24>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@fe005c00 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xfe068000 0x0 0x24>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@fe006800 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xfe06a000 0x0 0x24>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@fe006c00 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xfe06c000 0x0 0x24>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@fe06e000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xfe06e000 0x0 0x24>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc0: spi@fe050000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0xfe050000 0x0 0x44>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@fe052000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0xfe052000 0x0 0x44>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spifc: spi@fe056000 {
compatible = "amlogic,spifc";
status = "disabled";
reg = <0x0 0xfe056000 0x0 0x80>;
/* clocks = <&clkc CLKID_CLK81>; */
/* clock-names = "core"; */
pinctrl-names = "default";
pinctrl-0 = <&spifc_pins>;
#address-cells = <1>;
#size-cells = <0>;
spi-flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <20000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
status = "disabled";
};
spi-nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <20000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
status = "disabled";
};
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,g12a-eth-dwmac";
phy_cntl1 = <0x41054147>;
pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
analog_val = <0x20200000 0x0000c000 0x00000023>;
status = "disabled";
};
saradc: adc@fe026000 {
compatible = "amlogic,meson-saradc";
reg = <0x0 0xfe026000 0x0 0x48>;
status = "disabled";
};
nand: nfc@fe08c800 {
compatible = "amlogic,meson-nfc";
reg = <0x0 0xfe08c800 0x0 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clk_reg = <0 0xfe08c000>;
};
apb: apb@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x1000000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
watchdog@2100 {
compatible = "amlogic,meson-sc2-wdt";
reg = <0x0 0x2100 0x0 0x10>;
clocks = <&xtal>;
clock-names = "wdt-clk";
};
sd_emmc_a: sdio {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x88000 0x0 0x800>;
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
pinname = "sdio";
};
sd_emmc_b: sd {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x8a000 0x0 0x800>;
interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
pinname = "sd";
};
sd_emmc_c: emmc {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x8c000 0x0 0x800>;
interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
pinname = "emmc";
};
};
dwc3: dwc3@fde00000 {
compatible = "snps,dwc3","synopsys,xhci-dwc3";
status = "disable";
reg = <0x0 0xfde00000 0x0 0x100000>;
phys = <&usb2_phy_v2>, <&usb3_phy_v2>;
phy-names = "usb2-phy", "usb3-phy";
};
usb2_phy_v2: usb2phy@fe03a000 {
compatible = "amlogic, amlogic-new-usb2-v2";
status = "disable";
#address-cells = <2>;
#size-cells = <2>;
phy-version = <2>;
reg = <0x0 0xfe03a000 0x0 0x80
0x0 0xFE002000 0x0 0x100
0x0 0xfe03c000 0x0 0x2000
0x0 0xfe03e000 0x0 0x2000>;
dwc2_a_reg = <0xfdd00000>;
#phy-cells = <0>;
};
usb3_phy_v2: usb3phy@fe03a080 {
compatible = "amlogic, amlogic-new-usb3-v2";
status = "disable";
#address-cells = <2>;
#size-cells = <2>;
phy-version = <3>;
reg = <0x0 0xfe03a080 0x0 0x20>;
phy-reg = <0xfe03c000>;
phy-reg-size = <0x2000>;
usb2-phy-reg = <0xfe03a000>;
usb2-phy-reg-size = <0x80>;
#phy-cells = <0>;
};
ir: meson-ir {
compatible = "amlogic, meson-ir";
reg = <0x0 0xfe084040 0x44 0x0>, /*Multi-format IR controller*/
<0x0 0xfe084000 0x20 0x0>; /*Legacy IR controller*/
protocol = <REMOTE_TYPE_NEC>;
status = "disabled";
};
};
};