| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <common.h> |
| #include <asm/arch/clock.h> |
| #include <asm/arch/clk_measure_tab.h> |
| #include <asm/arch/io.h> |
| #include <asm/arch/secure_apb.h> |
| |
| unsigned long clk_util_clk_msr(unsigned long clk_mux) |
| { |
| unsigned int regval = 0; |
| |
| writel(0, MSR_CLK_REG0); |
| /* Set the measurement gate to 64uS */ |
| /* 64uS is enough for measure the frequence? */ |
| setbits_le32(MSR_CLK_REG0, 64 - 1); |
| /* Disable continuous measurement */ |
| /* Disable interrupts */ |
| clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18)); |
| clrbits_le32(MSR_CLK_REG0, 0x7f << 20); |
| setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16)); |
| /* Wait for the measurement to be done */ |
| regval = readl(MSR_CLK_REG0); |
| do { |
| regval = readl(MSR_CLK_REG0); |
| } while (regval & (1 << 31)); |
| |
| /* Disable measuring */ |
| clrbits_le32(MSR_CLK_REG0, 1 << 16); |
| regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff; |
| |
| return (regval >> 6); |
| } |
| |
| int clk_msr(int index) |
| { |
| unsigned int index_total = sizeof(clk_msr_table) / sizeof(clk_msr_table[0]); |
| int i; |
| |
| if (index == 0xff) { |
| for (i = 0; i < index_total; i++) |
| printf("[%4d][%4ld MHz] %s\n", i, clk_util_clk_msr(i), clk_msr_table[i]); |
| } else { |
| if (index >= index_total) { |
| printf("clk msr legal range: [0-%d]\n", index_total-1); |
| return -1; |
| } |
| printf("[%4d][%4ld MHz] %s\n", index, clk_util_clk_msr(index), clk_msr_table[index]); |
| } |
| |
| return 0; |
| } |